Gate drive circuit, display panel and display device

Abstract

The invention discloses a gate drive circuit, a display panel and a display device. The gate drive circuit comprises: a trigger unit comprising a first trigger unit for outputting a light emitting control signal and a second trigger unit for outputting a first scanning signal, the first scanning signal comprising a plurality of first effective pulses in at least one cut-off level period of the light emitting control signal, and the second scanning signal comprising a plurality of second effective pulses in at least one cut-off level period of the light emitting control signal; the first effective pulse is used for controlling conduction of the transistor; the waveform conversion unit is electrically connected with the output end of the first trigger unit and the output end of the second trigger unit and used for outputting a second scanning signal under the control of the light emitting control signal, a second effective pulse of the second scanning signal is used for controlling conduction of the transistor, and the second scanning signal and the first scanning signal are opposite in phase. According to the embodiment of the invention, the multi-pulse second scanning signal can be output, and the display performance of a display product can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the display performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a gate driving circuit, a display panel and a display device, which can output a multi-pulse second scanning signal, which is beneficial to improving the display performance of the display product.

[0005] In the first aspect, an embodiment of the present application provides a gate drive circuit, including: a trigger unit, including a first trigger unit and a second trigger unit, the first trigger unit is used to output a light-emitting control signal, and the second trigger unit is used to output a first scan signal. In at least one cut-off level period of the light-emitting control signal, the first scan signal includes a plurality of first valid pulses, and the first valid pulse is used to control the conduction of a P-type transistor in a pixel circuit; a waveform conversion unit, electrically connected to the output end of the first trigger unit and the output end of the second trigger unit, and used to output a second scan signal under the control of the light-emitting control signal, and the second valid pulse of the second scan signal is used to control the conduction of an N-type transistor in the pixel circuit, and the second scan signal is inverted to the first scan signal.

[0006] In a possible implementation of the first aspect, the waveform conversion unit includes a NAND gate circuit, a gating module, and an output control module;

[0007] The first input end of the NAND gate circuit is electrically connected to the output end of the first trigger unit, the second input end of the NAND gate circuit is electrically connected to the output end of the second trigger unit, and the output end of the NAND gate circuit is electrically connected to the input end of the gating module;

[0008] The control end of the gating module is electrically connected to the output end of the first trigger unit, and the output end of the gating module is electrically connected to the input end of the output control module and the output end of the waveform conversion unit. The gating module is used to selectively connect its input end to the input end of the output control module, or connect its input end to the output end of the waveform conversion unit under the control of the output signal of the first trigger unit;

[0009] The control end of the output control module is electrically connected to the output end of the first trigger unit, and the output end of the output control module is electrically connected to the output end of the waveform conversion unit. The output control module is used to output the signal from the output end of the NAND gate circuit under the control of the output signal of the first trigger unit.

[0010] In a possible implementation of the first aspect, the waveform conversion unit further includes a voltage stabilization module;

[0011] The NAND gate circuit, the gating module and the output control module are all electrically connected to the output end of the first trigger unit through the voltage stabilizing module, and the voltage stabilizing module is used to stabilize the light emitting control signal to a high level and a low level.

[0012] In a possible implementation of the first aspect, the gating module includes a first transistor and a second transistor, the first electrode of the first transistor and the first electrode of the second transistor are connected to each other as the input end of the gating module, the second electrode of the first transistor is electrically connected to the input end of the output control module, the second electrode of the second transistor is electrically connected to the output end of the waveform conversion unit, and the gate of the first transistor and the gate of the second transistor are electrically connected to the output end of the first trigger unit; one of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor.

[0013] In a possible implementation of the first aspect, the output control module includes a third transistor, a fourth transistor, and a first inverter;

[0014] The gate of the third transistor and the gate of the fourth transistor are electrically connected to the output terminal of the first trigger unit, the first electrode of the third transistor is electrically connected to the first A power supply terminal, the second electrode of the third transistor is electrically connected to the first inverter, the first electrode of the fourth transistor is electrically connected to the first B power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first inverter;

[0015] The input end of the first inverter serves as the input end of the output control module, and the output end of the first inverter serves as the output end of the output control module;

[0016] The third transistor and the fourth transistor are of the same type.

[0017] In a possible implementation of the first aspect, the voltage stabilizing module includes a second inverter and a third inverter connected in series;

[0018] Preferably, the second inverter and the third inverter are electrically connected to the second power supply terminal A and the second power supply terminal B, the voltage of the second power supply terminal A is PVGH2, the voltage of the second power supply terminal B is PVGL2, the voltage of the first power supply terminal A is PVGH1, the voltage of the first power supply terminal B is PVGL1, and the threshold voltage of the N-type transistor in the second inverter and the third inverter is Vth_igzo , the threshold voltage of the P-type transistors in the second inverter and the third inverter is V th_ltps ;

[0019] Among them, PVGH2>PVGH+V th_igzo , PVGL2=PVGL+V th_ltps .

[0020] In a possible implementation of the first aspect, the light emitting control signal output by the first trigger unit is used to drive K rows of pixels in the display panel, where K≥2.

[0021] A trigger unit includes a first trigger unit and K cascaded second trigger units, and K waveform conversion units;

[0022] The K waveform conversion units are all electrically connected to the output end of the first trigger unit;

[0023] The K cascaded second trigger units are electrically connected to the K waveform conversion units in a one-to-one correspondence.

[0024] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display panel, including:

[0025] Pixel circuit;

[0026] And the gate driving circuit as described in any one of the embodiments of the first aspect;

[0027] The gate driving circuit is electrically connected to the pixel circuit.

[0028] In a possible implementation manner of the second aspect, the pixel circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0029] The gate of the fifth transistor is electrically connected to the output end of the first trigger unit, the gate of the sixth transistor is electrically connected to the output end of the second trigger unit, and the gate of the seventh transistor is electrically connected to the output end of the waveform conversion unit.

[0030] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device, comprising a display panel as described in any one of the embodiments in the second aspect.

[0031] According to the gate drive circuit, display panel and display device provided by the embodiments of the present application, the waveform conversion unit directly inverts the first scanning signal to obtain a second scanning signal having multiple second valid pulses. The second scanning signal is used to control the N-type transistor, thereby realizing multiple data signal writing control on the LTPO type pixel circuit, which is beneficial to improve the first frame brightness ratio of the LTPO type display panel.

[0032] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0034] Figure 1 A schematic diagram showing a characteristic curve of a transistor;

[0035] Figure 2 A schematic diagram showing brightness of a display panel for multiple frames;

[0036] Figure 3 A schematic diagram showing a structure of a gate drive circuit provided in an embodiment of the present application is shown;

[0037] Figure 4 A schematic diagram showing a structure of a pixel circuit provided in an embodiment of the present application is shown;

[0038] Figure 5 A timing diagram showing an output signal of a gate driving circuit provided in an embodiment of the present application;

[0039] Figure 6 Another schematic diagram of the structure of the gate driving circuit provided in the embodiment of the present application is shown;

[0040] Figure 7 A schematic diagram showing a structure of a NAND gate circuit in a gate drive circuit provided in an embodiment of the present application is shown;

[0041] Figure 8 A timing diagram showing some signals of a gate driving circuit provided in an embodiment of the present application;

[0042] Fig. 9 Another structural schematic diagram of a gate driving circuit provided in an embodiment of the present application is shown;

[0043] Fig.10 A schematic structural diagram of a first inverter in a gate drive circuit provided in an embodiment of the present application is shown;

[0044] Fig.11 A schematic diagram showing a structure of an inverter of a voltage stabilizing module in a gate driving circuit provided in an embodiment of the present application is shown;

[0045] Fig.12A timing diagram of a gate driving circuit provided by an embodiment of the present application is shown;

[0046] Fig.13 Another structural schematic diagram of a gate driving circuit provided in an embodiment of the present application is shown;

[0047] Fig.14 Show Fig.13 A timing diagram of

[0048] Fig.15 A schematic diagram showing a structure of a first trigger unit in a gate drive circuit provided in an embodiment of the present application is shown;

[0049] Fig.16 Show Fig.15 A timing diagram of

[0050] Fig.17 A schematic diagram showing a structure of a second trigger unit in a gate drive circuit provided in an embodiment of the present application is shown;

[0051] Fig.18 Show Fig.17 A timing diagram of

[0052] Fig.19 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown.

[0053] Description of reference numerals:

[0054] 100. Gate driving circuit;

[0055] 10. Trigger unit;

[0056] 11. A first trigger unit; 12. A second trigger unit;

[0057] 20. Waveform conversion unit;

[0058] 21. NAND gate circuit; 22. gating module; 23. output control module; 231. first inverter; 24. voltage stabilizing module; 242. second inverter; 243. third inverter;

[0059] 200. Display panel;

[0060] 1000. Display device. DETAILED DESCRIPTION

[0061] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0062] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0063] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0064] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0065] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0066] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0067] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0068] The display panel utilizes a pixel circuit to drive the light-emitting element to emit light, and the transistor in the pixel circuit is driven and controlled by a gate driving circuit.

[0069] The pixel circuit includes a low temperature polysilicon (LTPS) type pixel circuit. When the thin film transistor (TFT) in the LTPS type pixel circuit is working, when the black screen turns to the white screen, the threshold voltage (Vth) of the thin film transistor is positively shifted due to the bias voltage and temperature during the light emission process. Figure 1 As shown, Figure 1 The dotted line in the middle represents the characteristic curve before Vth shift, and the solid line represents the characteristic curve after Vth forward shift. When the black screen turns to the white screen, the TFT working state before data is written (refer to Vgs1). It can be seen that the change in the characteristics of the thin film transistor causes the pixel charging rate in the display panel to increase, resulting in insufficient response of the display panel in the first frame, such as Figure 2 The display panel shown has dim brightness in the first frame.

[0070] A related solution is to use a scan driving circuit to output a multi-pulse scan signal (Scan) to improve the Vth offset, wherein the multi-pulse Scan signal is used to control the writing of data signals.

[0071] With the development of display technology, low-temperature polycrystalline oxide (LTPO) technology has emerged. In LTPO technology, the pixel circuit includes not only P-type transistors but also N-type transistors. However, the LTPO type pixel circuit is affected by the existing circuit driving factors and cannot flexibly realize the multi-pulse scanning signal of the N-type transistor used to write data signals. Therefore, for LTPO type display panels, there is still a problem of poor first frame response.

[0072] Based on the above technical problems, an embodiment of the present application provides a gate driving circuit, a display panel and a display device. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0073] Figure 3 FIG. 1 is a schematic diagram showing a structure of a gate drive circuit provided in an embodiment of the present application. Figure 3 As shown, the gate driving circuit 100 provided in the embodiment of the present application includes a trigger unit 10 and a waveform conversion unit 20 .

[0074] The trigger unit 10 includes a first trigger unit 11 and a second trigger unit 12. The first trigger unit 11 is used to output a light-emitting control signal EM, and the second trigger unit 12 is used to output a first scanning signal Scan_P. In at least one cut-off level period of the light-emitting control signal EM, the first scanning signal Scan_P includes a plurality of first valid pulses. The first valid pulse Scan_P is used to control the conduction of the P-type transistor in the pixel circuit.

[0075] The waveform conversion unit 20 is electrically connected to the output end of the first trigger unit 11 and the output end of the second trigger unit 12, and is used to output the second scanning signal Scan_N under the control of the light-emitting control signal EM. The second effective pulse of the second scanning signal Scan_N is used to control the conduction of the N-type transistor in the pixel circuit. The second scanning signal Scan_N is inverted with the first scanning signal Scan_P.

[0076] It is understandable that the light emitting control signal EM can be used to control whether the pixels in the display panel emit light, the first scan signal Scan_P can be used to control the P-type transistor in the pixel circuit, and the second scan signal Scan_N can be used to control the N-type transistor in the pixel circuit.

[0077] As an example, Figure 4 A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown. Figure 4 As shown, the pixel circuit includes a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7. The number of the fifth transistor M5 can be 2. The pixel circuit also includes a driving transistor DT. The connection method of each transistor in the pixel circuit is shown in FIG. Figure 4 , I will not go into details here.

[0078] The gate of the fifth transistor M5 is connected to the light emitting control signal EM, the gate of the sixth transistor M6 is connected to the first scanning signal Scan_P, and the gate of the seventh transistor M7 is connected to the second scanning signal Scan_N.

[0079] The fifth transistor M5 can be used to control whether the pixel emits light, and the sixth transistor M6 and the seventh transistor M7 are used to control whether the data signal data is written into the gate of the driving transistor DT.

[0080] Figure 5 A timing diagram of the output signal of the gate drive circuit provided in the embodiment of the present application is shown. In the embodiment of the present application, the cut-off level of the light-emitting control signal EM is taken as an example as a high level and the conduction level is a low level. In addition, the first effective pulse of the first scanning signal Scan_P is used to control the conduction of the P type, and the first effective pulse of the first scanning signal Scan_P is a low level pulse. The second effective pulse of the second scanning signal Scan_N is used to control the conduction of the N type transistor, and the second effective pulse of the second scanning signal Scan_N is a high level pulse. The second scanning signal Scan_N is inverted with the first scanning signal Scan_P. It can be seen that the number of the second effective pulses is the same as the number of the first effective pulses. Figure 5 As shown, in the period when the light emitting control signal EM is at a high level, the first scanning signal Scan_P includes three first effective pulses at a low level, and the second scanning signal Scan_N includes three second effective pulses at a high level.

[0081] According to the gate drive circuit provided in the embodiment of the present application, the waveform conversion unit directly inverts the first scanning signal to obtain a second scanning signal having multiple second effective pulses. The second scanning signal is used to control the N-type transistor, thereby realizing multiple data signal writing control on the LTPO type pixel circuit, which is beneficial to improve the first frame brightness ratio of the LTPO type display panel.

[0082] Exemplarily, the first trigger unit and the second trigger unit can adopt an existing circuit structure (which will be exemplarily described below), that is, use the existing light-emitting control signal and the first scanning signal as the trigger signal, so that there is no need to add an additional trigger signal circuit, which can save the frame space of the screen body, is easy to implement, and is conducive to reducing costs without reducing production capacity. In addition, in the display driving process of the display panel, the second scanning signal follows the change of the first scanning signal, which is convenient for realizing the control of the effective pulse width and quantity of the scanning signal during the display process.

[0083] The circuit structure of the waveform conversion unit is exemplarily introduced below. It should be noted that other circuit structures that can realize the function of the waveform conversion unit are within the protection scope of this application.

[0084] In some embodiments, Figure 6 As shown, the waveform conversion unit 20 includes a NAND gate circuit 21 , a gating module 22 and an output control module 23 .

[0085] The first input terminal of the NAND gate circuit 21 is electrically connected to the output terminal of the first trigger unit 11 , the second input terminal of the NAND gate circuit 21 is electrically connected to the output terminal of the second trigger unit 12 , and the output terminal of the NAND gate circuit 21 is electrically connected to the input terminal of the gating module 22 .

[0086] The control end of the gating module 22 is electrically connected to the output end of the first trigger unit 11, and the output end of the gating module 22 is electrically connected to the input end of the output control module 23 and the output end Nscan of the waveform conversion unit 20. The gating module 22 is used to selectively connect its input end and the input end of the output control module 23, or connect its input end and the output end of the waveform conversion unit 20 under the control of the output signal of the first trigger unit 11.

[0087] The control end of the output control module 23 is electrically connected to the output end of the first trigger unit 11, and the output end of the output control module 23 is electrically connected to the output end Nscan of the waveform conversion unit 20. The output control module 23 is used to output the signal from the output end of the NAND gate circuit 21 under the control of the output signal of the first trigger unit 11.

[0088] It can be understood that the signal output from the output terminal Nscan of the waveform conversion unit 20 comes from the output terminal of the NAND gate circuit 21, and the selection module 22 can control the signal output path from the output terminal of the NAND gate circuit 21 to the output terminal Nscan of the waveform conversion unit 20, wherein the first path is: the signal output from the output terminal of the NAND gate circuit 21 passes through the selection module 22, the input terminal of the output control module 23, and the output terminal of the output control module 23 to reach the output terminal Nscan of the waveform conversion unit 20; the second set of paths is: the signal output from the output terminal of the NAND gate circuit 21 passes through the selection module 22 and then reaches the output terminal Nscan of the waveform conversion unit 20.

[0089] The two input terminals of the NAND gate circuit 21 are connected to the output terminals of the first trigger unit 11 and the second trigger unit 12 respectively. Figure 7 As shown, the NAND gate circuit 21 includes transistors M211 to M214, transistors M211 and M212 are P-type transistors, transistors M213 and M214 are N-type transistors, the first input terminal IN1 of the NAND gate circuit 21 is electrically connected to the output terminal of the first trigger unit 11, the second input terminal IN2 of the NAND gate circuit 21 is electrically connected to the output terminal of the second trigger unit 12, and the output terminal of the NAND gate circuit 21 is marked as OUT21. The working logic of the NAND gate circuit 21 is shown in Table 1. It should be noted that in each working logic table of the present application, 0 represents a low level and 1 represents a high level.

[0090] Table 1

[0091]

[0092] It can be seen that when the light control signal output by the first trigger unit 11 is at a cut-off level (e.g., high level 1), the NAND gate circuit 21 can output a signal that is inverted with the first scanning signal (the signal connected to IN2). In this way, it is easy to realize that the second scanning signal finally output by the waveform conversion unit has multiple second valid pulses.

[0093] The first trigger unit 11 is used to output a light emitting control signal EM, such as Figure 8 As shown, the inventors have found that in the related art, the working process of the first trigger unit 11 includes the Ta stage and the Tb stage. In the Ta stage, the first trigger unit 11 outputs a stable cutoff level (for example, a high level). In the Tb stage (which can be understood as an intermediate state stage), the output voltage of the first trigger unit 11 is not stable.

[0094] In view of the above technical problems, in some optional embodiments, please refer to Figure 6 The waveform conversion unit 20 may further include a voltage stabilizing module 24; the NAND gate circuit 21, the selection module 22 and the output control module 23 are all electrically connected to the output end of the first trigger unit 11 through the voltage stabilizing module 24, and the voltage stabilizing module 11 is used to stabilize the output signal of the first trigger unit 11 to a high level and a low level.

[0095] Please continue to refer to Figure 8 , Figure 8 The signal output by the voltage stabilizing module 11 is marked as EMA. For example, in the Tb stage, the voltage stabilizing module can stabilize the unstable voltage into a high voltage.

[0096] In the embodiment of the present application, by providing a voltage stabilizing module 24, the signal output by the first trigger unit can be stabilized to a high level and a low level, thereby avoiding an unstable level in the Tb stage, thereby improving the stability of the second scanning signal.

[0097] The following is an illustrative introduction to the circuit structures of the gating module, output control module, and voltage stabilizing module in the waveform conversion unit. It should be noted that other circuit structures that can realize the functions of the gating module, output control module, and voltage stabilizing module are all within the protection scope of this application.

[0098] In some embodiments, Fig. 9As shown, the gating module 22 includes a first transistor M1 and a second transistor M2, the first electrode of the first transistor M1 and the first electrode of the second transistor M2 are connected to each other as the input end of the gating module 22, the second electrode of the first transistor M2 is electrically connected to the input end of the output control module 23, the second electrode of the second transistor M2 is electrically connected to the output end Nscan of the waveform conversion unit 20, and the gate of the first transistor M1 and the gate of the second transistor M2 are electrically connected to the output end of the first trigger unit 11. One of the first transistor M1 and the second transistor M2 is a P-type transistor, and the other is an N-type transistor.

[0099] For example, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor.

[0100] In an embodiment of the present application, the selection module is composed of two transistors of opposite types. The first transistor can be used as a first transmission path from the output end of the NAND gate circuit to the output end Nscan, and the second transistor can be used as a second transmission path from the output end of the NAND gate circuit to the output end Nscan, thereby facilitating the selective control of the output signal.

[0101] In some embodiments, Fig. 9 As shown, the output control module 23 includes a third transistor M3, a fourth transistor M4 and a first inverter 231. The gate of the third transistor M3 and the gate of the fourth transistor M4 are electrically connected to the output end of the first trigger unit 11, the first electrode of the third transistor M3 is electrically connected to the first power supply terminal PVGH1, the second electrode of the third transistor M3 is electrically connected to the first inverter 231, the first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal PVGL1, and the second electrode of the fourth transistor M4 is electrically connected to the first inverter 231; the input end of the first inverter 231 serves as the input end of the output control module 23, and the output end of the first inverter 231 serves as the output end of the output control module 23. The third transistor M3 and the fourth transistor M4 are of the same type. For example, the third transistor M3 and the fourth transistor M4 are P-type transistors.

[0102] The third transistor M3 and the fourth transistor M4 are used to transmit the voltage of the first A power supply terminal PVGH1 and the first B power supply terminal PVGL1 to the first inverter 231. When the third transistor M3 and the fourth transistor M4 are turned on, the first inverter 231 is in a working state. When the third transistor M3 and the fourth transistor M4 are turned off, the first inverter 231 is in a non-working state.

[0103] The third transistor M3 and the fourth transistor M4 together with the first inverter 231 form an inverter circuit with a control circuit. Whether the first inverter 231 can output a signal is controlled by the signal output by the first trigger unit 11.

[0104] For a clearer description of the working process of the output control module 23, please refer to Fig.10 The first inverter 231 includes a transistor M2311 and a transistor M2312, wherein the transistor M2311 is a P-type transistor and the transistor M2312 is an N-type transistor. In addition, the input terminal of the output control module 23 is marked as IN3, the output terminal is marked as OUT23, and the control terminal is marked as A, wherein the control terminal A is electrically connected to the output terminal of the first trigger unit 11. The connection relationship of each transistor in the output control module 23 is detailed in Fig.10 , I will not go into details here.

[0105] The working logic of the output control module 23 is shown in Table 2.

[0106] Table 2

[0107]

[0108] It can be seen that when the light-emitting control signal output by the first trigger unit 11 is a cut-off level (for example, a high level 1), the first inverter 231 is in a non-working state, and when the light-emitting control signal output by the first trigger unit 11 is a conduction level (for example, a low level 0), the first inverter 231 is in a working state, which can invert the input signal and then output it.

[0109] In some embodiments, Fig. 9 As shown, the voltage stabilizing module 24 includes a second inverter 242 and a third inverter 243 connected in series.

[0110] The second inverter 242 has the same structure as the third inverter 243, and the power supply terminals connected to the two are also the same. The input terminal of the second inverter 242 is connected to the output terminal of the first trigger unit 11, and the output terminal of the second inverter 242 is connected to the input terminal of the third inverter 243. The output terminal of the third inverter 243 serves as the output terminal of the voltage stabilizing module 24.

[0111] Exemplarily, the structures of the second inverter 242 and the third inverter 243 are as follows: Fig.11 As shown, the second inverter 242 and the third inverter 243 may include a transistor M2411 and a transistor M2412 , wherein the transistor M2411 is a P-type transistor and the transistor M2412 is an N-type transistor. Fig.11 Here, IN3 represents the input terminal of the inverter, and OUT24 represents the output terminal of the inverter.

[0112] The working logic of the second inverter 242 and the third inverter 243 is shown in Table 3.

[0113] Table 3

[0114] Input signal Output signal 0 1 1 0

[0115] In some embodiments, Fig. 9 As shown, the second inverter 242 and the third inverter 243 are electrically connected to the second power supply terminal A and the second power supply terminal B, the voltage of the second power supply terminal A is PVGH2, the voltage of the second power supply terminal B is PVGL2, the voltage of the first power supply terminal A is PVGH1, the voltage of the first power supply terminal B is PVGL1, and the threshold voltage of the N-type transistors in the second inverter 242 and the third inverter 243 is V th_igzo , the threshold voltage of the P-type transistors in the second inverter 242 and the third inverter 243 is V th_ltps ; Among them, PVGH2>PVGH+V th_igzo , PVGL2=PVGL+V th_ltps In this way, it is ensured that the signal output by the first trigger unit is stabilized at a high level and a low level.

[0116] The following combination Fig. 9 and Fig.12 , the working process of the gate drive circuit is introduced as a whole.

[0117] The working process of the gate drive circuit can be divided into the B0 stage, the B1 stage and the B2 stage, wherein in the B0 stage and the B2 stage, the EMA signal is at a low level, and the signal output by the NAND gate circuit 21 is transmitted to the output terminal Nscan through the first path described above, and the "AND logic" is executed. In the B1 stage, the EMA signal is at a high level, and the signal output by the NAND gate circuit 21 is transmitted to the output terminal Nscan through the second path described above, and the "AND logic" is executed. The output logic of the gate drive circuit is shown in Table 4.

[0118] Table 4

[0119]

[0120]

[0121] In some embodiments, the light emitting control signal output by the first trigger unit 11 can be used to drive multiple rows of pixels in the display panel. For example, the light emitting control signal output by the first trigger unit 11 is used to drive K rows of pixels in the display panel, where K≥2 and K is an integer. This can reduce the number of first trigger units, which is beneficial to narrow borders.

[0122] like Fig.13 As shown, a trigger unit 10 may include a first trigger unit 11 and K cascaded second trigger units 12, and K waveform conversion units 20. Fig.13K=2 is used as an example. The K waveform conversion units 20 are all electrically connected to the output end of the first trigger unit 11; the K cascaded second trigger units 12 are electrically connected to the K waveform conversion units 20 in a one-to-one correspondence. In addition, the K waveform conversion units 20 can share a voltage stabilizing module 24.

[0123] like Fig.13 , two cascaded second trigger units, the signal output by one second trigger unit is marked as Scan_P1, and the signal output by the other second trigger unit is marked as Scan_P2, two waveform conversion units, the output end of one waveform conversion unit is marked as Nscan1, and the output end of the other waveform conversion unit is marked as Nscan2, the output timing is as follows Fig.14 As shown, multiple waveform conversion units connected to the same first trigger unit can output multiple valid pulses.

[0124] The structures of the first trigger unit and the second trigger unit are exemplarily introduced below. It should be noted that other circuit structures that can realize the functions of the first trigger unit and the second trigger unit are within the protection scope of the present application.

[0125] As an example, Fig.15 As shown, the first trigger unit includes transistors T1 to T13 and capacitors C1 to C3, wherein the connection relationship of each device is detailed in Fig.15 , I will not go into details here. Fig.16 As shown, the first trigger unit can output a light emitting control signal EM.

[0126] As an example, Fig.17 As shown, the second trigger unit includes transistors T14 to T21 and capacitors C4 to C5, wherein the connection relationship of each device is detailed in Fig.17 , I will not go into details here. Fig.18 As shown, the second trigger unit can output a multi-pulse first scanning signal Scan_P.

[0127] In summary, each functional module in the gate drive circuit is composed of transistors, which can utilize the existing production process, thereby improving the picture quality of the display product without increasing costs or reducing production capacity.

[0128] Exemplarily, the P-type transistor in the gate driving circuit may be an LTPS transistor, and the N-type transistor may be an Indium Gallium Zinc Oxide (IGZO) transistor.

[0129] Based on the same inventive concept, an embodiment of the present application further provides a display panel. The display panel includes a pixel circuit and a gate driving circuit as described in any of the above embodiments. The gate driving circuit is electrically connected to the pixel circuit.

[0130] The display panel provided in the embodiment of the present application has the beneficial effects of the gate driving circuit described in any of the above embodiments, which will not be described one by one here.

[0131] In some embodiments, Figure 4 As shown, the pixel circuit includes a fifth transistor, a sixth transistor and a seventh transistor;

[0132] The gate of the fifth transistor is electrically connected to the output end of the first trigger unit, the gate of the sixth transistor is electrically connected to the output end of the second trigger unit, and the gate of the seventh transistor is electrically connected to the output end of the waveform conversion unit.

[0133] The pixel circuit includes a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7. The number of the fifth transistor M5 may be two. The pixel circuit also includes a driving transistor DT. The connection method of each transistor in the pixel circuit is shown in FIG. Figure 4 , I will not go into details here.

[0134] The gate of the fifth transistor M5 is connected to the light emitting control signal EM, the gate of the sixth transistor M6 is connected to the first scanning signal Scan_P, and the gate of the seventh transistor M7 is connected to the second scanning signal Scan_N.

[0135] It is understandable that the fifth transistor M5 and the sixth transistor M6 are P-type transistors, and the seventh transistor M7 is an N-type transistor. The pixel circuit is an LTPO type pixel circuit, and the first scan signal Scan_P and the second scan signal Scan_N are both multi-pulse signals, so that multiple data writing can be achieved to improve the problem of dark brightness in the first frame of the display panel.

[0136] It should be noted that some transistors in the embodiments of the present application are N-type transistors, and some transistors are P-type transistors. For N-type transistors, the on-level is a high level, and the off-level is a low level. That is, when the gate potential of the N-type transistor is a high level, the first pole and the second pole are connected, and when the gate potential of the N-type transistor is a low level, the first pole and the second pole are disconnected. For P-type transistors, the on-level is a low level, and the off-level is a high level. That is, when the gate potential of the P-type transistor is a low level, the first pole and the second pole are connected, and when the gate potential of the P-type transistor is a high level, the first pole and the second pole are disconnected.

[0137] In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, according to the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / shut down the transistor.

[0138] The electrical connection described in the present application may be a direct connection, that is, a connection between two components, or an indirect connection, that is, an indirect connection between two components may be formed through one or more elements.

[0139] The present application also provides a display device, including the display panel provided by the present application. Fig.19 , Fig.19 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.19 The provided display device 1000 includes the display panel 200 provided by any of the above embodiments of the present application, and the display panel 200 includes the gate driving circuit described in any of the above embodiments. Fig.19 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0140] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A gate drive circuit, characterized in that: include: A trigger unit, comprising a first trigger unit and a second trigger unit, wherein the first trigger unit is used to output a light emitting control signal, and the second trigger unit is used to output a first scanning signal, wherein the first scanning signal comprises a plurality of first effective pulses in at least one cut-off level period of the light emitting control signal, and the first effective pulses are used to control the conduction of a P-type transistor in a pixel circuit; A waveform conversion unit is electrically connected to the output end of the first trigger unit and the output end of the second trigger unit, and is used to output a second scanning signal under the control of the light-emitting control signal, wherein the second effective pulse of the second scanning signal is used to control the conduction of the N-type transistor in the pixel circuit, and the second scanning signal is inverted with the first scanning signal.

2. The gate driving circuit according to claim 1, characterized in that: The waveform conversion unit includes a NAND gate circuit, a gating module and an output control module; The first input end of the NAND gate circuit is electrically connected to the output end of the first trigger unit, the second input end of the NAND gate circuit is electrically connected to the output end of the second trigger unit, and the output end of the NAND gate circuit is electrically connected to the input end of the gating module; The control end of the gating module is electrically connected to the output end of the first trigger unit, and the output end of the gating module is electrically connected to the input end of the output control module and the output end of the waveform conversion unit. The gating module is used to selectively connect its input end to the input end of the output control module, or connect its input end to the output end of the waveform conversion unit under the control of the output signal of the first trigger unit; The control end of the output control module is electrically connected to the output end of the first trigger unit, and the output end of the output control module is electrically connected to the output end of the waveform conversion unit. The output control module is used to output the signal from the output end of the NAND gate circuit under the control of the output signal of the first trigger unit.

3. The gate driving circuit according to claim 2, characterized in that: The waveform conversion unit also includes a voltage stabilization module; The NAND gate circuit, the gating module and the output control module are all electrically connected to the output end of the first trigger unit through the voltage stabilizing module, and the voltage stabilizing module is used to stabilize the light emitting control signal to a high level and a low level.

4. The gate drive circuit according to claim 2 or 3, characterized in that: The gating module includes a first transistor and a second transistor, wherein the first electrode of the first transistor and the first electrode of the second transistor are connected to each other as the input end of the gating module, the second electrode of the first transistor is electrically connected to the input end of the output control module, the second electrode of the second transistor is electrically connected to the output end of the waveform conversion unit, and the gate of the first transistor and the gate of the second transistor are electrically connected to the output end of the first trigger unit; one of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor.

5. The gate drive circuit according to claim 2 or 3, characterized in that: The output control module includes a third transistor, a fourth transistor and a first inverter; The gate of the third transistor and the gate of the fourth transistor are electrically connected to the output terminal of the first trigger unit, the first electrode of the third transistor is electrically connected to the first power supply terminal A, the second electrode of the third transistor is electrically connected to the first inverter, the first electrode of the fourth transistor is electrically connected to the first power supply terminal B, and the second electrode of the fourth transistor is electrically connected to the first inverter; The input end of the first inverter serves as the input end of the output control module, and the output end of the first inverter serves as the output end of the output control module; The third transistor and the fourth transistor are of the same type.

6. The gate driving circuit according to claim 3, characterized in that: The voltage stabilizing module comprises a second inverter and a third inverter connected in series; Preferably, the second inverter and the third inverter are electrically connected to the second power supply terminal A and the second power supply terminal B, the voltage of the second power supply terminal A is PVGH2, the voltage of the second power supply terminal B is PVGL2, the voltage of the first power supply terminal A is PVGH1, the voltage of the first power supply terminal B is PVGL1, and the threshold voltage of the N-type transistor in the second inverter and the third inverter is V th_igzo , the threshold voltage of the P-type transistor in the second inverter and the third inverter is V th_ltps ; Among them, PVGH2>PVGH+V th_igzo , PVGL2=PVGL+V th_ltps .

7. The gate drive circuit according to any one of claims 1 to 3, characterized in that: The light emitting control signal output by the first trigger unit is used to drive K rows of pixels in the display panel, where K≥2. One of the trigger units includes one of the first trigger units, K cascaded second trigger units, and K waveform conversion units; The K waveform conversion units are all electrically connected to the output end of the first trigger unit; The K cascaded second trigger units are electrically connected to the K waveform conversion units in a one-to-one correspondence.

8. A display panel, characterized in that: include: Pixel circuit; And the gate drive circuit according to any one of claims 1 to 7; The gate driving circuit is electrically connected to the pixel circuit.

9. The display panel according to claim 8, characterized in that: The pixel circuit includes a fifth transistor, a sixth transistor and a seventh transistor; The gate of the fifth transistor is electrically connected to the output end of the first trigger unit, the gate of the sixth transistor is electrically connected to the output end of the second trigger unit, and the gate of the seventh transistor is electrically connected to the output end of the waveform conversion unit.

10. A display device, characterized in that: Comprising the display panel according to claim 8 or 9.

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