Gate driving circuit, display panel and display device

Abstract

The application discloses a gate driving circuit, a display panel and a display device. The gate driving circuit comprises a trigger unit, the trigger unit comprising a first trigger unit and a second trigger unit, the first trigger unit being configured to output a light-emitting control signal, and the second trigger unit being configured to output a first scanning signal, the first scanning signal comprising a plurality of first active pulses for turning on a control transistor during at least one off-level period of the light-emitting control signal; and a waveform conversion unit electrically connected to an output end of the first trigger unit and an output end of the second trigger unit, configured to output a second scanning signal under the control of the light-emitting control signal, the second scanning signal comprising a second active pulse for turning on the control transistor, and the second scanning signal being opposite to the first scanning signal. According to the embodiment of the application, the second scanning signal with multiple pulses can be outputted, and the display performance of the display product can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit, a display panel, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body, and wide application range, becoming the mainstream display device.

[0003] However, the display performance of current OLED display products needs to be improved. Summary of the Invention

[0004] The embodiments of the present application provide a gate drive circuit, a display panel, and a display device, which can output a multi-pulse second scanning signal, thereby improving the display performance of a display product.

[0005] In the first aspect, an embodiment of the present application provides a gate drive circuit, comprising: a trigger unit, comprising a first trigger unit and a second trigger unit, the first trigger unit being used to output a light-emitting control signal, the second trigger unit being used to output a first scan signal, and within at least one cut-off level period of the light-emitting control signal, the first scan signal comprises a plurality of first valid pulses, and the first valid pulse is used to control the conduction of a P-type transistor in a pixel circuit; a waveform conversion unit, electrically connected to the output end of the first trigger unit and the output end of the second trigger unit, and being used to output a second scan signal under the control of the light-emitting control signal, the second valid pulse of the second scan signal being used to control the conduction of an N-type transistor in the pixel circuit, and the second scan signal being inverted to the first scan signal.

[0006] In a possible implementation of the first aspect, the waveform conversion unit includes a NAND gate circuit, a gating module, and an output control module;

[0007] The first input terminal of the NAND gate circuit is electrically connected to the output terminal of the first trigger unit, the second input terminal of the NAND gate circuit is electrically connected to the output terminal of the second trigger unit, and the output terminal of the NAND gate circuit is electrically connected to the input terminal of the strobe module;

[0008] The control end of the gating module is electrically connected to the output end of the first trigger unit, and the output end of the gating module is electrically connected to the input end of the output control module and the output end of the waveform conversion unit. The gating module is used to selectively connect its input end to the input end of the output control module, or connect its input end to the output end of the waveform conversion unit under the control of the output signal of the first trigger unit;

[0009] The control end of the output control module is electrically connected to the output end of the first trigger unit, and the output end of the output control module is electrically connected to the output end of the waveform conversion unit. The output control module is used to output the signal from the output end of the NAND gate circuit under the control of the output signal of the first trigger unit.

[0010] In a possible implementation of the first aspect, the waveform conversion unit further includes a voltage stabilization module;

[0011] The NAND gate circuit, the strobe module and the output control module are all electrically connected to the output end of the first trigger unit through the voltage stabilizing module. The voltage stabilizing module is used to stabilize the light emitting control signal to a high level and a low level.

[0012] In a possible implementation of the first aspect, the gating module includes a first transistor and a second transistor, the first electrode of the first transistor and the first electrode of the second transistor are connected to each other as the input end of the gating module, the second electrode of the first transistor is electrically connected to the input end of the output control module, the second electrode of the second transistor is electrically connected to the output end of the waveform conversion unit, and the gate of the first transistor and the gate of the second transistor are electrically connected to the output end of the first trigger unit; one of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor.

[0013] In a possible implementation of the first aspect, the output control module includes a third transistor, a fourth transistor, and a first inverter;

[0014] The gate of the third transistor and the gate of the fourth transistor are electrically connected to the output terminal of the first trigger unit, the first electrode of the third transistor is electrically connected to the first power supply terminal A, the second electrode of the third transistor is electrically connected to the first inverter, the first electrode of the fourth transistor is electrically connected to the first power supply terminal B, and the second electrode of the fourth transistor is electrically connected to the first inverter;

[0015] The input end of the first inverter serves as the input end of the output control module, and the output end of the first inverter serves as the output end of the output control module;

[0016] The third transistor and the fourth transistor are of the same type.

[0017] In a possible implementation of the first aspect, the voltage stabilizing module includes a second inverter and a third inverter connected in series;

[0018] Preferably, the second inverter and the third inverter are electrically connected to the second power supply terminal A and the second power supply terminal B, the voltage of the second power supply terminal A is PVGH2, the voltage of the second power supply terminal B is PVGL2, the voltage of the first power supply terminal A is PVGH1, the voltage of the first power supply terminal B is PVGL1, and the threshold voltage of the N-type transistor in the second inverter and the third inverter is Vth_igzo The threshold voltage of the P-type transistor in the second inverter and the third inverter is V th_ltps ;

[0019] PVGH2>PVGH1+V th_igzo , and PVGL2=PVGL1+V th_ltps .

[0020] In a possible implementation manner of the first aspect, the light-emitting control signal output by the first trigger unit is used to drive K rows of pixels in the display panel, K≥2,

[0021] One trigger unit includes one first trigger unit and K cascaded second trigger units, and K waveform conversion units;

[0022] The K waveform conversion units are electrically connected with the output end of the first trigger unit;

[0023] The K cascaded second trigger units are electrically connected with the K waveform conversion units one by one.

[0024] Based on the same inventive concept, in a second aspect, the embodiments of the present application provide a display panel, comprising:

[0025] A pixel circuit;

[0026] and the gate drive circuit as described in any one of the embodiments of the first aspect;

[0027] The gate drive circuit is electrically connected with the pixel circuit.

[0028] In a possible implementation manner of the second aspect, the pixel circuit includes a fifth transistor, a sixth transistor and a seventh transistor;

[0029] The gate of the fifth transistor is electrically connected with the output end of the first trigger unit, the gate of the sixth transistor is electrically connected with the output end of the second trigger unit, and the gate of the seventh transistor is electrically connected with the output end of the waveform conversion unit.

[0030] Based on the same inventive concept, in a third aspect, the embodiments of the present application provide a display device, comprising the display panel as described in any one of the embodiments of the second aspect.

[0031] According to the gate drive circuit, the display panel and the display device provided by the embodiments of the present application, the waveform conversion unit directly performs inversion processing on the first scanning signal to obtain a second scanning signal with multiple second effective pulses, and the second scanning signal is used to control the N-type transistor, so that the write control of the LTPO type pixel circuit can be performed multiple times, thereby being conducive to improving the first frame brightness ratio of the LTPO type display panel.

[0032] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0034] Figure 1 A schematic diagram showing a characteristic curve of a transistor;

[0035] Figure 2 A schematic diagram showing the brightness of a display panel over multiple frames;

[0036] Figure 3 A schematic structural diagram of a gate drive circuit provided in an embodiment of the present application is shown;

[0037] Figure 4 A schematic structural diagram of a pixel circuit provided in an embodiment of the present application is shown;

[0038] Figure 5 A timing diagram showing an output signal of a gate drive circuit provided by an embodiment of the present application;

[0039] Figure 6 Another structural schematic diagram of a gate drive circuit provided in an embodiment of the present application is shown;

[0040] Figure 7 A schematic diagram showing a structure of a NAND gate circuit in a gate drive circuit provided in an embodiment of the present application is shown;

[0041] Figure 8 A timing diagram showing some signals of the gate drive circuit provided by an embodiment of the present application;

[0042] Figure 9 Another structural schematic diagram of the gate drive circuit provided in an embodiment of the present application is shown;

[0043] Figure 10 A schematic structural diagram of a first inverter in a gate drive circuit provided in an embodiment of the present application is shown;

[0044] Figure 11 A schematic structural diagram of an inverter of a voltage stabilizing module in a gate drive circuit provided in an embodiment of the present application is shown;

[0045] Figure 12A timing diagram of a gate drive circuit provided by an embodiment of the present application is shown;

[0046] Figure 13 Another structural schematic diagram of the gate drive circuit provided in an embodiment of the present application is shown;

[0047] Figure 14 Show Figure 13 A timing diagram of

[0048] Figure 15 A schematic structural diagram of a first trigger unit in a gate drive circuit provided in an embodiment of the present application is shown;

[0049] Figure 16 Show Figure 15 A timing diagram of

[0050] Figure 17 A schematic structural diagram of a second trigger unit in a gate drive circuit provided in an embodiment of the present application is shown;

[0051] Figure 18 Show Figure 17 A timing diagram of

[0052] Figure 19 A schematic structural diagram of a display device provided in an embodiment of the present application is shown.

[0053] Description of reference numerals:

[0054] 100. Gate drive circuit;

[0055] 10. Trigger unit;

[0056] 11. First trigger unit; 12. Second trigger unit;

[0057] 20. Waveform conversion unit;

[0058] 21. NAND gate circuit; 22. gating module; 23. output control module; 231. first inverter; 24. voltage stabilizing module; 242. second inverter; 243. third inverter;

[0059] 200. Display panel;

[0060] 1000. Display device. DETAILED DESCRIPTION

[0061] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0062] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0063] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0064] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0065] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0066] It will be apparent to those skilled in the art that various modifications and variations can be made to this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application may be combined with each other unless there is any inconsistency.

[0067] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0068] The display panel utilizes pixel circuits to drive light-emitting elements to emit light, and transistors in the pixel circuits are driven and controlled by gate drive circuits.

[0069] The pixel circuit includes a low-temperature polysilicon (LTPS) type pixel circuit. During operation, when the black screen turns to the white screen, the threshold voltage (Vth) of the thin film transistor in the LTPS type pixel circuit is affected by the bias voltage and temperature during the light-emitting process, causing a positive shift in the threshold voltage (Vth) of the thin film transistor. Figure 1 As shown, Figure 1 The dotted line in the middle represents the characteristic curve before Vth shift, and the solid line represents the characteristic curve after Vth forward shift. When the black screen turns to the white screen, the TFT working state before data is written (refer to Vgs1). It can be seen that the change in the characteristics of the thin film transistor causes the pixel charging rate in the display panel to increase, resulting in insufficient response of the display panel in the first frame, such as Figure 2 The display panel shown has dim brightness in the first frame.

[0070] A related solution is to use a scan driving circuit to output a multi-pulse scan signal (Scan) to improve the Vth offset, wherein the multi-pulse Scan signal is used to control the writing of data signals.

[0071] With the development of display technology, low-temperature polycrystalline oxide (LTPO) technology has emerged. In LTPO technology, pixel circuits include not only P-type transistors but also N-type transistors. However, LTPO pixel circuits are affected by existing circuit driving factors and cannot flexibly implement multi-pulse scanning signals to control the N-type transistors used for data signal writing. As a result, LTPO display panels still suffer from poor first-frame response.

[0072] Based on the above technical problems, the embodiments of the present application provide a gate driving circuit, a display panel and a display device, and the embodiments of the present application will be described below with reference to the accompanying drawings.

[0073] Figure 3 FIG. 1 shows a schematic diagram of a structure of a gate drive circuit provided in an embodiment of the present application. Figure 3 As shown, the gate driving circuit 100 provided in the embodiment of the present application includes a trigger unit 10 and a waveform conversion unit 20 .

[0074] The trigger unit 10 includes a first trigger unit 11 and a second trigger unit 12. The first trigger unit 11 is used to output a light-emitting control signal EM, and the second trigger unit 12 is used to output a first scan signal Scan_P. In at least one cut-off level period of the light-emitting control signal EM, the first scan signal Scan_P includes multiple first valid pulses. The first valid pulse Scan_P is used to control the conduction of the P-type transistor in the pixel circuit.

[0075] The waveform conversion unit 20 is electrically connected to the output end of the first trigger unit 11 and the output end of the second trigger unit 12, and is used to output the second scanning signal Scan_N under the control of the light-emitting control signal EM. The second effective pulse of the second scanning signal Scan_N is used to control the conduction of the N-type transistor in the pixel circuit. The second scanning signal Scan_N is inverted with the first scanning signal Scan_P.

[0076] It is understandable that the light emitting control signal EM can be used to control whether the pixels in the display panel emit light, the first scan signal Scan_P can be used to control the P-type transistor in the pixel circuit, and the second scan signal Scan_N can be used to control the N-type transistor in the pixel circuit.

[0077] As an example, Figure 4 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the pixel circuit includes a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7. The number of the fifth transistor M5 can be two. The pixel circuit also includes a driving transistor DT. The connection method of each transistor in the pixel circuit is shown in FIG. Figure 4 , I will not go into details here.

[0078] A gate of the fifth transistor M5 is connected to the light emitting control signal EM, a gate of the sixth transistor M6 is connected to the first scan signal Scan_P, and a gate of the seventh transistor M7 is connected to the second scan signal Scan_N.

[0079] The fifth transistor M5 can be used to control whether the pixel emits light, and the sixth transistor M6 and the seventh transistor M7 are used to control whether the data signal data is written into the gate of the driving transistor DT.

[0080] Figure 5 A timing diagram of the output signal of the gate drive circuit provided in an embodiment of the present application is shown. In the embodiments of the present application, the cut-off level of the light-emitting control signal EM is taken as an example as a high level and the conduction level is a low level. In addition, the first effective pulse of the first scanning signal Scan_P is used to control the conduction of the P type, and the first effective pulse of the first scanning signal Scan_P is a low-level pulse. The second effective pulse of the second scanning signal Scan_N is used to control the conduction of the N-type transistor, and the second effective pulse of the second scanning signal Scan_N is a high-level pulse. The second scanning signal Scan_N is inverted with the first scanning signal Scan_P. It can be seen that the number of the second effective pulses is the same as the number of the first effective pulses. As shown in FIG. Figure 5 As shown, during the period when the light emitting control signal EM is at a high level, the first scan signal Scan_P includes three first effective pulses at a low level, and the second scan signal Scan_N includes three second effective pulses at a high level.

[0081] According to the gate drive circuit provided in the embodiment of the present application, the waveform conversion unit directly inverts the first scanning signal to obtain a second scanning signal having multiple second valid pulses. The second scanning signal is used to control the N-type transistor, thereby realizing multiple data signal writing control on the LTPO type pixel circuit, which is beneficial to improving the first frame brightness ratio of the LTPO type display panel.

[0082] For example, the first trigger unit and the second trigger unit can employ existing circuit structures (which will be exemplified below). Specifically, the existing light-emission control signal and the first scan signal are used as trigger signals. This eliminates the need for additional trigger signal circuitry, saves screen frame space, is easy to implement, and helps reduce costs without sacrificing production capacity. Furthermore, during the display panel's display driving process, the second scan signal follows the first scan signal, facilitating control of the effective pulse width and number of the scan signal during the display process.

[0083] The circuit structure of the waveform conversion unit is exemplarily introduced below. It should be noted that other circuit structures that can realize the functions of the waveform conversion unit are within the protection scope of this application.

[0084] In some embodiments, as Figure 6 As shown, the waveform conversion unit 20 includes a NAND gate circuit 21 , a gating module 22 and an output control module 23 .

[0085] The first input terminal of the NAND gate circuit 21 is electrically connected to the output terminal of the first trigger unit 11 , the second input terminal of the NAND gate circuit 21 is electrically connected to the output terminal of the second trigger unit 12 , and the output terminal of the NAND gate circuit 21 is electrically connected to the input terminal of the strobe module 22 .

[0086] The control end of the gating module 22 is electrically connected to the output end of the first trigger unit 11, and the output end of the gating module 22 is electrically connected to the input end of the output control module 23 and the output end Nscan of the waveform conversion unit 20. The gating module 22 is used to selectively connect its input end and the input end of the output control module 23, or to connect its input end and the output end of the waveform conversion unit 20 under the control of the output signal of the first trigger unit 11.

[0087] The control end of the output control module 23 is electrically connected to the output end of the first trigger unit 11, and the output end of the output control module 23 is electrically connected to the output end Nscan of the waveform conversion unit 20. The output control module 23 is used to output the signal from the output end of the NAND gate circuit 21 under the control of the output signal of the first trigger unit 11.

[0088] It can be understood that the signal output from the output terminal Nscan of the waveform conversion unit 20 comes from the output terminal of the NAND gate circuit 21, and the selection module 22 can control the signal output path from the output terminal of the NAND gate circuit 21 to the output terminal Nscan of the waveform conversion unit 20, wherein the first path is: the signal output from the output terminal of the NAND gate circuit 21 passes through the selection module 22, the input terminal of the output control module 23, and the output terminal of the output control module 23 to reach the output terminal Nscan of the waveform conversion unit 20; the second set of paths is: the signal output from the output terminal of the NAND gate circuit 21 passes through the selection module 22 and then reaches the output terminal Nscan of the waveform conversion unit 20.

[0089] The two input terminals of the NAND gate circuit 21 are connected to the output terminals of the first trigger unit 11 and the second trigger unit 12 respectively. Figure 7 As shown, the NAND gate circuit 21 includes transistors M211 to M214, where transistors M211 and M212 are P-type transistors, and transistors M213 and M214 are N-type transistors. The first input terminal IN1 of the NAND gate circuit 21 is electrically connected to the output terminal of the first trigger unit 11, and the second input terminal IN2 of the NAND gate circuit 21 is electrically connected to the output terminal of the second trigger unit 12. The output terminal of the NAND gate circuit 21 is marked as OUT21. The working logic of the NAND gate circuit 21 is shown in Table 1. It should be noted that in the various working logic tables of this application, 0 represents a low level and 1 represents a high level.

[0090] Table 1

[0091]

[0092] As can be seen, when the light-emission control signal output by the first trigger unit 11 is at a cutoff level (e.g., high level 1), the NAND gate circuit 21 can output a signal that is inversely proportional to the first scanning signal (the signal input to IN2). This facilitates the second scanning signal ultimately output by the waveform conversion unit to have multiple second valid pulses.

[0093] The first trigger unit 11 is used to output a light emitting control signal EM, such as Figure 8 As shown, the inventors have found that in the related art, the working process of the first trigger unit 11 includes the Ta stage and the Tb stage. In the Ta stage, the first trigger unit 11 outputs a stable cutoff level (for example, a high level). In the Tb stage (which can be understood as an intermediate state stage), the output voltage of the first trigger unit 11 is not stable.

[0094] Regarding the above technical issues, in some optional embodiments, please refer to Figure 6 The waveform conversion unit 20 may further include a voltage stabilizing module 24; the NAND gate circuit 21, the selection module 22 and the output control module 23 are all electrically connected to the output end of the first trigger unit 11 through the voltage stabilizing module 24, and the voltage stabilizing module 11 is used to stabilize the output signal of the first trigger unit 11 to a high level and a low level.

[0095] Please continue to refer to Figure 8 , Figure 8 The signal output by the voltage stabilizing module 11 is marked as EMA. For example, in the Tb stage, the voltage stabilizing module can stabilize the unstable voltage into a high voltage.

[0096] In the embodiment of the present application, by providing a voltage stabilizing module 24, the signal output by the first trigger unit can be stabilized to a high level and a low level, avoiding an unstable level in the Tb stage, thereby improving the stability of the second scanning signal.

[0097] The following is an illustrative introduction to the circuit structures of the gating module, output control module, and voltage stabilization module in the waveform conversion unit. It should be noted that other circuit structures that can realize the functions of the gating module, output control module, and voltage stabilization module are all within the scope of protection of this application.

[0098] In some embodiments, as Figure 9As shown, the gating module 22 includes a first transistor M1 and a second transistor M2. The first electrode of the first transistor M1 and the first electrode of the second transistor M2 are connected to each other as the input terminal of the gating module 22. The second electrode of the first transistor M2 is electrically connected to the input terminal of the output control module 23. The second electrode of the second transistor M2 is electrically connected to the output terminal Nscan of the waveform conversion unit 20. The gate of the first transistor M1 and the gate of the second transistor M2 are electrically connected to the output terminal of the first trigger unit 11. One of the first transistor M1 and the second transistor M2 is a P-type transistor, and the other is an N-type transistor.

[0099] For example, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor.

[0100] In an embodiment of the present application, the selection module is composed of two transistors of opposite types. The first transistor can serve as a first transmission path from the output end of the NAND gate circuit to the output end Nscan, and the second transistor can serve as a second transmission path from the output end of the NAND gate circuit to the output end Nscan, thereby facilitating the selective control of the output signal.

[0101] In some embodiments, as Figure 9 As shown, the output control module 23 includes a third transistor M3, a fourth transistor M4, and a first inverter 231. The gates of the third transistor M3 and the fourth transistor M4 are electrically connected to the output terminal of the first trigger unit 11. The first electrode of the third transistor M3 is electrically connected to the first power supply terminal PVGH1, the second electrode of the third transistor M3 is electrically connected to the first inverter 231, the first electrode of the fourth transistor M4 is electrically connected to the first power supply terminal PVGL1, and the second electrode of the fourth transistor M4 is electrically connected to the first inverter 231. The input terminal of the first inverter 231 serves as the input terminal of the output control module 23, and the output terminal of the first inverter 231 serves as the output terminal of the output control module 23. The third transistor M3 and the fourth transistor M4 are of the same type. For example, the third transistor M3 and the fourth transistor M4 are P-type transistors.

[0102] The third transistor M3 and the fourth transistor M4 are used to transmit the voltage of the first power supply terminal PVGH1 and the first power supply terminal PVGL1 to the first inverter 231. When the third transistor M3 and the fourth transistor M4 are turned on, the first inverter 231 is in an operating state. When the third transistor M3 and the fourth transistor M4 are turned off, the first inverter 231 is in a non-operating state.

[0103] The third transistor M3 and the fourth transistor M4 together with the first inverter 231 form an inverter circuit with a control circuit. Whether the first inverter 231 can output a signal is controlled by the signal output by the first trigger unit 11.

[0104] To more clearly explain the working process of the output control module 23, please refer to Figure 10 The first inverter 231 includes a transistor M2311 and a transistor M2312. The transistor M2311 is a P-type transistor and the transistor M2312 is an N-type transistor. In addition, the input terminal of the output control module 23 is marked as IN3, the output terminal is marked as OUT23, and the control terminal is marked as A. The control terminal A is electrically connected to the output terminal of the first trigger unit 11. The connection relationship of each transistor in the output control module 23 is detailed in Figure 10 , I will not go into details here.

[0105] The working logic of the output control module 23 is shown in Table 2.

[0106] Table 2

[0107]

[0108] It can be seen that when the light-emitting control signal output by the first trigger unit 11 is at the cut-off level (for example, high level 1), the first inverter 231 is in a non-working state. When the light-emitting control signal output by the first trigger unit 11 is at the on-level (for example, low level 0), the first inverter 231 is in a working state, which can invert the input signal and then output it.

[0109] In some embodiments, as Figure 9 As shown, the voltage stabilizing module 24 includes a second inverter 242 and a third inverter 243 connected in series.

[0110] The second inverter 242 and the third inverter 243 have the same structure and are connected to the same power supply terminal. The input of the second inverter 242 is connected to the output of the first trigger unit 11, and the output of the second inverter 242 is connected to the input of the third inverter 243. The output of the third inverter 243 serves as the output of the voltage regulator module 24.

[0111] For example, the structures of the second inverter 242 and the third inverter 243 are as follows: Figure 11 As shown, the second inverter 242 and the third inverter 243 may include a transistor M2411 and a transistor M2412 , wherein the transistor M2411 is a P-type transistor and the transistor M2412 is an N-type transistor. Figure 11 Here, IN3 represents the input terminal of the inverter, and OUT24 represents the output terminal of the inverter.

[0112] The operating logic of the second inverter 242 and the third inverter 243 is shown in Table 3.

[0113] Table 3

[0114]

[0115] In some embodiments, as Figure 9 As shown, the second inverter 242 and the third inverter 243 are electrically connected to the second power supply terminal A and the second power supply terminal B. The voltage of the second power supply terminal A is PVGH2, the voltage of the second power supply terminal B is PVGL2, the voltage of the first power supply terminal A is PVGH1, the voltage of the first power supply terminal B is PVGL1, and the threshold voltage of the N-type transistors in the second inverter 242 and the third inverter 243 is V th_igzo , the threshold voltage of the P-type transistors in the second inverter 242 and the third inverter 243 is V th_ltps ; Among them, PVGH2>PVGH1+V th_igzo PVGL2=PVGL1+V th_ltps In this way, it is ensured that the signal output by the first trigger unit is stabilized at a high level and a low level.

[0116] The following combination Figure 9 and Figure 12 , which generally introduces the working process of the gate drive circuit.

[0117] The gate drive circuit's operating process can be divided into phases B0, B1, and B2. During phases B0 and B2, the EMA signal is low, and the signal output by the NAND gate circuit 21 is transmitted to the output terminal Nscan via the first path described above, executing an AND logic. During phase B1, the EMA signal is high, and the signal output by the NAND gate circuit 21 is transmitted to the output terminal Nscan via the second path described above, executing an AND logic. The output logic of the gate drive circuit is shown in Table 4.

[0118] Table 4

[0119]

[0120] In some embodiments, the light-emitting control signal output by the first trigger unit 11 can be used to drive multiple rows of pixels in the display panel. For example, the light-emitting control signal output by the first trigger unit 11 can be used to drive K rows of pixels in the display panel, where K ≥ 2 and K is an integer. This can reduce the number of first trigger units and facilitate a narrow bezel.

[0121] like Figure 13 As shown, a trigger unit 10 may include a first trigger unit 11 and K cascaded second trigger units 12, and K waveform conversion units 20. Figure 13 K = 2 is used as an example. Each of the K waveform conversion units 20 is electrically connected to the output of the first trigger unit 11; the K cascaded second trigger units 12 are electrically connected to the K waveform conversion units 20 in a one-to-one correspondence. Furthermore, the K waveform conversion units 20 can share a single voltage stabilization module 24.

[0122] As shown in Figure 13 , two second trigger units are cascaded, a signal output by one second trigger unit is marked as Scan_P1, a signal output by the other second trigger unit is marked as Scan_P2, two waveform conversion units, an output end of one waveform conversion unit is marked as Nscan1, and an output end of the other waveform conversion unit is marked as Nscan2, and output timing is as shown in Figure 14 , multiple valid pulses can be output by multiple waveform conversion units connected to the same first trigger unit.

[0123] The structure of the first trigger unit and the second trigger unit is described below by way of example. It should be noted that other circuit structures capable of achieving the functions of the first trigger unit and the second trigger unit are within the scope of the present application.

[0124] As an example, as shown in Figure 15 , the first trigger unit includes transistors T1-T13 and capacitors C1-C3, and the connection relationship of each device is shown in Figure 15 , which will not be described again here. As shown in Figure 16 , the first trigger unit can output a light-emitting control signal EM.

[0125] As an example, as shown in Figure 17 , the second trigger unit includes transistors T14-T21 and capacitors C4-C5, and the connection relationship of each device is shown in Figure 17 , which will not be described again here. As shown in Figure 18 , the second trigger unit can output a first scanning signal Scan_P with multiple pulses.

[0126] In summary, each functional module in the gate drive circuit is composed of a transistor, so that the existing production process can be used, thereby improving the picture quality of the display product without increasing the cost and reducing the production capacity.

[0127] By way of example, the P-type transistor in the gate drive circuit can be an LTPS transistor, and the N-type transistor can be an Indium Gallium Zinc Oxide (IGZO) transistor.

[0128] Based on the same inventive concept, the present application also provides a display panel. The display panel includes a pixel circuit and a gate drive circuit as described in any of the above embodiments. The gate drive circuit is electrically connected to the pixel circuit.

[0129] The display panel provided by the embodiments of the present application has the beneficial effects of the gate drive circuit described in any of the above embodiments, which will not be described again.

[0130] In some embodiments, as Figure 4 As shown, the pixel circuit includes a fifth transistor, a sixth transistor and a seventh transistor;

[0131] The gate of the fifth transistor is electrically connected to the output end of the first trigger unit, the gate of the sixth transistor is electrically connected to the output end of the second trigger unit, and the gate of the seventh transistor is electrically connected to the output end of the waveform conversion unit.

[0132] The pixel circuit includes a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7. The number of the fifth transistor M5 can be two. The pixel circuit also includes a driving transistor DT. The connection method of each transistor in the pixel circuit is shown in FIG. Figure 4 , I will not go into details here.

[0133] A gate of the fifth transistor M5 is connected to the light emitting control signal EM, a gate of the sixth transistor M6 is connected to the first scan signal Scan_P, and a gate of the seventh transistor M7 is connected to the second scan signal Scan_N.

[0134] It is understood that the fifth transistor M5 and the sixth transistor M6 are P-type transistors, and the seventh transistor M7 is an N-type transistor. This pixel circuit is an LTPO type pixel circuit, and the first scan signal Scan_P and the second scan signal Scan_N are both multi-pulse signals, which can achieve multiple data writes to improve the problem of dim brightness in the first frame of the display panel.

[0135] It should be noted that some transistors in the embodiments of the present application are N-type transistors, and some transistors are P-type transistors. For N-type transistors, the on-level is a high level, and the off-level is a low level. That is, when the gate potential of the N-type transistor is a high level, the first and second poles are connected, and when the gate potential of the N-type transistor is a low level, the first and second poles are disconnected. For P-type transistors, the on-level is a low level, and the off-level is a high level. That is, when the gate potential of the P-type transistor is a low level, the first and second poles are connected, and when the gate potential of the P-type transistor is a high level, the first and second poles are disconnected.

[0136] In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, depending on the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor.

[0137] The electrical connection described in the present application can be a direct connection, i.e. a connection between two components, or an indirect connection, i.e. an indirect connection between two components through one or more elements.

[0138] The present application also provides a display device comprising the display panel provided by the present application. Please refer to Figure 19 , Figure 19 is a structural schematic diagram of a display device provided by an embodiment of the present application. Figure 19 The display device 1000 provided by the present application comprises the display panel 200 provided by any of the above embodiments of the present application, and the display panel 200 comprises the gate drive circuit described in any of the above embodiments. Figure 19 The embodiment only takes a mobile phone as an example to describe the display device 1000, and it can be understood that the display device provided by the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with display functions, and the present application does not specifically limit this. The display device provided by the embodiments of the present application has the beneficial effects of the display panel provided by the embodiments of the present application, and specific descriptions can be referred to the specific descriptions of the display panel in the above embodiments, which will not be described here.

[0139] According to the embodiments of the present application as described above, these embodiments do not describe all the details, nor limit the present application to only the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A gate drive circuit, characterized in that: include: a trigger unit comprising a first trigger unit and a second trigger unit, wherein the first trigger unit is configured to output a light-emitting control signal, and the second trigger unit is configured to output a first scanning signal, wherein the first scanning signal includes a plurality of first effective pulses during at least one off-level period of the light-emitting control signal, and the first effective pulses are configured to control the conduction of a P-type transistor in a pixel circuit; A waveform conversion unit is electrically connected to the output end of the first trigger unit and the output end of the second trigger unit, and is used to output a second scanning signal under the control of the light-emitting control signal, wherein the second effective pulse of the second scanning signal is used to control the conduction of the N-type transistor in the pixel circuit, and the second scanning signal is inverted with respect to the first scanning signal.

2. The gate drive circuit according to claim 1, wherein: The waveform conversion unit includes a NAND gate circuit, a gating module and an output control module; The first input terminal of the NAND gate circuit is electrically connected to the output terminal of the first trigger unit, the second input terminal of the NAND gate circuit is electrically connected to the output terminal of the second trigger unit, and the output terminal of the NAND gate circuit is electrically connected to the input terminal of the gating module; The control end of the gating module is electrically connected to the output end of the first trigger unit, and the output end of the gating module is electrically connected to the input end of the output control module and the output end of the waveform conversion unit. The gating module is used to selectively connect its input end to the input end of the output control module, or connect its input end to the output end of the waveform conversion unit under the control of the output signal of the first trigger unit; The control end of the output control module is electrically connected to the output end of the first trigger unit, and the output end of the output control module is electrically connected to the output end of the waveform conversion unit. The output control module is used to output the signal from the output end of the NAND gate circuit under the control of the output signal of the first trigger unit.

3. The gate drive circuit according to claim 2, wherein: The waveform conversion unit also includes a voltage stabilization module; The NAND gate circuit, the strobe module and the output control module are all electrically connected to the output end of the first trigger unit through the voltage stabilizing module. The voltage stabilizing module is used to stabilize the light emitting control signal to a high level and a low level.

4. The gate drive circuit according to claim 2 or 3, characterized in that: The gating module includes a first transistor and a second transistor, the first electrode of the first transistor and the first electrode of the second transistor are connected to each other as the input end of the gating module, the second electrode of the first transistor is electrically connected to the input end of the output control module, the second electrode of the second transistor is electrically connected to the output end of the waveform conversion unit, and the gate of the first transistor and the gate of the second transistor are electrically connected to the output end of the first trigger unit; one of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor.

5. The gate drive circuit according to claim 2 or 3, characterized in that: The output control module includes a third transistor, a fourth transistor and a first inverter; The gate of the third transistor and the gate of the fourth transistor are electrically connected to the output terminal of the first trigger unit, the first electrode of the third transistor is electrically connected to the first power supply terminal A, the second electrode of the third transistor is electrically connected to the first inverter, the first electrode of the fourth transistor is electrically connected to the first power supply terminal B, and the second electrode of the fourth transistor is electrically connected to the first inverter; The input end of the first inverter serves as the input end of the output control module, and the output end of the first inverter serves as the output end of the output control module; The third transistor and the fourth transistor are of the same type.

6. The gate driving circuit according to claim 3, wherein: The voltage stabilizing module includes a second inverter and a third inverter connected in series.

7. The gate driving circuit according to claim 6, wherein: The second inverter and the third inverter are electrically connected to the second power supply terminal A and the second power supply terminal B. The voltage of the second power supply terminal A is PVGH2, the voltage of the second power supply terminal B is PVGL2, the voltage of the first power supply terminal A is PVGH1, the voltage of the first power supply terminal B is PVGL1, and the threshold voltage of the N-type transistors in the second inverter and the third inverter is V th_igzo , the threshold voltage of the P-type transistors in the second inverter and the third inverter is V th_ltps ; Among them, PVGH2>PVGH1+V th_igzo PVGL2=PVGL1+V th_ltps .

8. The gate drive circuit according to any one of claims 1 to 3, characterized in that: The light emitting control signal output by the first trigger unit is used to drive K rows of pixels in the display panel, where K≥2. One of the trigger units includes one of the first trigger units, K cascaded second trigger units, and K waveform conversion units; The K waveform conversion units are all electrically connected to the output end of the first trigger unit; The K cascaded second trigger units are electrically connected to the K waveform conversion units in a one-to-one correspondence.

9. A display panel, characterized in that: include: pixel circuit; and the gate drive circuit according to any one of claims 1 to 8; The gate driving circuit is electrically connected to the pixel circuit.

10. The display panel according to claim 9, wherein: The pixel circuit includes a fifth transistor, a sixth transistor and a seventh transistor; The gate of the fifth transistor is electrically connected to the output end of the first trigger unit, the gate of the sixth transistor is electrically connected to the output end of the second trigger unit, and the gate of the seventh transistor is electrically connected to the output end of the waveform conversion unit.

11. A display device, characterized in that: The device comprises a display panel according to claim 9 or 10.

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