Display substrate, testing method thereof and display device

Abstract

The invention provides a display substrate, a testing method thereof and a display device. The display substrate has a display area and a peripheral area arranged around the display area, and includes: a plurality of gate lines extending in a first direction; a plurality of data lines extending in a second direction; the at least two driving circuits are located in the peripheral area and are configured to provide gate driving signals and source driving signals for a plurality of pixel driving circuits which are located in the display area and are arranged in an array mode through a plurality of gate lines and a plurality of data lines, and the pixel driving circuits comprise a plurality of rows and a plurality of columns; one or more test signal lines located in the peripheral area and extending to a side opposite to a respective one of the at least two driving circuits, each test signal line including a plurality of branches at a point of the side, each branch extending from the point to connect to the respective pixel driving circuit, therefore, a test signal is provided for the corresponding pixel driving circuit in an inspection test process. And at least one test signal terminal configured to provide a test signal to one or more test signal lines.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a testing method thereof, and a display device. Background Art

[0002] As the size of display screens becomes larger and the cost of module back-end materials becomes higher, it is particularly important to intercept defective products in advance to avoid wasting materials in the back-end modules, thereby saving costs. However, as the screen size increases, the space required for the switch transistor (SW TFT) and its signal line for inspection and testing (cell test) also gradually increases, resulting in the conventional design under the integrated circuit (IC) no longer being able to meet the design requirements. If it is forced to be placed on the side where the integrated circuit is located, the space on that side will increase, and the screen border will increase. This is obviously contrary to the existing design concept of pursuing a narrow border and does not meet the needs of the public. Summary of the invention

[0003] In a first aspect, the present disclosure provides a display substrate having a display area and a peripheral area arranged around the display area, and comprising: a plurality of gate lines extending along a first direction; a plurality of data lines extending along a second direction; at least two driving circuits located in the peripheral area and configured to provide gate driving signals and source driving signals to a plurality of pixel driving circuits arranged in an array including a plurality of rows and columns located in the display area through the plurality of gate lines and the plurality of data lines, respectively; one or more test signal lines located in the peripheral area and extending to a side opposite to a corresponding driving circuit of the at least two driving circuits, each test signal line comprising a plurality of branches at a point on the side, each branch extending from the point to be connected to a corresponding pixel driving circuit, thereby providing a test signal to the corresponding pixel driving circuit during an inspection test; and at least one test signal terminal configured to provide the test signal to the one or more test signal lines.

[0004] In some embodiments of the present disclosure, the peripheral area includes a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, wherein the first side connects the third side and the fourth side, and the second side connects the third side and the fourth side; and the peripheral area includes a first corner located between the first side and the fourth side, a second corner located between the second side and the fourth side, a third corner located between the second side and the third side, and a fourth corner located between the first side and the third side.

[0005] In some embodiments of the present disclosure, the at least two driving circuits include a source driving circuit, which is located on the first side of the peripheral area and is configured to provide the source driving signal to the pixel driving circuit in the same column located in the display area through the corresponding data line; the at least one test signal terminal includes a first test signal terminal, which is arranged at a position of the source driving circuit on the first side of the peripheral area close to the first corner; and a second test signal terminal, which is arranged at a position of the source driving circuit on the first side of the peripheral area close to the first corner; the one or more test signal lines include a first test signal line and a second test signal line; one end of the first test signal line is connected to the first test signal terminal, and a second test signal line is connected from the first test signal terminal along the The fourth side extends from the first corner to the second corner, and extends along the second side from the second corner to a first point on the second side of the peripheral area; one end of the second test signal line is connected to the second test signal end, and extends from the second test signal end from the first corner to the second corner along the fourth side, and extends along the second side from the second corner to a second point on the second side of the peripheral area; the first test signal line is configured to provide a first test signal from the first test signal end to the odd-column pixel driving circuit during an inspection test; and the second test signal line is configured to provide a second test signal from the second test signal end to the even-column pixel driving circuit during an inspection test.

[0006] In some embodiments of the present disclosure, the first test signal line is divided into a plurality of branches at the first point located on the second side of the peripheral area, and each branch is connected to a corresponding data line to provide the first test signal to the same odd-numbered column pixel driving circuit during the inspection test; and the second test signal line is divided into a plurality of branches at the second point located on the second side of the peripheral area, and each branch is connected to a corresponding data line to provide the second test signal to the same even-numbered column pixel driving circuit during the inspection test.

[0007] In some embodiments of the present disclosure, the data line connected to each branch of the first test signal line provides the first test signal from the first test signal terminal and the source drive signal from the source drive circuit to the same odd-numbered column pixel drive circuit; and the data line connected to each branch of the second test signal line provides the second test signal from the second test signal terminal and the source drive signal from the source drive circuit to the same even-numbered column pixel drive circuit.

[0008] In some embodiments of the present disclosure, all odd-numbered column pixel driving circuits are arranged in a mirror-symmetrical manner with respect to a straight line passing through the first point and perpendicular to the first side and the second side; and all even-numbered column pixel driving circuits are arranged in a mirror-symmetrical manner with respect to a straight line passing through the second point and perpendicular to the first side and the second side.

[0009] In some embodiments of the present disclosure, the display substrate includes a plurality of sub-pixels arranged in an array including a plurality of rows and columns located in the display area, and the plurality of sub-pixels are arranged in a one-to-one correspondence with the plurality of pixel driving circuits; the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; the at least two driving circuits include a source driving circuit, which is located on the first side of the peripheral area and is configured to provide the source driving signal to the pixel driving circuit in the same column located in the display area through a corresponding data line; the at least one test signal terminal includes a first sub-pixel test signal terminal, which is arranged near the source driving circuit on the first side of the peripheral area The first corner portion; a second sub-pixel test signal terminal, which is arranged at a position of the source driving circuit on the first side of the peripheral area close to the first corner portion; and a third sub-pixel test signal terminal, which is arranged at a position of the source driving circuit on the first side of the peripheral area close to the first corner portion; the one or more test signal lines include a first sub-pixel test signal line, a second sub-pixel test signal line and a third sub-pixel test signal line; one end of the first sub-pixel test signal line is connected to the first sub-pixel test signal terminal, and extends from the first sub-pixel test signal terminal along the fourth side from the first corner portion to the second corner portion, and along The second side extends from the second corner to a first point located on the second side of the peripheral area; one end of the second sub-pixel test signal line is connected to the second sub-pixel test signal end, and extends from the second sub-pixel test signal end along the fourth side from the first corner to the second corner, and extends from the second corner along the second side to a second point located on the second side of the peripheral area; one end of the third sub-pixel test signal line is connected to the third sub-pixel test signal end, and extends from the third sub-pixel test signal end along the fourth side from the first corner to the second corner, and extends from the second corner along the second side to a third point located on the second side of the peripheral area; the first sub-pixel test signal line is configured to provide a first test signal from the first sub-pixel test signal end to all column pixel drive circuits corresponding to the first sub-pixel during an inspection test; the second sub-pixel test signal line is configured to provide a second test signal from the second sub-pixel test signal end to all column pixel drive circuits corresponding to the second sub-pixel during an inspection test; and the third sub-pixel test signal line is configured to provide a third test signal from the third sub-pixel test signal end to all column pixel drive circuits corresponding to the third sub-pixel during an inspection test.

[0010] In some embodiments of the present disclosure, the first sub-pixel test signal line is divided into a plurality of branches at the first point located on the second side of the peripheral area, each branch being connected to a corresponding data line, so as to provide the first test signal from the first sub-pixel test signal terminal to the corresponding column of pixel driving circuits corresponding to the first sub-pixel during the inspection test; the second sub-pixel test signal line is divided into a plurality of branches at the second point located on the second side of the peripheral area, each branch being connected to a corresponding data line, so as to provide the second test signal from the second sub-pixel test signal terminal to the corresponding column of pixel driving circuits corresponding to the second sub-pixel during the inspection test; and the third sub-pixel test signal line is divided into a plurality of branches at the third point located on the second side of the peripheral area, each branch being connected to a corresponding data line, so as to provide the third test signal from the third sub-pixel test signal terminal to the corresponding column of pixel driving circuits corresponding to the third sub-pixel during the inspection test.

[0011] In some embodiments of the present disclosure, the data line connected to each branch of the first sub-pixel test signal line provides the first test signal from the first sub-pixel test signal terminal and the source drive signal from the source drive circuit to a corresponding column of pixel drive circuits corresponding to the first sub-pixel; the data line connected to each branch of the second sub-pixel test signal line provides the second test signal from the second sub-pixel test signal terminal and the source drive signal from the source drive circuit to a corresponding column of pixel drive circuits corresponding to the second sub-pixel; and the data line connected to each branch of the third sub-pixel test signal line provides the third test signal from the third sub-pixel test signal terminal and the source drive signal from the source drive circuit to a corresponding column of pixel drive circuits corresponding to the third sub-pixel.

[0012] In some embodiments of the present disclosure, all column pixel driving circuits corresponding to the first sub-pixel are arranged in mirror symmetry with respect to a straight line passing through the first point and perpendicular to the first side and the second side; all column pixel driving circuits corresponding to the second sub-pixel are arranged in mirror symmetry with respect to a straight line passing through the second point and perpendicular to the first side and the second side; and all column pixel driving circuits corresponding to the third sub-pixel are arranged in mirror symmetry with respect to a straight line passing through the third point and perpendicular to the first side and the second side.

[0013] In some embodiments of the present disclosure, the at least two driving circuits include a gate driving circuit, which is located on the third side of the peripheral area and is configured to provide the gate driving signal to the pixel driving circuit in the same row located in the display area through the corresponding gate line; the at least one test signal terminal includes a first test signal terminal, which is arranged at a position of the gate driving circuit on the first side of the peripheral area close to the third corner; and a second test signal terminal, which is arranged at a position of the gate driving circuit on the first side of the peripheral area close to the third corner; the one or more test signal lines include a first test signal line and a second test signal line; one end of the first test signal line is connected to the first test signal terminal, and a second test signal line is transmitted from the first test signal terminal along the first test signal terminal. The second test signal line extends from the third corner to the second corner along the second side, and extends from the second corner to a first point on the fourth side of the peripheral area along the fourth side; one end of the second test signal line is connected to the second test signal end, and extends from the second test signal end along the second side from the third corner to the second corner, and extends from the second corner to a second point on the fourth side of the peripheral area along the fourth side; the first test signal line is configured to provide a first test signal from the first test signal end to the odd-row pixel driving circuit during the inspection test; and the second test signal line is configured to provide a second test signal from the second test signal end to the even-row pixel driving circuit during the inspection test.

[0014] In some embodiments of the present disclosure, the first test signal line is divided into a plurality of branches at the first point located on the fourth side of the peripheral area, and each branch is connected to a corresponding gate line to provide the first test signal to the same odd-numbered row pixel driving circuit during the inspection test; and the second test signal line is divided into a plurality of branches at the second point located on the fourth side of the peripheral area, and each branch is connected to a corresponding gate line to provide the second test signal to the same even-numbered row pixel driving circuit during the inspection test.

[0015] In some embodiments of the present disclosure, the gate line connected to each branch of the first test signal line provides the first test signal from the first test signal terminal and the gate drive signal from the gate drive circuit to the same odd-numbered row pixel drive circuit; and the gate line connected to each branch of the second test signal line provides the second test signal from the second test signal terminal and the gate drive signal from the gate drive circuit to the same even-numbered row pixel drive circuit.

[0016] In some embodiments of the present disclosure, all odd-numbered row pixel driving circuits are arranged in mirror-symmetry with respect to a straight line passing through the first point and perpendicular to the third side and the fourth side; and all even-numbered row pixel driving circuits are arranged in mirror-symmetry with respect to a straight line passing through the second point and perpendicular to the third side and the fourth side.

[0017] In some embodiments of the present disclosure, the display substrate also includes a switching signal terminal, which is arranged on the same side as the at least one test signal terminal; a switching signal line, which extends in the peripheral area and is connected to the switching signal terminal; and a plurality of switching transistors, which are connected to the switching signal line, the one or more test signal lines and the corresponding pixel driving circuit; wherein the plurality of switching transistors are configured to control the one or more test signal lines through the switching signal provided by the switching signal line to provide the test signal to the corresponding pixel driving circuit during the inspection test.

[0018] In some embodiments of the present disclosure, the display substrate further includes a base substrate; a first conductive layer, which is located on the base substrate and has a first opening therein; a gate insulating layer, which is located on a side of the first conductive layer away from the base substrate and is located in the first opening; a passivation layer, which is located on a side of the gate insulating layer away from the base substrate; a second opening and a third opening, which extend through the gate insulating layer and the passivation layer; and a second conductive layer, which is located on a side of the passivation layer away from the base substrate and covers the second opening and the third opening to contact the first conductive layer; wherein the orthographic projection of the first opening on the base substrate does not overlap with the orthographic projection of the second opening on the base substrate at least partially; the first opening is located on the base substrate The orthographic projection on the bottom substrate and the orthographic projection of the third opening on the base substrate at least partially do not overlap; and the spacing between the two parts of the first conductive layer disconnected by the first opening is greater than or equal to 20um; wherein each of the one or more test signal lines includes a first part and a second part; the switch signal line includes a first part and a second part; the first part of each test signal line and the first part of the switch signal line are located in the first conductive layer; and the second part of each test signal line and the second part of the switch signal line are located in the second conductive layer; and the first opening, the second opening and the third opening are located at the first corner and the second corner, or at the second corner and the third corner.

[0019] In a second aspect, the present disclosure provides a display device, comprising the display substrate described in the first aspect, and one or more integrated circuits connected to the display substrate.

[0020] In a third aspect, the present disclosure provides a method for testing the display substrate described in the first aspect, the method comprising an inspection test phase: in the inspection test phase, a test signal is provided to the one or more test signal lines through the at least one test signal terminal, and the test signal is transmitted to the corresponding pixel driving circuit through the one or more test signal lines to test the display substrate; and after the inspection test phase, the at least one test signal terminal is bound and connected to a corresponding terminal of a driving circuit to provide a ground signal to the one or more test signal lines through the driving circuit through the at least one test signal terminal during the display phase of the display substrate.

[0021] In some embodiments of the present disclosure, the display substrate further includes: a switching signal terminal, which is arranged on the same side as the at least one test signal terminal; a switching signal line, which extends in the peripheral area and is connected to the switching signal terminal; and a plurality of switching transistors, which are connected to the switching signal line, the one or more test signal lines and the corresponding pixel driving circuit; wherein the method further includes: in the inspection test phase, providing a switching signal from the switching signal terminal to the plurality of switching transistors through the switching signal line, thereby controlling the one or more test signal lines to provide the test signal to the corresponding pixel driving circuit during the inspection test phase; and after the inspection test phase, binding the switching signal terminal to the corresponding terminal of the driving circuit, so as to provide a low-level signal to the switching signal line through the switching signal terminal through the driving circuit during the display phase of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0023] Figure 1 is a plan view of a display substrate according to some embodiments of the present disclosure.

[0024] Figure 2 The display area and the peripheral area of ​​the display substrate in some embodiments of the present disclosure are shown.

[0025] Figure 3 A schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure is shown.

[0026] Figure 4a A schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure is shown.

[0027] Figure 4b Schematic diagrams showing alternative structures of a display substrate in some embodiments according to the present disclosure.

[0028] Figure 5 Schematic diagram showing signal attenuation caused by excessive signal line resistance.

[0029] Figure 6a Shown along Figure 4a Cross-sectional view along line AA'.

[0030] Figure 6b The bonding connection between the switch signal line, the first test signal line, and the second test signal line and the driving circuit after the inspection test process is shown.

[0031] Figure 7 A schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure is shown.

[0032] Figure 8 A schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure is shown.

[0033] Fig. 9 A flow chart of a method for testing a display substrate according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0034] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0035] The present disclosure relates to medium and large-sized products with Gate & Source ICs, and specifically, to a display substrate and a display device including a gate driving circuit and a source driving circuit, wherein the gate driving circuit and the source driving circuit are respectively configured to drive pixel driving circuits arranged in an array in rows and columns.

[0036] In some embodiments of the present disclosure, medium and large-sized products refer to display devices with a display screen size of more than 7 inches. The display substrate and display device of the present disclosure are particularly suitable for LCD (Liquid Crystal Display) in ADS (Advanced Super Dimension Switching) display mode.

[0037] Generally, the manufacturing process of LCD includes: Array process, Cell process and MDL process (i.e., module assembly process). The Cell process includes an inspection and testing process. As the last step of the Cell process, the inspection and testing process uses electrical means to test the single display substrate formed by the previous process to detect defective products in time and avoid waste caused by defective products flowing into the later process.

[0038] Therefore, the present disclosure provides a display substrate and a test method thereof, and a display device, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a display substrate. In some embodiments, the display substrate has a display area and a peripheral area arranged around the display area, and includes: a plurality of gate lines extending along a first direction; a plurality of data lines extending along a second direction; at least two drive circuits located in the peripheral area, and configured to provide a gate drive signal and a source drive signal to a plurality of pixel drive circuits arranged in an array including multiple rows and columns located in the display area through a plurality of gate lines and a plurality of data lines; one or more test signal lines located in the peripheral area, and extending to a side opposite to a corresponding drive circuit of the at least two drive circuits, each test signal line including a plurality of branches at a point on the side, each branch extending from the point to connect to the corresponding pixel drive circuit, so as to provide a test signal to the corresponding pixel drive circuit during the inspection test; and at least one test signal terminal, which is configured to provide a test signal to one or more test signal lines.

[0039] Various suitable pixel drive circuits may be used in the display substrate described in the present disclosure. Examples of suitable drive circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. Various suitable light-emitting elements may be used in the display substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0040] Figure 1 is a plan view of a display substrate according to some embodiments of the present disclosure. Figure 1, the display substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The display substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of first voltage supply lines Vdd, and respective second voltage supply lines (e.g., low voltage supply lines). Each sub-pixel Sp emits light driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of the light-emitting element through a corresponding first voltage supply line in a plurality of first voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to a cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0041] Figure 2 1 shows a display area and a peripheral area of ​​a display substrate according to some embodiments of the present disclosure. Figure 2In some embodiments, the display substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area DA" refers to the area of ​​the display substrate that actually displays an image. Optionally, the display area DA may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel, for example, the area corresponding to the pixel electrode in the liquid crystal display or the area corresponding to the light-emitting layer in the organic light-emitting display. Optionally, the sub-pixel area is the light-emitting area of ​​the red sub-pixel. Optionally, the sub-pixel area is the light-emitting area of ​​the green sub-pixel. Optionally, the sub-pixel area is the light-emitting area of ​​the blue sub-pixel. Optionally, the sub-pixel area is the light-emitting area of ​​the white sub-pixel. The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, for example, the area corresponding to the black matrix in the liquid crystal display or the area corresponding to the pixel defining layer in the organic light-emitting display. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between two adjacent sub-pixel areas in two adjacent pixels. Optionally, the inter-sub-pixel area is the area between the sub-pixel area of ​​the red sub-pixel and the sub-pixel area of ​​the adjacent green sub-pixel. Optionally, the inter-subpixel region is the region between the subpixel region of the red subpixel and the subpixel region of the adjacent blue subpixel. Optionally, the inter-subpixel region is the region between the subpixel region of the green subpixel and the subpixel region of the adjacent blue subpixel. As used herein, the term "peripheral area PA" refers to the following area of ​​a display substrate (e.g., an opposing substrate or an array substrate) in a display panel: in this area, various circuits and wires are provided to transmit signals to the display substrate. In order to increase the transparency of the display device, opaque or light-proof components (e.g., batteries, printed circuit boards, metal frames) of the display device can be arranged in the peripheral area PA instead of in the display area DA.

[0042] In some embodiments of the present disclosure, Figure 2 As shown, the peripheral area PA includes a first side SP and a second side SO opposite to each other, and a third side GP and a fourth side GO opposite to each other, wherein the first side SP connects the third side GP and the fourth side GO, and the second side SO connects the third side GP and the fourth side GO. In some embodiments of the present disclosure, as Figure 2 As shown, the peripheral area PA includes a first corner CR1 located between the first side SP and the fourth side GO, a second corner CR2 located between the second side SO and the fourth side GO, a third corner CR3 located between the second side SO and the third side GP, and a fourth corner CR4 located between the first side SP and the third side GP.

[0043] In some embodiments of the present disclosure, the display substrate includes at least two driving circuits located in the peripheral area PA, and the at least two driving circuits are configured to provide gate driving signals and source driving signals to a plurality of pixel driving circuits PDC arranged in an array including a plurality of rows and columns located in the display area DA through a plurality of gate lines GL and a plurality of data lines DL. Figure 2 As shown, at least two driving circuits include a source driving circuit SIC and a gate driving circuit GIC, the source driving circuit SIC is located at the first side SP of the peripheral area PA, and the gate driving circuit GIC is located at the third side GP of the peripheral area PA. In some embodiments of the present disclosure, the source driving circuit SIC is configured to provide a source driving signal to the pixel driving circuit PDC located in the display area DA to drive the corresponding light-emitting element to emit light, and the gate driving circuit GIC is configured to provide a gate driving signal to the pixel driving circuit PDC located in the display area DA. In the embodiments of the present disclosure, at least two driving circuits including a source driving circuit SIC and a gate driving circuit GIC are used as an example for description.

[0044] Figure 3 Schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure. Figure 3 In some embodiments, the display substrate includes a plurality of pixel units PX arranged in an array, that is, the display substrate includes M columns of pixel units PX, where M is a positive integer greater than or equal to 1. Figure 3 Two adjacent columns of pixel units PX are shown, that is, the (2k-1)th column of pixel units PX and the (2k)th column of pixel units PX, where 1≤k≤M / 2. In some embodiments of the present disclosure, each pixel unit PX includes a corresponding first sub-pixel Sp1, a corresponding second sub-pixel Sp2, and a corresponding third sub-pixel Sp3. Optionally, each pixel unit PX of the display substrate includes a corresponding first sub-pixel Sp1, a corresponding second sub-pixel Sp2, and a corresponding third sub-pixel Sp3. The multiple sub-pixels in the display substrate are arranged in an array. In one example, the array of multiple sub-pixels includes a S1-S2-S3 format repeating array, where S1 represents the corresponding first sub-pixel Sp1, S2 represents the corresponding second sub-pixel Sp2, and S3 represents the corresponding third sub-pixel Sp3. In another example, the S1-S2-S3 format is a C1-C2-C3 format, where C1 represents the corresponding first sub-pixel Sp1 of the first color, C2 represents the corresponding second sub-pixel Sp2 of the second color, and C3 represents the corresponding third sub-pixel Sp3 of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel Sp1 is a red sub-pixel, the corresponding second sub-pixel Sp2 is a green sub-pixel, and the corresponding third sub-pixel Sp3 is a blue sub-pixel.

[0045] In some embodiments of the present disclosure, Figure 3 As shown, the first sub-pixel Sp1, the second sub-pixel Sp2 and the third sub-pixel Sp3 of each pixel unit PX are arranged in sequence along the first direction DR1. In an alternative embodiment, the first sub-pixel Sp1, the second sub-pixel Sp2 and the third sub-pixel Sp3 of each pixel unit PX may be arranged in sequence along the second direction DR2. In an alternative embodiment, the first sub-pixel Sp1, the second sub-pixel Sp2 and the third sub-pixel Sp3 of each pixel unit PX may be arranged in sequence along a direction different from the first direction DR1 and the second direction DR2. In an alternative embodiment, the first sub-pixel Sp1, the second sub-pixel Sp2 and the third sub-pixel Sp3 of each pixel unit PX may be arranged in sequence in other ways. The present disclosure does not specifically limit the arrangement of the first sub-pixel Sp1, the second sub-pixel Sp2 and the third sub-pixel Sp3 of each pixel unit PX.

[0046] In an alternative embodiment, each pixel unit PX includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each pixel unit PX of the display substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The multiple sub-pixels in the display substrate are arranged in an array. In one example, the array of multiple sub-pixels includes a S1-S2-S3-S4 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents a corresponding first subpixel of a first color, C2 represents a corresponding second subpixel of a second color, C3 represents a corresponding third subpixel of a third color, and C2' represents a corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is an RGBG format, where a corresponding first subpixel is a red subpixel, a corresponding second subpixel is a green subpixel, a corresponding third subpixel is a blue subpixel, and a corresponding fourth subpixel is a green subpixel.

[0047] As used herein, the terms "column (2k-1)" and "column (2k)" are used in the context of column K. The display substrate may or may not include additional columns before the first column in column K and / or additional columns after the last column in column K. In the context of the display substrate, the term "column (2k-1)" does not necessarily mean an odd column, and the term "column (2k)" does not necessarily mean an even column. In one example, the column (2k-1) is an odd column in the context of column K, but may be an even column in the context of the display substrate. In another example, the column (2k-1) is an odd column in the context of column K, and is also an odd column in the context of the display substrate. In one example, the column (2k) is an even column in the context of column K, but may be an odd column in the context of the display substrate. In another example, the column (2k) is an even column in the context of column K, and is also an even column in the context of the display substrate.

[0048] In some embodiments of the present disclosure, Figure 3 As shown, the display substrate includes a plurality of gate lines extending along a first direction DR1 and a plurality of data lines DL extending along a second direction DR2. The plurality of gate lines and the plurality of data lines DL intersect each other, and a sub-pixel (a first sub-pixel Sp1, a second sub-pixel Sp2, or a third sub-pixel Sp3) is disposed at each intersection of the plurality of gate lines and the plurality of data lines DL. In some embodiments of the present disclosure, as Figure 3 As shown, each gate line includes a first gate line GL1 and a second gate line GL2.

[0049] In some embodiments of the present disclosure, Figure 3 As shown, the source driving circuit SIC is configured to provide a source driving signal to the pixel driving circuit PDC corresponding to the sub-pixels in the same column of the display area DA (i.e., the pixel driving circuit PDC corresponding to the first sub-pixel Sp1 in the same column, the pixel driving circuit PDC corresponding to the second sub-pixel Sp2 in the same column, or the pixel driving circuit PDC corresponding to the third sub-pixel Sp3 in the same column) through the corresponding data line DL to drive the corresponding sub-pixels to emit light.

[0050] In some embodiments of the present disclosure, Figure 3 As shown, the sub-pixels in the same column are sub-pixels of the same color, for example, the sub-pixels in the same column are the first sub-pixels Sp1 in the same column, the second sub-pixels Sp2 in the same column, or the third sub-pixels Sp3 in the same column. Alternatively, in other embodiments of the present disclosure, the sub-pixels in the same column include sub-pixels of any color, for example, the sub-pixels in the same column include the first sub-pixel Sp1, the second sub-pixel Sp2, and / or the third sub-pixel Sp3, and the present disclosure does not specifically limit this.

[0051] In some embodiments of the present disclosure, Figure 3As shown, the gate driving circuit GIC is configured to provide a gate driving signal to the pixel driving circuits PDC corresponding to the sub-pixels in the same row in the display area DA through the corresponding first gate line GL1 and the corresponding second gate line GL2 to control these pixel driving circuits PDC.

[0052] Figure 4a Schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure. Figure 4a As shown, along the first direction DR1, Figure 4a M columns of pixel units PX are shown in sequence, including the 1st column of pixel units PX, the 2nd column of pixel units PX, ..., the (2k-1)th column of pixel units PX, the (2k)th column of pixel units PX, ..., the (M-1)th column of pixel units PX, and the Mth column of pixel units PX.

[0053] In some embodiments of the present disclosure, the display substrate also includes one or more test signal lines, which are located in the peripheral area PA and extend to a side opposite to a corresponding one of the at least two drive circuits, each test signal line including a plurality of branches at a point on the side, each branch extending from the point to be connected to the corresponding pixel drive circuit, thereby providing a first test signal or a second test signal to the corresponding pixel drive circuit during an inspection test; and at least one test signal terminal, which is configured to provide a test signal to one or more test signal lines.

[0054] Reference Figure 4a In some embodiments, in addition to Figure 3 In the structure shown, the display substrate further includes a plurality of switch transistors STFT, each of which is arranged at one end of a data line DL connected to a column of pixel units PX, and the other end of the data line DL is connected to a source driving circuit SIC.

[0055] In some embodiments of the present disclosure, the display substrate further includes a switch signal terminal SW, which is arranged on the same side as at least one test signal terminal. Figure 4a As shown, the switch signal terminal SW is disposed at the first side SP of the peripheral area PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral area PA) and is configured to provide a switch signal to each switch transistor STFT through a switch signal line SWL. In some embodiments of the present disclosure, as Figure 4aAs shown, one end of the switching signal line SWL is connected to the switching signal terminal SW, and extends from the switching signal terminal SW along the first direction DR1 toward the fourth side GO to the first corner CR1, and then extends from the first corner CR1 along the fourth side GO to the second corner CR2, and further, extends from the second corner CR2 along the second side SO to be connected to each switching transistor STFT, and control the switching of the switching transistor STFT by providing a switching signal to each switching transistor STFT.

[0056] The higher the resolution and the greater the screen load, the larger the channel width-to-length ratio W / L of the required switching transistor STFT will be.

[0057] In some embodiments of the present disclosure, the one or more test signal lines include a first test signal line DOL and a second test signal line DEL. In some embodiments of the present disclosure, at least one test signal terminal includes a first test signal terminal DO, which is arranged at a position of the source driver circuit on the first side of the peripheral area PA close to the first corner CR1; and a second test signal terminal DE, which is arranged at a position of the source driver circuit on the first side of the peripheral area PA close to the first corner CR1.

[0058] like Figure 4a As shown, the first test signal terminal DO is disposed at the first side SP of the peripheral area PA and close to the fourth side GO (ie, located at the first corner CR1 of the peripheral area PA), and is configured to provide a first test signal DOS to the odd-numbered pixel units PX through the first test signal line DOL.

[0059] like Figure 4a As shown, the second test signal terminal DE is disposed at the first side SP of the peripheral area PA and close to the fourth side GO (ie, located at the first corner CR1 of the peripheral area PA), and is configured to provide a second test signal DES to the even-numbered column pixel units PX through a second test signal line DEL.

[0060] like Figure 4a As shown, the display substrate further includes a common electrode terminal Vcom, which is configured to provide a test signal during the inspection test process, so as to test the display substrate.

[0061] In the prior art, the first test signal line DOL or the second test signal line DEL sequentially provides a test signal to all column pixel units PX from one side of the display substrate to the other side of the display substrate (eg, from the fourth side GO to the third side GP). Figure 5 The schematic diagram shows that the signal line resistance is too large, which leads to signal attenuation. Figure 5As shown, as the distance between the signal lines increases, the resistance of the signal lines becomes larger and larger. Therefore, in the prior art, a single-sided input test signal will cause signal attenuation, thereby causing display abnormalities (i.e., display inconsistency) on the left and right sides (the third side GP and the fourth side GO) of the display substrate.

[0062] In some embodiments of the present disclosure, Figure 4a As shown, one end of the first test signal line DOL is connected to the first test signal terminal DO, and extends from the first test signal terminal DO along the first direction DR1 toward the fourth side GO to the first corner CR1, and then extends from the first corner CR1 to the second corner CR2 along the fourth side GO, and further, extends from the second corner CR2 to the first point O near the center of the display substrate along the second side SO. In some embodiments of the present disclosure, as Figure 4a As shown, the first test signal line DOL is divided into a plurality of branches at a first point O on the second side SO of the peripheral area PA, and each branch is connected to a switch transistor STFT located in an odd column. In this way, the switch transistors STFT of all odd columns are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the first side SP and the second side SO, so that the first test signal DOS is transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate at the same time, avoiding display abnormality (i.e., display inconsistency) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by gradual attenuation of the first test signal DOS.

[0063] like Figure 4a As shown, the first test signal line DOL is divided into two branches at the first point O on the second side SO of the peripheral area PA, namely, a first branch OL1 and a second branch OL2, the first branch OL1 extends along the first direction DR1 toward the third side GP, and the second branch OL2 extends along the first direction DR1 toward the fourth side GO. The display substrate further includes a plurality of first lead lines OLL, each of which extends along the second direction DR2, and one end of each of the first lead lines OLL is connected to a switch transistor STFT located in an odd-numbered column, and the other end of each of the first lead lines OLL is connected to a corresponding position of a corresponding branch, as shown in FIG. Figure 4a In this way, the corresponding positions where each first lead line OLL is connected to the first branch OL1 and the second branch OL2 are arranged in mirror symmetry with respect to the first point O.

[0064] In some embodiments of the present disclosure, Figure 4aAs shown, in each odd-numbered column, the source driving circuit SIC is connected to one end of each data line DL, each data line DL is connected to a column of pixel units PX, and then connected to a switch transistor STFT, and the switch transistor STFT is connected to the corresponding branch through the corresponding first lead OLL, and then connected to the first point O near the center of the display substrate, all the first lead lines OLL converge into a first test signal line DOL at the first point O through the first branch OL1 and the second branch OL2, and the first test signal line DOL extends from the first point O along the second side SO, the fourth side GO and the first side SP to the first test signal terminal DO. In some embodiments of the present disclosure, as Figure 4a As shown, the first test signal DOS from the first test signal terminal DO and the source drive signal from the source drive circuit SIC are provided to each column of pixel units PX through the same data line DL. In some embodiments of the present disclosure, there are L odd-numbered columns of switch transistors STFT and N even-numbered columns of switch transistors STFT, where L+N=M. Wherein, L is a positive integer greater than or equal to 1; and N is a positive integer greater than or equal to 1.

[0065] In some embodiments of the present disclosure, all odd-numbered columns of switch transistors STFT (i.e., L odd-numbered columns of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the first side SP and the second side SO. For example, the first odd-numbered column of switch transistors STFT (i.e., the 1st column of switch transistors STFT among the M columns of switch transistors STFT) and the last odd-numbered column of switch transistors STFT (i.e., the Mth column of switch transistors STFT or the (M-1)th column of switch transistors STFT among the M columns of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the first side SP and the second side SO, and the second odd-numbered column of switch transistors STFT (i.e., the 3rd column of switch transistors STFT among the M columns of switch transistors STFT) and the second-to-last odd-numbered column of switch transistors STFT (i.e., the Mth column of switch transistors STFT or the (M-1)th column of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the first side SP and the second side SO. The (M-2)th column of switching transistors STFT or the (M-3)th column of switching transistors STFT in the body transistor STFT are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the first side SP and the second side SO, ..., when L is an odd number, the (L+1) / 2th odd column of switching transistors STFT is located on the straight line passing through the first point O and perpendicular to the first side SP and the second side SO; when L is an even number, the L / 2th odd column of switching transistors STFT and the (L+2) / 2th odd column of switching transistors STFT are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the first side SP and the second side SO. In this way, all odd-numbered columns of switching transistors STFT (i.e., L odd-numbered columns of switching transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the first side SP and the second side SO, so that the first test signal DOS is simultaneously transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate, thereby avoiding abnormal display (i.e., inconsistent display) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by the gradual attenuation of the first test signal DOS.

[0066] Similarly, in some embodiments of the present disclosure, Figure 4a As shown, one end of the second test signal line DEL is connected to the second test signal terminal DE, and extends from the second test signal terminal DE along the first direction DR1 toward the fourth side GO to the first corner CR1, and then extends from the first corner CR1 to the second corner CR2 along the fourth side GO, and further, extends from the second corner CR2 to the second point E near the center of the display substrate along the second side SO. In some embodiments of the present disclosure, as Figure 4aAs shown, the second test signal line DEL is divided into a plurality of branches at the second point E on the second side SO of the peripheral area PA, and each branch is connected to a switch transistor STFT located in an even-numbered column. In this way, the switch transistors STFT of all even-numbered columns are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the first side SP and the second side SO, so that the second test signal DES is transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate at the same time, avoiding display abnormality (i.e., display inconsistency) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by the gradual attenuation of the second test signal DES.

[0067] like Figure 4a As shown, the second test signal line DEL is divided into two branches at the second point E on the second side SO of the peripheral area PA, namely, a first branch EL1 and a second branch EL2, the first branch EL1 extends along the first direction DR1 toward the third side GP, and the second branch EL2 extends along the first direction DR1 toward the fourth side GO. The display substrate further includes a plurality of second lead lines ELL, each of which extends along the second direction DR2, and one end of each of the second lead lines ELL is connected to a switch transistor STFT located in an even-numbered column, and the other end of each of the second lead lines ELL is connected to a corresponding position of a corresponding branch, as shown in FIG. Figure 4a In this way, the corresponding positions where the second leads ELL are connected to the first branch EL1 and the second branch EL2 are arranged in a mirror-symmetrical manner about the second point E.

[0068] In some embodiments of the present disclosure, Figure 4a As shown, in each even-numbered column, the source driving circuit SIC is connected to one end of each data line DL, each data line DL is connected to a column of pixel units PX, and then connected to a switch transistor STFT, and the switch transistor STFT is connected to the corresponding branch through the corresponding second lead ELL, and then connected to the second point E near the center of the display substrate, and all the second lead ELLs converge into a second test signal line DEL at the second point E through the first branch EL1 and the second branch EL2, and the second test signal line DEL extends from the second point E along the second side SO, the fourth side GO and the first side SP to the second test signal terminal DE. In some embodiments of the present disclosure, as Figure 4a As shown, the second test signal DES from the second test signal terminal DE and the source driving signal from the source driving circuit SIC are provided to each column of pixel units PX through the same data line DL.

[0069] In some embodiments of the present disclosure, all the switch transistors STFTs of the even columns (i.e., the switch transistors STFTs of the N even columns) are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the first side SP and the second side SO. For example, the first switch transistor STFT of the even column (i.e., the 2nd switch transistor STFT of the M columns of switch transistors STFT) and the last switch transistor STFT of the even column (i.e., the Mth switch transistor STFT of the M columns of switch transistors STFT or the (M-1)th switch transistor STFT of the M columns of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the first side SP and the second side SO, and the second switch transistor STFT of the even column (i.e., the 4th switch transistor STFT of the M columns of switch transistors STFT) and the second-to-last switch transistor STFT of the even column (i.e., the Mth switch transistor STFT of the M columns of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the first side SP and the second side SO. The (M-2)th column of switching transistors STFT or the (M-3)th column of switching transistors STFT in the body transistor STFT are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the first side SP and the second side SO, ..., when N is an odd number, the (N+1) / 2th even column of switching transistors STFT is located on a straight line passing through the second point E and perpendicular to the first side SP and the second side SO; when N is an even number, the N / 2th even column of switching transistors STFT and the (N+2) / 2th even column of switching transistors STFT are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the first side SP and the second side SO. In this way, the switching transistors STFT of all even-numbered columns (i.e., the switching transistors STFT of N even-numbered columns) are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the first side SP and the second side SO, so that the second test signal DES is simultaneously transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate, thereby avoiding abnormal display (i.e., inconsistent display) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by the gradual attenuation of the second test signal DES.

[0070] exist Figure 4a In the illustrated embodiment, a switch transistor STFT is provided in each column of pixel units PX as an example for description, that is, a column of first sub-pixels Sp1, a column of second sub-pixels Sp2, and a column of third sub-pixels Sp3 included in each column of pixel units PX share a switch transistor STFT. In an alternative embodiment, a switch transistor STFT is provided in each column of sub-pixels. That is, a switch transistor STFT is provided in each column of first sub-pixels Sp1, a switch transistor STFT is provided in each column of second sub-pixels Sp2, and a switch transistor STFT is provided in each column of third sub-pixels Sp3. The present disclosure does not make specific limitations on this.

[0071] exist Figure 4aIn the embodiment shown, M columns of pixel units PX are divided into odd columns of pixel units PX and even columns of pixel units PX that are alternately arranged in sequence, and two test signal lines (i.e., a first test signal line DOL and a second test signal line DEL) are set to provide a first test signal DOS to the odd columns of pixel units PX and a second test signal DES to the even columns of pixel units PX, respectively, to perform an inspection test process. In an alternative embodiment, the same test signal line can be used to simultaneously provide the same test signal to the M columns of pixel units PX to perform an inspection test process. In an alternative embodiment, three test signal lines can also be set for each color of sub-pixel unit to control each column of sub-pixels in each column of pixel units PX, respectively. The present disclosure does not specifically limit this.

[0072] The switch signal line SWL, the first test signal line DOL, and the second test signal line DEL need to extend from the first side SP of the peripheral area PA along the fourth side GO to the second side SO opposite to the first side SP. Therefore, the lengths of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are too long, and at the places where the extension directions of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are changed (i.e., at the first corner CR1 and / or the second corner CR2, as shown in FIG. Figure 4a The portion within the dotted box in the middle) is prone to electrostatic discharge (ESD), which can cause abnormal function of the signal line, causing the functional connection holes and wiring inside the display substrate to burn out, resulting in poor display and affecting product yield.

[0073] Figure 6a Shown along Figure 4a AA' in FIG. 1 . In some embodiments of the present disclosure, the second test signal line DEL is described as being located at the second corner CR2. The switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are located at a point where the extension direction changes (i.e., at the first corner CR1 and / or the second corner CR2, as shown in FIG. 1 ). Figure 4a The part within the dotted box in the figure has a similar structure.

[0074] In some embodiments of the present disclosure, Figure 6aAs shown, the display substrate includes a base substrate BS; a first conductive layer CT1, which is located on the base substrate BS and has a first opening AP1 therein; a gate insulating layer GI, which is located on a side of the first conductive layer CT1 away from the base substrate BS and is located in the first opening AP1; a passivation layer PVX, which is located on a side of the gate insulating layer GI away from the base substrate BS; a second opening AP2 and a third opening AP3, which extend through the gate insulating layer GI and the passivation layer PVX. The orthographic projection of the first opening AP1 on the base substrate BS does not overlap with the orthographic projection of the second opening AP2 on the base substrate BS at least partially. The orthographic projection of the first opening AP1 on the base substrate BS does not overlap with the orthographic projection of the third opening AP3 on the base substrate BS at least partially. The display substrate also includes a second conductive layer CT2, which is located on a side of the passivation layer PVX away from the base substrate BS and covers the second opening AP2 and the third opening AP3 to contact the first conductive layer CT1.

[0075] In some embodiments of the present disclosure, each test signal line (first test signal line DOL or second test signal line DEL) includes a first portion located at the first conductive layer CT1 and a second portion located at the second conductive layer CT2; the switching signal line SWL includes a first portion located at the first conductive layer CT1 and a second portion located at the second conductive layer CT2; the first opening AP1, the second opening AP2 and the third opening AP3 are located at the first corner CR1 and the second corner CR2.

[0076] In some embodiments of the present disclosure, the first opening AP1 divides the first conductive layer CT1 into two parts disconnected from each other, the two parts are electrically insulated by the part of the gate insulating layer GI located in the first opening AP1, and are connected together by the second conductive layer CT2 at the second opening AP2 and the third opening AP3, thereby realizing the connection of the second test signal line DEL at the second corner CR2. In this way, it is possible to avoid abnormal signal line function caused by electrostatic discharge (ESD) at the extension direction change point of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL, thereby avoiding burning of the functional connection holes and wiring inside the display substrate, avoiding poor display problems, and improving product yield.

[0077] In some embodiments of the present disclosure, Figure 6a As shown, the distance D between the two parts of the first conductive layer CT1 separated by the first opening AP1 is greater than or equal to 20 um.

[0078] Each test signal line or switch signal line SWL turns and extends at a corner, such as Figure 4aAs shown, each test signal line and switch signal line SWL extends along the first side SP, turns 90 degrees at the first corner CR1, and then extends along the fourth side GO, then turns 90 degrees at the second corner CR2, and then extends along the second side SO. Therefore, each test signal line or switch signal line SWL may include three parts, namely, a first part extending along the first side SP, a second part extending along the fourth side GO, and a third part extending along the second side SO.

[0079] like Figure 6a The general idea of ​​the broken wire jump hole setting method shown is that in the two parts located on both sides of the corresponding corner, the first opening AP1, the second opening AP2 and the third opening AP3 are set at the part with a larger length to achieve a better anti-static effect.

[0080] like Figure 4a and Figure 6a As shown, on both sides of the first corner CR1 are the first and second parts of each test signal line or switch signal line SWL, and the length of the second part is greater than the length of the first part, so the first opening AP1, the second opening AP2, and the third opening AP3 are arranged at one end of the second part close to the first corner CR1. Similarly, on both sides of the second corner CR2 are the second and third parts of each test signal line or switch signal line SWL, and the length of the third part is greater than the length of the second part, so the first opening AP1, the second opening AP2, and the third opening AP3 are arranged at one end of the third part close to the second corner CR2. Figure 4a The bold line in the dotted frame shows the position of the break jump hole setting.

[0081] Figure 4b Schematic diagrams showing alternative structures of display substrates in some embodiments of the present disclosure are shown. In alternative embodiments, Figure 4b and Figure 6a As shown, the first opening AP1, the second opening AP2 and the third opening AP3 are arranged at one end of the first part close to the first corner CR1, and at one end of the second part close to the second corner CR2, that is, the first opening AP1, the second opening AP2 and the third opening AP3 are arranged on the part with a shorter length. Figure 4a and Figure 4b The antistatic effects achieved by the embodiments are not much different, but Figure 4a The antistatic effect achieved by the embodiment is better than Figure 4a Figure 4b The antistatic effect achieved by the embodiment.

[0082] In an alternative embodiment, the first opening AP1, the second opening AP2, and the third opening AP3 may be provided at a portion having a greater length or at a portion having a greater length of each test signal line or switch signal line SWL. Figure 6a The broken wire jump hole setting methods shown can all achieve better anti-static effects.

[0083] In some embodiments of the present disclosure, various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer CT1. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer CT1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0084] In some embodiments of the present disclosure, examples of suitable second conductive layer CT2 materials include, but are not limited to, metal conductive electrode materials and non-metal conductive electrode materials. Examples of suitable metal conductive electrode materials include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates thereof. Examples of suitable non-metal conductive electrode materials include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO).

[0085] In some embodiments of the present disclosure, examples of materials of the gate insulating layer GI and the passivation layer PVX include various appropriate resin materials, polyimide, silicon oxide (SiOy), silicon nitride (SiNy, such as Si3N4), and silicon oxynitride (SiOxNy).

[0086] In some embodiments of the present disclosure, the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL have lost their function after the inspection test process, which is equivalent to a floating signal line. After the inspection test process, during the MDL process, the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are bound to a drive circuit, so that when in use, the first test signal line DOL and the second test signal line DEL are provided with a ground (GND) signal through the drive circuit, and a low level signal (VGL) is provided to the switch signal line SWL to completely turn off the switch transistor STFT. In this way, crosstalk between signals is prevented during use and abnormal screen display caused by possible signal coupling is avoided.

[0087] Figure 6bFIG. 4 shows the binding connection between the switch signal line, the first test signal line, the second test signal line and the driving circuit after the inspection test process. Figure 4a and Figure 6b As shown, during the MDL process, the switch signal terminal SW, the first test signal terminal DO and the second test signal terminal DE are bound and connected to corresponding terminals of the driving circuit IC (for example, the ground terminal and the low voltage signal terminal of the driving circuit IC, etc.), so that when in use, the driving circuit IC provides a low level signal (VGL) to the switch signal line SWL through the switch signal terminal SW to completely turn off the switching transistor STFT, and provides a ground (GND) signal to the first test signal line DOL and the second test signal line DEL through the first test signal terminal DO and the second test signal terminal DE respectively through the driving circuit IC.

[0088] Figure 7 Schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure. Figure 7 As shown, along the first direction DR1, Figure 7 M columns of pixel units PX are shown in sequence. Specifically, along the first direction DR1, Figure 7 The first sub-pixel Sp1 in the first column, the second sub-pixel Sp2 in the first column, the third sub-pixel Sp3 in the first column, ..., the first sub-pixel Sp1 in the Mth column, the second sub-pixel Sp2 in the Mth column, and the third sub-pixel Sp3 in the Mth column are shown in sequence. Figure 7 In some embodiments, in addition to Figure 3 In the structure shown, the display substrate also includes a plurality of switching transistors STFT, each switching transistor STFT is arranged at one end of a data line DL connected to a column of sub-pixels (i.e., a column of first sub-pixels Sp1, a column of second sub-pixels Sp2 or a column of third sub-pixels Sp3), and the other end of the data line DL is connected to a source driving circuit SIC.

[0089] In some embodiments of the present disclosure, Figure 7 As shown, the display substrate further includes a switch signal terminal SW, which is disposed at the first side SP of the peripheral area PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral area PA) and is configured to provide a switch signal to each switch transistor STFT through a switch signal line SWL. In some embodiments of the present disclosure, as Figure 7As shown, one end of the switching signal line SWL is connected to the switching signal terminal SW, and extends from the switching signal terminal SW along the first direction DR1 toward the fourth side GO to the first corner CR1, and then extends from the first corner CR1 along the fourth side GO to the second corner CR2, and further, extends from the second corner CR2 along the second side SO to be connected to each switching transistor STFT, and control the switching of the switching transistor STFT by providing a switching signal to each switching transistor STFT.

[0090] In some embodiments of the present disclosure, at least one test signal terminal includes a first sub-pixel test signal terminal DSp1, which is arranged at a position of the source driving circuit on the first side of the peripheral area PA close to the first corner CR1; a second sub-pixel test signal terminal DSp2, which is arranged at a position of the source driving circuit on the first side of the peripheral area PA close to the first corner CR1; and a third sub-pixel test signal terminal DSp3, which is arranged at a position of the source driving circuit on the first side of the peripheral area PA close to the first corner CR1; one or more test signal lines include a first sub-pixel test signal line DSpL1, a second sub-pixel test signal line DSpL2 and a third sub-pixel test signal line DSpL3.

[0091] In some embodiments of the present disclosure, Figure 7 As shown, the first subpixel test signal terminal DSp1 is set on the first side SP of the peripheral area PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral area PA), and is configured to provide a first test signal DR for each column of first subpixels Sp1 through the first subpixel test signal line DSpL1.

[0092] In some embodiments of the present disclosure, Figure 7 As shown, the second sub-pixel test signal terminal DSp2 is arranged on the first side SP of the peripheral area PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral area PA), and is configured to provide a second test signal DG for each column of the second sub-pixel Sp2 through the second sub-pixel test signal line DSpL2.

[0093] In some embodiments of the present disclosure, Figure 7 As shown, the third sub-pixel test signal terminal DSp3 is set on the first side SP of the peripheral area PA and close to the fourth side GO (i.e., located at the first corner CR1 of the peripheral area PA), and is configured to provide a third test signal DB for each column of the third sub-pixel Sp3 through the third sub-pixel test signal line DSpL3.

[0094] In some embodiments of the present disclosure, Figure 7As shown, one end of the first sub-pixel test signal line DSpL1 is connected to the first sub-pixel test signal terminal DSp1, and extends from the first sub-pixel test signal terminal DSp1 along the first direction DR1 toward the fourth side GO to the first corner CR1, and then extends from the first corner CR1 to the second corner CR2 along the fourth side GO, and further, extends from the second corner CR2 to the first point O1 near the center of the display substrate along the second side SO. In some embodiments of the present disclosure, as Figure 7 As shown, the first sub-pixel test signal line DSpL1 is divided into a plurality of branches at a first point O1 on the second side SO of the peripheral area PA, and each branch is connected to a column of first sub-pixels Sp1. In this way, all M columns of first sub-pixels Sp1 are arranged in mirror symmetry with respect to a straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO, so that the first test signal DR is transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate at the same time, avoiding display abnormality (i.e., display inconsistency) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by gradual attenuation of the first test signal DR.

[0095] like Figure 7 As shown, the first sub-pixel test signal line DSpL1 is divided into two branches at the first point O1 on the second side SO of the peripheral area PA, namely, a first branch O11 and a second branch O12, the first branch O11 extends along the first direction DR1 toward the third side GP, and the second branch O12 extends along the first direction DR1 toward the fourth side GO. The display substrate further includes a plurality of first lead lines OLL1, each of which extends along the second direction DR2, and one end of each of the first lead lines OLL1 is connected to a switch transistor STFT corresponding to a column of first sub-pixels Sp1, and the other end of each of the first lead lines OLL1 is connected to a corresponding position of a corresponding branch, as shown in FIG. Figure 7 In this way, the corresponding positions where each first lead line OLL1 is connected to the first branch O11 and the second branch O12 are arranged in mirror symmetry with respect to the first point O1.

[0096] In some embodiments of the present disclosure, Figure 7As shown, in each column of first sub-pixels Sp1, the source driving circuit SIC is connected to one end of each data line DL, each data line DL is connected to a column of first sub-pixels Sp1, and then connected to a switch transistor STFT, and the switch transistor STFT is connected to the corresponding branch through the corresponding first lead OLL1, and then connected to the first point O1 near the center of the display substrate, all the first lead lines OLL1 converge into a first sub-pixel test signal line DSpL1 at the first point O1 through the first branch O11 and the second branch O12, and the first sub-pixel test signal line DSpL1 extends from the first point O1 along the second side SO, the fourth side GO and the first side SP to the first sub-pixel test signal terminal DSp1. In some embodiments of the present disclosure, as Figure 7 As shown, the first sub-pixel Sp1 in each column is provided with the first test signal DR from the first sub-pixel test signal terminal DSp1 and the source driving signal from the source driving circuit SIC through the same data line DL.

[0097] In some embodiments of the present disclosure, the switch transistors STFT corresponding to all M columns of first sub-pixels Sp1 (ie, the first M switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO. For example, the switching transistor STFT corresponding to the first sub-pixel Sp1 in the first column and the switching transistor STFT corresponding to the first sub-pixel Sp1 in the last column are arranged in mirror symmetry with respect to a straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO, the switching transistor STFT corresponding to the first sub-pixel Sp1 in the second column and the switching transistor STFT corresponding to the first sub-pixel Sp1 in the second-to-last column are arranged in mirror symmetry with respect to a straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO, ..., when M is an odd number, the switching transistor STFT corresponding to the first sub-pixel Sp1 in the (M+1) / 2th column is located on the straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO; when M is an even number, the switching transistor STFT corresponding to the first sub-pixel Sp1 in the M / 2th column and the switching transistor STFT corresponding to the first sub-pixel Sp1 in the (M+2) / 2th column are arranged in mirror symmetry with respect to a straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO. In this way, the switching transistors STFT corresponding to all M columns of the first sub-pixels Sp1 (i.e., the first M switching transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O1 and perpendicular to the first side SP and the second side SO, so that the first test signal DR is simultaneously transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate, thereby avoiding abnormal display (i.e., inconsistent display) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by the gradual attenuation of the first test signal DR.

[0098] In some embodiments of the present disclosure, Figure 7 As shown, one end of the second sub-pixel test signal line DSpL2 is connected to the second sub-pixel test signal terminal DSp2, and extends from the second sub-pixel test signal terminal DSp2 along the first direction DR1 toward the fourth side GO to the first corner CR1, and then extends from the first corner CR1 to the second corner CR2 along the fourth side GO, and further, extends from the second corner CR2 to the second point O2 near the center of the display substrate along the second side SO. In some embodiments of the present disclosure, as Figure 7 As shown, the second sub-pixel test signal line DSpL2 is divided into a plurality of branches at the second point O2 on the second side SO of the peripheral area PA, and each branch is connected to a column of second sub-pixels Sp2. In this way, all M columns of second sub-pixels Sp2 are arranged in mirror symmetry with respect to a straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO, so that the second test signal DG is transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate at the same time, avoiding display abnormality (i.e., display inconsistency) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by the gradual attenuation of the second test signal DG.

[0099] like Figure 7 As shown, the second sub-pixel test signal line DSpL2 is divided into two branches at the second point O2 on the second side SO of the peripheral area PA, namely, a first branch O21 and a second branch O22, the first branch O21 extends along the first direction DR1 toward the third side GP, and the second branch O22 extends along the first direction DR1 toward the fourth side GO. The display substrate further includes a plurality of second lead lines OLL2, each of which extends along the second direction DR2, and one end of each of the second lead lines OLL2 is connected to a switch transistor STFT corresponding to a column of second sub-pixels Sp2, and the other end of each of the second lead lines OLL2 is connected to a corresponding position of a corresponding branch, as shown in FIG. Figure 7 In this way, the corresponding positions where the second lead wires OLL2 are connected to the first branch O21 and the second branch O22 are arranged in mirror symmetry with respect to the second point O2.

[0100] In some embodiments of the present disclosure, Figure 7As shown, in each column of second sub-pixels Sp2, the source driving circuit SIC is connected to one end of each data line DL, each data line DL is connected to a column of second sub-pixels Sp2, and then connected to a switch transistor STFT, and the switch transistor STFT is connected to the corresponding branch through the corresponding second lead OLL2, and then connected to the second point O2 near the center of the display substrate, all the second lead lines OLL2 converge into a second sub-pixel test signal line DSpL2 at the second point O2 through the first branch O21 and the second branch O22, and the second sub-pixel test signal line DSpL2 extends from the second point O2 along the second side SO, the fourth side GO and the first side SP to the second sub-pixel test signal terminal DSp2. In some embodiments of the present disclosure, as Figure 7 As shown, the second sub-pixel Sp2 in each column is provided with the second test signal DG from the second sub-pixel test signal terminal DSp2 and the source driving signal from the source driving circuit SIC through the same data line DL.

[0101] In some embodiments of the present disclosure, the switch transistors STFT corresponding to all M columns of the second sub-pixels Sp2 (ie, the second M switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO. For example, the switching transistor STFT corresponding to the second sub-pixel Sp2 in the first column and the switching transistor STFT corresponding to the second sub-pixel Sp2 in the last column are arranged in mirror symmetry with respect to a straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO, the switching transistor STFT corresponding to the second sub-pixel Sp2 in the second column and the switching transistor STFT corresponding to the second sub-pixel Sp2 in the second-to-last column are arranged in mirror symmetry with respect to a straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO, ..., when M is an odd number, the switching transistor STFT corresponding to the second sub-pixel Sp2 in the (M+1) / 2th column is located on the straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO; when M is an even number, the switching transistor STFT corresponding to the second sub-pixel Sp2 in the M / 2th column and the switching transistor STFT corresponding to the second sub-pixel Sp2 in the (M+2) / 2th column are arranged in mirror symmetry with respect to a straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO. In this way, the switching transistors STFT corresponding to all M columns of the second sub-pixels Sp2 (i.e., the second M switching transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the second point O2 and perpendicular to the first side SP and the second side SO, so that the second test signal DG is simultaneously transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate, thereby avoiding abnormal display (i.e., inconsistent display) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by the gradual attenuation of the second test signal DG.

[0102] In some embodiments of the present disclosure, Figure 7 As shown, one end of the third sub-pixel test signal line DSpL3 is connected to the third sub-pixel test signal terminal DSp3, and extends from the third sub-pixel test signal terminal DSp3 along the first direction DR1 toward the fourth side GO to the first corner CR1, and then extends from the first corner CR1 to the second corner CR2 along the fourth side GO, and further, extends from the second corner CR2 to a third point O3 near the center of the display substrate along the second side SO. In some embodiments of the present disclosure, as Figure 7 As shown, the third sub-pixel test signal line DSpL3 is divided into a plurality of branches at the third point O3 on the second side SO of the peripheral area PA, and each branch is connected to a column of third sub-pixels Sp3. In this way, all M columns of third sub-pixels Sp3 are arranged in mirror symmetry about a straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO, so that the third test signal DB is transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate at the same time, avoiding display abnormality (i.e., display inconsistency) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by the gradual attenuation of the third test signal DB.

[0103] like Figure 7 As shown, the third sub-pixel test signal line DSpL3 is divided into two branches at the third point O3 on the second side SO of the peripheral area PA, namely, a first branch O31 and a second branch O32, the first branch O31 extends along the first direction DR1 toward the third side GP, and the second branch O32 extends along the first direction DR1 toward the fourth side GO. The display substrate further includes a plurality of third lead lines OLL3, each of which extends along the second direction DR2, and one end of each of which is connected to a switch transistor STFT corresponding to a column of third sub-pixels Sp3, and the other end of each of which is connected to a corresponding position of a corresponding branch, as shown in FIG. Figure 7 In this way, the corresponding positions where the third lead wires OLL3 are connected to the first branch O31 and the second branch O32 are arranged in mirror symmetry with respect to the third point O3.

[0104] In some embodiments of the present disclosure, Figure 7As shown, in each column of third sub-pixels Sp3, the source driving circuit SIC is connected to one end of each data line DL, each data line DL is connected to a column of third sub-pixels Sp3, and then connected to a switch transistor STFT, and the switch transistor STFT is connected to the corresponding branch through the corresponding third lead OLL3, and then connected to the third point O3 near the center of the display substrate, all the third leads OLL3 converge into a third sub-pixel test signal line DSpL3 at the third point O3 through the first branch O31 and the second branch O32, and the third sub-pixel test signal line DSpL3 extends from the third point O3 along the second side SO, the fourth side GO and the first side SP to the third sub-pixel test signal terminal DSp3. In some embodiments of the present disclosure, as Figure 7 As shown, the third sub-pixel Sp3 in each column is provided with the third test signal DB from the third sub-pixel test signal terminal DSp3 and the source driving signal from the source driving circuit SIC through the same data line DL.

[0105] In some embodiments of the present disclosure, the switch transistors STFT corresponding to all M columns of the third sub-pixels Sp3 (ie, the third M switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO. For example, the switching transistor STFT corresponding to the third sub-pixel Sp3 in the first column and the switching transistor STFT corresponding to the third sub-pixel Sp3 in the last column are arranged in mirror symmetry with respect to a straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO, the switching transistor STFT corresponding to the third sub-pixel Sp3 in the second column and the switching transistor STFT corresponding to the third sub-pixel Sp3 in the second-to-last column are arranged in mirror symmetry with respect to a straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO, ..., when M is an odd number, the switching transistor STFT corresponding to the third sub-pixel Sp3 in the (M+1) / 2th column is located on the straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO; when M is an even number, the switching transistor STFT corresponding to the third sub-pixel Sp3 in the M / 2th column and the switching transistor STFT corresponding to the third sub-pixel Sp3 in the (M+2) / 2th column are arranged in mirror symmetry with respect to a straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO. In this way, the switching transistors STFT corresponding to all M columns of the third sub-pixels Sp3 (i.e., the third M switching transistors STFT) are arranged in mirror symmetry about a straight line passing through the third point O3 and perpendicular to the first side SP and the second side SO, so that the third test signal DB is simultaneously transmitted to the left and right sides (the third side GP and the fourth side GO) of the display substrate, thereby avoiding abnormal display (i.e., inconsistent display) on the left and right sides (the third side GP and the fourth side GO) of the display substrate caused by the gradual attenuation of the third test signal DB.

[0106] exist Figure 7 In the embodiment shown, M columns of pixel units PX are divided into M columns of first sub-pixels Sp1, M columns of second sub-pixels Sp2, and M columns of third sub-pixels Sp3 which are alternately arranged in sequence, and three test signal lines (i.e., a first test signal line DSpL1, a second test signal line DSpL2, and a third test signal line DSpL3) are set to provide test signals (i.e., a first test signal DR, a second test signal DG, and a third test signal DB) to the M columns of first sub-pixels Sp1, the M columns of second sub-pixels Sp2, and the M columns of third sub-pixels Sp3, respectively, to perform an inspection test process.

[0107] In an alternative embodiment, in an LCD product applying dual-gate (DRD) driving technology, DY / DC / DM test signals are typically provided for M columns of first sub-pixels Sp1, M columns of second sub-pixels Sp2, and M columns of third sub-pixels Sp3, wherein DY / DC / DM represent yellow test signals, cyan test signals, and magenta test signals, respectively.

[0108] In an alternative embodiment, six test signal lines are set, that is, the first test signal line DSpL1 is divided into two test signal lines DSpL1+ and DSpL1- providing test signals DR+ and DR- with opposite polarities, the second test signal line DSpL2 is divided into two test signal lines DSpL2+ and DSpL2- providing test signals DG+ and DG- with opposite polarities, and the third test signal line DSpL3 is divided into two test signal lines DSpL3+ and DSpL3- providing test signals DB+ and DB- with opposite polarities. The two test signal lines DSpL1+ and DSpL1- are provided with test signals DR+ and DR- with opposite polarities for the first sub-pixels Sp1 in two adjacent columns of pixel units PX, the two test signal lines DSpL2+ and DSpL2- are provided with test signals DG+ and DG- with opposite polarities for the second sub-pixels Sp2 in two adjacent columns of pixel units PX, and the two test signal lines DSpL3+ and DSpL3- are provided with test signals DB+ and DB- with opposite polarities for the third sub-pixels Sp3 in two adjacent columns of pixel units PX. The present disclosure does not impose any specific limitation on this.

[0109] The switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 need to extend from the first side SP of the peripheral area PA along the fourth side GO to the second side SO opposite to the first side SP. Therefore, the lengths of the switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 are too long, and at the places where the extension directions of the switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 are changed (i.e., at the first corner CR1 and / or the second corner CR2, as shown in FIG. Figure 7 The portion within the dotted box in the middle) is prone to electrostatic discharge (ESD), which can cause abnormal function of the signal line, causing the functional connection holes and wiring inside the display substrate to burn out, resulting in poor display and affecting product yield.

[0110] like Figure 6a As shown in the cross-sectional view, in some embodiments of the present disclosure, taking the second test signal line DSpL2 as an example, the switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2 and the third test signal line DSpL3 are at the place where the extension direction changes (i.e., at the first corner CR1 and / or the second corner CR2, as shown in FIG. Figure 7 The part within the dotted box in the figure has a similar structure.

[0111] In some embodiments of the present disclosure, Figure 6a As shown, the display substrate includes a base substrate BS; a first conductive layer CT1, which is located on the base substrate BS and has a first opening AP1 therein; a gate insulating layer GI, which is located on a side of the first conductive layer CT1 away from the base substrate BS and is located in the first opening AP1; a passivation layer PVX, which is located on a side of the gate insulating layer GI away from the base substrate BS; a second opening AP2 and a third opening AP3, which extend through the gate insulating layer GI and the passivation layer PVX. The orthographic projection of the first opening AP1 on the base substrate BS does not overlap with the orthographic projection of the second opening AP2 on the base substrate BS at least partially. The orthographic projection of the first opening AP1 on the base substrate BS does not overlap with the orthographic projection of the third opening AP3 on the base substrate BS at least partially. The display substrate also includes a second conductive layer CT2, which is located on a side of the passivation layer PVX away from the base substrate BS and covers the second opening AP2 and the third opening AP3 to contact the first conductive layer CT1.

[0112] In some embodiments of the present disclosure, each test signal line (a first test signal line DSpL1, a second test signal line DSpL2 or a third test signal line DSpL3) includes a first portion located at the first conductive layer CT1 and a second portion located at the second conductive layer CT2; the switch signal line SWL includes a first portion located at the first conductive layer CT1 and a second portion located at the second conductive layer CT2; the first opening AP1, the second opening AP2 and the third opening AP3 are located at the first corner CR1 and the second corner CR2.

[0113] In some embodiments of the present disclosure, the first opening AP1 divides the first conductive layer CT1 into two parts disconnected from each other, and the two parts are electrically insulated by the part of the gate insulating layer GI located in the first opening AP1, and are connected together by the second conductive layer CT2 at the second opening AP2 and the third opening AP3, thereby realizing the connection of the second test signal line DSpL2 at the second corner CR2. In this way, it is possible to avoid the switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 from having abnormal signal line functions caused by electrostatic discharge (ESD) at the point where the extension direction changes (i.e., at the first corner CR1 and / or the second corner CR2), avoid burning out the functional connection holes and wiring inside the display substrate, avoid display defects, and thus improve product yield.

[0114] In some embodiments of the present disclosure, Figure 6a As shown, the distance D between the two parts of the first conductive layer CT1 separated by the first opening AP1 is greater than or equal to 20 um.

[0115] In some embodiments of the present disclosure, various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer CT1. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer CT1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0116] In some embodiments of the present disclosure, examples of suitable second conductive layer CT2 materials include, but are not limited to, metal conductive electrode materials and non-metal conductive electrode materials. Examples of suitable metal conductive electrode materials include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or laminates thereof. Examples of suitable non-metal conductive electrode materials include, but are not limited to, various transparent metal oxide electrode materials and transparent carbon nanotubes. Examples of transparent metal oxide materials include, but are not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO).

[0117] In some embodiments of the present disclosure, examples of materials of the gate insulating layer GI and the passivation layer PVX include various appropriate resin materials, polyimide, silicon oxide (SiOy), silicon nitride (SiNy, such as Si3N4), and silicon oxynitride (SiOxNy).

[0118] In some embodiments of the present disclosure, the switch signal line SWL, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 have lost their functions after the inspection test process, which is equivalent to a floating signal line. After the MDL process, when in use, the first test signal line DSpL1, the second test signal line DSpL2, and the third test signal line DSpL3 are all connected to the ground (GND) signal, and the switch signal line SWL is connected to the low level signal (VGL) to completely turn off the switch transistor STFT to prevent crosstalk between signals and avoid abnormal screen display caused by possible signal coupling.

[0119] exist Figures 4a to 7 In the embodiment shown, the switch transistor STFT is arranged on the second side SO opposite to the first side SP where the source driving circuit SIC is located, and the test signal line and the switch signal line SWL are both led to the second side SO, thereby avoiding the wiring difficulty caused by the small space on the first side SP and effectively utilizing the space on the second side SO. Furthermore, the uniform film thickness of the entire display substrate can be achieved.

[0120] Figure 8 Schematic diagram showing the structure of a display substrate in some embodiments of the present disclosure. Figure 8 As shown, along the first direction DR1, Figure 8 The first column of pixel units PX and the Mth column of pixel units PX are shown in sequence. Along the second direction DR2, Figure 8 Q rows of pixel units PX are shown in sequence, including the 1st row of pixel units PX, the 2nd row of pixel units PX, ..., the (2q-1)th row of pixel units PX, the (2q)th row of pixel units PX, ..., the (Q-1)th row of pixel units PX, and the Qth row of pixel units PX. Wherein, Q is a positive integer greater than or equal to 1, and 1≤q≤Q / 2. Figure 8 In some embodiments, in addition to Figure 3 In the structure shown, the display substrate further includes a plurality of switching transistors STFT, each of which is arranged at one end of a gate line GL (a first gate line GL1 or a second gate line GL2) connected to a row of pixel units PX, and the other end of the gate line is connected to a gate driving circuit GIC. Figure 8In the embodiment, each switch transistor STFT is arranged at one end of a first gate line GL1 connected to a row of pixel units PX, and the other end of the first gate line GL1 is connected to a gate drive circuit GIC. In an alternative embodiment, each switch transistor STFT is arranged at one end of a second gate line GL2 connected to a row of pixel units PX, and the other end of the second gate line GL2 is connected to a gate drive circuit GIC.

[0121] In some embodiments of the present disclosure, Figure 8 As shown, the display substrate further includes a switch signal terminal SW, which is disposed at the third side GP of the peripheral area PA and close to the second side SO (i.e., located at the third corner CR3 of the peripheral area PA) and is configured to provide a switch signal to each switch transistor STFT through a switch signal line SWL. In some embodiments of the present disclosure, as Figure 8 As shown, one end of the switching signal line SWL is connected to the switching signal terminal SW, and extends from the switching signal terminal SW along the second direction DR2 toward the second side SO to the third corner CR3, and then extends from the third corner CR3 to the second corner CR2 along the second side SO, and further extends from the second corner CR2 along the fourth side GO to be connected to each switching transistor STFT, and control the switching of the switching transistor STFT by providing a switching signal to each switching transistor STFT.

[0122] In some embodiments of the present disclosure, at least one test signal terminal includes a first test signal terminal DO, which is arranged at a position of the gate driving circuit GIC on the first side of the peripheral area PA close to the third corner CR3; and a second test signal terminal DE, which is arranged at a position of the gate driving circuit GIC on the first side of the peripheral area PA close to the third corner CR3; one or more test signal lines include a first test signal line DOL and a second test signal line DEL.

[0123] In some embodiments of the present disclosure, Figure 8 As shown, the first test signal terminal DO is disposed at the third side GP of the peripheral area PA and close to the second side SO (ie, located at the third corner CR3 of the peripheral area PA), and is configured to provide a first test signal DOS to the odd-numbered pixel units PX through the first test signal line DOL.

[0124] In some embodiments of the present disclosure, Figure 8 As shown, the second test signal terminal DE is arranged at the third side GP of the peripheral area PA and close to the second side SO (ie, located at the third corner CR3 of the peripheral area PA), and is configured to provide a second test signal DES to the even-numbered pixel units PX through the second test signal line DEL.

[0125] In the prior art, the first test signal line DOL or the second test signal line DEL sequentially provides a test signal to all column pixel units PX from one side of the display substrate to the other side of the display substrate (eg, from the second side SO to the first side SP). Figure 5 The schematic diagram shows that the signal line resistance is too large, which leads to signal attenuation. Figure 5 As shown, as the distance between signal lines increases, the resistance of the signal lines becomes larger and larger. Therefore, in the prior art, a single-sided input test signal will cause signal attenuation, thereby causing display abnormalities (i.e., inconsistent displays) on both sides (the first side SP and the second side SO) of the display substrate.

[0126] In some embodiments of the present disclosure, Figure 8 As shown, one end of the first test signal line DOL is connected to the first test signal terminal DO, and extends from the first test signal terminal DO along the second direction DR2 toward the second side SO to the third corner CR3, and then extends from the third corner CR3 to the second corner CR2 along the second side SO, and further, extends from the second corner CR2 to the first point O near the center of the display substrate along the fourth side GO. In some embodiments of the present disclosure, as Figure 8 As shown, the first test signal line DOL is divided into a plurality of branches at the first point O on the fourth side GO of the peripheral area PA, and each branch is connected to a switch transistor STFT located in an odd row. In this way, the switch transistors STFT of all odd rows are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO, so that the first test signal DOS is transmitted to the upper and lower sides (the first side SP and the second side SO) of the display substrate at the same time, avoiding display abnormality (i.e., display inconsistency) on the upper and lower sides (the first side SP and the second side SO) of the display substrate caused by the gradual attenuation of the first test signal DOS.

[0127] like Figure 8 As shown, the first test signal line DOL is divided into two branches at the first point O on the fourth side GO of the peripheral area PA, namely, a first branch OL1 and a second branch OL2, the first branch OL1 extends along the second direction DR2 toward the second side SO, and the second branch OL2 extends along the second direction DR2 toward the first side SP. The display substrate further includes a plurality of first lead lines OLL, each of which extends along the first direction DR1, and one end of each of the first lead lines OLL is connected to a switch transistor STFT located in an odd-numbered row, and the other end of each of the first lead lines OLL is connected to a corresponding position of a corresponding branch, as shown in FIG. Figure 8 In this way, the corresponding positions where each first lead line OLL is connected to the first branch OL1 and the second branch OL2 are arranged in mirror symmetry with respect to the first point O.

[0128] In some embodiments of the present disclosure, Figure 8 As shown, in each odd row, the gate driving circuit GIC is connected to one end of each first gate line GL1, each first gate line GL1 is connected to a row of pixel units PX, and then connected to a switch transistor STFT, and the switch transistor STFT is connected to the corresponding branch through the corresponding first lead OLL, and then connected to the first point O near the center of the display substrate, all the first lead lines OLL converge into a first test signal line DOL at the first point O through the first branch OL1 and the second branch OL2, and the first test signal line DOL extends from the first point O along the fourth side GO, the second side SO and the third side GP to the first test signal terminal DO. In some embodiments of the present disclosure, as Figure 8 As shown, the first test signal DOS from the first test signal terminal DO and the gate driving signal from the gate driving circuit GIC are provided to each row of pixel units PX through the same first gate line GL1.

[0129] In some embodiments of the present disclosure, there are O odd-numbered rows of switch transistors STFT and P even-numbered rows of switch transistors STFT, where O+P=Q. O is a positive integer greater than or equal to 1, and P is a positive integer greater than or equal to 1.

[0130] In some embodiments of the present disclosure, all odd-numbered rows of switch transistors STFT (i.e., O odd-numbered rows of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO. For example, the first odd-numbered row of switch transistors STFT (i.e., the 1st row of switch transistors STFT in the Q rows of switch transistors STFT) and the last odd-numbered row of switch transistors STFT (i.e., the Qth row of switch transistors STFT or the (Q-1)th row of switch transistors STFT in the Q rows of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO, and the second odd-numbered row of switch transistors STFT (i.e., the 3rd row of switch transistors STFT in the Q rows of switch transistors STFT) and the second-to-last odd-numbered row of switch transistors STFT (i.e., the Qth row of switch transistors STFT or the (Q-1)th row of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO. The (Q-2)th row of switching transistors STFT or the (Q-3)th row of switching transistors STFT in the body transistor STFT are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO, ..., when O is an odd number, the (O+1) / 2th odd row of switching transistors STFT is located on the straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO; when O is an even number, the O / 2th odd row of switching transistors STFT and the (O+2) / 2th odd row of switching transistors STFT are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO. In this way, the switching transistors STFT of all odd rows (i.e., the switching transistors STFT of O odd rows) are arranged in mirror symmetry with respect to a straight line passing through the first point O and perpendicular to the third side GP and the fourth side GO, so that the first test signal DOS is simultaneously transmitted to the upper and lower sides (the first side SP and the second side SO) of the display substrate, thereby avoiding abnormal display (i.e., inconsistent display) on the upper and lower sides (the first side SP and the second side SO) of the display substrate caused by the gradual attenuation of the first test signal DOS.

[0131] Similarly, in some embodiments of the present disclosure, Figure 8 As shown, one end of the second test signal line DEL is connected to the second test signal terminal DE, and extends from the second test signal terminal DE along the second direction DR2 toward the second side SO to the third corner CR3, and then extends from the third corner CR3 to the second corner CR2 along the second side SO, and further, extends from the second corner CR2 to the second point E near the center of the display substrate along the fourth side GO. In some embodiments of the present disclosure, as Figure 8As shown, the second test signal line DEL is divided into a plurality of branches at the second point E on the fourth side GO of the peripheral area PA, and each branch is connected to a switch transistor STFT located in an even-numbered row. In this way, the switch transistors STFT of all even-numbered rows are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO, so that the second test signal DES is transmitted to the upper and lower sides (the first side SP and the second side SO) of the display substrate at the same time, avoiding abnormal display (i.e., inconsistent display) on the upper and lower sides (the first side SP and the second side SO) of the display substrate caused by the gradual attenuation of the second test signal DES.

[0132] like Figure 8 As shown, the second test signal line DEL is divided into two branches at the fourth side GO of the peripheral area PA at the second point E, namely, a first branch EL1 and a second branch EL2, the first branch EL1 extends toward the second side SO along the second direction DR2, and the second branch EL2 extends toward the first side SP along the second direction DR2. The display substrate further includes a plurality of second lead lines ELL, each of which extends along the first direction DR1, and one end of each of the second lead lines ELL is connected to a switch transistor STFT located in an even-numbered row, and the other end of each of the second lead lines ELL is connected to a corresponding position of a corresponding branch, as shown in FIG. Figure 8 In this way, the corresponding positions where the second leads ELL are connected to the first branch EL1 and the second branch EL2 are arranged in a mirror-symmetrical manner about the second point E.

[0133] In some embodiments of the present disclosure, Figure 8 As shown, in each even-numbered row, the gate driving circuit GIC is connected to one end of each first gate line GL1, each first gate line GL1 is connected to a row of pixel units PX, and then connected to a switch transistor STFT, and the switch transistor STFT is connected to the corresponding branch through the corresponding second lead ELL, and then connected to the second point E near the center of the display substrate, and all the second lead lines ELL converge into a second test signal line DEL at the second point E through the first branch EL1 and the second branch EL2, and the second test signal line DEL extends from the second point E along the fourth side GO, the second side SO and the third side GP to the second test signal terminal DE. In some embodiments of the present disclosure, as Figure 8 As shown, the second test signal DES from the second test signal terminal DE and the gate driving signal from the gate driving circuit GIC are provided to each row of pixel units PX through the same first gate line GL1.

[0134] In some embodiments of the present disclosure, all the switch transistors STFTs of the even-numbered rows (i.e., the switch transistors STFTs of the P even-numbered rows) are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO. For example, the first switch transistor STFT of the even-numbered row (i.e., the 2nd switch transistor STFT of the Q-numbered row of switch transistors STFT) and the last switch transistor STFT of the even-numbered row (i.e., the Qth switch transistor STFT of the Q-numbered row of switch transistors STFT or the (Q-1)th switch transistor STFT of the Q-numbered row of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO, and the second switch transistor STFT of the even-numbered row (i.e., the 4th switch transistor STFT of the Q-numbered row of switch transistors STFT) and the second-to-last switch transistor STFT of the even-numbered row (i.e., the Qth switch transistor STFT of the Q-numbered row of switch transistors STFT) are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO. The (Q-2)th row of switching transistors STFT or the (Q-3)th row of switching transistors STFT in the body transistor STFT are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO, ..., when P is an odd number, the (P+1) / 2th even row of switching transistors STFT is located on a straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO; when P is an even number, the P / 2th even row of switching transistors STFT and the (P+2) / 2th even row of switching transistors STFT are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO. In this way, the switching transistors STFT of all even-numbered rows (i.e., the switching transistors STFT of P even-numbered rows) are arranged in mirror symmetry with respect to a straight line passing through the second point E and perpendicular to the third side GP and the fourth side GO, so that the second test signal DES is simultaneously transmitted to the upper and lower sides (the first side SP and the second side SO) of the display substrate, thereby avoiding display abnormalities (i.e., inconsistent displays) on the upper and lower sides (the first side SP and the second side SO) of the display substrate caused by the gradual attenuation of the second test signal DES.

[0135] exist Figure 8In the embodiment shown, the Q-row pixel units PX are divided into odd-row pixel units PX and even-row pixel units PX that are alternately arranged in sequence, and two test signal lines (i.e., a first test signal line DOL and a second test signal line DEL) are set to provide a first test signal DOS to the odd-row pixel units PX and a second test signal DES to the even-row pixel units PX, respectively, to perform an inspection test process. In an alternative embodiment, the same test signal can be provided to the Q-row pixel units PX at the same time through the same test signal line to perform an inspection test process. In an alternative embodiment, three test signal lines can also be set for each color of the sub-pixel unit to control the sub-pixels of the same color in each row of pixel units PX, respectively. That is, the first test signal line is connected to all the first sub-pixels Sp1 in each row of pixel units PX to control them, the second test signal line is connected to all the second sub-pixels Sp2 in each row of pixel units PX to control them, and the third test signal line is connected to all the third sub-pixels Sp3 in each row of pixel units PX to control them. Specifically, a first switch transistor STFT and a first connection line are set for all first sub-pixels Sp1 in each row of pixel units PX, a second switch transistor STFT and a second connection line are set for all second sub-pixels Sp2 in each row of pixel units PX, and a third switch transistor STFT and a third connection line are set for all third sub-pixels Sp3 in each row of pixel units PX. The first switch transistor STFT, the second switch transistor STFT, and the third switch transistor STFT are respectively connected to three test signal lines, and test signals are provided to the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 through the first connection line, the second connection line, and the third connection line to perform an inspection test process. In an alternative embodiment, in an LCD product using dual-gate (DRD) driving technology, DY / DC / DM test signals can also be provided to the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3. In an alternative embodiment, six test signal lines may be provided, that is, test signals DR+ and DR- with opposite polarities are provided for the adjacent first sub-pixel Sp1, test signals DG+ and DG- with opposite polarities are provided for the adjacent second sub-pixel Sp2, and test signals DB+ and DB- with opposite polarities are provided for the adjacent third sub-pixel Sp3. The present disclosure does not impose any specific limitation on this.

[0136] The switch signal line SWL, the first test signal line DOL, and the second test signal line DEL need to extend from the third side GP of the peripheral area PA along the second side SO to the fourth side GO opposite to the third side GP. Therefore, the lengths of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are too long, and at the location where the extension directions of the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are changed (i.e., at the third corner portion CR3 and / or the second corner portion CR2, as shown in FIG. Figure 8 The portion within the dotted box in the middle) is prone to electrostatic discharge (ESD), which can cause abnormal function of the signal line, causing the functional connection holes and wiring inside the display substrate to burn out, resulting in poor display and affecting product yield.

[0137] The switch signal line SWL, the first test signal line DOL, and the second test signal line DEL are located at a position where the extension direction changes (ie, at the third corner portion CR3 and / or the second corner portion CR2, as shown in FIG. Figure 8 The portion within the dotted box has Figure 6a The structure is similar to that shown in FIG. Among them, the first opening AP1, the second opening AP2 and the third opening AP3 are located at the second corner CR2 and the third corner CR3. In this way, it is possible to avoid abnormal signal line function caused by electrostatic discharge (ESD) at the switch signal line SWL, the first test signal line DOL and the second test signal line DEL at the point where the extension direction changes (i.e., at the third corner CR3 and / or the second corner CR2), avoid burning of the functional connection holes and wiring inside the display substrate, avoid display defects, and thus improve product yield.

[0138] In some embodiments of the present disclosure, the switch signal line SWL, the first test signal line DOL, and the second test signal line DEL have lost their functions after the inspection test process, which is equivalent to a floating signal line. After the MDL process, when in use, the first test signal line DOL and the second test signal line DEL are both connected to the ground (GND) signal, and the switch signal line SWL is connected to the low level signal (VGL) to completely turn off the switch transistor STFT to prevent crosstalk between signals and avoid abnormal screen display caused by possible signal coupling.

[0139] exist Figure 8 In the embodiment shown, the switch transistor STFT is arranged on the fourth side GO opposite to the third side GP where the gate drive circuit GIC is located, and the test signal line and the switch signal line SWL are both led to the fourth side GO, thereby avoiding the wiring difficulties caused by the small space on the third side GP and effectively utilizing the space on the fourth side GO. Furthermore, the uniform film thickness of the entire display substrate can be achieved.

[0140] In another aspect, the present disclosure provides a display device, including a display substrate as described herein or manufactured by a method as described herein, and one or more integrated circuits connected to the display substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a liquid crystal display device.

[0141] In another aspect, the present disclosure provides a method for testing the display substrate described herein. Fig. 9 A flow chart of a method for testing a display substrate according to some embodiments of the present disclosure is shown. Fig. 9 As shown, the method includes an inspection test phase: in the inspection test phase, a test signal is provided to the one or more test signal lines through the at least one test signal terminal, and the test signal is transmitted to the corresponding pixel driving circuit through the one or more test signal lines to test the display substrate; and after the inspection test phase, the at least one test signal terminal is bound and connected to a corresponding terminal of a driving circuit to provide a ground signal to the one or more test signal lines through the at least one test signal terminal through the driving circuit during the display phase of the display substrate.

[0142] In some embodiments of the present disclosure, the display substrate further comprises: a switch signal terminal, which is arranged on the same side as the at least one test signal terminal; a switch signal line, which extends in the peripheral area and is connected to the switch signal terminal; and a plurality of switch transistors, which are connected to the switch signal line, the one or more test signal lines and the corresponding pixel drive circuit; wherein the method further comprises: in the inspection test phase, providing a switch signal from the switch signal terminal to the plurality of switch transistors through the switch signal line, thereby controlling the one or more test signal lines to provide the test signal to the corresponding pixel drive circuit during the inspection test phase; and after the inspection test phase, binding the switch signal terminal to the corresponding terminal of the drive circuit, so as to provide a low level signal to the switch signal line through the switch signal terminal through the drive circuit during the display phase of the display substrate. The above description of the embodiments of the present invention has been given for the purpose of illustration and description. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiment disclosed. Therefore, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and changes will be obvious to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be limited by the attached claims and their equivalents, wherein all terms are meant to be their broadest reasonable meaning unless otherwise stated. Therefore, the term "the invention, the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiment of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the attached claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature and should not be interpreted as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that without departing from the scope of the present invention defined by the attached claims, those skilled in the art may make changes to the described embodiments. In addition, the elements and components in this disclosure are not intended to be contributed to the public, regardless of whether the element or component is explicitly stated in the attached claims.

Claims

1. A display substrate having a display area and a peripheral area arranged around the display area, and comprising: A plurality of grid lines extending along a first direction; A plurality of data lines extending along a second direction; At least two driving circuits are located in the peripheral area and are configured to provide gate driving signals and source driving signals to a plurality of pixel driving circuits arranged in an array including a plurality of rows and columns located in the display area through the plurality of gate lines and the plurality of data lines; one or more test signal lines located in the peripheral area and extending to a side opposite to a corresponding one of the at least two drive circuits, each test signal line including a plurality of branches at a point on the side, each branch extending from the point to be connected to a corresponding pixel drive circuit, thereby providing a test signal to the corresponding pixel drive circuit during an inspection test; as well as At least one test signal terminal is configured to provide the test signal to the one or more test signal lines.

2. The display substrate according to claim 1, wherein: The peripheral region includes a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, wherein the first side connects the third side and the fourth side, and the second side connects the third side and the fourth side; and The peripheral area includes a first corner located between the first side and the fourth side, a second corner located between the second side and the fourth side, a third corner located between the second side and the third side, and a fourth corner located between the first side and the third side.

3. The display substrate according to claim 2, wherein: The at least two driving circuits include a source driving circuit located at the first side of the peripheral area and configured to provide the source driving signal to the pixel driving circuits in the same column located in the display area through corresponding data lines; The at least one test signal terminal includes a first test signal terminal, which is arranged at a position of the source driving circuit on the first side of the peripheral area close to the first corner; and a second test signal terminal disposed at a position of the source driving circuit on the first side of the peripheral region close to the first corner; The one or more test signal lines include a first test signal line and a second test signal line; One end of the first test signal line is connected to the first test signal terminal, and extends from the first test signal terminal along the fourth side from the first corner to the second corner, and along the second side from the second corner to a first point located on the second side of the peripheral area; One end of the second test signal line is connected to the second test signal terminal, and extends from the second test signal terminal along the fourth side from the first corner to the second corner, and along the second side from the second corner to a second point located on the second side of the peripheral area; The first test signal line is configured to provide the odd-numbered column pixel driving circuit with a first test signal from the first test signal terminal during an inspection test; as well as The second test signal line is configured to provide the second test signal from the second test signal terminal to the even-numbered column pixel driving circuit during the inspection test.

4. The display substrate according to claim 3, wherein: The first test signal line is divided into a plurality of branches at the first point located on the second side of the peripheral area, each branch being connected to a corresponding data line to provide the first test signal to the same odd-numbered column pixel driving circuit during the inspection test; as well as The second test signal line is divided into a plurality of branches at the second point located on the second side of the peripheral area, and each branch is connected to a corresponding data line to provide the second test signal to the same even-numbered column pixel driving circuit during the inspection test.

5. The display substrate according to claim 4, wherein: The data line connected to each branch of the first test signal line provides the first test signal from the first test signal terminal and the source driving signal from the source driving circuit to the same odd-numbered column pixel driving circuit; as well as The data line connected to each branch of the second test signal line provides the second test signal from the second test signal terminal and the source driving signal from the source driving circuit to the pixel driving circuit in the same even column.

6. The display substrate according to claim 5, wherein: All odd-numbered column pixel driving circuits are arranged in mirror symmetry with respect to a straight line passing through the first point and perpendicular to the first side and the second side; and All the pixel driving circuits in even columns are arranged in mirror symmetry with respect to a straight line passing through the second point and perpendicular to the first side and the second side.

7. The display substrate according to claim 2, wherein: The display substrate includes a plurality of sub-pixels arranged in an array in a plurality of rows and columns in the display area, and the plurality of sub-pixels are arranged in a one-to-one correspondence with the plurality of pixel driving circuits; the plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel; The at least two driving circuits include a source driving circuit located at the first side of the peripheral area and configured to provide the source driving signal to the pixel driving circuits in the same column located in the display area through corresponding data lines; The at least one test signal terminal includes a first sub-pixel test signal terminal, which is arranged at a position of the source driving circuit on the first side of the peripheral area close to the first corner; a second sub-pixel test signal terminal, which is disposed at a position of the source driving circuit on the first side of the peripheral area close to the first corner; and a third sub-pixel test signal terminal, which is disposed at a position of the source driving circuit on the first side of the peripheral area close to the first corner; The one or more test signal lines include a first sub-pixel test signal line, a second sub-pixel test signal line, and a third sub-pixel test signal line; One end of the first sub-pixel test signal line is connected to the first sub-pixel test signal terminal, and extends from the first sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and extends from the second corner along the second side to a first point located on the second side of the peripheral area; One end of the second sub-pixel test signal line is connected to the second sub-pixel test signal terminal, and extends from the second sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and extends from the second corner along the second side to a second point located on the second side of the peripheral area; One end of the third sub-pixel test signal line is connected to the third sub-pixel test signal terminal, and extends from the third sub-pixel test signal terminal along the fourth side from the first corner to the second corner, and extends along the second side from the second corner to a third point located on the second side of the peripheral area; The first sub-pixel test signal line is configured to provide a first test signal from the first sub-pixel test signal terminal to all column pixel driving circuits corresponding to the first sub-pixel during an inspection test; The second sub-pixel test signal line is configured to provide a second test signal from the second sub-pixel test signal terminal to all column pixel driving circuits corresponding to the second sub-pixel during an inspection test; as well as The third sub-pixel test signal line is configured to provide a third test signal from the third sub-pixel test signal terminal to all column pixel driving circuits corresponding to the third sub-pixel during an inspection test.

8. The display substrate according to claim 7, wherein: The first sub-pixel test signal line is divided into a plurality of branches at the first point located on the second side of the peripheral area, each branch being connected to a corresponding data line, so as to provide the first test signal from the first sub-pixel test signal terminal to a corresponding column of pixel driving circuits corresponding to the first sub-pixel during an inspection test; The second sub-pixel test signal line is divided into a plurality of branches at the second point located on the second side of the peripheral area, each branch being connected to a corresponding data line, so as to provide the second test signal from the second sub-pixel test signal terminal to a corresponding column of pixel driving circuits corresponding to the second sub-pixel during the inspection test process; as well as The third sub-pixel test signal line is divided into a plurality of branches at the third point located on the second side of the peripheral area, and each branch is connected to a corresponding data line to provide the third test signal from the third sub-pixel test signal terminal to a corresponding column of pixel driving circuits corresponding to the third sub-pixel during the inspection test.

9. The display substrate according to claim 8, wherein: The data line connected to each branch of the first sub-pixel test signal line provides the first test signal from the first sub-pixel test signal terminal and the source drive signal from the source drive circuit to a corresponding column of pixel drive circuits corresponding to the first sub-pixel; The data line connected to each branch of the second sub-pixel test signal line provides the second test signal from the second sub-pixel test signal terminal and the source drive signal from the source drive circuit to a corresponding column of pixel drive circuits corresponding to the second sub-pixel; as well as The data line connected to each branch of the third sub-pixel test signal line provides the third test signal from the third sub-pixel test signal terminal and the source drive signal from the source drive circuit to a corresponding column of pixel drive circuits corresponding to the third sub-pixel.

10. The display substrate according to claim 9, wherein: All column pixel driving circuits corresponding to the first sub-pixel are arranged in mirror symmetry with respect to a straight line passing through the first point and perpendicular to the first side and the second side; All column pixel driving circuits corresponding to the second sub-pixel are arranged in mirror symmetry with respect to a straight line passing through the second point and perpendicular to the first side and the second side; and All column pixel driving circuits corresponding to the third sub-pixel are arranged in mirror symmetry with respect to a straight line passing through the third point and perpendicular to the first side and the second side.

11. The display substrate according to claim 2, wherein: The at least two driving circuits include a gate driving circuit located at the third side of the peripheral area and configured to provide the gate driving signal to the pixel driving circuits in the same row located in the display area through corresponding gate lines; The at least one test signal terminal includes a first test signal terminal disposed at a position of the gate drive circuit on the first side of the peripheral region close to the third corner; and a second test signal terminal disposed at a position of the gate drive circuit on the first side of the peripheral region close to the third corner; The one or more test signal lines include a first test signal line and a second test signal line; One end of the first test signal line is connected to the first test signal terminal, and extends from the first test signal terminal along the second side from the third corner to the second corner, and along the fourth side from the second corner to a first point located on the fourth side of the peripheral area; One end of the second test signal line is connected to the second test signal terminal, and extends from the second test signal terminal along the second side from the third corner to the second corner, and along the fourth side from the second corner to a second point located on the fourth side of the peripheral area; The first test signal line is configured to provide the odd-row pixel driving circuit with a first test signal from the first test signal terminal during the inspection test; as well as The second test signal line is configured to provide the second test signal from the second test signal terminal to the pixel driving circuit of the even-numbered rows during the inspection test.

12. The display substrate according to claim 11, wherein: The first test signal line is divided into a plurality of branches at the first point located on the fourth side of the peripheral area, each branch being connected to a corresponding gate line to provide the first test signal to the same odd-numbered row pixel driving circuit during the inspection test; as well as The second test signal line is divided into a plurality of branches at the second point located on the fourth side of the peripheral area, and each branch is connected to a corresponding gate line to provide the second test signal to the same even-numbered row pixel driving circuit during the inspection test.

13. The display substrate according to claim 12, wherein: The gate line connected to each branch of the first test signal line provides the first test signal from the first test signal terminal and the gate drive signal from the gate drive circuit to the same odd-numbered row pixel drive circuit; as well as The gate line connected to each branch of the second test signal line provides the second test signal from the second test signal terminal and the gate drive signal from the gate drive circuit to the pixel drive circuit in the same even-numbered row.

14. The display substrate according to claim 13, wherein: All odd-numbered-row pixel driving circuits are arranged in mirror symmetry with respect to a straight line passing through the first point and perpendicular to the third side and the fourth side; and All pixel driving circuits in even-numbered rows are arranged in mirror symmetry with respect to a straight line passing through the second point and perpendicular to the third side and the fourth side.

15. The display substrate according to any one of claims 2 to 14, further comprising a switch signal terminal, which is arranged on the same side as the at least one test signal terminal; a switch signal line extending in the peripheral region and connected to the switch signal terminal; as well as a plurality of switch transistors connected to the switch signal line, the one or more test signal lines and corresponding pixel drive circuits; The plurality of switch transistors are configured to control the one or more test signal lines to provide the test signal to the corresponding pixel driving circuit during an inspection test by using a switch signal provided by the switch signal line.

16. The display substrate according to claim 15, further comprising: substrate substrate; A first conductive layer, which is located on the base substrate and has a first opening therein; a gate insulating layer, which is located on a side of the first conductive layer away from the base substrate and is located in the first opening; A passivation layer, located on a side of the gate insulating layer away from the substrate; a second opening and a third opening extending through the gate insulating layer and the passivation layer; as well as A second conductive layer, which is located on a side of the passivation layer away from the base substrate and covers the second opening and the third opening to contact the first conductive layer; Wherein, the orthographic projection of the first opening on the base substrate and the orthographic projection of the second opening on the base substrate at least partially do not overlap; The orthographic projection of the first opening on the substrate and the orthographic projection of the third opening on the substrate at least partially do not overlap; and The distance between the two parts of the first conductive layer disconnected by the first opening is greater than or equal to 20 um; wherein each of the one or more test signal lines comprises a first portion and a second portion; The switch signal line includes a first portion and a second portion; A first portion of each test signal line and a first portion of the switch signal line are located in the first conductive layer; and The second portion of each test signal line and the second portion of the switch signal line are located in the second conductive layer; and The first opening, the second opening, and the third opening are located at the first corner and the second corner, or at the second corner and the third corner.

17. A display device comprising the display substrate according to any one of claims 1 to 16, and one or more integrated circuits connected to the display substrate.

18. A method for testing a display substrate according to any one of claims 1 to 16, the method comprising an inspection test phase: In the inspection test phase, a test signal is provided to the one or more test signal lines through the at least one test signal terminal, and the test signal is transmitted to a corresponding pixel driving circuit through the one or more test signal lines to test the display substrate; and After the inspection test phase, the at least one test signal terminal is bound and connected to a corresponding terminal of a driving circuit to provide a ground signal to the one or more test signal lines through the at least one test signal terminal via the driving circuit during the display phase of the display substrate.

19. The method according to claim 18, wherein: The display substrate further comprises: a switch signal terminal, which is arranged on the same side as the at least one test signal terminal; a switch signal line extending in the peripheral region and connected to the switch signal terminal; and a plurality of switch transistors connected to the switch signal line, the one or more test signal lines and corresponding pixel drive circuits; The method further comprises: providing a switch signal from the switch signal end to the plurality of switch transistors via the switch signal line during the inspection test phase, thereby controlling the one or more test signal lines to provide the test signal to the corresponding pixel driving circuit during the inspection test phase; and After the inspection test phase, the switch signal end is bound and connected to a corresponding terminal of the drive circuit, so that during the display phase of the display substrate, the drive circuit provides a low level signal to the switch signal line through the switch signal end.

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