A read / write circuit for a multi-valued dynamic memory cell based on OTS

Abstract

This application discloses a read / write circuit for a multi-value dynamic storage unit (MWS) based on an OTS, relating to the field of memory read / write circuit technology. The circuit includes a write control module and a read control module, both connected to the OTS-based MWS. Under the control of a write control signal, the write control module generates different write operation voltages based on a reference voltage and multiple input signals, and applies them to the two ends of the storage unit's capacitor, thus realizing the write operation of the MWS. Under the action of a read control signal, the read control module reads four storage states of the storage unit and outputs them in a four-bit encoded form. This application can generate different write operation voltages by adjusting the values ​​of each input signal, which can be used as write voltages for different states of the MWS. Furthermore, the read control module can read different storage states of the storage unit separately and output the read data in a four-bit encoded form.

Description

Technical Field

[0001] This application relates to the field of memory read / write circuit technology, and in particular to a read / write circuit for a multi-value dynamic memory cell based on OTS. Background Technology

[0002] Dynamic memory cells based on OTS (Ovonic Threshold Switch) consist of a gate transistor and a capacitor connected in series. As a two-port device, it offers advantages over traditional DRAM memory, including higher storage density and easier three-dimensional integration. By adjusting the operating voltage applied across the memory cell, it can exhibit four voltage states, thus enabling two-value, four-state multi-value storage. This improves the data storage capacity of a single device without altering its structure. Compared to traditional memory cells, multi-value dynamic memory cells can store multiple bits of information. However, this stored information requires external circuitry for reading and writing. This necessitates that the external read / write circuitry of multi-value memory cells be capable of reading and writing to each state. Existing external read / write circuitry designed for single-value memory cells is unsuitable for multi-value dynamic memory circuits. Therefore, how to construct an external read / write circuit suitable for multi-value dynamic memory circuits to achieve reading and writing to each state is a pressing issue that needs to be addressed. Summary of the Invention

[0003] The purpose of this application is to provide a read / write circuit for a multi-valued dynamic memory cell based on OTS, which can realize read and write operations on the multi-valued dynamic memory cell.

[0004] To achieve the above objectives, this application provides the following solution:

[0005] In a first aspect, this application provides a read / write circuit for a multi-value dynamic storage cell based on an OTS, comprising: a write control module and a read control module. Both the write control module and the read control module are connected to the multi-value dynamic storage cell; the multi-value dynamic storage cell includes: an OTS selector and a storage cell capacitor; the write control module receives a write control signal, a reference voltage, and multiple input signals, and is used to generate a write operation voltage based on the reference voltage and multiple input signals under the control of the write control signal, and apply it to both ends of the storage cell capacitor; the read control module receives a read control signal, and is used to output the operating state of the multi-value dynamic storage cell in a four-bit encoded form under the action of the read control signal.

[0006] Optionally, the read control module includes: a first transistor, a first diode group, a second diode group, a third diode group, a fourth diode group, a first voltage comparison unit, a second voltage comparison unit, a third voltage comparison unit, and a fourth voltage comparison unit.

[0007] The first transistor's control terminal receives a read control signal; the first terminal of the first transistor is connected to the multi-value dynamic storage unit; the second terminal of the first transistor is connected to the anode of the first diode group and the cathode of the third diode group, respectively; the cathode of the first diode group is connected to the anode of the second diode group and the voltage input terminal of the second voltage comparator, respectively; the anode of the third diode group is connected to the cathode of the fourth diode group and the voltage input terminal of the fourth voltage comparator, respectively; the cathode of the second diode group is connected to the voltage input terminal of the first voltage comparator, and the anode of the fourth diode group is connected to the voltage input terminal of the third voltage comparator.

[0008] When the read control signal is high, the read control module starts to work. The first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit and the fourth voltage comparison unit are used to compare the voltage at their respective voltage input terminals with their respective preset voltages and output high or low levels. The outputs of the four voltage comparison units are used to characterize the working state of the multi-value dynamic storage unit.

[0009] Optionally, when the multi-value dynamic storage unit is in a low-voltage state with a positive bias, the first diode group is turned on, and the second, third, and fourth diode groups are turned off, and the first, second, third, and fourth voltage comparison units output 0, 1, 0, and 0, respectively.

[0010] When the multi-value dynamic storage unit is in a high-voltage state with positive bias, the first and second diode groups are turned on, while the third and fourth diode groups are turned off, and the first, second, third, and fourth voltage comparison units output 1, 1, 0, and 0, respectively.

[0011] When the multi-value dynamic storage unit is in a low-voltage state with negative bias, the third diode group is turned on, and the first, second, and fourth diode groups are turned off. The first, second, third, and fourth voltage comparison units output 0, 0, 0, and 1, respectively.

[0012] When the multi-value dynamic storage unit is in a high-voltage state with negative bias, the third and fourth diode groups are turned on, while the first and second diode groups are turned off, and the first, second, third, and fourth voltage comparison units output 0, 0, 1, and 1, respectively.

[0013] Optionally, the write control module includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first inverter, a second inverter, a third inverter, and an operational amplifier.

[0014] The output of the operational amplifier is connected to the multi-value dynamic storage unit; the inverting input of the operational amplifier is connected to the first terminal of the second transistor, the first terminal of the fourth transistor, and the first terminal of the sixth transistor, respectively; the non-inverting input of the operational amplifier is connected to the first terminal of the fourth resistor, the first terminal of the third transistor, the first terminal of the fifth transistor, and the first terminal of the seventh transistor, respectively.

[0015] After the second terminals of the sixth and seventh transistors are connected, they are connected to the first terminal of the first resistor; after the second terminals of the fourth and fifth transistors are connected, they are connected to the first terminal of the second resistor; after the second terminals of the second and third transistors are connected, they are connected to the first terminal of the third resistor; after the second terminals of the fourth and third resistors are connected, they are connected to the first terminal of the fifth resistor; after the second terminals of the second and fifth resistors are connected, they are connected to the first terminal of the sixth resistor; after the second terminal of the sixth resistor is connected to the second terminal of the first resistor, a reference voltage is applied.

[0016] The control terminal of the second transistor is connected to the first input signal, and the control terminal of the third transistor is connected to the first input signal through the first inverter; the control terminal of the fourth transistor is connected to the second input signal, and the control terminal of the fifth transistor is connected to the second input signal through the second inverter; the control terminal of the sixth transistor is connected to the third input signal, and the control terminal of the seventh transistor is connected to the third input signal through the third inverter.

[0017] The inverting input of the operational amplifier is also connected to the write control signal through the seventh resistor, and the non-inverting input of the operational amplifier is also grounded; the two ends of the eighth resistor are connected to the inverting input and the output of the operational amplifier, respectively.

[0018] When the write control module is working, it generates different write operation voltages based on the different values ​​of the reference voltage, the first input signal, the second input signal, and the third input signal, and applies them to the two ends of the memory cell capacitor.

[0019] Optionally, the resistance of the first resistor is 2R, the resistance of the second resistor is 2R, the resistance of the third resistor is 2R, the resistance of the fourth resistor is 2R, the resistance of the fifth resistor is R, the resistance of the sixth resistor is R, and the resistance of the eighth resistor is 2R.

[0020] Optionally, the control signal and the resistance value of the seventh resistor satisfy the following relationship:

[0021] .

[0022] in, V CONTROL To write control signals, R 7 represents the resistance value of the seventh resistor. V ref This is the reference voltage value.

[0023] Optionally, the current flowing through the first resistor is The current flowing through the second resistor is The current flowing through the third resistor is The first input signal, the second input signal, and the third input signal are used to control the current, respectively. IR 1. Current IR 2. Current IR 3. Whether the current can flow into the inverting input of the operational amplifier.

[0024] Optionally, the write control signal and the set current generated by the seventh resistor are... The set current is used to adjust the output voltage of the operational amplifier. V O The absolute values ​​of the maximum positive value and the minimum negative value are equal.

[0025] Optionally, the output voltage of the operational amplifier is as follows:

[0026] .

[0027] in, V O This is the output voltage of the operational amplifier. V ref For reference voltage value, IN 1 is the first input signal. IN 2 is the second input signal. IN 3 is the third input signal.

[0028] Optionally, by adjusting the values ​​of the first, second, and third input signals, eight different output voltages can be generated. V O Two positive voltages and two negative voltages can be selected as the write operation voltages.

[0029] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0030] This application provides a read / write circuit for a multi-value dynamic storage cell based on an OTS (Optical Time Synchronization) module, comprising: a write control module and a read control module, both connected to the OTS-based multi-value dynamic storage cell; the write control module receives a write control signal, a reference voltage, and multiple input signals, and under the control of the write control signal, generates write operation voltages of different values ​​according to the reference voltage and multiple input signals, which are applied to the two ends of the storage cell capacitor to realize the write operation of the multi-value dynamic storage cell; the read control module receives a read control signal, and under the action of the read control signal, reads out four storage states of the storage cell and outputs them in the form of a four-bit code. This application can generate different values ​​of write operation voltage by adjusting the values ​​of each input signal, which can be used as the write voltage for different states of the multi-value dynamic storage cell. In addition, the read control module can read out different storage states of the storage cell separately and output the read data in the form of a four-bit code. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a functional block diagram of a read / write circuit for a multi-value dynamic storage unit based on OTS, provided in one embodiment of this application.

[0033] Figure 2 This is a schematic diagram of the circuit structure of a read / write circuit for a multi-value dynamic storage unit based on OTS, provided in an embodiment of this application.

[0034] Figure label:

[0035] M1 - First transistor; M2 - Second transistor; M3 - Third transistor; M4 - Fourth transistor; M5 - Fifth transistor; M6 - Sixth transistor; M7 - Seventh transistor; D1 - First diode group; D2 - Second diode group; D3 - Third diode group; D4 - Fourth diode group; C1 - Memory cell capacitor; OTS - OTS selector transistor; Q1 - Operational amplifier; INV1 - First inverter; INV2 - Second inverter; INV3 - Third inverter; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; R6 - Sixth resistor; R7 - Seventh resistor; R8 - Eighth resistor; IN 1-First input signal; IN 2-Second input signal; IN 3-Third input signal; Vref -Reference voltage; V CONTROL - Write control signals; V Read_control - Read control signal; OUT1 - Output signal of the first voltage comparison unit; OUT2 - Output signal of the second voltage comparison unit; OUT3 - Output signal of the third voltage comparison unit; OUT4 - Output signal of the fourth voltage comparison unit. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] First, let's introduce the characteristics of the OTS-based dynamic memory cell: The OTS-based multi-value dynamic memory cell consists of an OTS selector and a memory cell capacitor connected in series. The OTS selector has two states: high resistance and low resistance. When the voltage across the OTS selector exceeds the threshold voltage Vth, the OTS selector switches from the high resistance state to the low resistance state. When the voltage across the OTS selector in the low resistance state is lower than the holding voltage Vhold, the OTS selector switches from the low resistance state to the high resistance state. When an operating voltage ±Vin1 (Vin1 amplitude range between Vth and Vth+Vhold) is applied across the OTS-based multi-value dynamic memory cell consisting of the OTS selector and the memory cell capacitor connected in series, the voltage across the memory cell capacitor is maintained at ±(Vin1-Vhold). When an operating voltage ±Vin2 (Vin2 amplitude greater than Vth+Vhold) is applied across the OTS-based multi-value dynamic memory cell consisting of the OTS selector and the memory cell capacitor connected in series, the voltage across the memory cell capacitor is maintained at ±Vhold.

[0039] Based on the characteristics of the multi-value dynamic storage cell based on OTS, the write circuit needs to generate four different write operation voltages to perform write operations on the storage cell, and the read circuit needs to convert the four states of the storage cell into four different codes.

[0040] In one exemplary embodiment, such as Figure 1As shown, a read / write circuit for a multi-valued dynamic storage cell based on an OTS is provided, including a write control module and a read control module. Both the write control module and the read control module are connected to the multi-valued dynamic storage cell; the multi-valued dynamic storage cell includes an OTS selector transistor and a storage cell capacitor C1; a write control signal is input to the write control module. V CONTROL Reference voltage V ref With multiple input signals, the write control module is used to write control signals. V CONTROL Under the control of the reference voltage V ref The write operation voltage is generated by multiple input signals and applied across the capacitor C1 in the memory cell; the read control module receives the read control signal. V Read_control The read control module is used for reading control signals. V Read_control Under its influence, the working status of the multi-value dynamic storage unit is output in four-bit encoded form.

[0041] Specifically, such as Figure 2 The circuit structure shown includes a read control module comprising: a first transistor M1, a first diode group D1, a second diode group D2, a third diode group D3, a fourth diode group D4, a first voltage comparison unit, a second voltage comparison unit, a third voltage comparison unit, and a fourth voltage comparison unit.

[0042] The first transistor M1 is connected to a read control signal. V Read_control The first terminal of the first transistor M1 is connected to the multi-value dynamic storage cell, and the second terminal of the first transistor M1 is connected to the positive terminal of the first diode group D1 and the negative terminal of the third diode group, respectively. The negative terminal of the first diode group D1 is connected to the positive terminal of the second diode group D2 and the voltage input terminal of the second voltage comparator, respectively. The positive terminal of the third diode group D3 is connected to the negative terminal of the fourth diode group D4 and the voltage input terminal of the fourth voltage comparator, respectively. The negative terminal of the second diode group is connected to the voltage input terminal of the first voltage comparator, and the positive terminal of the fourth diode group D4 is connected to the voltage input terminal of the third voltage comparator.

[0043] Reading control signals V Read_controlWhen the voltage level is high, the read control module starts working. The first, second, third, and fourth voltage comparison units are used to compare the voltage at their respective input terminals with their respective preset voltages, outputting a high or low level. The outputs of the four voltage comparison units (OUT1, OUT2, OUT3, OUT4) are used to characterize the working state of the multi-value dynamic storage unit. Specifically, in the first and second voltage comparison units, when the input voltage of the voltage comparison unit is greater than the preset voltage of the voltage comparison unit, a high level is output, recorded as 1; otherwise, it is recorded as 0. In the third and fourth voltage comparison units, when the input voltage of the voltage comparison unit is less than the preset voltage of the voltage comparison unit, a high level is output, recorded as 1; otherwise, it is recorded as 0.

[0044] Specifically, when the multi-value dynamic storage unit is in a low voltage state with positive bias, the first diode group D1 is turned on, the second diode group D2, the third diode group D3 and the fourth diode group D4 are turned off, and the first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit and the fourth voltage comparison unit output 0, 1, 0 and 0 respectively.

[0045] When the multi-value dynamic storage unit is in a high-voltage state with positive bias, the first diode group D1 and the second diode group D2 are turned on, the third diode group D3 and the fourth diode group D4 are turned off, and the first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit and the fourth voltage comparison unit output 1, 1, 0 and 0 respectively.

[0046] When the multi-value dynamic storage unit is in a low-voltage state with negative bias, the third diode group D3 is turned on, the first diode group D1, the second diode group D2 and the fourth diode group D4 are turned off, and the first voltage comparator, the second voltage comparator, the third voltage comparator and the fourth voltage comparator output 0, 0, 0 and 1 respectively.

[0047] When the multi-value dynamic storage unit is in a high-voltage state with negative bias, the third diode group D3 and the fourth diode group D4 are turned on, the first diode group D1 and the second diode group D2 are turned off, and the first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit and the fourth voltage comparison unit output 0, 0, 1 and 1 respectively.

[0048] Similarly, Figure 2The circuit structure shown includes a write control module comprising a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first inverter INV1, a second inverter INV2, a third inverter INV3, and an operational amplifier Q1.

[0049] The output of operational amplifier Q1 is connected to a multi-value dynamic storage unit; the inverting input of operational amplifier Q1 is connected to the first terminal of the second transistor M2, the first terminal of the fourth transistor M4, and the first terminal of the sixth transistor M6, respectively; the non-inverting input of operational amplifier Q1 is connected to the first terminal of the fourth resistor R4, the first terminal of the third transistor M3, the first terminal of the fifth transistor M5, and the first terminal of the seventh transistor M7, respectively.

[0050] After the second terminals of the sixth transistor M6 and the seventh transistor M7 are connected, they are connected to the first terminal of the first resistor R1; after the second terminals of the fourth transistor M4 and the fifth transistor M5 are connected, they are connected to the first terminal of the second resistor R2; after the second terminal of the second transistor M2 and the third transistor M3 are connected, they are connected to the first terminal of the third resistor R3; after the second terminals of the fourth resistor R4 and the third resistor R3 are connected, they are connected to the first terminal of the fifth resistor R5; after the second terminals of the second resistor R2 and the fifth resistor R5 are connected, they are connected to the first terminal of the sixth resistor R6; after the second terminal of the sixth resistor R6 is connected to the second terminal of the first resistor R1, a reference voltage is applied. V ref .

[0051] The control terminal of the second transistor M2 is connected to the first input signal. IN 1. The control terminal of the third transistor M3 is connected to the first input signal through the first inverter INV1. IN 1; The control terminal of the fourth transistor M4 is connected to the second input signal. IN 2. The control terminal of the fifth transistor M5 is connected to the second input signal through the second inverter INV2. IN 2; The control terminal of the sixth transistor M6 is connected to the third input signal. IN 3. The control terminal of the seventh transistor M7 is connected to the third input signal through the third inverter INV3. IN 3.

[0052] The inverting input of operational amplifier Q1 is also connected to the write control signal through resistor R7. V CONTROLThe non-inverting input of operational amplifier Q1 is also grounded; the two ends of the eighth resistor R8 are connected to the inverting input and the output of operational amplifier Q1, respectively.

[0053] When the write control module is working, it is used to determine the reference voltage. V ref First input signal IN 1. Second input signal IN 2 and the third input signal IN Different values ​​generate different write operation voltages, which are applied to both ends of the memory cell capacitor C1.

[0054] Specifically, in this embodiment, the resistance of the first resistor R1 is 2R, the resistance of the second resistor R2 is 2R, the resistance of the third resistor R3 is 2R, the resistance of the fourth resistor R4 is 2R, the resistance of the fifth resistor R5 is R, the resistance of the sixth resistor R6 is R, and the resistance of the eighth resistor R8 is 2R. The write control signal... V CONTROL The resistance value of the seventh resistor R7 satisfies the following relationship:

[0055] .

[0056] in, V CONTROL To write control signals, R 7 represents the resistance value of the seventh resistor, R7. V ref This is the reference voltage value.

[0057] according to Figure 2 From the structure of the read / write circuit shown, it can be seen that the current flowing through the first resistor R1 is... The current flowing through the second resistor R2 is The current flowing through the third resistor R3 is First input signal IN 1. Second input signal IN 2. Third input signal IN 3 are used to control the current respectively. IR 1. Current IR 2. Current IR 3. Can the current flow into the inverting input of operational amplifier Q1? Additionally, write the control signal. V CONTROL The set current generated by the seventh resistor R7 is The set current is used to adjust the output voltage of operational amplifier Q1. V O The absolute values ​​of the maximum positive value and the minimum negative value are equal, which means that the operating voltage applied to the memory cell is equal. V OThe same value can be achieved in both the forward and reverse directions.

[0058] The output voltage of operational amplifier Q1 is shown in the following formula:

[0059] .

[0060] in, V O This is the output voltage of operational amplifier Q1. V ref For reference voltage value, IN 1 is the first input signal. IN 2 is the second input signal. IN 3 is the third input signal; specifically, when the input signal... IN 1. IN 2. IN When 3 is high, the corresponding value in the above formula is 1; otherwise, it is 0.

[0061] Based on the characteristics of the multi-value dynamic storage unit based on OTS analyzed in the previous embodiments, by changing the input signal IN 1. IN 2. IN The value of 3 can change the output voltage. V O The values ​​are used to select appropriate input signals. IN 1. IN 2. IN 3. Ensure that the generated voltage meets the operating voltage ranges VIN1 and VIN2: ±Vin1 (Vin1 amplitude range is between Vth and Vth+Vhold); ±Vin2 (Vin2 amplitude is greater than Vth+Vhold).

[0062] Specifically, by adjusting the first input signal IN 1. Second input signal IN 2 and the third input signal IN A value of 3 can produce eight different output voltages. V O Two positive voltages and two negative voltages can be selected as the write operation voltages. After these four write operation voltages are applied to the memory cell capacitor C1, the voltage across the memory cell capacitor C1 will have four states, realizing the write operation of the multi-value dynamic memory cell.

[0063] In another exemplary embodiment of this application, the first diode group D1, the second diode group D2, the third diode group D3, and the fourth diode group D4 are all composed of crystal diodes with voltage drop.

[0064] As a concrete example, for a multi-valued dynamic memory cell based on OTS, its threshold voltage Vth is 4.1V and its holding voltage Vhold is 1.2V. Then its four operating voltages should meet the following requirements:

[0065] ±Vin1 (Vin1 amplitude range between 4.1V and 5.3V); ±Vin2 (Vin2 amplitude greater than 5.3V).

[0066] If the operating voltages are selected as ±5V and ±7V, then the operating voltages satisfy the following expression:

[0067] .

[0068] In this embodiment, the following is selected V ref If the voltage is -8V, then:

[0069] When input signal IN 1. IN 2. IN When 3 are 0, 1, and 1 respectively, the output voltage V O It is 5V;

[0070] When input signal IN 1. IN 2. IN When 3 are 1, 1, and 1 respectively, the output voltage is... V O It is 7V;

[0071] When input signal IN 1. IN 2. IN When 3 represents 1, 0, and 0 respectively, the output voltage V O -5V;

[0072] When input signal IN 1. IN 2. IN 3. Output voltage when 0, 0, 0 respectively V O It is -7V.

[0073] That is, by setting the input signal IN 1. IN 2. IN 3 can be 011, 111, 100, or 000 to implement the writing of the corresponding state.

[0074] Correspondingly, the voltages for the four storage states of the multi-value dynamic storage cell are ±3.8V and ±1.2V, respectively.

[0075] When the storage cell is 1.2V, diode group D1 is turned on, while diode groups D2, D3, and D4 are turned off, and the four voltage comparison units output 0, 1, 0, and 0.

[0076] When the storage cell is at 3.8V, diode groups D1 and D2 are turned on, while diode groups D3 and D4 are turned off, and the four voltage comparison units output 1, 1, 0, 0.

[0077] When the storage cell is -1.2V, diode group D3 is turned on, while diode groups D1, D2, and D4 are turned off, and the four voltage comparison units output 0, 0, 0, and 1.

[0078] When the storage cell is -3.8V, diode groups D3 and D4 are turned on, while diode groups D1 and D2 are turned off, and the four voltage comparison units output 0, 0, 1, and 1.

[0079] Therefore, it is possible to read the data stored in the four states of the multi-value dynamic storage unit.

[0080] The above embodiments of this application provide a read / write circuit for a multi-value dynamic storage unit based on an OTS. Under the control of a write control signal, the write control module generates different write operation voltages based on a reference voltage and multiple input signals, and applies them to both ends of the storage unit capacitor to realize the write operation of the multi-value dynamic storage unit. Under the action of a read control signal, the read control module reads out the four storage states of the storage unit and outputs them in the form of a four-bit code. The solution provided in this embodiment can generate different write operation voltages by adjusting the values ​​of each input signal, which can be used as write voltages for different states of the multi-value dynamic storage unit. In addition, the read control module can read out the different storage states of the storage unit and output the read data in the form of a four-bit code.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A read / write circuit for a multi-value dynamic storage unit based on OTS, characterized in that, include: Write control module and read control module; Both the write control module and the read control module are connected to the multi-value dynamic storage unit; Multi-value dynamic memory cells include: OTS gate transistors and memory cell capacitors; The write control module receives a write control signal, a reference voltage, and multiple input signals. Under the control of the write control signal, the write control module generates a write operation voltage based on the reference voltage and multiple input signals, and applies it to both ends of the capacitor in the storage unit. The read control module receives a read control signal and outputs the working state of the multi-value dynamic storage unit in a four-bit encoded form under the action of the read control signal. The write control module includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first inverter, a second inverter, a third inverter, and an operational amplifier; The output terminal of the operational amplifier is connected to the multi-value dynamic storage unit; the inverting input terminal of the operational amplifier is connected to the first terminal of the second transistor, the first terminal of the fourth transistor, and the first terminal of the sixth transistor, respectively; the non-inverting input terminal of the operational amplifier is connected to the first terminal of the fourth resistor, the first terminal of the third transistor, the first terminal of the fifth transistor, and the first terminal of the seventh transistor, respectively. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor, and then connected to the first terminal of the first resistor; the second terminal of the fourth transistor is connected to the second terminal of the fifth transistor, and then connected to the first terminal of the second resistor; the second terminal of the second transistor is connected to the second terminal of the third transistor, and then connected to the first terminal of the third resistor; the second terminal of the fourth resistor is connected to the second terminal of the third resistor, and then connected to the first terminal of the fifth resistor; the second terminal of the second resistor is connected to the second terminal of the fifth resistor, and then connected to the first terminal of the sixth resistor; the second terminal of the sixth resistor is connected to the second terminal of the first resistor, and then connected to the reference voltage. The control terminal of the second transistor is connected to the first input signal, and the control terminal of the third transistor is connected to the first input signal through the first inverter; the control terminal of the fourth transistor is connected to the second input signal, and the control terminal of the fifth transistor is connected to the second input signal through the second inverter; the control terminal of the sixth transistor is connected to the third input signal, and the control terminal of the seventh transistor is connected to the third input signal through the third inverter; The inverting input terminal of the operational amplifier is also connected to the write control signal through the seventh resistor, and the non-inverting input terminal of the operational amplifier is also grounded; the two ends of the eighth resistor are respectively connected to the inverting input terminal and the output terminal of the operational amplifier. When the write control module is in operation, it generates different write operation voltages based on the different values ​​of the reference voltage, the first input signal, the second input signal, and the third input signal, and applies them to both ends of the memory cell capacitor.

2. The read / write circuit for a multi-value dynamic storage unit based on OTS according to claim 1, characterized in that, The read control module includes: a first transistor, a first diode group, a second diode group, a third diode group, a fourth diode group, a first voltage comparison unit, a second voltage comparison unit, a third voltage comparison unit, and a fourth voltage comparison unit; The first transistor's control terminal receives a read control signal; the first terminal of the first transistor is connected to a multi-value dynamic storage unit; the second terminal of the first transistor is connected to the anode of the first diode group and the cathode of the third diode group; the cathode of the first diode group is connected to the anode of the second diode group and the voltage input terminal of the second voltage comparator; the anode of the third diode group is connected to the cathode of the fourth diode group and the voltage input terminal of the fourth voltage comparator; the cathode of the second diode group is connected to the voltage input terminal of the first voltage comparator; and the anode of the fourth diode group is connected to the voltage input terminal of the third voltage comparator. When the read control signal is high, the read control module starts to work. The first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit and the fourth voltage comparison unit are respectively used to compare the voltage at their respective voltage input terminals with their respective preset voltages and output high or low levels. The outputs of the four voltage comparison units are used to characterize the working state of the multi-value dynamic storage unit.

3. The read / write circuit for a multi-value dynamic storage unit based on OTS according to claim 2, characterized in that, When the multi-value dynamic storage unit is in a low voltage state with positive bias, the first diode group is turned on, and the second diode group, the third diode group, and the fourth diode group are turned off. The first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit, and the fourth voltage comparison unit output 0, 1, 0, and 0, respectively. When the multi-value dynamic storage unit is in a positive bias high voltage state, the first diode group and the second diode group are turned on, the third diode group and the fourth diode group are turned off, and the first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit and the fourth voltage comparison unit output 1, 1, 0 and 0 respectively; When the multi-value dynamic storage unit is in a low-voltage state with negative bias, the third diode group is turned on, and the first diode group, the second diode group, and the fourth diode group are turned off. The first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit, and the fourth voltage comparison unit output 0, 0, 0, and 1, respectively. When the multi-value dynamic storage unit is in a high-voltage state with negative bias, the third diode group and the fourth diode group are turned on, the first diode group and the second diode group are turned off, and the first voltage comparison unit, the second voltage comparison unit, the third voltage comparison unit and the fourth voltage comparison unit output 0, 0, 1 and 1 respectively.

4. The read / write circuit for a multi-value dynamic storage unit based on OTS according to claim 1, characterized in that, The resistance of the first resistor is 2R, the resistance of the second resistor is 2R, the resistance of the third resistor is 2R, the resistance of the fourth resistor is 2R, the resistance of the fifth resistor is R, the resistance of the sixth resistor is R, and the resistance of the eighth resistor is 2R.

5. The read / write circuit for a multi-value dynamic storage unit based on OTS according to claim 4, characterized in that, The write control signal and the resistance value of the seventh resistor satisfy the following relationship: ； in, V CONTROL To write control signals, R 7 represents the resistance value of the seventh resistor. V ref This is the reference voltage value.

6. The read / write circuit for a multi-value dynamic storage unit based on OTS according to claim 5, characterized in that, The current flowing through the first resistor is The current flowing through the second resistor is The current flowing through the third resistor is The first input signal, the second input signal, and the third input signal are respectively used to control the current. IR 1. Current IR 2. Current IR 3. Whether the current can flow into the inverting input of the operational amplifier.

7. The read / write circuit for a multi-value dynamic storage unit based on OTS according to claim 6, characterized in that, The write control signal and the set current generated by the seventh resistor are The set current is used to adjust the output voltage of the operational amplifier. V O The absolute values ​​of the maximum positive value and the minimum negative value are equal.

8. The read / write circuit for a multi-value dynamic storage unit based on OTS according to claim 6, characterized in that, The output voltage of the operational amplifier is shown in the following formula: ； in, V O The output voltage of the operational amplifier is... V ref For reference voltage value, IN 1 is the first input signal. IN 2 is the second input signal. IN 3 is the third input signal.

9. The read / write circuit for a multi-value dynamic storage unit based on OTS according to claim 8, characterized in that, By adjusting the values ​​of the first input signal, the second input signal, and the third input signal, eight different output voltages can be generated. V O Two positive voltages and two negative voltages can be selected as the write operation voltages.

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