Control circuit

Abstract

The embodiment of the invention discloses a control circuit, which comprises a period control module, a conduction time control module and a driving module, and is characterized in that the period control module is used for outputting a first control signal; the driving module is used for controlling a first switching tube in the step-down PFC circuit to be switched on under the condition that the first control signal is suddenly changed from a low level to a high level; the conduction time control module is used for outputting a second control signal, and when a first product of the first average current value and the current conduction time of the first switching tube reaches a second preset threshold value, the second control signal is suddenly changed from a low level to a high level; the first average current value is an average current value of the first current signal in a switching period of the first switching tube; and the driving module is used for controlling the first switching tube to be switched off under the condition that the second control signal is suddenly changed from the low level to the high level. According to the embodiment of the invention, the control cost of the step-down PFC circuit can be saved.

Description

Technical Field

[0001] The present application relates to driving technology, applied in the field of electronics, and in particular to a control circuit. Background Art

[0002] With the rapid development of fast charging technology, the power supply of consumer electronic devices such as mobile phones, tablets, computers and notebooks, and televisions is constantly increasing. Therefore, it is necessary to equip their power adapters with power factor correction (PFC) circuits to meet the requirements of GB17625.1 and IEC61000-3-2 standards for input current harmonics. For adapter power supplies, when the power is above 100W, an active PFC circuit is usually required. The active PFC circuit controls the DC / DC conversion circuit composed of power electronic switching devices so that the average input current value of the PFC circuit changes with the input voltage value, thereby achieving power factor correction. In order to be suitable for high-power scenarios, the working mode of the conversion circuit in the active PFC circuit is usually continuous current mode (continuous conduction mode, CCM), and in CCM mode, the control principle of the traditional PFC circuit is to sample the input voltage and multiply it with the output voltage value of the voltage outer loop circuit as a reference value for the control of the current inner loop circuit, thereby controlling the average input current to follow the sinusoidal input voltage to achieve power factor correction. The above control method is complex and costly.

[0003] For an active PFC circuit (i.e., Boost PFC) in which the DC / DC conversion circuit is a boost circuit, the prior art adopts a peak current single-cycle control method, which can achieve the effect of average current following the input voltage without sampling the input voltage, thereby simplifying the PFC circuit control in CCM mode. However, a buck PFC circuit (such as BuckPFC) is usually used in scenarios where voltage reduction is required. Since the circuit structures of the buck PFC circuit and the Boost PFC circuit are different, the input current of the buck PFC circuit is discontinuous and the peak input current and average input current of the buck PFC circuit do not have a linear relationship, the above-mentioned peak current single-cycle control method is no longer applicable. Therefore, how to save the control cost of the buck PFC circuit is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The embodiment of the present application discloses a control circuit for saving the control cost of a buck-type PFC circuit.

[0005] In the first aspect, the embodiment of the present application provides a control circuit, which includes a period control module 11, a conduction time control module 12 and a drive module 13, wherein: the period control module 11 is used to output a first control signal V_ON, and the period of the first control signal V_ON is a first preset threshold value; the drive module 13 is used to control the first switch tube Q1 in the buck power factor correction PFC circuit 2 to be turned on when the first control signal V_ON suddenly changes from a low level to a high level, and the working mode of the buck PFC circuit 2 is a continuous current mode CCM, and the input current of the buck PFC circuit 2 is The current value is equal to the current value of the first current signal I_Q1 flowing through the first switch tube Q1; the on-time control module 12 is used to output the second control signal V_OFF. When the first product of the first average current value and the current on-time of the first switch tube Q1 reaches the second preset threshold, the second control signal V_OFF suddenly changes from a low level to a high level. The first average current value is the average current value of the first current signal I_Q1 within a switching cycle of the first switch tube Q1; the driving module 13 is used to control the first switch tube Q1 to be turned off when the second control signal V_OFF suddenly changes from a low level to a high level.

[0006] The above control circuit can control the maximum value of the first product (i.e., equal to the product of the average input current value of the buck PFC circuit 2 and the total conduction time of the first switch tube Q1) to be a constant value (i.e., equal to the second preset threshold value) within a single switching cycle of the first switch tube Q1 in the buck PFC circuit 2, so as to control the average input current value of the buck PFC circuit 2 to follow the input voltage value, thereby controlling the buck PFC circuit 2 to achieve power factor correction without sampling the input voltage, thereby reducing the control cost of the buck PFC circuit 2.

[0007] In combination with the first aspect, in a possible implementation, the on-time control module 12 includes a current sampling module 121 and an operation module 122, wherein: the current sampling module 121 is used to convert the first current signal I_Q1 into a first voltage signal V_CS, and the current value of the first current signal I_Q1 is proportional to the voltage value of the first voltage signal V_CS; the operation module 122 is used to operate the first voltage signal V_CS when the first switch tube Q1 is turned on to generate a second voltage signal V_INT2, and the voltage value of the second voltage signal V_INT2 is proportional to the first product; the operation module 122 is also used to output a second control signal V_OFF, and when the voltage value of the second voltage signal V_INT2 reaches a third preset threshold, the second control signal V_OFF suddenly changes from a low level to a high level.

[0008] The control circuit can sample the first current signal I_Q1 flowing through the first switch tube Q1, and calculate the first voltage signal V_CS obtained after sampling when the first switch tube Q1 is turned on, so that the voltage value of the second voltage signal V_INT2 calculated during the conduction period of the first switch tube Q1 is proportional to the first product, and the maximum value of the voltage value of the second voltage signal V_INT2 is a constant value (i.e., equal to the third preset threshold), thereby indirectly making the maximum value of the first product in a single switching cycle of the first switch tube Q1 a constant value, and further controlling the average input current value of the Buck PFC circuit 21 to follow the input voltage value.

[0009] In combination with the first aspect, or any of the above-mentioned possible implementations of the first aspect, in another possible implementation, the operation module 122 includes a voltage amplifier circuit GAIN, a voltage sampling and holding circuit S / H, an addition and subtraction operation circuit SUM, and an integration circuit 1221; the positive input terminal of the addition and subtraction operation circuit SUM is connected to the output terminal of the voltage amplifier circuit GAIN, the negative input terminal of the addition and subtraction operation circuit SUM is connected to the output terminal of the voltage sampling and holding circuit S / H, and the output terminal of the addition and subtraction operation circuit SUM is connected to the input terminal of the integration circuit 1221, wherein: the voltage amplifier circuit GAIN is used to amplify the first voltage signal V_CS to output a third voltage signal V_GAIN, and the third voltage signal V_GAIN The voltage value of AIN is proportional to the voltage value of the first voltage signal V_CS; the voltage sampling and holding circuit S / H is used to output a fourth voltage signal V_SH, and the voltage value of the fourth voltage signal V_SH is equal to the initial voltage value of the first voltage signal V_CS when the first switch tube Q1 starts to turn on; the addition and subtraction circuit SUM is used to output a fifth voltage signal V_SUM, and the voltage value of the fifth voltage signal V_SUM is equal to the difference between the voltage value of the third voltage signal V_GAIN and the voltage value of the fourth voltage signal V_SH; the integration circuit 1221 is used to perform a secondary integration of the fifth voltage signal V_SUM over time when the first switch tube Q1 is turned on, so as to generate a second voltage signal V_INT2.

[0010] In combination with the first aspect, or any one of the above-mentioned possible implementations of the first aspect, in another possible implementation, the operation module 122 also includes a comparator CMP and a voltage loop module 1222, the positive input terminal of the comparator CMP is connected to the output terminal of the integration circuit 1221, and the negative input terminal of the comparator CMP is connected to the output terminal of the voltage loop module 1222, wherein: the voltage loop module 1222 is used to output a sixth voltage signal V_C according to a voltage difference between a reference voltage signal and an output voltage signal V_OUT of the buck PFC circuit 2, and the voltage value of the sixth voltage signal V_C is equal to a third preset threshold value; the comparator CMP is used to compare the sixth voltage signal V_C with the second voltage signal V_INT2, and output a second control signal V_OFF.

[0011] In combination with the first aspect, or any of the above-mentioned possible implementations of the first aspect, in another possible implementation, the first input end of the integration circuit 1221 is connected to the output end of the addition and subtraction circuit SUM, the first output end of the driving module 13 is connected to the gate of the first switch tube Q1, the second output end of the driving module 13 is connected to the second input end of the integration circuit 1221, the first input end of the driving module 13 is connected to the output end of the cycle control module 11, and the second input end of the driving module 13 is connected to the output end of the comparator CMP, wherein: the driving module 13 is also used to control the integration circuit 1221 to output the second voltage signal V_INT2 when the first control signal V_ON suddenly changes from a low level to a high level; the driving module 13 is also used to control the voltage value of the second voltage signal V_INT2 to be zero when the second control signal V_OFF suddenly changes from a low level to a high level.

[0012] In combination with the first aspect, or any of the above possible implementations of the first aspect, in another possible implementation, the integration circuit 1221 includes a first integration circuit 1221 and a second integration circuit 1221, a first input end of the integration circuit 1221 is connected to a first input end of the first integration circuit 1221, an output end of the first integration circuit 1221 is connected to a first input end of the second integration circuit 1221, an output end of the second integration circuit 1221 is connected to an output end of the integration circuit 1221, and a second input end of the integration circuit 1221 is connected to a second input end of the first integration circuit 1221 and a second input end of the second integration circuit 1221, wherein: the driving module 13 is configured to drive the first input end of the integration circuit 1221 through the first input end of the driving module 13; The second output terminal outputs the third control signal V_RST. When the first control signal V_ON suddenly changes from a low level to a high level, the third control signal V_RST suddenly changes from a high level to a low level. When the second control signal V_OFF suddenly changes from a low level to a high level, the third control signal V_RST suddenly changes from a low level to a high level. The first integration circuit 1221 is used to perform a first-order integration of the fifth voltage signal V_SUM with respect to time to generate a seventh voltage signal when the third control signal V_RST is at a low level. The second integration circuit 1221 is used to perform a first-order integration of the seventh voltage signal with respect to time to generate a second voltage signal V_INT2 when the third control signal V_RST is at a low level.

[0013] In combination with the first aspect, or any one of the above-mentioned possible implementations of the first aspect, in another possible implementation, the driving module 13 includes a trigger SR and a driving circuit DRV, a first input end of the driving module 13 is connected to a set end of the trigger SR, a second input end of the driving module 13 is connected to a reset end of the trigger SR, a first output end of the trigger SR is connected to an input end of the driving circuit DRV, an output end of the driving circuit DRV is connected to a first output end of the driving module 13, and a second output end of the trigger SR is connected to a second output end of the driving module 13.

[0014] In combination with the first aspect, or any of the above possible implementations of the first aspect, in another possible implementation, the voltage value V of the second voltage signal V_INT2 is cs_int2 Satisfies the following formula:

[0015] V cs_int2 =β 0 *∫ 0 t (∫ 0 t V cs_s dt)dt

[0016] V cs_s =V cs_g -V cs0 =3Vcs -V cs 0

[0017] Among them, β 0 is the preset secondary integral coefficient, V cs_s is the voltage value of the fifth voltage signal V_SUM, V cs_g is the voltage value of the third voltage signal V_GAIN, V cs0 is the voltage value of the fourth voltage signal V_SH, V cs is the voltage value of the first voltage signal V_CS.

[0018] In combination with the first aspect, or any one of the above possible implementations of the first aspect, in another possible implementation, the buck PFC circuit 2 includes a buck Buck PFC circuit 21, a forward topology PFC circuit 71, or a push-pull topology PFC circuit 72.

[0019] In a second aspect, an embodiment of the present application provides a control device, which includes the control circuit described in the first aspect or any possible implementation manner of the first aspect.

[0020] In a third aspect, an embodiment of the present application provides a PFC device, which includes the control circuit and the buck PFC circuit described in the first aspect or any possible implementation manner of the first aspect.

[0021] The beneficial effects of the related devices provided in the second and third aspects of this application can refer to the beneficial effects of the technical solution of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The following is a brief introduction to the drawings required for describing the embodiments of the present application.

[0023] Figure 1 is a structural schematic diagram of a control circuit provided in an embodiment of the present application;

[0024] Figure 2 is a structural schematic diagram of another control circuit provided in an embodiment of the present application;

[0025] Figure 3 It is a structural schematic diagram of a voltage loop module provided in an embodiment of the present application;

[0026] Figure 4 is a structural schematic diagram of a driving module provided in an embodiment of the present application;

[0027] Figure 5 is a signal waveform diagram provided in an embodiment of the present application;

[0028] Figure 6It is another signal waveform diagram provided in an embodiment of the present application;

[0029] Figure 7a It is a structural diagram of a Buck PFC circuit provided in an embodiment of the present application;

[0030] Figure 7b It is a structural schematic diagram of a forward topology PFC circuit provided in an embodiment of the present application;

[0031] Figure 7c It is a schematic diagram of the structure of a push-pull topology PFC circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0033] See also Figure 1 , Figure 1 1 is a schematic diagram of a control circuit provided in an embodiment of the present application. The control circuit 1 comprises a cycle control module 11, a conduction time control module 12 and a drive module 13. The output terminal a of the cycle control module 11 is connected to the first input terminal b of the drive module. 1 The output terminal c of the conduction time control module 12 is connected to the second input terminal b of the driving module 2 The control circuit 1 can control the average input current value I of the buck PFC circuit 2 avg Follow the input voltage value V in changes, thereby achieving power factor correction.

[0034] The buck PFC circuit 2 includes a first switch tube Q1. The input current value I in =I1 is equal to the current value I of the first current signal I_Q1 flowing through the first switch tube Q1 1 , and the working mode of the buck PFC circuit 2 is the continuous current mode CCM. It can be understood that the first switch tube Q1 can be regarded as the main switch tube in the buck PFC circuit 2. The embodiment of the present application does not strictly limit the specific circuit structure of the buck PFC circuit 2. For example, the buck PFC circuit 2 can be a buck Buck PFC circuit, a forward topology PFC circuit, or a push-pull topology PFC circuit. In addition, in actual applications, the DC power at the input end of the buck PFC circuit 2 is usually obtained by converting the AC power of the AC power supply through AC / DC. For example, Figure 1As shown, the input end of the buck PFC circuit 2 is connected to the AC / DC conversion circuit 3, and the AC / DC conversion circuit 3 includes an AC power supply S, an electromagnetic interference (EMI) filter circuit 31 and a rectifier bridge DBI. The output end of the AC power supply S is connected to the rectifier bridge DBI through the EMI filter circuit 31, and the output end of the rectifier bridge DBI is connected to the input end of the buck PFC circuit 2. The EMI filter circuit 31 is used to filter out circuit interference, and the rectifier bridge DBI is used to convert the sinusoidal AC voltage signal V_AC output by the AC power supply S into a steamed-wave DC voltage signal (i.e., the input voltage signal V_IN of the buck PFC circuit 2) for output.

[0035] From the output side, the input voltage value V in , average input current value I avg And the equivalent impedance R e Satisfy formula (1-1):

[0036] v in =I avg *R e (1-1)

[0037] According to the volt-second balance principle, in the continuous current mode CCM, the output voltage value V of the buck PFC circuit 2 is out and input voltage value V in The ratio of the duty cycle D of the first switch tube Q1 on Assume that the proportionality coefficient is k 1 , then the output voltage value V out 、Input voltage value V in and duty cycle D on Satisfy formula (1-2):

[0038]

[0039] Formula (1-3) is obtained from formula (1-1) and formula (1-2):

[0040]

[0041] Among them, T on The first switch tube Q1 in a single switching cycle T s The total dry time (hereinafter referred to as the total dry time T on ).

[0042] In the control circuit 1, the period control module 11 is used to output the first control signal V_ON, and the period of the first control signal is the first preset threshold. The driving module 13 is used to control the first switch tube Q1 in the buck PFC circuit 2 to turn on when the first control signal suddenly changes from a low level to a high level. It can be understood that the first control signal V_ON is a continuous and periodic voltage signal composed of a combination of high and low levels. Optionally, the first control signal V_ON can be a pulse signal with a fixed frequency.

[0043] The on-time control module 12 is used to output a second control signal V_OFF. When the first average current value is equal to the current on-time t of the first switch tube Q1, on When the first product of reaches the second preset threshold, the second control signal V_OFF changes from a low level to a high level, and the first average current value is the first current signal I_Q1 in a single switching cycle T of the first switch tube Q1. s The driving module 13 is used to control the first switch tube to turn off when the second control signal suddenly changes from a low level to a high level. It can be understood that the total on time T of the first switch tube Q1 is on is the time when the first product reaches the second preset threshold, and the switching period T of the first switch Q1 s is a constant value, which is equal to the period of the first control signal V_ON, that is, equal to the first preset threshold. Then, in a single switching period T of the first switch tube Q1 s The maximum value of the first product is equal to the first average current value and the total conduction time T on The product of is always equal to the second preset threshold. in =I1 is equal to the current value I of the first current signal I_Q1 flowing through the first switch tube Q1 1 The first average current value is equal to the average input current value I of the buck PFC circuit 2. avg The maximum value of the first product is equal to the average input current value I of the buck PFC circuit 2. avg The total conduction time T of the first switch tube Q1 on The product of .

[0044] It can be seen from formula (1-3) that the left side of formula (1-3) is the maximum value of the first product, and the right side of the formula is the second preset threshold. s is a constant value, and the output voltage V when the buck PFC circuit 2 is working stably out can be regarded as a constant value, so the control circuit 1 can realize the equivalent impedance R of the buck PFC circuit 2 eis a constant value, then, from formula (1-1), it can be seen that the average input current value I of the buck PFC circuit 2 is avg Follow the input voltage value V in change.

[0045] It can be seen that the control circuit 1 in the embodiment of the present application can control the average input current value I of the buck PFC circuit 2 within a single switching cycle of the first switch tube Q1 in the buck PFC circuit 2. avg The total conduction time T of the first switch tube Q1 on The product of is a constant value (i.e., equal to the second preset threshold value) to control the average input current value I of the buck PFC circuit 2. avg Follow the input voltage value V in The step-down PFC circuit 2 is controlled to achieve power factor correction without sampling the input voltage, thereby saving the control cost of the step-down PFC circuit.

[0046] Combined with the following Figures 2 to 7c right Figure 1 The working principle of the control circuit 1 shown is further explained.

[0047] In an optional embodiment, Figure 1 The step-down PFC circuit 2 shown is a Buck PFC circuit, the first control signal V_ON is a pulse signal with a fixed frequency, and the on-time control module 12 includes a current sampling module and an operation module. Figure 2 , Figure 2 It is a structural schematic diagram of another control circuit provided in an embodiment of the present application.

[0048] like Figure 2 As shown, the Buck PFC circuit 21 includes a first capacitor C1, a second capacitor C2, a first diode D1, a first switch tube Q1 and a first inductor L1. 1 Connect one end of the first capacitor C1, the cathode of the first diode D1, one end of the second capacitor C2 and the positive output end o of the Buck PFC circuit 21 1 The anode of the first diode D1 is connected to one end of the first inductor L1 and the drain of the first switch tube Q1, and the other end of the second capacitor C2 is connected to the other end of the first inductor L1 and the negative output end of the Buck PFC circuit 21. 2 , the negative input terminal i of the Buck PFC circuit 21 2 The other end of the first capacitor C1, the source of the first switch tube Q1 and the reference ground are connected.

[0049] The first input terminal e of the conduction time control module 12 in the control circuit 1 1The second input terminal e of the conduction time control module 12 is connected to the source of the first switch tube Q1. 2 The output terminal of the Buck PFC circuit 21 is connected to the first output terminal d of the driving module 13. 1 The gate of the first switch tube Q1 is connected to the second output terminal d of the driving module 13. 2 The third input terminal e connected to the conduction time control module 12 3 The output terminal a of the cycle control module 11 is connected to the first input terminal b of the driving module. 1 and the fourth input terminal e of the conduction time control module 12 4 The output terminal c of the conduction time control module 12 is connected to the second input terminal b of the driving module 2 .

[0050] The conduction time control module 12 includes a current sampling module 121 and a calculation module 122. The input terminal f of the current sampling module 121 is connected to the first input terminal e of the conduction time control module 12. 1 The output terminal g of the current sampling module 121 is connected to the first input terminal h of the operation module 122 1 , the second input terminal h of the operation module 122 2 The second input terminal e connected to the conduction time control module 12 2 , the third input terminal h of the operation module 122 3 The third input terminal e connected to the conduction time control module 12 3 , the fourth input terminal h of the operation module 122 4 The fourth input terminal e connected to the conduction time control module 12 4 , the output terminal j of the operation module 122 is connected to the output terminal c of the conduction time control module 12 .

[0051] The current sampling module 121 is used to convert the first current signal I_Q1 into a first voltage signal V_CS. The current value I of the first current signal I_Q1 is 1 and the voltage value V of the first voltage signal V_CS csThe period control module 11 is used to output a first control signal V_ON to the driving module 13. The first control signal V_ON is a pulse signal with a fixed frequency, and the period of the pulse signal is a first preset threshold. The driving module 13 is used to output a fourth control signal V_GATE to the first switch tube Q1. When the first control signal V_ON suddenly changes from a low level to a high level, the fourth control signal V_GATE suddenly changes from a low level to a high level, thereby controlling the first switch tube Q1 to be turned on. Optionally, since the current signal flowing through the first inductor L1 when the first switch tube Q1 is turned on is equivalent to the first current signal I_Q1 flowing through the first switch tube Q1, the input terminal f of the current sampling module 121 can also be connected to one end of the first inductor L1 in the Buck PFC circuit 21 to sample the first current signal I_Q1.

[0052] The operation module 122 in the on-time control module 12 is used to operate the first voltage signal V_CS to generate a second voltage signal V_INT2 when the first switch tube Q1 is turned on. The voltage value V cs_int2 and the first product (which is equivalent to the average input current value Iavg of the Buck PFC circuit 21 and the current on-time t of the first switch tube Q1 on The operation module 122 is also used to output a second control signal V_OFF to the driving module 13. When the voltage value V of the second voltage signal V_INT2 is cs_int2 When the third preset threshold is reached, the second control signal V_OFF changes from low level to high level. When the second control signal V_OFF changes from low level to high level, the fourth control signal V_GATE output by the driving module 13 changes from high level to low level, thereby controlling the first switch tube Q1 to be turned off.

[0053] Understandably, Figure 2 The control circuit 1 shown can sample the first current signal I_Q1 flowing through the first switch tube Q1, and calculate the first voltage signal V_CS obtained after sampling when the first switch tube Q1 is turned on, so that the voltage value V of the second voltage signal V_INT2 calculated during the conduction period of the first switch tube Q1 is cs_int2 is proportional to the first product, and makes the voltage value V of the second voltage signal V_INT2 cs_int2 is a constant value (i.e., equal to the third preset threshold), thereby indirectly making the maximum value of the first product (i.e., the average input current value I of the buck PFC circuit 2) within a single switching cycle of the first switch tube Q1 avg The total conduction time T of the first switch tube Q1 on The product of ( ) is a constant value, thereby controlling the average input current value I of the Buck PFC circuit 21 avgFollow the input voltage value V in change.

[0054] For example, Figure 2 As shown, the operation module 122 in the on-time control module 12 includes a voltage amplifier circuit GAIN, a voltage sampling and holding circuit S / H, an addition and subtraction operation circuit SUM, an integration circuit 1221 , a comparator CMP and a voltage loop module 1222 .

[0055] The first input terminal h of the operation module 122 is 1 The input terminal of the voltage amplifier circuit GAIN is connected to the first input terminal k of the voltage sampling and holding circuit S / H. 1 , the second input terminal k of the circuit S / H 2 The fourth input terminal h connected to the operation module 122 4 The output end of the voltage amplifier circuit GAIN is connected to the positive input end of the addition and subtraction operation circuit SUM, the output end of the voltage sampling and holding circuit S / H is connected to the negative input end of the addition and subtraction operation circuit, and the output end of the addition and subtraction operation circuit SUM is connected to the first input end m of the integration circuit 1221 1 , the second output terminal m of the integration circuit 1221 2 The third input terminal h connected to the operation module 122 3 The output end of the integration circuit 1221 is connected to the positive input end of the comparator CMP, the negative input end of the comparator CMP is connected to the output end p of the voltage loop module 1222, and the input end n of the voltage loop module 1222 is connected to the second input end h of the operation module 122. 2 The output end of the comparator CMP is connected to the output end j of the operation module 122.

[0056] The voltage amplifier circuit GAIN is used to amplify the first voltage signal V_CS output by the current sampling module 121 to output a third voltage signal V_GAIN. The voltage value V cs_g and the voltage value V of the first voltage signal V_CS csis proportional to. The voltage sampling and holding circuit S / H is used to start sampling the current voltage value of the first voltage signal V_CS when the first control signal V_ON suddenly changes from a low level to a high level (i.e., at the moment when the first switch tube Q1 is turned on), and when the voltage sampling and holding circuit S / H suddenly changes from a high level to a low level, it maintains the sampled current voltage value and outputs a fourth voltage signal V_SH. It can be understood that it takes a certain amount of time for the voltage sampling and holding circuit S / H to perform voltage sampling, and the sampling time is equal to the time when the first control signal V_ON is at a high level. As mentioned above, the first control signal V_ON is a pulse signal with a fixed frequency. In actual applications, the time (i.e., the pulse width) of the first control signal V_ON at a high level can be set according to the time required for sampling and holding, which does not affect its control effect on the switching period of the first switch tube Q1, and this time is usually short. In other words, the voltage value V of the fourth voltage signal V_SH is cs_h It can be regarded as equal to the initial voltage value V of the first voltage signal V_CS when the first switch tube Q1 starts to conduct. cs0 The addition and subtraction circuit SUM is used to output a fifth voltage signal V_SUM. The voltage value V of the fifth voltage signal V_SUM is cs_s is equal to the voltage value V of the third voltage signal V_GAIN cs_g and the voltage value V of the fourth voltage signal V_SH cs_h (ie, the initial voltage value V of the first voltage signal V_CS cs0 )

[0057] The driving module 13 is also used to output the 2The third control signal V_RST is output to the integration circuit 1221. When the first control signal V_ON suddenly changes from a low level to a high level, the third control signal V_RST suddenly changes from a high level to a low level. When the second control signal V_OFF suddenly changes from a low level to a high level, the third control signal V_RST suddenly changes from a low level to a high level. The integration circuit 1221 is used to start performing a secondary integration of the fifth voltage signal V_SUM with respect to time to generate the second voltage signal V_INT2 when the third control signal V_RST suddenly changes from a high level to a low level. It is also used to control the voltage of the second voltage signal V_INT2 to be zero (that is, the integration circuit 1221 is reset, and the voltage of the positive input terminal of the comparator CMP is zero) when the third control signal V_RST suddenly changes from a high level to a low level next time, and the fifth voltage signal V_SUM is again integrated with respect to time to generate the second voltage signal V_INT2. That is, the integration circuit 1221 can perform a secondary integration of the fifth voltage signal V_SUM with respect to time to generate a second voltage signal V_INT2 when the first switch tube Q1 is turned on. The voltage loop module 1222 is used to output a sixth voltage signal V_C according to the voltage difference between the reference voltage signal and the output voltage signal VOUT of the Buck_PFC circuit 21. The voltage value V c It is understandable that the output voltage Vout of the Buck PFC circuit 21 when it is working stably can be regarded as a constant value, so the voltage value V of the sixth voltage signal V_C is c Can be considered as a constant value.

[0058] The comparator CMP is used to compare the sixth voltage signal V_C and the second voltage signal V_INT2, and output the second control signal V_OFF. It can be understood that after the first switch tube Q1 is turned on, the second voltage signal V_INT2 gradually increases. cs_int2 is equal to the voltage value V of the sixth voltage signal V_C c , the second control signal V_OFF changes from a low level to a high level, the first switch tube Q1 is turned off, the integration circuit 1221 stops the integration operation, and the voltage value V of the second voltage signal V_INT2 is cs_int2 Therefore, in a single switching cycle of the first switch Q1, the voltage value V of the second voltage signal V_INT2 is cs_int2 The maximum value of is a constant value, which is equal to the voltage value V of the sixth voltage signal V_C. c .

[0059] Furthermore, during the conduction period of the first switch tube Q1, the voltage value V of the second voltage signal V_INT2 is cs_int2Proportional to the first product. For example, the gain of the voltage amplifier circuit GAIN is 3, and the secondary integral coefficient of the integration circuit 1221 is β 0 , then the voltage value V of the second voltage signal V_INT2 cs_int2 It can satisfy formula (1-4) and formula (1-5):

[0060]

[0061] V cs_s =V cs_g -V cs0 =3V cs -V cs0 (1-5)

[0062] Wherein, formula (1-4) is the integral formula when the integral circuit 1221 is working, T s is a single switching cycle of the first switch tube Q1, V cs_s is the voltage value of the fifth voltage signal V_SUM, V cs_g is the voltage value of the third voltage signal V_GAIN, V cs0 is the initial voltage value of the first voltage signal V_CS, V cs is the voltage value of the first voltage signal V_CS.

[0063] Based on the working principle of the Buck PFC circuit 21, in a single switching cycle of the first switch tube Q1, the voltage value V of the first voltage signal V_CS is cs Satisfy formula (1-6):

[0064]

[0065] Among them, k 2 is the rising slope of the first voltage signal V_CS.

[0066] According to formulas (1-4) to (1-6), during the conduction period of the first switch tube Q1, the voltage value V of the second voltage signal V_INT2 is cs_int2 Satisfy formula (1-7):

[0067]

[0068]

[0069] It can be seen from formula (1-6) that in a single switching cycle of the first switch tube Q1, the average voltage value V of the first voltage signal V_CS is cs_avg Satisfy formula (1-8):

[0070]

[0071] Since the current value I of the first current signal I_Q1 is 1 (i.e., equivalent to the input current value I of the Buck PFC circuit 21 in ) and the voltage value V of the first voltage signal V_CS cs is proportional to, then the average input current value I of the Buck PFC circuit 21 avg and the average voltage value V of the first voltage signal V_CS cs_avg Proportional, assuming that the sampling ratio is k 3 , then the average input current value I avg And the average voltage value V cs_avg Satisfy formula (1-9):

[0072] V cs_avg =k 3 *I avg (1-9)

[0073] Therefore, by combining formula (1-7) to formula (1-9), the first product (i.e., the average input current value Iavg of the Buck PFC circuit 21 and the current on-time t of the first switch tube Q1) is on The product of ) satisfies formula (1-10):

[0074]

[0075] It can be seen that when the gain of the voltage amplifier circuit GAIN is 3, the secondary integration coefficient of the integration circuit 1221 is β 0 , and the integral formula of the integral circuit 1221 when working satisfies the formula (1-4), during the conduction period of the first switch tube Q1, the voltage value V of the second voltage signal V_INT2 is cs_int2 Proportional to the first product.

[0076] Furthermore, it can be known from formula (1-7) that during the conduction period of the first switch tube Q1, the maximum voltage value V of the second voltage signal V_INT2 is cs_int2(max) Satisfy formula (1-11):

[0077]

[0078] From formula (1-10), it can be seen that the maximum value of the first product (i.e., the average input current value I of the Buck PFC circuit 21) avg The total conduction time T of the first switch tube Q1 on The product of ) satisfies formula (1-12):

[0079]

[0080] Optionally, due to the switching period T of the first switch tube Q1 s It can be regarded as a constant value, and the secondary integral coefficient β of the integral circuit 1221 0 Can be

[0081] It can be seen from this that Figure 2 The control circuit 1 shown can control the maximum value of the first product to be a constant value within a single switching cycle of the first switch tube Q1. Based on formula (1-3), it can be seen that when the maximum value of the first product is a constant value, the average input current value I of the Buck PFC circuit 21 is avg Follow the input voltage value V in change.

[0082] Below Figure 2 The specific circuit structures of the integration circuit 1221, the voltage loop module 1222 and the driving module 13 are exemplarily described.

[0083] Optional, such as Figure 2 As shown, the integration circuit 1221 may include a first integration circuit INT1 and a second integration circuit INT2. The first input terminal m of the integration circuit 1221 1 The first input terminal of the first integration circuit INT1 is connected to the output terminal of the first integration circuit INT1, and the first input terminal of the second integration circuit INT2 is connected to the output terminal of the first integration circuit INT1. 2 The second input terminal of the first integration circuit INT1 is connected to the second input terminal of the second integration circuit INT2 , and the output terminal of the second integration circuit INT2 is connected to the output terminal of the integration circuit 1221 .

[0084] Specifically, the first integration circuit INT1 is used to integrate the fifth voltage signal V_SUM with respect to time in the first stage when the third control signal V_RST is at a low level to generate the seventh voltage signal V_INT1. The second integration circuit INT2 is used to integrate the seventh voltage signal V_INT1 with respect to time in the first stage when the third control signal V_RST is at a low level to generate the second voltage signal V_INT2.

[0085] The voltage value V of the seventh voltage signal V_INT1 cs_int1 It can satisfy formula (1-13):

[0086]

[0087] Then, the voltage value V of the second voltage signal V_INT2 is cs_int2 It can satisfy formula (1-14):

[0088]

[0089] Wherein, formula (1-13) and formula (1-14) are respectively the integral formulas when the first integral circuit INT1 and the second integral circuit INT2 are working, β 1 is the primary integration coefficient of the first integration circuit INT1, β 2 is the first-level integration coefficient of the first integration circuit INT2.

[0090] From formula (1-14), it can be seen that when the first integration coefficient β of the first integration circuit INT1 is 1 and the first-order integration coefficient β of the second integration circuit INT2 2 The product of 0 When , formula (1-14) is the same as formula (1-4). It should be noted that this application applies to β 1 and β 2 The respective values ​​are not strictly limited, for example, β 1 and β 2 Can be equal to

[0091] In addition, in actual applications, when the third control signal V_RST suddenly changes from a high level to a low level, the first integration circuit INT1 and the second integration circuit INT2 usually do not integrate the voltage signal immediately, but wait for a period of time before integrating the voltage signal. That is to say, the first integration circuit INT1 and the second integration circuit INT2 are provided with a buffer time T banking , to filter out the current ringing and noise when the first switch tube Q1 is turned on. Buffer time T banking The setting can be realized by the internal circuits of the first integration circuit INT1 and the second integration circuit INT2, or can be realized by the first control signal V_ON. Taking the first integration circuit INT1 as an example, the first integration circuit INT1 includes a third input terminal, and the third input terminal of the first integration circuit INT1 is connected to the fourth input terminal h of the operation module 122. 4 (That is, the first integration circuit INT1 can receive the first control signal V_ON). The first integration circuit INT1 will start the integration operation only when the third control signal V_RST is at a low level and the first control signal V_ON changes from a high level to a low level. In other words, the buffer time T banking It can be equal to the time that the first control signal V_ON is at a high level.

[0092] Optional, see Figure 3 , Figure 3 is a schematic diagram of the structure of a voltage loop module provided in an embodiment of the present application. Figure 3 As shown, the input terminal n of the voltage loop module 1222 includes a first sub-input terminal n 11 and the second sub-input terminal n12 The voltage loop module 1222 includes a voltage detection module VSENCE and a loop compensation module LOOP. 1 The first sub-input terminal n connected to the voltage loop module 1222 11 , the negative output terminal o of the Buck PFC circuit 21 2 The second sub-input terminal n connected to the voltage loop module 1222 12 , the first sub-input terminal n of the voltage loop module 1222 11 The first input terminal of the voltage detection module VSENCE is connected to the second sub-input terminal n of the voltage loop module 1222. 12 The second input terminal of the voltage detection module VSENCE is connected, the output terminal of the voltage detection module VSENCE is connected to the first input terminal of the loop compensation module LOOP, and the output terminal of the loop compensation module LOOP is connected to the output terminal p of the voltage loop module 1222.

[0093] Specifically, the voltage detection module VSENCE is used to output an eighth voltage signal V_FB, and the voltage value of the eighth voltage signal V_FB is equal to the output voltage value V of the Buck PFC circuit 21. out The loop compensation module LOOP is used to output the sixth voltage signal V_C according to the voltage difference between the reference voltage signal V_REF and the eighth voltage signal V_FB. In practical applications, the loop compensation module LOOP may include a PI compensation or a type II compensation circuit.

[0094] Optional, see Figure 4 , Figure 4 Schematic diagram of a driving module provided in an embodiment of the present application. Figure 4 As shown, the driving module 13 includes a trigger SR and a driving circuit DRV. The first input terminal b of the driving module 13 1 Connect the set terminal S of the trigger SR, the second input terminal b of the driving module 13 2 The first output terminal Q of the trigger SR is connected to the reset terminal R of the trigger SR, the first output terminal Q of the trigger SR is connected to the input terminal of the driving circuit DRV, and the output terminal of the driving circuit DRV is connected to the first output terminal d of the driving module 13. 1 , the second output terminal of the flip-flop SR The second output terminal d connected to the driving module 13 2 .

[0095] Specifically, the driving circuit DRV is used to amplify the fifth control signal V_SR outputted from the first output terminal of the trigger SR to generate a fourth control signal V_GATE. The fourth control signal V_GATE has the same change trend as the fifth control signal V_SR.

[0096] It can be understood that when the first control signal V_ON received by the reset terminal R of the flip-flop SR suddenly changes from a low level to a high level, and the second control signal V_OFF received by the set terminal S of the flip-flop SR is a low level, then the fourth control signal V_GATE suddenly changes from a low level to a high level, and remains at a high level before the next second control signal V_OFF suddenly changes from a low level to a high level, and the first switch tube Q1 is in a conducting state. At the same time, the third control signal V_RST output by the second output terminal of the flip-flop SR suddenly changes from a high level to a low level, and remains at a low level before the second control signal V_OFF suddenly changes from a low level to a high level, and the integration circuit 1221 can be in a working state when the first switch tube Q1 is turned on.

[0097] After the first switch tube Q1 is turned on, the voltage value V of the second voltage signal V_INT2 generated by the integration circuit 1221 is cs_int2 gradually increases and reaches the voltage value V of the sixth voltage signal V_C c , the second control signal V_OFF received by the reset terminal R of the trigger SR suddenly changes from a low level to a high level, then the fourth control signal V_GATE suddenly changes from a high level to a low level, and remains at a low level before the next time the first control signal V_ON suddenly changes from a low level to a high level, and the first switch tube Q1 is switched to the off state. At the same time, the third control signal V_RST output by the second output terminal of the trigger SR suddenly changes from a low level to a high level, and remains at a high level before the next time the first control signal V_ON suddenly changes from a low level to a high level, and the integration circuit 1221 can be in a reset state when the first switch tube Q1 is turned off.

[0098] It can be seen from this that Figure 2 The control circuit 1 shown in FIG. 1 controls the average input current value I of the Buck PFC circuit 21. avg Follow the input voltage value V in When the signal changes, it involves the synergy between multiple signals. In order to better understand the working principle of the control circuit 1, the following is a further explanation based on the signal waveform diagram. Figure 5 , Figure 5 It is a signal waveform diagram provided in an embodiment of the present application.

[0099] Waveforms 501 to 510 are respectively waveforms of the first control signal V_ON, the first current signal I_Q1 (equivalent to the input current signal I_IN of the BuckPFC circuit 21), the first voltage signal V_CS, the third voltage signal V_GAIN, the fifth voltage signal V_SUM, the third control signal V_RST, the seventh voltage signal V_INT1, the second voltage signal V_INT2, the second control signal V_OFF and the fourth control signal V_GATE. Based on the waveform 501 of the first current signal I_Q1, it can be understood that in a single switching cycle T of the first switch tube Q1, s The input current of the internal Buck PFC circuit 21 is discontinuous and the peak input current and the average input current thereof do not have a linear relationship.

[0100] Combination Figures 2 to 5 It can be understood that when the first control signal V_ON output by the cycle control module 11 in the control circuit 1 suddenly changes from a low level to a high level, the fourth control signal V_GATE output by the drive circuit DRV in the drive module 13 suddenly changes from a low level to a high level and remains at a high level. The first switch tube Q1 in the Buck PFC circuit 21 starts to conduct (i.e., current flows through the first switch tube Q1), and the voltage sampling and holding circuit S / H starts to collect the initial voltage value V of the first voltage signal V_CS. cs0 , and outputs a fourth voltage signal V_SH when the first control signal V_ON changes from a high level to a low level (the voltage value of the fourth voltage signal V_SH is the initial voltage value V cs0 ). At the same time, the third control signal V_RST output by the trigger SR in the driving module 13 changes from a high level to a low level and remains at a low level, and the first integration circuit INT1 and the second integration circuit INT1 in the integration circuit 1221 start to perform a first-level integration operation respectively. Specifically, during the conduction time T of the first switch tube Q1 on The voltage value of the first voltage signal V_CS output by the current sampling module 121 follows the current value of the first current signal I_Q1 and shows an upward trend. The voltage amplifier circuit GAIN in the conduction time control module 12 amplifies the first voltage signal V_CS and outputs a third voltage signal V_GAIN. The addition and subtraction circuit SUM performs a voltage value V_GAIN on the third voltage signal V_GAIN. cs_g and the initial voltage value V of the first voltage signal V_CS cs0 The first integration circuit INT1 performs a first-level integration operation on the fifth voltage signal V_SUM and outputs a seventh voltage signal V_INT1. The second integration circuit INT2 performs a first-level integration operation on the seventh voltage signal V_INT1 and outputs a second voltage signal V_INT2. The voltage value V of the second voltage signal V_INT2 iscs_int2 It is showing a gradual upward trend.

[0101] When the voltage value of the second voltage signal V_INT2 is V cs_int2 The voltage value V of the sixth voltage signal V_C output by the voltage loop module 1222 is reached c , the second control signal V_OFF output by the comparator CMP suddenly changes from a low level to a high level, the trigger SR is reset and the fourth control signal V_GATE output by the drive circuit DRV suddenly changes from a high level to a low level, and is maintained at a low level. The first switch tube Q1 in the Buck PFC circuit 21 begins to turn off (i.e., no current flows through the first light-on tube Q1), and the voltage sampling and holding circuit S / H still outputs the fourth voltage signal until the first control signal V_ON output by the next cycle control module 11 suddenly changes from a low level to a high level, and then the initial voltage value of the first voltage signal V_CS will be collected again. At the same time, the third control signal V_RST output by the trigger SR in the drive module 13 suddenly changes from a low level to a high level, and is maintained at a high level, and the first integration circuit INT1 and the second integration circuit INT1 in the integration circuit 1221 stop performing the first-level integration operation (i.e., they are reset). Specifically, during the turn-off time T of the first switch tube Q1 off During the period, the seventh voltage signal V_INT1 and the second voltage signal V_INT2 are both zero. The first switch tube Q1 will not be turned on again until the first control signal V_ON output by the control module 11 changes from a low level to a high level in the next cycle.

[0102] Combined with the working principle of the control circuit 1 described in detail above, it can be known that Figure 2 The control circuit 1 shown can control the average input current value I of the Buck PFC circuit 21 in a single cycle of the first switch Q1. avg Follow the input voltage value V in Therefore, from the perspective of the AC power source S, in a single power frequency cycle of the AC power source S, the average input current value I of the Buck PFC circuit 21 is avg Follow the input voltage value V in For easier understanding, see Figure 6 , Figure 6 This is another signal waveform diagram provided in an embodiment of the present application.

[0103] Waveforms 601 to 604 are respectively the sinusoidal AC voltage signal V_AC output by the AC power source S, the AC current signal I_AC output by the AC power source S, the input voltage signal V_IN of the Buck PFC circuit 21 , and the input current signal I_IN of the Buck PFC circuit 21 .

[0104] like Figure 6As shown, since the Buck PFC circuit 21 is a step-down circuit, in a single power frequency cycle T of the AC power source S ac In the circuit, only the voltage value V of the input voltage signal V_IN of the Buck PFC circuit 21 is in Greater than the output voltage V of the Buck PFC circuit 21 out , the current value of the AC current signal I_AC and the current value of the input current signal I_IN are not zero.

[0105] And, because Figure 2 The control circuit 1 shown in FIG. 1 is used for a single switching cycle T of the first switch tube Q1 in the Buck PFC circuit 21. s The current signal flowing through the first switch tube Q1 is sampled in real time, so that in a single switching cycle T s Tracking control target. Therefore, Figure 2 The control circuit 1 shown has a fast response speed and can achieve fast convergence for circuit disturbances, thereby reducing the current oscillation generated in the Buck PFC circuit 21 during the control process. Figure 6 It can be seen from the marks 611 and 612 in FIG. 2 that the Buck PFC circuit 21 basically does not generate current oscillation.

[0106] It should be noted that Figure 2 The Buck PFC circuit 21 shown is a low-end drive Buck PFC circuit (ie, the source voltage of the main switch tube in the Buck PFC circuit is zero). The embodiment of the present application does not strictly limit the circuit structure of the Buck PFC circuit 21. Figure 2 The structure of the Buck PFC circuit 21 shown is only an example.

[0107] Optional, Figure 2 The Buck PFC circuit 21 shown can also be a high-end drive Buck PFC circuit (ie, the source voltage of the main switch tube in the Buck PFC circuit is not zero). Figure 7a , Figure 7a is a schematic diagram of the structure of a Buck PFC circuit provided in an embodiment of the present application. Figure 2 The Buck PFC circuit 21 shown, Figure 7a The electrical components in the Buck PFC circuit 21 shown are the same, but the connection methods between the electrical components are different. Specifically, the positive input terminal i of the Buck PFC circuit 21 1 One end of the first capacitor C1 is connected to the drain of the first switch tube Q1, the source of the first switch tube Q1 is connected to the cathode of the first diode D1 and one end of the first inductor L1, and the other end of the first inductor L1 is connected to one end of the second capacitor C2 and the positive output end of the Buck PFC circuit 21.1 , the negative input terminal i of the Buck PFC circuit 21 2 , the other end of the first capacitor C1, the anode of the first diode D1, the other end of the second capacitor C2 and the negative output end o of the Buck PFC circuit 21 2 Both are connected to the reference ground.

[0108] It is understandable that Figure 2 The Buck PFC circuit 21 and Figure 7a The Buck PFC circuit 21 shown, the proportionality coefficient k in formula (1-2) 1 are all 1. Therefore, see the detailed description above. Figure 2 It can be seen from the working principle of the control circuit 1 shown that Figure 2 The Buck PFC circuit 21 shown is Figure 7a When the Buck PFC circuit 21 shown is replaced, the control circuit 1 can still control Figure 7a The average input current value of the Buck PFC circuit 21 shown changes with the input voltage value, thereby achieving power factor correction.

[0109] Optional, Figure 2 The Buck PFC circuit 21 shown may also be a forward topology PFC circuit. For example, see Figure 7b , Figure 7b Schematic diagram of a forward topology PFC circuit provided in an embodiment of the present application. Figure 7b As shown, the forward topology PFC circuit 71 includes a third capacitor C3, a fourth capacitor C4, a second switch tube Q2, a second diode D2, a third diode D3, a second inductor L2, a first main winding N p1 , the first secondary winding N s1 , the first iron core F1.

[0110] Specifically, the positive input terminal i of the forward topology PFC circuit 71 3 Connect one end of the third capacitor C3 and the first primary winding N p1 One end of the first main winding N p1 The other end of the positive topology PFC circuit 71 is connected to the drain of the second switch tube Q2, and the negative input terminal i 4 The other end of the third capacitor C3 and the source of the second switch tube Q2 are all connected to the reference ground. p1 and the first secondary winding N s1 Wound on the first core F1, the first secondary winding N s1One end of the second inductor L2 is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the cathode of the third diode D3 and one end of the second inductor L2, and the other end of the second inductor L2 is connected to one end of the fourth capacitor C4 and the positive output end o of the forward topology PFC circuit 71. 3 , the negative output terminal o of the forward topology PFC circuit 71 4 Connect the first secondary winding N s1 the other end of the third diode D3, the anode of the third diode D3 and the other end of the fourth capacitor C4.

[0111] Understandably, Figure 7b The second switch tube Q2 in the forward topology PFC circuit 71 shown in FIG. Figure 2 The first switch Q1 in the Buck PFC circuit 21 shown in FIG. Figure 2 The Buck PFC circuit 21 shown, the proportionality coefficient k in formula (1-2) 1 is 1. Figure 7b The forward topology PFC circuit 71 shown, the proportionality coefficient k in formula (1-2) 1 The first secondary winding N s1 The number of turns of the first main winding N p1 The ratio of the number of turns, that is, the proportionality coefficient k 1 remains a constant value. Therefore, see the detailed description above. Figure 2 It can be seen from the working principle of the control circuit 1 shown that Figure 2 The Buck PFC circuit 21 shown is Figure 7b When the forward topology PFC circuit 71 shown is replaced, the control circuit 1 can still control the average input current value of the forward topology PFC circuit 71 to follow the input voltage value, thereby achieving power factor correction.

[0112] Optional, Figure 2 The Buck PFC circuit 21 shown may also be a push-pull topology PFC circuit. For example, see Figure 7c , Figure 7c Schematic diagram of a push-pull topology PFC circuit provided by an embodiment of the present application. Figure 7c As shown, the push-pull topology PFC circuit 72 includes a fourth capacitor C4, a fifth capacitor C5, a third switch tube Q3, a fourth switch tube Q4, a fourth diode D4, a fifth diode D5, a third inductor L3, a second primary winding N p2 , the third main winding N p3 , the second secondary winding N s2 and the third secondary winding N s3 .

[0113] Specifically, the positive input terminal i of the push-pull topology PFC circuit 725 Connect one end of the fourth capacitor C4 and the third main winding N p3 One end of the second main winding N p2 and the third main winding N p3 After being connected in series, the main side series winding is formed, and the second main side winding N p2 One end of the third primary winding N is connected to the drain of the third switch tube Q3. p3 The other end of the push-pull topology PFC circuit 72 is connected to the drain of the fourth switch tube Q4, and the negative input terminal i 6 , the other end of the fourth capacitor C4, the source of the third switch tube Q3, and the source of the fourth switch tube Q4 are all connected to the reference ground. s2 and the third secondary winding N s3 After being connected in series, the secondary series winding is formed. The primary series winding and the secondary series winding are wound on the second core F2. The second secondary winding N s2 One end of the fourth diode D4 is connected to the anode of the fourth diode D4, the cathode of the fourth diode D4 is connected to one end of the third inductor L3 and the cathode of the fifth diode D5, and the anode of the fifth diode D5 is connected to the third secondary winding N s3 The other end of the third inductor L3 is connected to one end of the fifth capacitor C5 and the positive output end o of the push-pull topology PFC circuit 72. 5 The other end of the fifth capacitor C5 is connected to the third secondary winding N s3 One end and the negative output end of the push-pull topology PFC circuit 72 o 6 .

[0114] Understandably, Figure 7c The third switch tube Q3 and the fourth switch tube Q4 in the push-pull topology PFC circuit 72 are alternately switched to output a voltage.

[0115] for Figure 2 The Buck PFC circuit 21 shown, the proportionality coefficient k in formula (1-2) 1 is 1. Figure 7b The push-pull topology PFC circuit 72 shown, the proportionality coefficient k in formula (1-2) is 1 It is twice the ratio between the number of turns of the primary series winding and the number of turns of the secondary series winding, that is, the proportionality coefficient k 1 remains a constant value. Therefore, see the detailed description above. Figure 2 It can be seen from the working principle of the control circuit 1 shown that Figure 2 The Buck PFC circuit 21 shown is Figure 7c When the push-pull topology PFC circuit 72 shown in FIG. 1 is replaced, the control circuit 1 can adopt the same method as that for the third switch tube Q3. Figure 2The same control method as the first switch tube Q1 in the Buck PFC circuit 21 is used to control the average input current value of the push-pull topology PFC circuit 72 to follow the input voltage value, thereby achieving power factor correction.

[0116] In summary, the control circuit in the embodiment of the present application can sample the current signal flowing through the main switch tube in real time within a single switching cycle of the main switch tube in the buck PFC circuit to control the average input current value of the buck PFC circuit to follow the input voltage value. It can not only control the buck PFC circuit to achieve power factor correction without sampling the input voltage, saving the control cost of the buck PFC circuit, but also achieve rapid convergence for circuit disturbances, reduce the current oscillation generated in the buck PFC circuit during the control process, and enhance the stability of the buck PFC circuit. In addition, the control circuit in the embodiment of the present application can be applied to a variety of buck PFC circuits, with a wide range of applications and high flexibility.

[0117] The "multiple" mentioned in the embodiments of this application refers to two or more. Also, unless otherwise specified, the "first" mentioned in the embodiments of this application is only used as a name identifier and is not used to limit the order, timing, priority or importance of multiple objects, such as the first control signal, the first switch tube, etc. The same rule applies to "second", "third" and "fourth", etc.

[0118] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A control circuit, characterized in that: The control circuit comprises a period control module (11), a conduction time control module (12) and a driving module (13), wherein: The period control module (11) is used to output a first control signal (V_ON), ​​and the period of the first control signal (V_ON) is a first preset threshold; The driving module (13) is used to control the first switch tube (Q1) in the buck-type power factor correction (PFC) circuit (2) to be turned on when the first control signal (V_ON) suddenly changes from a low level to a high level, the working mode of the buck-type PFC circuit (2) is a continuous current mode (CCM), and the input current value of the buck-type PFC circuit (2) is equal to the current value of the first current signal (I_Q1) flowing through the first switch tube (Q1); The on-time control module (12) is used to output a second control signal (V_OFF), and when a first product of a first average current value and a current on-time of the first switch tube (Q1) reaches a second preset threshold, the second control signal (V_OFF) suddenly changes from a low level to a high level, and the first average current value is an average current value of the first current signal (I_Q1) within a switching cycle of the first switch tube (Q1); The driving module (13) is used to control the first switch tube (Q1) to be turned off when the second control signal (V_OFF) suddenly changes from a low level to a high level.

2. The control circuit according to claim 1, characterized in that: The on-time control module (12) comprises a current sampling module (121) and a calculation module (122), wherein: The current sampling module (121) is used to convert the first current signal (I_Q1) into a first voltage signal (V_CS), and the current value of the first current signal (I_Q1) is proportional to the voltage value of the first voltage signal (V_CS); The operation module (122) is used to operate the first voltage signal (V_CS) to generate a second voltage signal (V_INT2) when the first switch tube (Q1) is turned on, and the voltage value of the second voltage signal (V_INT2) is proportional to the first product; The operation module (122) is also used to output the second control signal (V_OFF), and when the voltage value of the second voltage signal (V_INT2) reaches a third preset threshold, the second control signal (V_OFF) suddenly changes from a low level to a high level.

3. The control circuit according to claim 2, characterized in that: The operation module (122) comprises a voltage amplifier circuit (GAIN), a voltage sampling and holding circuit (S / H), an addition and subtraction operation circuit (SUM) and an integration circuit (1221); the positive input end of the addition and subtraction operation circuit (SUM) is connected to the output end of the voltage amplifier circuit (GAIN), the negative input end of the addition and subtraction operation circuit (SUM) is connected to the output end of the voltage sampling and holding circuit (S / H), and the output end of the addition and subtraction operation circuit (SUM) is connected to the input end of the integration circuit (1221), wherein: The voltage amplifier circuit (GAIN) is used to amplify the first voltage signal (V_CS) to output a third voltage signal (V_GAIN), and the voltage value of the third voltage signal (V_GAIN) is proportional to the voltage value of the first voltage signal (V_CS); The voltage sampling and holding circuit (S / H) is used to output a fourth voltage signal (V_SH), wherein the voltage value of the fourth voltage signal (V_SH) is equal to the initial voltage value of the first voltage signal (V_CS) when the first switch tube (Q1) starts to conduct; The addition and subtraction operation circuit (SUM) is used to output a fifth voltage signal (V_SUM), and the voltage value of the fifth voltage signal (V_SUM) is equal to the difference between the voltage value of the third voltage signal (V_GAIN) and the voltage value of the fourth voltage signal (V_SH); The integration circuit (1221) is used for performing a second-order integration of the fifth voltage signal (V_SUM) with respect to time to generate the second voltage signal (V_INT2) when the first switch tube (Q1) is turned on.

4. The control circuit according to claim 3, characterized in that: The operation module (122) further comprises a comparator (CMP) and a voltage loop module (1222), wherein the positive input terminal of the comparator (CMP) is connected to the output terminal of the integration circuit (1221), and the negative input terminal of the comparator (CMP) is connected to the output terminal of the voltage loop module (1222), wherein: The voltage loop module (1222) is used to output a sixth voltage signal (V_C) according to a voltage difference between a reference voltage signal and an output voltage signal (V_OUT) of the buck PFC circuit (2), wherein a voltage value of the sixth voltage signal (V_C) is equal to the third preset threshold value; The comparator (CMP) is used for comparing the sixth voltage signal (V_C) and the second voltage signal (V_INT2), and outputting the second control signal (V_OFF).

5. The control circuit according to claim 4, characterized in that: The first input end of the integration circuit (1221) is connected to the output end of the addition and subtraction circuit (SUM), the first output end of the driving module (13) is connected to the gate of the first switch tube (Q1), the second output end of the driving module (13) is connected to the second input end of the integration circuit (1221), the first input end of the driving module (13) is connected to the output end of the cycle control module (11), and the second input end of the driving module (13) is connected to the output end of the comparator (CMP), wherein: The driving module (13) is further used for controlling the integration circuit (1221) to output the second voltage signal (V_INT2) when the first control signal (V_ON) suddenly changes from a low level to a high level; The driving module (13) is also used for controlling the voltage value of the second voltage signal (V_INT2) to be zero when the second control signal (V_OFF) suddenly changes from a low level to a high level.

6. The control circuit according to claim 5, characterized in that: The integration circuit (1221) comprises a first integration circuit (INT1) and a second integration circuit (INT2), wherein a first input terminal of the integration circuit (1221) is connected to a first input terminal of the first integration circuit (INT1), an output terminal of the first integration circuit (INT1) is connected to a first input terminal of the second integration circuit (INT2), an output terminal of the second integration circuit (INT2) is connected to an output terminal of the integration circuit (1221), and a second input terminal of the integration circuit (1221) is connected to a second input terminal of the first integration circuit (INT1) and a second input terminal of the second integration circuit (INT2), wherein: The driving module (13) is used to output a third control signal (V_RST) through a second output terminal of the driving module (13); when the first control signal (V_ON) suddenly changes from a low level to a high level, the third control signal (V_RST) suddenly changes from a high level to a low level; and when the second control signal (V_OFF) suddenly changes from a low level to a high level, the third control signal (V_RST) suddenly changes from a low level to a high level; The first integration circuit (INT1) is used for performing a first-order integration of the fifth voltage signal (V_SUM) with respect to time to generate a seventh voltage signal when the third control signal (V_RST) is at a low level; The second integration circuit (INT2) is used for performing a first-order integration of the seventh voltage signal with respect to time to generate the second voltage signal (V_INT2) when the third control signal (V_RST) is at a low level.

7. The control circuit according to claim 6, characterized in that: The driving module (13) comprises a trigger (SR) and a driving circuit (DRV); a first input end of the driving module (13) is connected to a set end of the trigger (SR); a second input end of the driving module (13) is connected to a reset end of the trigger (SR); a first output end of the trigger (SR) is connected to an input end of the driving circuit (DRV); an output end of the driving circuit (DRV) is connected to a first output end of the driving module (13); and a second output end of the trigger (SR) is connected to a second output end of the driving module (13).

8. The control circuit according to any one of claims 3 to 7, characterized in that: The voltage value V of the second voltage signal (V_INT2) cs_int2 Satisfies the following formula: V cs_int2 =β0*∫0 t (∫0 t V cs_s dt)dt V cs_s =V cs_g -V cs0 =3V cs -V cs0 Wherein, the β0 is the preset secondary integral coefficient V cs_s is the voltage value of the fifth voltage signal (V_SUM), the V cs_g is the voltage value of the third voltage signal (V_GAIN), the V cs0 is the voltage value of the fourth voltage signal (V_SH), the V cs is the voltage value of the first voltage signal (V_CS).

9. The control circuit according to claim 8, characterized in that: The buck PFC circuit (2) comprises a buck Buck PFC circuit (21), a forward topology PFC circuit (71) or a push-pull topology PFC circuit (72).

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