A switching chip, a circuit system and an electronic device

Abstract

The present invention provides a switching chip, a circuit system and an electronic device. The chip includes a gate pin, a source pin and a drain pin. The gate pin is connected to a switching control signal, the source pin is connected to a power supply voltage, and the drain pin is connected to a load. A boost module is configured to boost the difference between the power supply voltage and the switching control signal and output a corresponding boosted voltage. An anti-backflow module is configured to disconnect the connection between its input terminal and output terminal when the switching control signal is at a high level; and establish the connection between its input terminal and output terminal when the switching control signal is at a low level. An NMOS transistor has its gate connected to the output terminal of the anti-backflow module, its drain connected to the source pin, and its source connected to the drain pin; a pull-down module is configured to pull down the gate voltage of the NMOS transistor to the source voltage of the NMOS transistor when the switching control signal is at a high level. The switching chip of the present invention can not only reduce the circuit cost of the chip, but also reduce the application cost of the chip.

Description

Technical Field

[0001] The present invention relates to the field of circuit switches, and particularly to a switching chip, a circuit system and an electronic device. Background Art

[0002] Using MOS transistors as switches has become a common technical means in the industry. Specific application scenarios are roughly divided into: high-side switches and low-side switches. Among them, the high-side switch is coupled between the power supply and the load. The low-side switch is coupled between the load and the ground terminal.

[0003] Although the prior art usually selects PMOS transistors as high-side switches. However, on the premise of the same breakdown voltage and the same impedance, the size of the PMOS transistor is 2 - 3.5 times that of the NMOS transistor. Therefore, compared with using PMOS transistors as high-side switches, using NMOS transistors as high-side switches can greatly save circuit costs.

[0004] However, existing switching chips that select NMOS transistors as high-side switches have high application costs because they need to re-design the boost circuit for different application scenarios and have low pin compatibility.

[0005] Therefore, providing a switching chip that can both reduce circuit costs and application costs has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0006] Embodiments of the present invention provide a switching chip, a circuit system and an electronic device, which can both reduce the circuit costs of the switching chip and reduce the application costs of the switching chip.

[0007] To solve the above technical problems, the technical solution of the present invention provides a switching chip, including:

[0008] A gate pin, a source pin and a drain pin, the gate pin is connected to a switch control signal, the source pin is connected to a power supply voltage, and the drain pin is connected to a load;

[0009] A boost module, whose ground terminal is connected to the gate pin, and whose power supply terminal is connected to the source pin, the boost module is used to boost the difference between the power supply voltage and the switch control signal, and output a corresponding boosted voltage;

[0010] An anti-backflow module, whose input terminal is connected to the output terminal of the boost module, the anti-backflow module is used for: when the switch control signal is at a high level, completely cut off the connection between its input terminal and output terminal; and when the switch control signal is at a low level, establish the connection between its input terminal and output terminal;

[0011] An NMOS transistor, whose drain is connected to the source pin, whose gate is connected to the output terminal of the anti-backflow module, and whose source is connected to the drain pin;

[0012] A pull-down module, which is used to pull down the gate voltage of the NMOS transistor to the source voltage of the NMOS transistor when the switch control signal is at a high level;

[0013] Wherein, the boost module, the anti-backflow module, the NMOS transistor and the pull-down module are all integrated in the same chip.

[0014] Optionally, the boost module is a charge pump.

[0015] Optionally, the charge pump is specifically a second-order voltage-doubling charge pump.

[0016] Optionally, the anti-backflow module includes a first PMOS transistor, whose gate is connected to the source pin, whose source is used as the input terminal of the anti-backflow module, whose drain is used as the output terminal of the anti-backflow module, and the substrate of the first PMOS transistor is connected to its own source.

[0017] Optionally, the anti-backflow module includes a second PMOS transistor, whose gate is connected to the source pin, whose source is used as the input terminal of the anti-backflow module, whose drain is used as the output terminal of the anti-backflow module, and its substrate is connected to the pole with the maximum voltage among its own source and its own drain.

[0018] Optionally, the pull-down module includes a pull-down resistor, the input terminal of the pull-down resistor is connected to the gate of the NMOS transistor, and the output terminal of the pull-down resistor is connected to the source of the NMOS transistor.

[0019] Optionally, the resistance value of the pull-down resistor is greater than or equal to a first threshold, and the first threshold is used to represent the minimum resistance value for maintaining the normal driving of the NMOS transistor.

[0020] Optionally, the difference between the power supply voltage and the high level of the switch control signal is less than a second threshold, and the second threshold is used to represent the minimum operating voltage of the boost module.

[0021] The technical solution of the present invention also provides a circuit system, including the switch chip.

[0022] The technical solution of the present invention also provides an electronic device, including the circuit system.

[0023] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0024] The switching chip provided by the technical solution of the present invention, compared with the high-side switching chip integrated with PMOS transistors, realizes the function of high-side switching by integrating NMOS transistors. Therefore, the chip area is greatly reduced under the same on-resistance, thereby reducing the circuit cost of the switching chip. At the same time, by multiplexing the ground terminal of the boost module as the input control terminal of the boost module, the switching chip can be compatible with the existing PMOS high-side switching chips without the need to additionally set a ground terminal pin, thereby improving the compatibility of the switching chip and further reducing the application cost of the switching chip. In addition, the boost module outputs a boosted voltage according to the difference between the external power supply voltage and the external switch control signal. Therefore, the conduction of the NMOS transistor by the boost module is independent of the parameters of the internal circuit of the boost module. Compared with the existing high-side switching chips integrated with NMOS transistors, the switching chip of the present invention does not need to redesign the boost module in different application scenarios, thereby further reducing the application cost of the switching chip.

[0025] At the same time, through the anti-backflow module and the pull-down module, it is ensured that the NMOS transistor is completely turned off when the switch control signal is at a high level, so as to ensure that the NMOS transistor can be turned off, and at the same time, 0 standby power consumption is achieved during shutdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the circuit structure of the switching chip provided by an embodiment of the present invention Figure 1 ;

[0027] Figure 2 Schematic diagram of the circuit structure of the switching chip provided by an embodiment of the present invention Figure 2 。 DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention. Terms such as "gate", "source", "drain", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0029] A high-side switch specifically refers to a switch disposed between a power supply voltage and a load, and is used to control the on and off between the power supply voltage and the load. If a PMOS transistor is used as the high-side switch, as long as the gate voltage of the PMOS transistor is pulled down to the ground terminal, the high-side switch can be turned on. If an NMOS transistor is used as the high-side switch, a voltage higher than the power supply voltage needs to be applied at the gate of the NMOS transistor to turn on the high-side switch. Therefore, a boost circuit needs to be additionally provided for the high-side switch of the NMOS transistor. Although using an NMOS transistor as the high-side switch requires an additional boost circuit to increase the complexity of the circuit, in the case of the same breakdown voltage and the same impedance, the size of the PMOS transistor is up to 2-3.5 times that of the NMOS transistor. Therefore, those skilled in the art still prefer to use the NMOS transistor as the high-side switch.

[0030] However, there are still the following problems when using an NMOS transistor as the high-side switch:

[0031] 1. When it is necessary to replace the high-side switch of the PMOS transistor with the high-side switch of the NMOS transistor, since an additional boost circuit is required inside the high-side switch of the NMOS transistor and this boost circuit needs to be grounded, an additional ground pin needs to be provided for the high-side switch of the NMOS transistor on the basis of the original high-side switch when replacing the switch. That is, the existing high-side switch of the NMOS transistor and the existing high-side switch of the PMOS transistor are not compatible in the pin architecture, thus increasing the application cost of the high-side switch of the replaced NMOS transistor.

[0032] 2. In different application scenarios of the existing high-side switch of the NMOS transistor, it is necessary to debug the parameters of the internal devices of the boost circuit to ensure that the voltage output by the boost circuit can fully turn on the NMOS transistor, thereby increasing the application cost of the high-side switch of the NMOS transistor in different application scenarios.

[0033] In view of this, the embodiments of the present invention provide a new switching chip to greatly reduce the application cost of the switching chip as a high-side switch in different application scenarios.

[0034] Among them, Figure 1 is the circuit structure schematic diagram of the switching chip provided by the embodiment of the present invention Figure 1 .

[0035] Please refer to Figure 1 , the switching chip provided by the embodiment of the present invention includes:

[0036] A gate pin G, a source pin S, and a drain pin D. The gate pin G is connected to a switch control signal V1, the source pin S is connected to a power supply voltage VDD, and the drain pin D is connected to a load;

[0037] A boost module, whose ground terminal AGND is connected to the gate pin G, and whose power supply terminal AVDD is connected to the source pin S. The boost module is used to boost the difference between the power supply voltage VDD and the switch control signal V1 and output a corresponding boost voltage VGC;

[0038] An anti-backflow module 20, whose input terminal is connected to the output terminal of the boost module. The anti-backflow module 20 is used for: when the switch control signal V1 is at a high level, completely disconnect the connection between its input terminal and output terminal; and when the switch control signal V1 is at a low level, establish the connection between its input terminal and output terminal;

[0039] An NMOS transistor M1, whose drain is connected to the source pin S, whose gate is connected to the output terminal of the anti-backflow module 20, and whose source is connected to the drain pin D;

[0040] A pull-down module 30, which is used to pull down the gate voltage of the NMOS transistor M1 to the source voltage of the NMOS transistor M1 when the switch control signal V1 is at a high level;

[0041] Among them, the boost module, the anti-backflow module 20, the NMOS transistor M1, and the pull-down module 30 are all integrated in the same chip.

[0042] The pin settings of the high-side switch of the existing PMOS transistor specifically include: the gate pin G, the source pin S, and the drain pin D, which respectively correspond to the gate, source, and drain of the PMOS transistor. The gate pin G of the high-side switch of the PMOS transistor is connected to the PWM pulse signal to drive the conduction or cut-off of the PMOS transistor; its source pin S is connected to the power supply voltage VDD; its drain pin D is connected to the input end of the load.

[0043] In order to make the pin architecture of the switch chip in the embodiment of the present invention compatible with the high-side switch of the existing PMOS transistor, the present invention multiplexes the ground terminal AGND of the boost module inside the switch chip as the input control terminal and connects it to the gate pin G of the switch chip, thereby avoiding the need to additionally set a ground pin for the ground terminal AGND of the boost module. In addition, the power supply terminal AVDD of the boost module is connected to the source pin S of the switch chip. When the source pin S of the switch chip of the present invention is connected to the power supply voltage VDD and the gate pin G is connected to the switch control signal V1, the boost module will directly boost according to the difference between the power supply voltage VDD and the switch control signal V1 and output the corresponding boosted voltage VGC.

[0044] If the switch control signal V1 is at a low level, the boosted voltage VGC is boosted to be greater than the power supply voltage VDD. For example, when the power supply voltage VDD is 5V and the switch control signal V1 is at a low level, the boost module will increase the 5V difference to 8V - 10V according to its own boosting ability. At this time, the anti-backflow module 20 establishes a connection between its input end and output end and outputs the boosted voltage VGC to the gate of the NMOS transistor M1 to turn on the NMOS transistor M1.

[0045] If the switch control signal V1 is at a high level, the boosted voltage VGC is approximately equal to the power supply voltage VDD. At this time, the anti-backflow module 20 completely cuts off the connection between its input end and output end. The pull-down module 30 then pulls down the gate voltage of the NMOS transistor M1 to the source voltage of the NMOS transistor M1 to turn off the NMOS transistor M1.

[0046] Therefore, through the above technical means, on the basis of integrating the NMOS transistor M1, the control method of the switch chip provided by the embodiment of the present invention is completely equivalent to the high-side switch of the existing PMOS transistor, thereby being compatible with the pin architecture of the high-side switch of the existing PMOS transistor, and further reducing the application cost of the switch chip.

[0047] In addition, the boost module of the switch chip outputs a boosted voltage VGC based on the difference between the externally input power supply voltage VDD and the externally input switch control signal V1. Therefore, the conduction of the NMOS transistor M1 by the boost module is independent of the parameters of the internal circuit of the boost module. Compared with the existing high-side switch chip integrating the NMOS transistor M1, the switch chip of the present invention does not need to redesign the boost module in different application scenarios, thereby further reducing the application cost of the switch chip.

[0048] Finally, through the anti-backflow module 20 and the pull-down module 30, it is ensured that the NMOS transistor M1 is completely turned off when the switch control signal V1 is at a high level, so as to ensure that the NMOS transistor can be turned off, and at the same time, 0 standby power consumption is achieved during shutdown.

[0049] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0050] Please refer to Figure 1 , as a specific embodiment, the boost module is a charge pump circuit, and the charge pump circuit is specifically a second-order voltage doubler charge pump. The power supply terminal AVDD of the second-order voltage doubler charge pump inputs the power supply voltage VDD connected to the source pin S, and the ground terminal AGND of the second-order voltage doubler charge pump is used as the input control terminal to input the switch control signal V1 connected to the gate pin G, so as to realize the multiplexing of the ground terminal AGND and the input control terminal of the second-order voltage doubler charge pump, so that the switch chip of the present invention embodiment does not need to additionally set a ground terminal AGND pin for the ground terminal AGND, thereby making the switch chip of the present invention embodiment compatible with the pin architecture of the existing PMOS transistor switch chip, and further reducing the application cost of the switch chip.

[0051] Since the second-order voltage doubler charge pump is a conventional technical means in the art, its specific circuit structure will not be described in detail here. Of course, in addition to the second-order voltage doubler charge pump, other types of charge pumps can also be selected for the boost module, which is not limited here.

[0052] Among them, Figure 2 is a schematic circuit structure of the switch chip provided by the embodiment of the present invention Figure 2 .

[0053] Please refer to Figure 2 , as a specific embodiment, the anti-backflow module 20 includes a first PMOS transistor M2, whose gate is connected to the source pin S, whose source is used as the input terminal of the anti-backflow module 20, whose drain is used as the output terminal of the anti-backflow module 20, and the substrate of the first PMOS transistor M2 is connected to its own source.

[0054] The pull-down module 30 includes a pull-down resistor R1. Among them, if the resistance value of the pull-down resistor R1 is too small, the pull-down resistor R1 will divert a large current, thereby affecting the charging of the gate voltage of the NMOS transistor M1, and further affecting the conduction of the NMOS transistor M1. Therefore, it is necessary to set the resistance value of the pull-down resistor R1 to be greater than or equal to a first threshold to ensure that the pull-down resistor R1 does not affect the normal conduction of the NMOS transistor M1.

[0055] Among them, the first threshold is used to represent the minimum resistance value for maintaining the normal driving of the NMOS transistor. For example, if the boost module can provide a driving current of 1 mA, the calculation formula for the first threshold is as follows: Rth = VGC / 10 μA; Formula (1) where, Rth is used to represent the first threshold; VGC is used to represent the gate-source voltage of the switching NMOS transistor.

[0056] When the gate-source voltage of the NMOS transistor is equal to 10 V, the first threshold is set to 1 MΩ. Of course, the specific value of the first threshold is related to the driving ability of the boost module and the gate-source voltage of the NMOS transistor, and is not limited here.

[0057] Please refer to Figure 2 , the following takes the power supply voltage VDD as 5 V specifically, the boost module as a second-order voltage-doubling charge pump, and the high and low levels of the switch control signal V1 as 5 V and 0 V respectively, to illustrate the working principles of the anti-backflow module 20 and the pull-down module 30:

[0058] When the switch control signal V1 is at a low level, the voltage difference between the power supply terminal AVDD and the ground terminal AGND of the boost module is 5 V. The boost module boosts this voltage difference and outputs a boosted voltage VGC of 10 V to the source of the first PMOS transistor M2. The gate of the first PMOS transistor M2 is connected to the power supply voltage VDD of 5 V. Therefore, the source-gate voltage difference of the first PMOS transistor M2 is 5 V, which is greater than the threshold voltage of the first PMOS transistor M2 and turns on the first PMOS transistor M2. Since the drain of the first PMOS transistor M2 is connected to the gate of the NMOS transistor M1, the boosted voltage VGC acts on the gate of the NMOS transistor M1 to turn on the NMOS transistor M1. Since the boosted voltage VGC has a strong driving ability at this time, the gate voltage of the NMOS transistor M1 will not be pulled down to the source voltage of the NMOS transistor M1 by the pull-down resistor R1. Therefore, the pull-down resistor R1 does not work.

[0059] When the switch control signal V1 is at a high level, the voltage difference between the power supply terminal AVDD and the ground terminal AGND of the boost module is 0V. This voltage difference is less than the normal operating voltage of the boost module. Therefore, the boost module outputs a boosted voltage VGC of approximately 5V to the source of the first PMOS transistor M2. The gate of the first PMOS transistor M2 is connected to the power supply voltage VDD of 5V. Therefore, the source-gate voltage difference of the first PMOS transistor M2 is approximately 0V, which is less than the threshold voltage of the first PMOS transistor M2, turning off the first PMOS transistor M2. Since the anode of the body diode of the first PMOS transistor M2 is connected to its own drain and the cathode of the body diode of the first PMOS transistor M2 is connected to its own source. Therefore, when the first PMOS transistor M2 is turned off, the boosted voltage VGC will not be transferred from its own source to its own drain through the body diode of the first PMOS transistor M2, preventing the boosted voltage VGC from acting on the gate of the NMOS transistor M1, thereby completely isolating between the output terminal of the boost module and the gate of the NMOS transistor M1. At this time, since the gate of the NMOS transistor M1 is in a floating state, the pull-down resistor R1 will pull down the gate voltage of the NMOS transistor M1 to its own source voltage, that is, the gate-source voltage of the NMOS is approximately 0V, thus ensuring that the NMOS transistor M1 is turned off.

[0060] Of course, in addition to the first PMOS transistor M2 described above, other PMOS transistor switch circuits with anti-backflow functions are also within the protection scope of the present invention and are not limited herein.

[0061] As a specific implementation manner, the switch control signal V1 is specifically a periodic PWM pulse signal. And the difference between the high level of the PWM pulse signal and the voltage value of the power supply voltage VDD is less than a second threshold. The second threshold is used to characterize the minimum operating voltage of the boost module.

[0062] As can be seen from the above, when the PWM pulse signal is at a high level, the boost module will output a boosted voltage VGC approximately equal to the power supply voltage VDD, which means that the boost module does not work. Also, since the boost module can only work normally when the voltage difference between its own power supply terminal AVDD and the ground terminal AGND is greater than a certain threshold. Therefore, by setting the difference between the high level of the PWM pulse signal and the power supply voltage VDD to be less than this threshold, it is ensured that the boost module does not work when the PWM pulse signal is at a high level, and further ensures that the anti-backflow module 20 functions, so that the pull-down module 30 turns off the NMOS transistor M1.

[0063] In summary, the switching chip provided by the embodiment of the present invention realizes the function of the high-side switch by integrating an NMOS transistor. Compared with the existing switching chip with a PMOS transistor, the area of the chip is greatly reduced, thereby reducing the circuit cost of the switching chip. At the same time, the switching chip provided by the embodiment of the present invention also multiplexes the ground terminal of the boost module as the input control terminal, so that the switching chip can be compatible with the existing PMOS high-side switching chip without an additional ground terminal pin, thereby improving the compatibility of the switching chip and further reducing the application cost of the switching chip. In addition, the boost module outputs a boost voltage according to the difference between the external power supply voltage and the external switch control signal. Therefore, the conduction of the NMOS transistor by the boost module is independent of the parameters of the internal circuit of the boost module. Compared with the existing high-side switching chip integrating an NMOS transistor, the switching chip of the present invention does not need to redesign the boost module in different application scenarios, thereby further reducing the application cost of the switching chip.

[0064] At the same time, through the anti-backflow module and the pull-down module, it is ensured that the NMOS transistor is completely turned off when the switch control signal is at a high level, so as to ensure that the NMOS transistor can be turned off, and at the same time, 0 standby power consumption is achieved during shutdown.

[0065] The embodiment of the present invention also provides a circuit system, including the switching chip provided by the embodiment of the present invention.

[0066] The embodiment of the present invention also provides an electronic device, including the circuit system provided by the embodiment of the present invention.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A switch chip, characterized in that: include: A gate pin, a source pin and a drain pin, wherein the gate pin is connected to a switch control signal, the source pin is connected to a power supply voltage, and the drain pin is connected to a load; A boost module, whose ground terminal is connected to the gate pin, and whose power terminal is connected to the source pin, and the boost module is used to boost the difference between the power supply voltage and the switch control signal, and output a corresponding boost voltage; An anti-backflow module, whose input end is connected to the output end of the boost module, and the anti-backflow module is used to: completely cut off the connection between its own input end and output end when the switch control signal is at a high level; and establish a connection between its own input end and output end when the switch control signal is at a low level; An NMOS tube, whose drain is connected to the source pin, whose gate is connected to the output end of the anti-backflow module, and whose source is connected to the drain pin; A pull-down module, used for pulling down the gate voltage of the NMOS tube to the source voltage of the NMOS tube when the switch control signal is at a high level; The boost module, the anti-backflow module, the NMOS tube and the pull-down module are all integrated in the same chip; The anti-backflow module comprises a first PMOS tube, whose gate is connected to the source pin, whose source serves as the input end of the anti-backflow module, and whose drain serves as the output end of the anti-backflow module. The substrate of the first PMOS tube is connected to its own source.

2. The switch chip according to claim 1, characterized in that: The boost module is a charge pump.

3. The switch chip according to claim 2, characterized in that: The charge pump is specifically a second-order voltage-doubling charge pump.

4. The switch chip according to claim 1, characterized in that: The anti-backflow module includes a second PMOS tube, whose gate is connected to the source pin, whose source serves as the input end of the anti-backflow module, whose drain serves as the output end of the anti-backflow module, and whose substrate is connected to the one with the largest voltage between its own source and its own drain.

5. The switch chip according to claim 1, characterized in that: The pull-down module comprises a pull-down resistor, an input end of the pull-down resistor is connected to the gate of the NMOS tube, and an output end of the pull-down resistor is connected to the source of the NMOS tube.

6. The switch chip according to claim 5, characterized in that: The resistance of the pull-down resistor is greater than or equal to 1 megohm.

7. The switch chip according to claim 1, characterized in that: The difference between the power supply voltage and the high level of the switch control signal is smaller than a first threshold value, and the first threshold value is used to represent the minimum operating voltage of the boost module.

8. A circuit system, characterized in that: A switch chip comprising any one of claims 1 to 7.

9. An electronic device, characterized in that: A circuit system comprising the circuit system of claim 8.

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