A flip-flop for determining an initial state

Abstract

The application provides a flip-flop for determining an initial state, comprising a transmission circuit, a first initial state circuit and a second initial state circuit; the transmission circuit is connected with the first initial state circuit and the second initial state circuit respectively; the transmission circuit comprises a first tri-state inverter, a second tri-state inverter and a first inverter connected in sequence; the first initial state circuit comprises a first gate circuit and a second inverter; the first initial state circuit is used for accelerating the flip-flop speed to lock the output of the first tri-state inverter; the second initial state circuit comprises a second gate circuit and a third inverter; the second initial state circuit is used for accelerating the flip-flop speed to lock the output of the second tri-state inverter. The application removes the reset circuit, reduces the number of gate circuits, improves the anti-interference ability of the flip-flop and improves the area utilization rate of the flip-flop.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flip-flop, in particular to a flip-flop for determining initial state. BACKGROUND

[0002] With the increasing scale of digital circuits, a very large scale integrated circuit needs a large number of flip-flops, and the traditional flip-flop needs a RSTN reset signal to define the initial state of the flip-flop, so that some reset circuit needs to be provided for the reset signal to realize its function, and the area in the flip-flop is very valuable, and the integration and density of the integrated circuit will be well optimized with every reduction of the area of the flip-flop.

[0003] However, the logic gate circuit occupied by the reset circuit has a certain number in the flip-flop, and the traditional flip-flop with reset needs 28 mos tubes in total, which is difficult to meet the requirements of high speed, low power consumption and small area of the integrated circuit. Therefore, it is necessary to design a flip-flop for determining initial state. SUMMARY

[0004] The purpose of the present application is to provide a flip-flop for determining initial state, so as to reduce the number of gate circuits by removing the reset circuit, improve the anti-interference ability of the flip-flop and improve the area utilization rate of the flip-flop.

[0005] To achieve the above purpose, the present application provides the following scheme:

[0006] A flip-flop for determining initial state, comprising: a transmission circuit, a first initial state circuit and a second initial state circuit; the transmission circuit is connected with the first initial state circuit and the second initial state circuit respectively;

[0007] The transmission circuit comprises a first tri-state inverter, a second tri-state inverter and a first inverter connected in sequence;

[0008] The first initial state circuit comprises a first gate circuit and a second inverter; the first initial state circuit is used for accelerating the flip-flop speed to lock the output of the first tri-state inverter;

[0009] The second initial state circuit comprises a second gate circuit and a third inverter; the second initial state circuit is used for accelerating the flip-flop speed to lock the output of the second tri-state inverter.

[0010] Optionally, the first tri-state inverter comprises a pmos tube P1, a pmos tube P2, an nmos tube N1 and an nmos tube N2 connected in sequence; the source of the pmos tube P1 is connected with a power supply, the gate of the pmos tube P1 is connected with the first initial state circuit, the source of the nmos tube N2 is grounded, and the connection ends of the pmos tube P2 and the nmos tube N1 are respectively connected with the second tri-state inverter and the first initial state circuit.

[0011] Optionally, the second tri-state inverter comprises a pmos transistor P6, a pmos transistor P7, an nmos transistor N6 and an nmos transistor N5 connected in sequence; a source of the pmos transistor P6 is connected with a power supply, gates of the pmos transistor P6 are connected with the first tri-state inverter and the second initial state circuit respectively, a source of the nmos transistor N5 is grounded, and connection ends of the pmos transistor P7 and the nmos transistor N6 are connected with the first inverter and the second initial state circuit respectively.

[0012] Optionally, the first inverter comprises a pmos transistor P11 and an nmos transistor N9 connected in sequence; a source of the pmos transistor P11 is connected with a power supply, a source of the nmos transistor N9 is grounded, and a gate connection end of the pmos transistor P11 and the nmos transistor N9 is connected with the second tri-state inverter.

[0013] Optionally, the first gate circuit comprises a pmos transistor P3, a pmos transistor P4 and an nmos transistor N3, and the second inverter comprises a pmos transistor P5 and an nmos transistor N4; a gate of the pmos transistor P3 is connected with the first tri-state inverter, a drain of the pmos transistor P3 is connected with a gate of the pmos transistor P4, a source of the pmos transistor P3 is connected with a power supply, sources of the pmos transistor P4 and the pmos transistor P5 are both connected with the power supply, a gate of the pmos transistor P4 is connected with a gate of the nmos transistor N3, a drain of the pmos transistor P5, a drain of the nmos transistor N4, the transmission circuit and the first gate circuit, a drain of the pmos transistor P4 is connected with a drain of the nmos transistor N3, a gate of the pmos transistor P5 and a gate of the nmos transistor N4 respectively, and sources of the nmos transistor N3 and the nmos transistor N4 are both grounded.

[0014] Optionally, the second gate circuit comprises a pmos transistor P8, a pmos transistor P9 and an nmos transistor N7, and the third inverter comprises a pmos transistor P10 and an nmos transistor N8; a gate of the pmos transistor P8 is connected with the second tri-state inverter, a drain of the pmos transistor P8 is connected with a gate of the pmos transistor P9, a source of the pmos transistor P8 is connected with a power supply, sources of the pmos transistor P9 and the pmos transistor P10 are both connected with the power supply, a gate of the pmos transistor P9 is connected with a gate of the nmos transistor N7, a drain of the pmos transistor P10, a drain of the nmos transistor N8, the transmission circuit and the second gate circuit, a drain of the pmos transistor P9 is connected with a drain of the nmos transistor N7, a gate of the pmos transistor P10 and a gate of the nmos transistor N8 respectively, and sources of the nmos transistor N7 and the nmos transistor N8 are both grounded.

[0015] According to the specific embodiments provided by the present application, the following technical effects are disclosed: the flip-flop for determining the initial state provided by the present application comprises a transmission circuit, a first initial state circuit and a second initial state circuit; the transmission circuit is connected with the first initial state circuit and the second initial state circuit respectively; the transmission circuit comprises a first tri-state inverter, a second tri-state inverter and a first inverter connected in sequence; the first initial state circuit comprises a first gate circuit and a second inverter; the first initial state circuit is used for accelerating the flip-flop speed to latch the output of the first tri-state inverter; the second initial state circuit comprises a second gate circuit and a third inverter; the second initial state circuit is used for accelerating the flip-flop speed to latch the output of the second tri-state inverter. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art without any creative effort based on these drawings.

[0017] Figure 1 The structure diagram of the flip-flop of the embodiment of the present application is shown in the figure.

[0018] Figure 2 The circuit structure diagram of the embodiment of the present application is shown in the figure.

[0019] Figure 3 The timing diagram of the flip-flop of the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the protection scope of the present application.

[0021] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail in combination with the drawings and specific embodiments.

[0022] The present application provides a flip-flop which does not need an additional reset signal and can reset the internal latch state by using the input signal only, and only needs 7 circuit transistors and 20 MOS transistors. Figure 1As shown, inv1 and inv2 are three-state inverters, inv3, inv4, and inv5 are inverters, nand1 and nand2 are NAND gates, A is the input signal, Y is the output signal, and CLKP and CLKN are complementary clocks. An embodiment of the present invention provides a trigger for determining an initial state, comprising: a transmission circuit, a first initial state circuit, and a second initial state circuit; the transmission circuit is connected to the first initial state circuit and the second initial state circuit, respectively. The transmission circuit includes a first three-state inverter, a second three-state inverter, and a first inverter connected in sequence; the first initial state circuit includes a first gate circuit and a second inverter; the first initial state circuit is used to accelerate the flipping speed and latch the output of the first three-state inverter; the second initial state circuit includes a second gate circuit and a third inverter; the second initial state circuit is used to accelerate the flipping speed and latch the output of the second three-state inverter.

[0023] Specifically, when CLKN is high, inv1 transmits input signal A to node B. nand1 and inv4 form a latch circuit, accelerating the flipping speed to latch the state of point B. This allows the initial state of point B to be controlled by nand1's input signal A, eliminating the need for a reset signal. When CLKN is low, inv1 outputs a high-impedance state, Z, and the potential at point B is maintained by nand1 and inv4. When CLKP is high, inv2 transmits input signal B to node C. nand2 and inv5 form a latch circuit, accelerating the flipping speed to latch the state of point C. This allows the initial state of point C to be controlled by nand2's input signal B, eliminating the need for a reset signal. When CLKP is low, inv2 outputs a high-impedance state, Z, and the potential at point C is maintained by latches nand2 and inv5, ultimately outputting state Y through inv3.

[0024] like Figure 2 As shown, the first tri-state inverter includes: pmos transistor P1, pmos transistor P2, nmos transistor N1, and nmos transistor N2. The source of pmos transistor P1 is connected to a power supply, the gate of pmos transistor P1 is connected to input signal A, and the drain of pmos transistor P1 is connected to the source of pmos transistor P2, forming a common node E. The gate of pmos transistor P2 is connected to clock CLKP, and the drain of pmos transistor P2 is connected to the drain of nmos transistor N1, forming a common node B. The gate of nmos transistor N1 is connected to clock CLKN, and the source of nmos transistor N1 is connected to the drain of nmos transistor N2, forming a common node F. The gate of nmos transistor N2 is connected to input signal A, and the source of nmos transistor N2 is grounded.

[0025] The second inverter includes: a PMOS transistor P6, a PMOS transistor P7, an NMOS transistor N6 and an NMOS transistor N5. The PMOS transistor P6 is connected to a power supply at a source, connected to a common node B at a gate, and connected to a PMOS transistor P7 at a drain to form a common node h. The PMOS transistor P7 is connected to a clock CLKN at a gate, connected to an NMOS transistor N6 at a drain to form a common node C. The NMOS transistor N6 is connected to a clock CLKP at a gate, connected to an NMOS transistor N5 at a source to form a common node i. The NMOS transistor N5 is connected to the common node B at a gate, and connected to a ground at a source.

[0026] The first inverter includes: a PMOS transistor P11 and an NMOS transistor N9. The PMOS transistor P11 is connected to a power supply at a source, the NMOS transistor N9 is connected to a ground at a source, the PMOS transistor P11 is connected to the common node C at a gate, and the NMOS transistor N9 is connected to the common node C at a gate. The PMOS transistor P11 is connected to an NMOS transistor N9 at a drain to form a common node and output a signal Y.

[0027] The first gate circuit includes: a PMOS transistor P3, a PMOS transistor P4 and an NMOS transistor N3. The second inverter includes: a PMOS transistor P5 and an NMOS transistor N4. The PMOS transistor P3 is connected to a power supply at a source, connected to an input signal A at a gate, and connected to a PMOS transistor P4 at a drain to form a common node B. The PMOS transistor P4 is connected to a power supply at a source, connected to an NMOS transistor N3 at a drain to form a common node g. The NMOS transistor N3 is connected to a ground at a source, connected to the common node B at a gate, and connected to the PMOS transistor P3 at a drain to form the common node B. The PMOS transistor P5 is connected to a power supply at a source, connected to the common node g at a gate, and connected to the NMOS transistor N3 at a drain to form the common node B. The NMOS transistor N4 is connected to the PMOS transistor P3 at a drain to form the common node B, connected to the PMOS transistor P4 at a drain to form the common node g, and connected to a ground at a source.

[0028] The second gate circuit includes pmos transistors P8, Pmos transistors P9, and Nmos transistors N7. The third inverter includes pmos transistors P10 and Nmos transistors N8. The source of pmos transistor P8 is connected to the power supply, the gate of pmos transistor P8 is connected to common node B, and the drain of pmos transistor P8 is connected to the gate of pmos transistor P9, forming common node C. The source of pmos transistor P9 is connected to the power supply, and the drain of pmos transistor P9 is connected to the drain of Nmos transistor N7, forming common node J. The source of Nmos transistor N7 is connected to ground, and the gate of Nmos transistor N7 is connected to the drain of pmos transistor P8, forming common node C. The source of pmos transistor P10 is connected to the power supply, the gate of pmos transistor P10 is connected to the drain of Nmos transistor N7, forming common node J, and the drain of pmos transistor P10 is connected to the gate of Nmos transistor N7, forming common node C. The drain of Nmos transistor N8 is connected to the drain of pmos transistor P8, forming common node C, and the gate of Nmos transistor N8 is connected to the drain of pmos transistor P9, forming common node J. The source of Nmos transistor N8 is grounded.

[0029] It should be noted that all MOSFETs used in the embodiments of the present invention are ULV MOSFETs. There are no special requirements for the power supply voltage except that the power supply voltage should not exceed the withstand voltage of the MOSFET, which greatly improves the adaptability of the trigger in actual manufacturing.

[0030] Specifically, if Figure 3 As shown in the figure, when the A input at time t1 is high, the clock CLKN remains stable within the time t1-t2 after the rising edge. During this period, P1, P3, P5, N3, N5, N6, N8, P7, P9, and P11 are in the off state, and P2, P4, N1, N2, N4, N7, N9, P6, P8, and P10 are in the on state, and the potential at point B is set to a low level, the potential at point C is set to a high level through P8, and the output signal Y is a low level. After the falling edge of the clock CLKN, it remains stable within the time t1-t2. During this period, P2, N1, P1, P3, P5, N3, N5, N8, P9, and P11 are in the off state, and P7, N6, P4, N2, N4, N7, N9, P6, P8, and P10 are in the on state. Point B maintains a low level state, point C maintains a high level state, and the output signal Y maintains a low level state.

[0031] When the A input at t1 moment is low level, the clock CLKN rising edge keeps stable for t1-t2 time, during which N2, N4, N6, P4, P6, P7, P8 are off state, N1, N3, P1, P2, P3, P5 are on state, B point is set to high level, C point keeps the state of last cycle, so that the switch state of N7, N8, N9, P9, P10, P11 is controlled by the state of C point of last cycle. And the clock CLKN falling edge keeps stable for t1-t2 time, during which N1, N2, N4, N7, N9, P2, P4, P6, P8, P10 are off state, N3, N5, N6, N8, P1, P3, P5, P7, P9, P11 are on state, B point maintains high level state, C point maintains low level state, the output signal Y is high level.

[0032] The beneficial effects of the present application are as follows:

[0033] 1) Compared with the traditional flip-flop, the present application reduces nearly 30% unnecessary circuit, greatly improves the utilization rate of flip-flop area, reduces the area waste, and improves the design efficiency.

[0034] 2) The present application maximally retains two latch circuits, improves the anti-interference ability of the flip-flop, and reduces the logic error problem caused by node leakage;

[0035] 3) Greatly improves the speed requirement range, and meets the simultaneous demand of high speed and low speed without causing logic misjudgment.

[0036] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be mutually referred to.

[0037] In the present application, specific examples are applied to describe the principles and implementation modes of the present application, and the above embodiment description is only used to help understand the method and core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In view of the above, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A flip-flop for determining an initial state, characterized by The utility model relates to a circuit for generating a first signal and a second signal, comprising: a transmission circuit, a first initial state circuit and a second initial state circuit; the transmission circuit is connected with the first initial state circuit and the second initial state circuit respectively; the transmission circuit comprises a first tri-state inverter, a second tri-state inverter and a first inverter connected in sequence; the first initial state circuit comprises a first gate circuit and a second inverter; the first initial state circuit is used for accelerating flip speed and latches the output of the first tri-state inverter; the first gate circuit comprises a pmos tube P3, a pmos tube P4 and an nmos tube N3, and the second inverter comprises a pmos tube P5 and an nmos tube N4; the gate of the pmos tube P3 is connected with an input signal, the drain of the pmos tube P3 is connected with the gate of the pmos tube P4, the source of the pmos tube P3 is connected with a power supply, the sources of the pmos tube P4 and the pmos tube P5 are both connected with a power supply, the gate of the pmos tube P4 is connected with the gate of the nmos tube N3, the drain of the pmos tube P5, the drain of the nmos tube N4 and the output terminal of the first tri-state inverter respectively, the drain of the pmos tube P4 is connected with the drain of the nmos tube N3, the gate of the pmos tube P5 and the gate of the nmos tube N4 respectively, and the sources of the nmos tube N3 and the nmos tube N4 are both grounded; the second initial state circuit comprises a second gate circuit and a third inverter; the second initial state circuit is used for accelerating flip speed and latches the output of the second tri-state inverter; the second gate circuit comprises a pmos tube P8, a pmos tube P9 and an nmos tube N7, and the third inverter comprises a pmos tube P10 and an nmos tube N8; the gate of the pmos tube P8 is connected with the output terminal of the first tri-state inverter, the drain of the pmos tube P8 is connected with the gate of the pmos tube P9, the source of the pmos tube P8 is connected with a power supply, the sources of the pmos tube P9 and the pmos tube P10 are both connected with a power supply, the gate of the pmos tube P9 is connected with the gate of the nmos tube N7, the drain of the pmos tube P10, the drain of the nmos tube N8 and the output terminal of the second tri-state inverter respectively, the drain of the pmos tube P9 is connected with the drain of the nmos tube N7, the gate of the pmos tube P10 and the gate of the nmos tube N8 respectively, and the sources of the nmos tube N7 and the nmos tube N8 are both grounded.

2. The flip-flop for determining an initial state according to claim 1, wherein the first tri-state inverter comprises a pmos tube P1, a pmos tube P2, an nmos tube N1 and an nmos tube N2 connected in sequence; the source of the pmos tube P1 is connected with a power supply, the gate of the pmos tube P1 and the gate of the nmos tube N2 are both connected with the input signal, the source of the nmos tube N2 is grounded, and the connection ends of the pmos tube P2 and the nmos tube N1 as the output terminal of the first tri-state inverter are connected with the second tri-state inverter and the first initial state circuit respectively.

3. The flip-flop for determining an initial state according to claim 1, wherein The second tri-state inverter comprises a pmos transistor P6, a pmos transistor P7, an nmos transistor N6 and an nmos transistor N5 connected in sequence; the source of the pmos transistor P6 is connected with a power supply; the gate of the pmos transistor P6 is connected with the gate of the nmos transistor N5, the output of the first tri-state inverter and the first initial state circuit respectively; the source of the nmos transistor N5 is grounded; the connection end of the pmos transistor P7 and the nmos transistor N6 serves as the output of the second tri-state inverter and is connected with the first inverter and the second initial state circuit respectively.

4. The flip-flop for determining an initial state according to claim 1, wherein The first inverter comprises a pmos transistor P11 and an nmos transistor N9 connected in sequence; the source of the pmos transistor P11 is connected with a power supply; the source of the nmos transistor N9 is grounded; the gate connection end of the pmos transistor P11 and the nmos transistor N9 is connected with the output of the second tri-state inverter.

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