Clock skew digital calibration method based on similar triangles

Abstract

The invention relates to a clock skew digital calibration method based on similar triangles, and belongs to the field of clock interleaving type digital-to-analog conversion circuits. The method comprises the following steps: firstly, carrying out preliminary calibration on sub-channel output through an imbalance and gain mismatch calibration module; a clock skew calibration module is adopted to perform clock skew calibration, the selected sub-channel is used as a reference, a correlation coefficient and a skew percentage are calculated by comparing sampling point difference values of a channel to be calibrated and a reference channel, a sampling error value is calculated according to the skew percentage by using a similar triangle principle, and an output code is compensated; therefore, accurate output after calibration is obtained. According to the calibration method, an additional reference channel is not needed, the selected sub-channel is directly used as the reference channel, calculation is relatively simple when the clock skew percentage is extracted, and the clock skew of the clock interleaving ADC can be rapidly calibrated with small resource consumption and power consumption.

Description

Technical Field

[0001] The invention belongs to the field of clock interleaving type digital-to-analog conversion circuits and relates to a clock deviation digital calibration method based on similar triangles. Background Art

[0002] With the rapid advancement of wireless communication technology, especially driven by 5G, the Internet of Things and future 6G technologies, the requirements for circuit processing speed have reached unprecedented heights. This trend has directly promoted the development of high-speed analog-to-digital converters (ADCs), making them a key component in modern communication systems. In the fields of high-speed signal processing, RF communications, radar systems, and high-precision measuring instruments, the demand for high-performance ADCs is growing to meet the requirements for higher data rates, lower power consumption, and smaller package sizes.

[0003] As an innovative solution, time-interleaved (TI) technology has emerged to break through the performance bottleneck of a single ADC through parallel processing, especially in terms of sampling rate. The TI ADC system connects multiple identical sub-ADCs in parallel, and each sub-ADC samples the input signal in sequence according to a predetermined timing, thereby synthesizing an output data stream that appears to be sampled at a higher frequency. This design cleverly takes advantage of parallel processing, and with a relatively small single ADC unit, it achieves a significant increase in sampling rate at the cost of increasing circuit area and moderately increasing power consumption, meeting the needs of high-speed application scenarios.

[0004] However, the advantages of TI ADC architecture are not without cost. In practical applications, due to differences in manufacturing processes, temperature changes, power supply fluctuations and other factors, there will inevitably be mismatches between the various sub-ADC channels. These mismatches become the key factors restricting the performance of TI ADC. Specifically, there are three main types of mismatches between channels: offset mismatch, gain mismatch and sampling time mismatch.

[0005] Offset mismatch refers to the inconsistency of the output levels of each sub-ADC at zero input. This is a fixed DC offset that can usually be corrected by simple calibration methods, such as one-time calibration or periodic calibration. Gain mismatch refers to the different amplification factors of the same input signal between sub-ADCs. This is also a static error. Its calibration method is relatively mature and can be compensated by accurately measuring the gain characteristics of each channel and applying digital signal processing algorithms.

[0006] Sampling time mismatch, also known as clock skew or time interleaving error, is one of the most difficult problems in TI ADC. It stems from the non-ideal synchronization of the sampling clocks of each sub-ADC, which causes the sampling point to shift on the actual time axis, thereby introducing high-frequency noise and harmonic distortion, seriously reducing the key dynamic performance indicators of TI ADC such as Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR). Summary of the invention

[0007] In view of this, an object of the present invention is to provide a clock deviation digital calibration method based on similar triangles to improve the influence of sampling time mismatch on TI ADC.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] A clock deviation digital calibration method based on similar triangles, firstly, performs offset mismatch calibration and gain mismatch calibration on digital codes output by several sub-channel ADCs through an offset mismatch calibration module and a gain mismatch calibration module of a clock interleaved digital-to-analog conversion circuit, and then completes clock deviation calibration through a clock deviation calibration module, wherein the clock deviation calibration module includes a clock deviation percentage detection module and an error calculation module, the clock deviation percentage detection module selects two sub-channel ADCs, takes one as a reference channel and the other as a channel to be calibrated, calculates a correlation coefficient containing clock deviation ΔT information through the difference between the sampling point of the channel to be calibrated and two adjacent sampling points of the reference channel, and obtains the clock deviation value percentage of the channel to be calibrated according to the difference ratio between the correlation coefficients; then, the error calculation module calculates the sampling error value of the digital code to be compensated according to the clock deviation value percentage through similar triangles, and calculates the output code corresponding to the channel to be calibrated and the compensation value to obtain the calibrated output code.

[0010] Furthermore, the clock deviation percentage detection module calculates the clock deviation between the reference channel and the channel to be calibrated as follows:

[0011] The k-1th sampling output of the reference channel is expressed as y1(k-1), the kth sampling output of the reference channel is expressed as y1(k), and the k-1th sampling output of the channel to be calibrated is expressed as y2(k-1). In the time domain, the k-1th sampling of the channel to be calibrated is between the k-1th and kth sampling of the reference channel; T is the sampling period of the clock interleaved ADC, and the sampling time deviation of the channel to be calibrated relative to the reference channel is ΔT, then:

[0012] The sampling interval between the k-1th sampling of the reference channel and the k-1th sampling of the channel to be calibrated is T+ΔT. The outputs y1(k-1) and y2(k-1) of the two samples are calculated to obtain (T+ΔT) 2 Correlation coefficient of information R(T+ΔT):

[0013]

[0014] The sampling interval between the k-1 sampling of the channel to be calibrated and the k sampling of the reference channel is T+ΔT. The outputs y2(k-1) and y1(k) of the two samplings are calculated to obtain (T-ΔT) 2 Correlation coefficient of information R(T-ΔT):

[0015]

[0016] The sampling interval between the k-1th sampling and the kth sampling of the reference channel is 2T. The outputs y2(k-1) and y1(k) of the two samplings are calculated to obtain (2T) 2 Correlation coefficient of information R(T):

[0017]

[0018] In the formula, α is the proportionality coefficient; R(T+ΔT) is the cumulative average of the square of the difference between one of the sampling points and the sampling point at the previous moment, and R(T-ΔT) is the cumulative average of the square of the difference between the sampling point and the sampling point at the next moment. The clock deviation ΔT between the channels causes a difference between R(T+ΔT) and R(T-ΔT):

[0019] R(T+ΔT)-R(T-ΔT)=4αTΔT

[0020] The correlation coefficient between the difference and the sampling period is R(T) = 4αT 2 The ratio is the clock deviation percentage of the channel D ΔT , which is expressed as:

[0021]

[0022] Where ΔT is the clock deviation between channels, D ΔT is the clock deviation percentage.

[0023] Furthermore, the error calculation module solves the compensation value e of the digital code to be compensated by the similar characteristics of the right triangle A formed by the values ​​of the two samples of the reference channel and the sampling interval in the time domain and the right triangle B formed by the difference between the ideal sampling point and the actual sampling point and the clock deviation in the time domain, where:

[0024]

[0025] The compensation value e is expressed as:

[0026]

[0027] After calculating the size of the compensation value e, add the compensation value e to the digital code output from the corresponding sampling point to obtain the calibrated output code. Based on the method based on similar triangles, the clock deviation percentage is obtained according to the correlation coefficient. Its calculation can be applied to any input signal. Therefore, the TI ADC calibrated by this algorithm has no requirements for the input signal and has better applicability. The correlation coefficient of this algorithm is calculated from the discrete sequence sampled between channels. The calculated result will be more accurate, and the process of calculating the clock deviation percentage is also very simple.

[0028] Furthermore, the offset mismatch calibration module obtains the offset value of each channel by accumulating and averaging the digital codes output by each channel, and then subtracts the offset of the reference channel from the offset of the remaining sub-channels to obtain the offset value of each channel relative to the reference channel. Finally, the offset mismatch calibration is completed by subtracting the offset value of each channel relative to the reference channel.

[0029] Furthermore, the gain mismatch calibration module first obtains the gain value of each channel by accumulating and averaging the absolute values ​​of the digital codes output by each channel, and then obtains the gain ratio of each channel to be calibrated relative to the reference channel by the ratio between the gain value of the reference channel and the gain value of each channel to be calibrated. Finally, the gain mismatch calibration is completed by multiplying the digital code output by each channel to be calibrated by its corresponding gain ratio.

[0030] Furthermore, the calibration method is for a channel number of 2 N When performing clock deviation calibration in TI-ADC where N is a positive integer, firstly N-1 +1 channel is used as the channel to be calibrated and the first channel is used as the reference channel for calibration; then the second N-2 +1 channel is used as the channel to be calibrated, with the first channel and the second channel having completed calibration N-1 +1 channel is the reference channel for calibration, 3×2 N-2 +1 channel to 2nd N-1 The +1 channel and the first channel are calibrated as reference channels; and so on until all channels are calibrated.

[0031] Further, the operation steps of the calibration method are:

[0032] S1, power on and reset the entire circuit so that all register values ​​in the calibration system are cleared to zero;

[0033] The output digital codes of S2 and TI-ADC are calibrated for offset mismatch and gain mismatch respectively, and the calibrated digital codes are input into the clock deviation calibration module for final calibration;

[0034] S3. The clock deviation percentage detection module in the clock deviation calibration module will detect the clock deviation percentage D between channels through the relationship between the correlation coefficients. ΔT Extract and calculate the clock deviation percentage D ΔT Input into the error calculation module for error calculation;

[0035] S4. Calculate the error value e that needs to be compensated by using the error calculation module based on similar triangles, and subtract the compensation value e from the actual sampled output code to complete the clock deviation calibration of the TI-ADC.

[0036] The beneficial effects of the present invention are:

[0037] The present invention directly extracts the correlation coefficient between the two channels through the digital codes output by the two-channel ADC. Since the existence of clock deviation will cause a certain difference in the calculated correlation coefficient, the percentage of the clock deviation between the two channels can be obtained by comparing the difference with the correlation coefficient corresponding to the sampling moment. Then, the value to be compensated is calculated by the characteristics that the right triangle formed by the difference between the two samples of the reference channel and the sampling interval in the time domain is approximately similar to the triangle formed by the error value to be calculated and the clock deviation in the time domain. Finally, the sampled digital code is subtracted from the compensation value to obtain the final calibrated output result. The calibration method does not require an additional reference channel, and directly uses the first channel as the reference channel. The calculation is relatively simple when extracting the percentage of the clock deviation, and the clock deviation of the clock interleaving ADC can be quickly calibrated with less resource consumption and power consumption.

[0038] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0040] Figure 1 It is an overall flow chart of the clock deviation digital calibration method of the present invention;

[0041] Figure 2 A schematic diagram of the clock deviation calculation process of the present invention;

[0042] Figure 3 It is a schematic diagram of the compensation value calculation principle based on similar triangles of the present invention;

[0043] Figure 4 It is a schematic diagram of the calibration effect of the present invention in the case of 10 bits and 16 channels;

[0044] Figure 5 It is a schematic diagram of the simulation results of the present invention, wherein: Figure 5 (a) is the FFT spectrum of the output signal before calibration. Figure 5 (b) is the FFT spectrum of the output signal after calibration. DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0046] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0047] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0048] See also Figure 1 to Figure 5 , which is a digital calibration method for clock deviation based on similar triangles.

[0049] Example

[0050] A digital calibration method for clock deviation based on similar triangles. In a clock interleaved digital-to-analog conversion circuit, such as Figure 1 As shown, it includes several sub-channel ADCs, an offset mismatch calibration module, a gain mismatch calibration module, a clock deviation percentage detection module and an error calculation module, wherein the digital code output after the sub-ADC sampling and quantization needs to be calibrated after the offset mismatch calibration and the gain mismatch calibration before the clock deviation calibration can be performed. Usually, a two-channel clock interleaved ADC is selected for clock deviation calibration. The clock deviation digital calibration method based on similar triangles proposed in the present invention uses one of the two-channel ADCs as a reference channel and the other channel as a channel to be calibrated, and calculates the clock deviation percentage of the channel to be calibrated according to the reference channel.

[0051] Offset mismatch can be obtained by accumulating and averaging the digital codes output by each channel to obtain the offset value of each channel, and then the offset of the remaining sub-channels minus the offset of the first channel can be obtained to obtain the offset value of each channel relative to the reference channel. Finally, each channel minus their offset relative to the reference channel can complete the offset mismatch calibration. Gain mismatch calibration requires taking the absolute value of the output code of each channel and accumulating and averaging it to obtain the gain value of each channel. The gain value of the first channel is divided by the gain value of each channel to obtain the gain ratio of each channel relative to the first channel. Finally, the output code of each channel is multiplied by their corresponding gain ratio to complete the gain mismatch calibration.

[0052] In the digital calibration process of clock deviation, usually, the first channel is selected as the reference channel, and the remaining channels are calibrated with the first channel as the channels to be calibrated. Similarly, any other channel can be selected as the reference channel, and the remaining channels can be selected as the channels to be calibrated. The correlation coefficient containing the clock deviation ΔT information is calculated by the difference between the sampling point of the channel to be calibrated and the two adjacent sampling points of the reference channel. The result of directly accumulating and averaging the digital code after offset mismatch calibration and gain mismatch calibration will inevitably be zero. Therefore, when calculating the correlation coefficient, it is necessary to square it to obtain two correlation coefficients containing clock deviation. The difference between them is divided by the correlation coefficient containing the sampling time T to obtain the percentage of the clock deviation value of the channel to be calibrated. Finally, the characteristics of similar triangles are used to calculate the sampling error value of the digital code that needs to be compensated. The digital calibration of the clock deviation of the channel is completed by subtracting the compensation value from the output code corresponding to the channel to be calibrated. Finally, the digital codes of each channel will be output in parallel, and after being interwoven together, they will form the output code of the TI-ADC.

[0053] After the square of the parameters is subtracted, the sliding average method is used to calculate the average value. It can effectively reduce the possibility of large differences in the calculated results of two consecutive clock deviations, which makes the distortion after calibration possible and ensures the continuity of the calibrated data. ΔT Only one division is required to complete the process, and no other complex calculations are required, which will save more resources and power consumption in circuit implementation.

[0054] The calibration module is mainly composed of a clock deviation percentage detection module and an error calculation module. The specific calculation process of the clock deviation percentage detection module to extract the clock deviation from the digital output code of the two-channel TI-ADC includes:

[0055] like Figure 2 As shown, the k-1th sampling output of the reference channel is represented as y1(k-1), the k-1th sampling output of the channel to be calibrated is represented as y2(k-1), and the kth sampling output of the reference channel is represented as y1(k). In the time domain, the k-1th sampling of the channel to be calibrated is between the k-1th and kth sampling of the reference channel. Assume that T is the sampling period of the clock interleaved ADC, and the sampling time deviation of the channel to be calibrated relative to the reference channel is ΔT. Therefore, the sampling interval between y1(k-1) and y2(k-1) is T+ΔT, and the result of subtracting and squaring them is (T+ΔT). 2 Similarly, the sampling interval between y2(k-1) and y1(k) is T-ΔT, and the result of subtracting their squares is (T-ΔT) 2 For y1(k) and y1(k-1), the interval between them is 2T, so the result of subtracting the squares will be (2T) 2 Related information. Through the following specific calculation expressions of related parameters:

[0056]

[0057]

[0058] Among them, α is the proportional coefficient. Since the calculation method is the same, the ratio of the three coefficients to the square of the sampling interval will also be the same, that is, the proportional coefficient α in the three parameters is the same.

[0059] By calculating the cumulative average R(T+ΔT) and R(T-ΔT) of the square of the difference between one of the sampling points and the previous sampling point and the next sampling point, the clock deviation ΔT between the channels will cause a difference between R(T+ΔT) and R(T-ΔT), R(T+ΔT)-R(T-ΔT)=4αTΔT, and the difference is divided by the correlation coefficient R(T)=4αT corresponding to the sampling period. 2The percentage of the clock deviation of the channel can be obtained. ΔT , the specific calculation formula is:

[0060]

[0061] Where ΔT is the clock deviation between channels, D ΔT is the clock deviation percentage.

[0062] like Figure 3 As shown, the error calculation module mainly obtains the value e that needs to be compensated on the digital code by using the characteristics that the right triangle A formed by the two sampling values ​​of the reference channel and the sampling interval in the time domain is approximately similar to the right triangle B formed by the difference between the ideal sampling point and the actual sampling point and the clock deviation in the time domain. The ratio of the height to the base of these two right triangles is the same, and we have:

[0063]

[0064] Transform it to get:

[0065]

[0066] After calculating the size of the compensation value e, the digital code output by the corresponding sampling point can be added with the compensation value e to obtain the calibrated output code. This method can effectively solve the problem of performance degradation of TI-ADC caused by clock deviation.

[0067] The present invention is a background calibration method, which does not need to interrupt the normal operation of TI-ADC during the calibration process, and mainly includes an offset mismatch calibration module, a gain mismatch calibration module and a clock deviation calibration module. According to the different number of sub-channels designed by TI-ADC, the number of clock deviation calibration modules will also increase, but the internal circuit of the clock deviation calibration module will not change.

[0068] After the chip is powered on and reset, TI-ADC starts sampling and quantization and outputs the quantized digital code. These digital codes will be calibrated after offset mismatch calibration and gain mismatch calibration before reaching the clock deviation calibration module. In the clock deviation calibration module, the clock deviation percentage D is calculated by the clock deviation percentage detection module. ΔT , the value e that needs to be compensated is calculated through the error calculation module. The calculation principle is to obtain the compensation value through the characteristics of similar triangles. Finally, the digital code of the channel with clock deviation is subtracted from the corresponding compensation value e to complete the clock deviation calibration.

[0069] This algorithm can also be used for other channels with a number of 2 N The clock deviation calibration is performed in the TI-ADC of , where N is a positive integer. The calibration method is similar to that of the 2-channel. The first step is to convert the second N-1The +1 channel is calibrated with the first channel as the reference channel; the second step is to calibrate the N-2 +1 channel is divided into first channel and second channel N-1 +1 channel (this channel has been calibrated) is used as the reference channel for calibration, N-2 +1 channel to 2nd N-1 The +1 channel and the first channel are calibrated as reference channels; and so on until all channels are calibrated.

[0070] Taking the four-channel TI ADC as an example, the first step is to calibrate the third channel with the first channel as the reference channel, use the first channel and the third channel, and the third channel and the next first channel to extract the clock deviation percentage, and calculate the compensation value in the error calculation module, and then add the output code of the third channel to its corresponding error value to complete the calibration of the three channels. The second step is to calibrate the second channel with the first channel and the third channel as the reference, and calibrate the fourth channel with the third channel and the first channel as the reference, that is, calibrate with the two adjacent channels as the reference, and the calibration method is the same as the calibration of the third channel.

[0071] The calibration of the eight-channel TI-ADC is similar to that of the four-channel one. The first step is to calibrate the fifth channel with the first channel and the next first channel as the reference channel; the second step is to calibrate the third channel with the first channel and the fifth channel as the reference channel, and calibrate the seventh channel with the fifth channel and the next first channel; the third step is to calibrate the second channel with the first channel and the third channel as the reference channel, calibrate the fourth channel with the third channel and the fifth channel as the reference channel, calibrate the sixth channel with the fifth channel and the seventh channel as the reference channel, and calibrate the eighth channel with the seventh channel and the next first channel as the reference channel. The digital calibration of the clock deviation of the eight-channel TI-ADC is now completed.

[0072] This embodiment also provides a calibration operation step of a clock deviation digital calibration method based on similar triangles, which includes:

[0073] Step 1: Power on and reset the entire circuit so that all register values ​​in the calibration system are cleared to zero;

[0074] Step 2: The output digital code of TI-ADC is calibrated for offset mismatch and gain mismatch respectively, and the calibrated digital code is input into the clock deviation calibration module for final calibration;

[0075] Step 3: The clock deviation percentage detection module in the clock deviation calibration module will detect the clock deviation percentage D between channels through the relationship between the correlation coefficients. ΔT Extract and calculate the clock deviation percentage D ΔT It will be input into the error calculation module for error calculation.

[0076] Step 4: Use the error calculation module based on similar triangles to calculate the error value e that needs to be compensated, and subtract the compensation value e from the actual sampled output code to complete the clock deviation calibration of the TI-ADC.

[0077] Based on the above calibration operation steps, this embodiment obtains corresponding simulation results.

[0078] like Figure 4 As shown in the figure, it is a simulation effect diagram of the calibration method designed by the present invention, which is a comparison diagram of the effective number of bits ENOB before and after calibration of a 10-bit 16-channel TI-ADC with a sampling rate of 5G / s. The clock deviation is set to a random 2%T~-2%T, and the offset error and dispute error are also set to plus or minus 2%. Figure 4 It can be seen from the figure that with the increase of the input signal frequency, under the condition that the clock deviation remains unchanged, if the TI-ADC is not calibrated for offset mismatch and gain mismatch, its effective number of bits will be only 6.8 bits at most. After the offset mismatch calibration and gain mismatch calibration are completed, the effective number of bits of the TI-ADC can reach 9.6 bits at most. When the input signal frequency increases, if the clock deviation calibration is not performed, the effective number of bits of the TI-ADC will also drop to about 5.9bbit. After the clock deviation calibration is performed, the effective number of bits of the TI-ADC can be maintained at about 9.5bit. Therefore, after the TI-ADC is calibrated using the algorithm of the present invention, the clock deviation is always maintained at about 9.5bit, which significantly improves the dynamic performance of the TI ADC.

[0079] like Figure 5 As shown in FIG. 1 , the simulation results of the calibration algorithm designed by the present invention in a 16-channel TI-ADC are shown. The frequency of the input signal is (incoherent sampling), fs is the sampling frequency of TI-ADC, where, Figure 5 (a) is the FFT spectrum of the output signal before calibration. Figure 5 (b) FFT spectrum of the calibrated output signal. Under the clock deviation of 2%T to -2%T, the SNDR before calibration is 37.6dB, ENOB is 5.9bit, and SFDR is 43.5dB. After calibration, the SNDR of the entire TI-ADC is improved from 37.6dB to 57.3dB, ENOB is improved from 5.9bit to 9.2bit, and SFDR is improved from 43.5dB to 61.3dB. The performance of the TI-ADC after calibration is significantly improved, and the effective number of bits is increased by 3.3bit, which effectively solves the problem of performance degradation of the TI-ADC caused by clock deviation.

[0080] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A digital calibration method for clock deviation based on similar triangles, characterized in that: First, the offset mismatch calibration module and gain mismatch calibration module of the clock interleaved digital-to-analog conversion circuit are used to perform offset mismatch calibration and gain mismatch calibration on the digital codes output by the ADCs of several sub-channels, and then the clock deviation calibration module is used to complete the clock deviation calibration, wherein: The clock deviation calibration module includes a clock deviation percentage detection module and an error calculation module. The clock deviation percentage detection module selects two sub-channel ADCs, takes one of them as a reference channel and the other as a channel to be calibrated, calculates the correlation coefficient containing the clock deviation ΔT information through the difference between the sampling point of the channel to be calibrated and the two adjacent sampling points of the reference channel, and obtains the clock deviation value percentage of the channel to be calibrated according to the difference ratio between the correlation coefficients; then the error calculation module calculates the sampling error value of the digital code to be compensated according to the clock deviation value percentage through similar triangles, and calculates the output code corresponding to the channel to be calibrated and the compensation value to obtain the calibrated output code.

2. The clock deviation digital calibration method based on similar triangles according to claim 1, characterized in that: The clock deviation percentage detection module calculates the clock deviation between the reference channel and the channel to be calibrated as follows: The k-1th sampling output of the reference channel is expressed as y1(k-1), the kth sampling output of the reference channel is expressed as y1(k), and the k-1th sampling output of the channel to be calibrated is expressed as y2(k-1). In the time domain, the k-1th sampling of the channel to be calibrated is between the k-1th and kth sampling of the reference channel; T is the sampling period of the clock interleaved ADC, and the sampling time deviation of the channel to be calibrated relative to the reference channel is ΔT, then: The sampling interval between the k-1th sampling of the reference channel and the k-1th sampling of the channel to be calibrated is T+ΔT. The outputs y1(k-1) and y2(k-1) of the two samples are calculated to obtain (T+ΔT) 2 Correlation coefficient of information R(T+ΔT): The sampling interval between the k-1 sampling of the channel to be calibrated and the k sampling of the reference channel is T+ΔT. The outputs y2(k-1) and y1(k) of the two samplings are calculated to obtain (T-ΔT) 2 Correlation coefficient of information R(T-ΔT): The sampling interval between the k-1th sampling and the kth sampling of the reference channel is 2T. The outputs y2(k-1) and y1(k) of the two samplings are calculated to obtain (2T) 2 Correlation coefficient of information R(T): In the formula, α is the proportionality coefficient; R(T+ΔT) is the cumulative average of the square of the difference between one of the sampling points and the sampling point at the previous moment, and R(T-ΔT) is the cumulative average of the square of the difference between the sampling point and the sampling point at the next moment. The clock deviation ΔT between the channels causes a difference between R(T+ΔT) and R(T-ΔT): R(T+ΔT)-R(T-ΔT)=4αTΔT The correlation coefficient between the difference and the sampling period is R(T) = 4αT 2 The ratio is the clock deviation percentage of the channel D ΔT , which is expressed as: Where ΔT is the clock deviation between channels, D ΔT is the clock deviation percentage.

3. The clock deviation digital calibration method based on similar triangles according to claim 2, characterized in that: The error calculation module solves the compensation value e of the digital code to be compensated by the similar characteristics of the right triangle A formed by the two sampling values ​​of the reference channel and the sampling interval in the time domain and the right triangle B formed by the difference between the ideal sampling point and the actual sampling point and the clock deviation in the time domain, where: The compensation value e is expressed as: After calculating the size of the compensation value e, the digital code output by the corresponding sampling point is added with the compensation value e to obtain the calibrated output code.

4. The clock deviation digital calibration method based on similar triangles according to claim 1, characterized in that: The offset mismatch calibration module obtains the offset value of each channel by accumulating and averaging the digital codes output by each channel, and then subtracts the offset of the reference channel from the offset of the remaining sub-channels to obtain the offset value of each channel relative to the reference channel. Finally, the offset mismatch calibration is completed by subtracting the offset value of each channel relative to the reference channel.

5. The clock deviation digital calibration method based on similar triangles according to claim 1, characterized in that: The gain mismatch calibration module first obtains the gain value of each channel by accumulating and averaging the absolute values ​​of the digital codes output by each channel, and then obtains the gain ratio of each channel to be calibrated relative to the reference channel by the ratio between the gain value of the reference channel and the gain value of each channel to be calibrated. Finally, the gain mismatch calibration is completed by multiplying the digital code output by each channel to be calibrated by its corresponding gain ratio.

6. The clock deviation digital calibration method based on similar triangles according to claim 1, characterized in that: The calibration method is for a channel number of 2 N When performing clock deviation calibration in TI-ADC where N is a positive integer, firstly N-1 +1 channel is used as the channel to be calibrated and the first channel is used as the reference channel for calibration; then the second N-2 +1 channel is used as the channel to be calibrated, with the first channel and the second channel having completed calibration N-1 +1 channel is the reference channel for calibration, 3×2 N-2 +1 channel to 2nd N-1 The +1 channel and the first channel are calibrated as reference channels; and so on until all channels are calibrated.

7. A clock deviation digital calibration method based on similar triangles according to any one of claims 1 to 6, characterized in that: The operation steps of the calibration method are: S1, power on and reset the entire circuit so that all register values ​​in the calibration system are cleared to zero; The output digital codes of S2 and TI-ADC are calibrated for offset mismatch and gain mismatch respectively, and the calibrated digital codes are input into the clock deviation calibration module for final calibration; S3. The clock deviation percentage detection module in the clock deviation calibration module will detect the clock deviation percentage D between channels through the relationship between the correlation coefficients. ΔT Extract and calculate the clock deviation percentage D ΔT Input into the error calculation module for error calculation; S4. Calculate the error value e that needs to be compensated by using the error calculation module based on similar triangles, and subtract the compensation value e from the actual sampled output code to complete the clock deviation calibration of the TI-ADC.

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