Integrated circuit and time synchronization method thereof

Abstract

The invention discloses an integrated circuit and a time synchronization method thereof. The method comprises the following steps: determining a target hardware timing unit from at least one hardware timing unit in a first integrated circuit; determining first time information of the target hardware timing unit; and based on the first time information, controlling a plurality of network communication units connected with the target hardware timing unit in the first integrated circuit to perform time synchronization with the target hardware timing unit. According to the method, the target hardware timing unit in the integrated circuit performs time synchronization on the plurality of network communication units in the integrated circuit, so that the time of the plurality of network communication units is consistent with the time of the target hardware timing unit, and the time unification among the plurality of network communication units in the integrated circuit can be ensured.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an integrated circuit and a time synchronization method thereof. Background Art

[0002] In the field of intelligent driving, in order to ensure driving safety, it is usually necessary to synchronize the chip with the external time with high precision through a hardware time synchronization mechanism. Since the intelligent driving chip or the integrated cabin chip includes multiple network communication units, each network communication unit has its own hardware timing unit. Therefore, when synchronizing the time of the intelligent driving chip or the integrated cabin chip, how to synchronize the time within the chip and ensure the time uniformity between different network communication units within the chip is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In order to solve the above technical problems, the present disclosure provides a time synchronization method for an integrated circuit, which can perform time synchronization on multiple network communication units in the integrated circuit.

[0004] A first aspect of the present disclosure provides a time synchronization method for an integrated circuit, comprising: determining a target hardware timing unit from at least one hardware timing unit in a first integrated circuit; determining first time information of the target hardware timing unit; and based on the first time information, controlling multiple network communication units in the first integrated circuit connected to the target hardware timing unit to perform time synchronization with the target hardware timing unit.

[0005] The second aspect of the present disclosure provides an integrated circuit, comprising: at least one hardware timing unit, multiple network communication units connected to each of the hardware timing units, and a processor; the processor is used to determine a target hardware timing unit in the at least one hardware timing unit; the target hardware timing unit is used to determine first time information of the target hardware timing unit and transmit the first time information of the target hardware timing unit to multiple network communication units connected to the target hardware timing unit; the multiple network communication units are used to perform time synchronization with the target hardware timing unit based on the first time information.

[0006] In a third aspect of the present disclosure, a computer program product is proposed. When an instruction processor in the computer program product is executed, the time synchronization method for integrated circuits proposed in the embodiment of the first aspect of the present disclosure is executed.

[0007] In a fourth aspect of the present disclosure, an electronic device comprises: a processor; a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the time synchronization method of the integrated circuit described in any one of the first aspects above; or, the electronic device comprises the integrated circuit described in the second aspect above.

[0008] The time synchronization method of the integrated circuit provided by the embodiment of the present disclosure can determine the target hardware timing unit in the integrated circuit during time synchronization, and based on the time information of the target hardware timing unit, control multiple network communication units connected to the target hardware timing unit to perform time synchronization with the target hardware timing unit. The present disclosure performs time synchronization on multiple network communication units in the integrated circuit through the target hardware timing unit in the integrated circuit, so that the time of the multiple network communication units is consistent with the time of the target hardware unit, thereby ensuring the time uniformity between the multiple network communication units in the integrated circuit; and the present disclosure performs time synchronization on multiple network communication units in the integrated circuit through the target hardware timing unit, so that the time synchronization can be completed centrally in the integrated circuit, thereby improving the efficiency of time synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A It is a schematic diagram of the structure of an integrated circuit provided by an exemplary embodiment of the present disclosure.

[0010] Figure 1B It is a schematic diagram of the structure of an integrated circuit provided by an exemplary embodiment of the present disclosure.

[0011] Figure 2 It is a flowchart of a time synchronization method for an integrated circuit provided by an exemplary embodiment of the present disclosure.

[0012] Figure 3 It is a flowchart of a time synchronization method for an integrated circuit provided by another exemplary embodiment of the present disclosure.

[0013] Figure 4 It is a scenario diagram of a time synchronization method provided by an exemplary embodiment of the present disclosure.

[0014] Figure 5 It is a scenario schematic diagram of a time synchronization method provided by yet another exemplary embodiment of the present disclosure.

[0015] Figure 6 It is a flowchart of a time synchronization method for an integrated circuit provided by another exemplary embodiment of the present disclosure.

[0016] Figure 7 It is a flowchart of a time synchronization method for an integrated circuit provided by yet another exemplary embodiment of the present disclosure.

[0017] Figure 8 It is a flowchart of a time synchronization method for an integrated circuit provided by yet another exemplary embodiment of the present disclosure.

[0018] Fig. 9 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0020] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0021] Application Overview

[0022] In smart driving chips or integrated chips, a hardware time synchronization mechanism is usually required to control the error between the chip and the external time within a very small range. When synchronizing the time of the smart driving chip or the integrated chip, since the smart driving chip or the integrated chip includes multiple network communication units, each network communication unit supports the corresponding time synchronization protocol, time synchronization can be performed through any network communication unit.

[0023] Exemplarily, taking the time synchronization of the cabin-driver integrated chip as an example, time synchronization can be performed through any network communication unit in the cabin-driver integrated chip, and when time synchronization is performed through any network communication unit, synchronization can be achieved by using a variety of timing modes. For example, when the first timing mode is used, the cabin-driver integrated chip can be used as a slave clock (timing slave), and the time of the cabin-driver integrated chip is externally synchronized. Under this timing mode, the on-chip time of the cabin-driver integrated chip can be adjusted to be consistent with the external time. For another example, when the second timing mode is used, the cabin-driver integrated chip can be used as a master clock (timing master), and the cabin-driver integrated chip is used to synchronize the time of the cabin-driver integrated chip to the external chip.

[0024] However, since each network communication unit in the chip has its own hardware timer, the time of different network communication units in the chip may be inconsistent. When the time of the integrated chip is synchronized through any network communication unit, it can only ensure that the time of the network communication unit is consistent with the external time, and it cannot ensure that the time of other network communication units in the integrated chip is consistent. Therefore, when synchronizing the time of the integrated chip, how to ensure the time uniformity between different network communication units in the chip is a technical problem that needs to be solved urgently.

[0025] The time synchronization method for an integrated circuit provided by an embodiment of the present disclosure determines a target hardware timing unit in at least one hardware timing unit of the integrated circuit during time synchronization, and performs time synchronization on multiple network communication units in the integrated circuit according to first time information of the target hardware timing unit, so that the times of the multiple network communication units are consistent with the time of the target hardware unit, thereby ensuring the time uniformity among the multiple network communication units in the integrated circuit; and the present disclosure performs time synchronization on the multiple network communication units in the integrated circuit through the target hardware timing unit, so that the time synchronization can be completed centrally within the integrated circuit, thereby improving the efficiency of time synchronization.

[0026] Exemplary Systems

[0027] Figure 1A FIG. 1 is a schematic diagram of the structure of an integrated circuit provided by an exemplary embodiment of the present disclosure. Figure 1A As shown, the integrated circuit 100 may include: at least one hardware clock module (Hardware Clock Module, HCM) 101, a plurality of network communication units 102 connected to each hardware clock module, and a processor 103.

[0028] The processor 103 is configured to determine a target hardware timing unit in the at least one hardware timing unit 101 .

[0029] The target hardware timing unit is used to determine the first time information of the target hardware timing unit and transmit the first time information to a plurality of network communication units 102 connected to the target hardware timing unit.

[0030] The plurality of network communication units 102 are configured to perform time synchronization with a target hardware timing unit based on the first time information.

[0031] In some embodiments, the target hardware timing unit may be a hardware timing unit determined by the processor in at least one hardware timing unit included in the integrated circuit based on the task to be executed. For example, a corresponding hardware timing unit may be configured for each preset task in each hardware timing unit 101 in the integrated circuit based on multiple preset tasks in advance; after generating the task to be executed, the processor may determine the target hardware timing unit corresponding to the task to be executed based on the task to be executed.

[0032] Exemplarily, the multiple network communication units may be communication interface circuits supporting multiple hardware time synchronization protocols, and the multiple network communication units include but are not limited to at least one of an Ethernet communication unit (Ethernet, Eth), a controller area network communication unit (Controller Area Network, CAN) and a high-speed serial computer expansion bus communication unit (Peripheral Component Interconnect Express, PCIe). The disclosed embodiments do not limit the types of the multiple network communication units in the integrated circuit, and the integrated circuit may also include other types of network communication units. The types of network communication units included in the integrated circuit are related to the functions, application scenarios and chip designs of the integrated circuit.

[0033] like Figure 1A As shown, at least one hardware timing unit 101 in the first integrated circuit includes HCM0 and HCM1, and multiple network communication units connected to HCM0 include CAN0 and CAN1, Eth 0 and Eth 1, PCIe0 and PCIe1, and multiple network communication units connected to HCM1 include CAN0 and CAN1, Eth 0 and Eth 1, PCIe0 and PCIe1. For example, if the task to be executed is an autonomous driving task, since the autonomous driving task corresponds to the hardware timing unit HCM0, the processor can determine the HCM0 corresponding to the autonomous driving task as the target hardware timing unit based on the autonomous driving task; if the task to be executed is a human-computer interaction task, since the human-computer interaction task corresponds to the hardware timing unit HCM1, the processor can determine the HCM1 corresponding to the human-computer interaction task as the target hardware timing unit based on the human-computer interaction task.

[0034] In some embodiments, the processor may also determine a timing mode and a time synchronization mode of a target hardware timing unit based on the task to be executed.

[0035] Exemplarily, the timing mode includes a first preset timing mode and a second preset timing mode. When the timing mode of the target hardware timing unit is the first preset timing mode, the integrated circuit can act as a slave clock (timing slave) to synchronize time with the first clock source; when the timing mode of the target hardware timing unit is the second preset timing mode, the integrated circuit can act as a master clock (timing master) to synchronize time with other integrated circuits.

[0036] Exemplarily, the time synchronization mode may include a first time synchronization mode and a second time synchronization mode. The first time synchronization mode refers to time synchronization through a pulse signal. For example, the first time synchronization mode may be synchronization with a pulse per second signal (Pulse Per Second, PPS); the second time synchronization mode refers to time synchronization through a target network communication unit in an integrated circuit. For example, the second time synchronization mode may be time synchronization through PCIe or through CAN. The disclosed embodiment does not limit the type of the target network communication unit. The target network communication unit may be any network communication unit in the integrated circuit connected to the target hardware timing unit. The target network communication unit may also be determined based on the actual design of the integrated circuit and the task to be performed.

[0037] For example, Figure 1A As shown, taking the task to be executed as an autonomous driving task as an example, the processor determines, based on the autonomous driving task, that the timing mode of the hardware timing unit HCM0 corresponding to the autonomous driving task is the first preset timing mode, and the time synchronization mode is synchronization with the PPS signal.

[0038] In some embodiments, the target hardware timing unit may determine the first time information of the target hardware timing unit based on a timing service mode and a time synchronization mode.

[0039] Exemplarily, when the timing mode is the first preset timing mode and the time synchronization mode is the first time synchronization mode, the target hardware timing unit can receive a first pulse signal sent by a first clock source, and based on the first pulse signal, determine the second time information of the first clock source, and based on the second time information, correct the current time information of the target hardware timing unit to obtain the first time information of the target hardware timing unit.

[0040] Exemplarily, when the timing mode is the first preset timing mode and the time synchronization mode is the second time synchronization mode, the first network communication unit corresponding to the second time synchronization mode among multiple network communication units receives the third time information sent by the first clock source, and corrects the current time information of the target hardware timing unit based on the third time information to obtain the first time information of the target hardware timing unit.

[0041] Exemplarily, when the timing mode is the second preset timing mode and the time synchronization mode is the first time synchronization mode or the second time synchronization mode, the target hardware timing unit can determine the first time information of the target hardware timing unit based on the current time information of the target hardware timing unit, that is, the first time information at this time is the current time information of the target hardware timing unit.

[0042] In some embodiments, Figure 1B As shown, the integrated circuit 100 may further include a system hardware timing unit 104. The target hardware timing unit is used to determine the system time information of the system hardware timing unit 104 in the integrated circuit; in response to the system time information of the system hardware timing unit 104 being different from the current time information of the target hardware timing unit, the target hardware timing unit controls the system hardware timing unit to perform time synchronization with the target hardware timing unit based on the current time information of the target hardware timing unit.

[0043] For example, Figure 1B As shown, taking the target hardware timing unit as HCM0 as an example, HCM0 can determine whether the system time information is the same as the current time information of HCM0 based on the system time information transmitted by the system hardware timing unit 104. If the system time information is different from the current time information of HCM0, the system hardware timing unit 104 can correct the system time information based on the time difference between the system time information and the current time information of HCM0, so that the system hardware timing unit 104 is synchronized with the HCM0 time.

[0044] The time synchronization method of the integrated circuit provided by the embodiment of the present disclosure performs time synchronization on multiple network communication units in the integrated circuit through the target hardware timing unit in the integrated circuit. No matter the integrated circuit adopts the first preset timing mode or the second preset timing mode, it can ensure the time uniformity among multiple network communication units in the integrated circuit; and because the first time information of the target hardware timing unit can be determined by different time synchronization modes for different tasks to be executed, the accuracy of the first time information is improved, thereby ensuring that the on-chip time and the external time are synchronized with high precision. In addition, because the present disclosure can synchronize the current time information of the target hardware timing unit to the system hardware timing unit, on the basis of ensuring the time uniformity of each network communication unit in the first integrated circuit, the system time information of the system hardware timing unit can also be made consistent with the time of each network communication unit, thereby ensuring the time uniformity of different hardware timing units in the chip.

[0045] Exemplary Methods

[0046] Figure 2 FIG. 1 is a flow chart of a time synchronization method for an integrated circuit provided by an exemplary embodiment of the present disclosure. Figure 1A or Figure 1B The integrated circuit shown in, or including the above Figure 1A or Figure 1B The integrated circuit shown in the electronic device, such as Figure 2 As shown, the method comprises the following steps:

[0047] Step 201: determine a target hardware timing unit from at least one hardware timing unit in a first integrated circuit.

[0048] In some embodiments, the first integrated circuit may be a system on chip (SOC), for example, the first integrated circuit may be a cabin-driver integrated chip or an intelligent driving chip. The first integrated circuit may include at least one hardware timing unit, and the embodiment of the present disclosure does not limit the number of hardware timing units included in the first integrated circuit.

[0049] For example, based on different application scenarios or business requirements, there may be multiple systems or multiple time zones inside an integrated circuit (such as the first integrated circuit or the second integrated circuit). In order to ensure that the integrated circuit supports synchronization of multiple time zones, a hardware timing unit may be configured for each time zone in the integrated circuit. Figure 1A As shown, if the integrated circuit has two time zone requirements, an independent hardware timing unit can be configured for each time zone in the integrated circuit, wherein the hardware timing unit HCM0 corresponds to one time zone and the hardware timing unit HCM1 corresponds to another time zone.

[0050] In some embodiments, the hardware timing unit may be a hardware timing circuit with a timing function. The hardware timing unit may receive time information sent by an external clock source, and may also modify the current time information of the hardware timing unit based on the time information sent by the external clock source; the hardware timing unit may also send its current time information to other integrated circuits.

[0051] In some embodiments, the first integrated circuit may further include a processor, and the target hardware timing unit may be a hardware timing unit determined by the processor based on at least one hardware timing unit in the first integrated circuit based on the task to be executed.

[0052] Exemplarily, different preset tasks can be configured for each hardware timing unit in at least one hardware timing unit in the first integrated circuit based on multiple preset tasks in advance; after generating the tasks to be executed, the processor can determine the target hardware timing unit corresponding to the tasks to be executed for different tasks to be executed. For different tasks to be executed, the target hardware timing units may be different or the same, which is not limited in the embodiments of the present disclosure and is determined according to actual usage.

[0053] For example, Figure 1A As shown, if the task to be executed is an autonomous driving task, since the autonomous driving task corresponds to the hardware timing unit HCM0, HCM0 can be determined as the target hardware timing unit; if the task to be executed is a human-computer interaction task, since the human-computer interaction task corresponds to the hardware timing unit HCM1, HCM1 can be determined as the target hardware timing unit.

[0054] Step 202: determine first time information of a target hardware timing unit.

[0055] In some embodiments, the first time information may be the time information of the target hardware timing unit after time synchronization with an external clock source; or, the first time information may also be the current time information of the target hardware timing unit without time synchronization.

[0056] Exemplarily, when the timing mode of the first integrated circuit is that the first integrated circuit acts as a slave clock, the first time information may be the time information of the target hardware timing unit after time synchronization with an external clock source; when the timing mode of the first integrated circuit is that the first integrated circuit acts as a master clock, the first integrated circuit does not need to perform time synchronization with an external clock source, so the first time information is the current time information of the target hardware timing unit.

[0057] Step 203: Based on the first time information, control a plurality of network communication units in the first integrated circuit that are connected to the target hardware timing unit to perform time synchronization with the target hardware timing unit.

[0058] Exemplarily, the target hardware timing unit may transmit the first time information to a plurality of network communication units connected to the target hardware timing unit, so that the times of the plurality of network communication units are synchronized with the target hardware timing unit based on the first time information.

[0059] For example, Figure 1A As shown, taking the target hardware timing unit as HCM0 as an example, HCM0 can transmit the first time information to CAN0 and CAN1, Eth0 and Eth1, and PCIe0 and PCIe1 connected to HCM0, and CAN0 and CAN1, Eth0 and Eth1, and PCIe0 and PCIe1 can perform time synchronization with HCM0 based on the first time information.

[0060] In some embodiments, each hardware timing unit in the first integrated circuit is connected to a plurality of network communication units. In this way, based on the time information of any hardware timing unit, the plurality of network communication units connected to the hardware timing unit can be controlled to synchronize time with the hardware timing unit, thereby ensuring that the time of the plurality of network communication units connected to the hardware timing unit is unified.

[0061] The time synchronization method of the integrated circuit provided by the embodiment of the present disclosure, when the integrated circuit performs time synchronization, determines the target hardware timing unit in at least one hardware timing unit of the integrated circuit, and performs time synchronization on multiple network communication units in the integrated circuit according to the first time information of the target hardware timing unit, so that the time of the multiple network communication units is consistent with the time of the target hardware unit, thereby ensuring the time uniformity between the multiple network communication units in the integrated circuit; and the present disclosure performs time synchronization on multiple network communication units in the integrated circuit through the target hardware timing unit, which can complete the time synchronization in the integrated circuit in a centralized manner, thereby improving the efficiency of time synchronization. In addition, since different time zones of the integrated circuit can correspond to different hardware timing units respectively, the corresponding hardware timing units can be controlled to perform time synchronization based on different time zones, so that the synchronization of different time zones in the integrated circuit can be independently maintained through different hardware timing units.

[0062] like Figure 3 As shown in the above Figure 2 Based on the illustrated embodiment, step 202 may include the following steps:

[0063] Step 2021, determine the time synchronization mode and timing mode of the target hardware timing unit.

[0064] In some embodiments, the processor may also determine a timing mode and a time synchronization mode of a target hardware timing unit based on the task to be executed.

[0065] Exemplarily, based on multiple preset tasks, corresponding timing modes and time synchronization modes can be pre-configured for each preset task; after generating a task to be executed, the processor can determine the timing mode and time synchronization mode corresponding to the task to be executed based on the task to be executed.

[0066] Exemplarily, the timing mode includes a first preset timing mode and a second preset timing mode. When the timing mode of the target hardware timing unit is the first preset timing mode, the first integrated circuit can be used as a slave clock to synchronize time with the first clock source; when the timing mode of the target hardware timing unit is the second preset timing mode, the first integrated circuit can be used as a master clock to synchronize time with other integrated circuits (such as the second integrated circuit).

[0067] Exemplarily, the time synchronization mode may include a first time synchronization mode and a second time synchronization mode. The first time synchronization mode refers to time synchronization through a pulse signal, for example, the first time synchronization mode may be synchronization through a PPS signal; the second time synchronization mode refers to time synchronization through a target network communication unit in the first integrated circuit, for example, the second time synchronization mode may be time synchronization through PCIe or through CAN.

[0068] Step 2022: Determine the first time information of the target hardware timing unit based on the time synchronization method and the timing method.

[0069] In some embodiments, the first time information is related to a timing mode and a time synchronization mode of a target hardware timing unit.

[0070] Exemplarily, when the timing mode is the first preset timing mode, the first time information can be the time information synchronized from the external clock source to the target hardware timing unit; when the timing mode is the second preset timing mode, the first time information is the current time information of the target hardware timing unit, and the first integrated circuit can provide external time synchronization based on the first time information.

[0071] In some embodiments, the processor can determine the timing mode and time synchronization mode of the target hardware timing unit based on the task to be executed, and transmit the timing mode and time synchronization mode to the target hardware timing unit. The target hardware timing unit can determine the first time information of the target hardware timing unit based on the timing mode and time synchronization mode.

[0072] When the timing mode and the time synchronization mode are different, the method of determining the first time information is also different. The following is an exemplary description of various implementation methods for determining the first time information.

[0073] In some embodiments, the above step 2022 may include: in response to the time synchronization mode being the first time synchronization mode and the timing mode being the first preset timing mode, the target hardware timing unit receives a first pulse signal sent by a first clock source; based on the first pulse signal, determines the second time information of the first clock source; based on the second time information, corrects the current time information of the target hardware timing unit to obtain the first time information of the target hardware timing unit.

[0074] Exemplarily, the first clock source is a global positioning system (GPS) chip or a Beidou timing chip, etc. The first pulse signal is a pulse per second signal PPS.

[0075] When the first integrated circuit needs to be synchronized with an external clock source (such as the first clock source) as a timing slave, the target hardware timing unit can obtain the time information of the first pulse signal at the rising edge after receiving the first pulse signal sent by the first clock source, and determine the time information of the first pulse signal at the rising edge as the second time information; then, determine the time difference between the second time information and the current time information of the target hardware timing unit, and then correct the current time information of the target hardware timing unit based on the time difference to obtain the first time information of the target hardware timing unit.

[0076] Figure 4 A schematic diagram of a time synchronization method provided by an exemplary embodiment of the present disclosure. Figure 4 As shown, taking the target hardware timing unit as HCM1 and the first pulse signal as PPS as an example, HCM1 receives the PPS signal sent by the first clock source, and determines the time information t1 of the PPS signal at the rising edge, and then determines the time difference between the time information t1 and the current time information t2 of the target hardware timing unit; HCM1 can correct the current time information t2 of HCM1 by the time difference, so that the current time information of the target hardware timing unit is consistent with the time information of the first clock source.

[0077] In some embodiments, the above step 2022 may include: in response to the time synchronization mode being the second time synchronization mode and the timing mode being the first preset timing mode, the first network communication unit receives the third time information sent by the first clock source; the target hardware timing unit corrects the current time information of the target hardware timing unit based on the third time information to obtain the first time information of the target hardware timing unit. The first network communication unit is a network communication unit corresponding to the second time synchronization mode among the multiple network communication units.

[0078] In some embodiments, the first network communication unit is a network communication unit corresponding to the second time synchronization mode determined among multiple network communication units based on the second time synchronization mode. When the second time synchronization mode is different, the determined first network communication unit is also different.

[0079] For example, Figure 4 As shown, taking the target hardware timing unit as HCM0 as an example. If the second time synchronization mode is to perform time synchronization through PCIe0, the first network communication unit is PCIe0 connected to HCM0, and PCIe0 receives the third time information sent by the first clock source; if the second time synchronization mode is to perform time synchronization through CAN0, the first network communication unit is CAN0 connected to HCM0, and CAN0 receives the third time information sent by the first clock source.

[0080] It should be noted that the embodiment of the present disclosure does not limit the type of the first network communication unit. Figure 4 This is only an exemplary illustration. In actual applications, the first network communication unit may also be a network communication unit such as CAN1, Eth1 or PCIe1, that is, the third time information sent by the first clock source may also be received through CAN1, Eth1 or PCIe1.

[0081] When the first integrated circuit needs to synchronize with an external clock source (such as the first clock source) as a timing slave, the target hardware timing unit receives the third time information sent by the first clock source transmitted by the first network communication unit; the target hardware timing unit can determine the time difference between the third time information and the current time information of the target hardware timing unit based on the third time information, and thus can correct the current time information of the target hardware timing unit based on the time difference to obtain the first time information of the target hardware timing unit.

[0082] For example, Figure 4 As shown, taking the target hardware timing unit as HCM0 and the first network communication unit as CAN0 as an example, CAN0 receives the third time information t3 sent by the first clock source, and transmits the third time information t3 to HCM0; HCM0 can determine the time difference between the third time information t3 and the current time information t2 of the target hardware timing unit, and correct the current time information t2 according to the time difference, so that the current information time of HCM0 is consistent with the time information of the first clock source.

[0083] In some embodiments, the above step 2022 may include: in response to the time synchronization mode being the first time synchronization mode or the second time synchronization mode, and the timing mode being the second preset timing mode, determining the first time information of the target hardware timing unit based on the current time information of the target hardware timing unit.

[0084] In order to ensure the time synchronization between the second integrated circuit and the first integrated circuit, the first integrated circuit can be used as a master clock (timing master) to provide external time. At this time, whether the first time synchronization method or the second time synchronization method is used, the current time information of the target hardware timing unit can be used as the first time information of the target hardware timing unit.

[0085] like Figure 5 As shown, it is a scene diagram of the time synchronization method provided by an exemplary embodiment of the present disclosure. Take the target hardware timing unit as HCM0 and the timing mode as the second preset timing mode as an example. When the first integrated circuit outputs time information to the second integrated circuit, no matter the time synchronization mode is the first time synchronization mode or the second time synchronization mode, the current time information of HCM0 is determined as the first time information, that is, the current time information of HCM0 is directly transmitted to the second integrated circuit.

[0086] The time synchronization method provided by the embodiment of the present disclosure can determine the time synchronization mode and timing mode of the target hardware timing unit, and determine the first time information of the target hardware timing unit based on the time synchronization mode and timing mode. Since the first time information of the target hardware timing unit can be obtained in a corresponding manner for different timing modes and time synchronization modes, the time synchronization of the first integrated circuit and the first clock source can be achieved based on the first time information of the target hardware timing unit, or the time synchronization of the second integrated circuit and the first integrated circuit can be achieved. The technical solution provided by the present disclosure can ensure the time uniformity between multiple network communication units in the integrated circuit regardless of whether the integrated circuit adopts the first preset timing mode or the second preset timing mode; and for different tasks to be executed, the first time information of the target hardware timing unit can be determined by different time synchronization modes, thereby improving the accuracy of the first time information, and then ensuring that the internal time and the external time are synchronized with high precision.

[0087] like Figure 6 As shown in the above Figure 3 Based on the embodiment shown, the following steps may also be included:

[0088] Step 204 , in response to the time synchronization mode being the first time synchronization mode and the timing mode being the second preset timing mode, generating a second pulse signal based on current time information of the target hardware timing unit.

[0089] After multiple network communication units in the first integrated circuit are time synchronized, if the first integrated circuit is used as a timing master, the first time synchronization method can be used to grant time to the second integrated circuit to achieve time synchronization between the first integrated circuit and the second integrated circuit.

[0090] Exemplarily, the second pulse signal is a PPS signal. The second integrated circuit may be a sensor detection circuit or any integrated circuit on an electronic device (such as a vehicle) that is different from the first integrated circuit. In some examples, the circuit structure of the second integrated circuit may be the same as that of the first integrated circuit, or may be different from the circuit structure of the first integrated circuit, and the embodiments of the present disclosure are not limited to this. For example, the first integrated circuit may be a cabin-to-car integrated chip in a vehicle, and the second integrated circuit may be a detection circuit of sensors such as cameras and radars in the vehicle.

[0091] Step 205: Send a second pulse signal to the second integrated circuit to synchronize the second integrated circuit with the first integrated circuit.

[0092] For example, Figure 5As shown, taking the target hardware timing unit as HCM1 and the second pulse signal as a PPS signal as an example, HCM1 can generate a PPS signal based on the current time information t4 and send the PPS signal to the second integrated circuit so that the second integrated circuit is time synchronized with the first integrated circuit.

[0093] When the first integrated circuit acts as a timing master to authorize other integrated circuits (such as a second integrated circuit), the target hardware timing unit can send a second pulse signal to the second integrated circuit; the second integrated circuit can determine the current time information of the first integrated circuit based on the received second pulse signal, and synchronize time with the first integrated circuit based on the current time information of the first integrated circuit.

[0094] like Figure 5 As shown, taking the target hardware timing unit as HCM1 and the second pulse signal as the PPS signal as an example, after the second integrated circuit receives the PPS signal sent by HCM1, it can determine the current time information t4 of HCM1 based on the PPS signal, and based on the current time information t4 of HCM1, correct the current time information t5 of the second integrated circuit, so that the current information time of the second integrated circuit is consistent with the current time information of the first integrated circuit.

[0095] The time synchronization method provided by the embodiment of the present disclosure can output the current time information of the target hardware timing unit to the second integrated circuit by generating a pulse signal through the target hardware timing unit and sending the pulse signal to the second integrated circuit when the timing mode is the second preset timing mode, so that the second integrated circuit can synchronize the time with the first integrated circuit based on the current time information of the target hardware timing unit, thereby realizing the external time synchronization function of the first integrated circuit on the basis of ensuring the unified time of each network communication unit in the chip.

[0096] like Figure 7 As shown in the above Figure 3 Based on the embodiment shown, the following steps may also be included:

[0097] Step 206, in response to the time synchronization mode being the second time synchronization mode and the timing mode being the second preset timing mode, determining a second network communication unit corresponding to the second time synchronization mode from a plurality of network communication units.

[0098] After multiple network communication units in the first integrated circuit are time synchronized, if the first integrated circuit serves as a timing master, the first integrated circuit can use a second time synchronization method to grant time to the second integrated circuit to achieve time synchronization between the first integrated circuit and the second integrated circuit.

[0099] In some embodiments, the second network communication unit is a network communication unit corresponding to the second time synchronization mode determined from multiple network communication units based on the second time synchronization mode. When the second time synchronization mode is different, the second network communication unit determined from the multiple network communication units is also different.

[0100] For example, Figure 5 As shown, taking the target hardware timing unit as HCM1 as an example, if the second time synchronization mode is time synchronization through Eth 1, the second network communication unit is Eth1 connected to HCM1; if the second time synchronization mode is time synchronization through CAN1, the second network communication unit is CAN1 connected to HCM1.

[0101] Step 207: Send the current time information of the second network communication unit to the second integrated circuit through the second network communication unit, so that the second integrated circuit is synchronized with the first integrated circuit.

[0102] When the first integrated circuit is used as a timing master to clock other integrated circuits (such as the second integrated circuit), the current time information of the second network communication unit can be sent to the second integrated circuit through the second network communication unit; the second integrated circuit can correct the current time information of the second integrated circuit based on the current time information of the second network communication unit to synchronize time with the first integrated circuit. The process of the second integrated circuit performing on-chip time synchronization can refer to the detailed description of the first integrated circuit in the first preset timing mode in the above embodiment, and the embodiment of the present disclosure will not be repeated here.

[0103] For example, Figure 5 As shown, taking the second network communication unit as Eth 1 as an example, the current time information t4 of Eth 1 is sent to the second integrated circuit through Eth1, so that the second integrated circuit can correct the current time information t5 of the second integrated circuit based on the current time information t4 of Eth 1, so that the current time information of the second integrated circuit is consistent with the current time information of the first integrated circuit.

[0104] It should be noted that the embodiment of the present disclosure does not limit the type of the second network communication unit. Figure 5 This is only an exemplary illustration. In actual applications, the second network communication unit may also be a network communication unit such as CAN0, Eth0 or PCIe0, that is, the current time information of the first integrated circuit may also be output to the second integrated circuit through CAN0, Eth0 or PCIe0.

[0105] The time synchronization method provided by the embodiment of the present disclosure, when the timing mode is the second preset timing mode, outputs the current time information of the target hardware timing unit to the second integrated circuit through the second network communication unit connected to the target hardware timing unit, so that the second integrated circuit is time-synchronized with the first integrated circuit based on the current time information of the target hardware timing unit, thereby realizing the external time synchronization function of the first integrated circuit on the basis of ensuring the time uniformity of each network communication unit in the chip.

[0106] like Figure 8 As shown in the above Figure 2 Based on the embodiment shown, the following steps are also included:

[0107] Step 208: Determine system time information of a system hardware timing unit in the first integrated circuit.

[0108] In some embodiments, the system hardware timing unit may transmit the system time information of the system hardware timing unit to the target hardware timing unit, so that the target hardware timing unit may determine the system time information of the system hardware timing unit.

[0109] In some embodiments, the system hardware timing unit is an existing hardware timing unit in the first integrated circuit, and the aforementioned at least one hardware timing unit is a hardware timing unit newly added in the integrated circuit in order to realize the on-chip time unification of multiple network communication units in the integrated circuit. In order to ensure the time synchronization between the system hardware timing unit and the target hardware timing unit, synchronization can be performed based on the system time information of the system hardware timing unit and the time information of the target hardware timing unit.

[0110] For example, Figure 1B As shown, the target hardware timing unit is HCM1, and the first integrated circuit also includes a system hardware timing unit 104. The system hardware timing unit 104 transmits the system time information T to HCM1, so that HCM1 can determine that the system time information of the system hardware timing unit 104 is T.

[0111] In some embodiments, the target hardware timing unit can compare the system time information of the system hardware timing unit with the current time information of the target hardware timing unit to determine whether the system time information of the system hardware timing unit is the same as the current time information of the target hardware timing unit; if the two are the same, no processing is performed, otherwise, the following step 209 is executed.

[0112] Step 209 , in response to the system time information of the system hardware timing unit being different from the current time information of the target hardware timing unit, the control system hardware timing unit and the target hardware timing unit are time synchronized based on the current time information of the target hardware timing unit.

[0113] In some embodiments, the current time information of the target hardware timing unit may be time information after time synchronization based on an external clock source, or the current time information of the target hardware timing unit may be time information not synchronized with an external clock source.

[0114] In some embodiments, when the system time information of the system hardware timing unit is different from the current time information of the target hardware timing unit, the target hardware timing unit can determine the time difference between the current time information of the target hardware timing unit and the system time information, and transmit the time difference to the system hardware timing unit; the system hardware timing unit can correct the system time information of the system hardware timing unit based on the time difference, so that the system hardware timing unit and the target hardware timing unit are synchronized in time.

[0115] For example, Figure 1B As shown, take the target hardware timing unit as HCM1 as an example. When HCM1 determines that the system time information T of the system hardware timing unit 104 is different from the current time information t0 of HCM1, HCM1 can calculate the time difference between its current time information and the system time information, and transmit the time difference to the system hardware timing unit 104; the system hardware timing unit 104 can correct the system time information based on the time difference, so that the system time information of the system hardware timing unit 104 is synchronized with the time of the target hardware timing unit. That is, the system time information of the system hardware timing unit 104 is synchronized with the time of each network communication unit.

[0116] The time synchronization method provided by the embodiment of the present disclosure can determine the system time information of the system hardware timing unit in the first integrated circuit, and when the system time information of the system hardware timing unit is different from the current time information of the target hardware timing unit, the system hardware timing unit is controlled to perform time synchronization with the target hardware timing unit based on the current time information of the target hardware timing unit. Since the embodiment of the present disclosure can synchronize the current time information of the target hardware timing unit to the system hardware timing unit, the system time information of the system hardware timing unit can be made consistent with the time of each network communication unit on the basis of ensuring the time uniformity of each network communication unit in the first integrated circuit, thereby ensuring the time uniformity of different hardware timing units in the chip.

[0117] Exemplary Electronic Devices

[0118] Fig. 9 This is a structural diagram of an electronic device provided in an embodiment of the present disclosure. The electronic device 90 includes at least one processor 91 and a memory 92.

[0119] The processor 91 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 90 to perform desired functions.

[0120] The memory 92 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 91 may execute one or more computer program instructions to implement the vehicle control method and / or other desired functions of the various embodiments of the present disclosure described above.

[0121] In one example, the electronic device 90 may further include: an input device 93 and an output device 94 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0122] The input device 93 may include various sensors, including but not limited to: a distance sensor for detecting the distance between the target object and the vehicle; an image sensor for collecting information about the vehicle's surrounding environment. In some examples, the input device may also include a pressure sensor for detecting seat pressure, determining whether there is a passenger, and the position of the passenger; a temperature sensor for monitoring the temperature in the cabin; a humidity sensor for monitoring the humidity in the cabin to assist in adjusting the interior environment; an air quality sensor for monitoring the air quality in the vehicle, such as carbon dioxide, volatile organic compounds (VOCs), etc.; a light sensor for detecting the light intensity inside and outside the vehicle; an acceleration sensor for detecting changes in the acceleration of the vehicle; a distance sensor for detecting the distance between the vehicle and other objects; a touch screen sensor for interaction with the vehicle's infotainment system; a biometric sensor, such as fingerprint recognition, facial recognition, etc.; a heart rate monitor for monitoring the driver's heart rate; a sound sensor for voice recognition and interaction to achieve voice control functions; a seat sensor for monitoring the use of the seat, such as whether the seat is occupied and the body shape of the passenger; a wireless communication sensor, such as Bluetooth, Wi-Fi, etc., for connecting with smart devices to achieve data transmission and remote control. In addition to the examples given above, the input device may also include more or fewer sensors, which will not be described in detail here.

[0123] The output device 94 can output various information or signals to other hardware or devices, which may include displays, vehicle audio, seats, windows, steering wheels, etc., as well as communication networks and remote output devices connected thereto, etc. The displays may include a plurality of different display screens such as a driver's display screen, a co-driver's display screen, and a rear display screen, and the vehicle audio may include a plurality of speakers arranged at different positions in the vehicle cabin, and different display screens or speakers may work independently.

[0124] Of course, to simplify, Fig. 9 Only some of the components related to the present disclosure in the electronic device 90 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 90 may also include any other appropriate components.

[0125] Exemplary computer program products and computer-readable storage media

[0126] In addition to the above-mentioned methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the time synchronization method for integrated circuits of various embodiments of the present disclosure described in the above-mentioned “Exemplary Method” section.

[0127] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0128] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps in the time synchronization method for integrated circuits of various embodiments of the present disclosure described in the above “Exemplary Method” section.

[0129] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0130] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0131] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the present claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A time synchronization method for an integrated circuit, comprising: determining a target hardware timing unit from at least one hardware timing unit in the first integrated circuit; Determining first time information of the target hardware timing unit; Based on the first time information, a plurality of network communication units in the first integrated circuit connected to the target hardware timing unit are controlled to perform time synchronization with the target hardware timing unit.

2. The method according to claim 1, wherein: The determining the first time information of the target hardware timing unit includes: Determine the time synchronization mode and timing mode of the target hardware timing unit; Based on the time synchronization mode and the timing mode, first time information of the target hardware timing unit is determined.

3. The method according to claim 2, wherein: The determining the first time information of the target hardware timing unit based on the time synchronization mode and the timing mode includes: In response to the time synchronization mode being the first time synchronization mode and the timing mode being the first preset timing mode, the target hardware timing unit receives a first pulse signal sent by a first clock source; Determining second time information of the first clock source based on the first pulse signal; The current time information of the target hardware timing unit is corrected based on the second time information to obtain the first time information of the target hardware timing unit.

4. The method according to claim 2, wherein: The determining the first time information of the target hardware timing unit based on the time synchronization mode and the timing mode includes: In response to the time synchronization mode being the second time synchronization mode and the timing mode being the first preset timing mode, the first network communication unit receives the third time information sent by the first clock source; wherein the first network communication unit is a network communication unit corresponding to the second time synchronization mode among the multiple network communication units; The target hardware timing unit corrects the current time information of the target hardware timing unit based on the third time information to obtain the first time information of the target hardware timing unit.

5. The method according to claim 2, wherein: The determining the first time information of the target hardware timing unit based on the time synchronization mode and the timing mode includes: In response to the time synchronization mode being the first time synchronization mode or the second time synchronization mode, and the timing mode being the second preset timing mode, first time information of the target hardware timing unit is determined based on current time information of the target hardware timing unit.

6. The method according to claim 5, further comprising: In response to the time synchronization mode being the first time synchronization mode and the timing mode being the second preset timing mode, generating a second pulse signal based on current time information of the target hardware timing unit; The second pulse signal is sent to a second integrated circuit to synchronize the time of the second integrated circuit with the first integrated circuit.

7. The method according to claim 5, further comprising: In response to the time synchronization mode being the second time synchronization mode and the timing mode being the second preset timing mode, determining a second network communication unit corresponding to the second time synchronization mode from the plurality of network communication units; The current time information of the second network communication unit is sent to the second integrated circuit through the second network communication unit, so that the second integrated circuit is synchronized with the first integrated circuit in time.

8. The method according to any one of claims 1 to 7, further comprising: Determining system time information of a system hardware timing unit in the first integrated circuit; In response to the system time information of the system hardware timing unit being different from the current time information of the target hardware timing unit, the system hardware timing unit is controlled to perform time synchronization with the target hardware timing unit based on the current time information of the target hardware timing unit.

9. An integrated circuit comprising: at least one hardware timing unit, a plurality of network communication units connected to each of the hardware timing units, and a processor; The processor is configured to determine a target hardware timing unit among the at least one hardware timing unit; The target hardware timing unit is used to determine the first time information of the target hardware timing unit and transmit the first time information of the target hardware timing unit to a plurality of network communication units connected to the target hardware timing unit; The multiple network communication units are used to perform time synchronization with the target hardware timing unit based on the first time information.

10. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the time synchronization method for an integrated circuit according to any one of claims 1 to 8.

11. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the time synchronization method for an integrated circuit according to any one of claims 1 to 8; Alternatively, the electronic device comprises the integrated circuit according to claim 9.

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