Correlated multi-sampling based tdi cmos image sensor analog domain accumulator and application method

Abstract

The application discloses a TDI type CMOS image sensor analog domain accumulator based on correlation multi-sampling, which comprises a correlation multi-sampling circuit and a 32-stage analog domain accumulator, the output end of the correlation multi-sampling circuit is connected with the input end of the 32-stage analog domain accumulator, the correlation multi-sampling circuit is used for performing multiple sampling averages on the signal output by a pixel, and the 32-stage analog domain accumulator is used for storing the output signal after the multiple sampling averages of the correlation multi-sampling circuit on a storage capacitor of an integrator; the multiple repeated operations realize the multi-stage accumulation in the analog domain; the application further discloses an application method of the TDI type CMOS image sensor analog domain accumulator based on correlation multi-sampling; when the correlation multi-sampling circuit performs multiple sampling averages on the signal output by a pixel, the noise of the signal is reduced, that is, the noise of the signal in each accumulation is reduced, therefore, along with the increase of the accumulation stages of the analog domain accumulator, the signal-to-noise ratio of the image sensor is continuously improved.

Description

Technical Field

[0001] This invention belongs to the field of TDI type image sensor technology, specifically relating to an analog domain accumulator for a TDI type CMOS image sensor based on correlation multisampling; it also relates to an application method of the analog domain accumulator for a TDI type CMOS image sensor based on correlation multisampling. Background Technology

[0002] Time-delay integration (TDI) technology involves taking multiple exposures of the same image and accumulating the information from the same pixels captured, thereby increasing the exposure time and enhancing the intensity of the acquired information. The number of rows N of the image sensor corresponds to the number of accumulations in the subsequent signal accumulator. Therefore, when capturing the same image, the information at any pixel in the image will be accumulated N times, increasing the signal energy by N. 2 The signal-to-noise ratio (SNR) of an image is increased by a factor of 1, while the noise energy generated during the entire accumulation process becomes N times the original value. Therefore, the increase in image signal strength is greater than the increase in noise, making it possible to obtain images with a higher SNR. Moreover, as the accumulation level increases, the SNR of the captured image also continuously improves. Therefore, time-delay integral image sensors are suitable for capturing images with higher SNR in low-light environments.

[0003] Charge-coupled device (CCD) image sensors, based on their structural characteristics, output image signals by transferring charge packets. The charge domain accumulator method used in TDI image sensors is well-suited to the pixel structure of CCD image sensors. During charge domain accumulation, the same signal charge packets can be transferred and accumulated based on the pixel structure of the CCD image sensor, along with specific timing. Moreover, the accumulation noise is very low. Therefore, the early development of TDI image sensors adopted the CCD image sensor structure. However, its disadvantages include high power consumption and difficulty in compatibility with CMOS processes. Later, with the continuous development of CMOS image sensor technology, the integration density has increased, cost and power consumption have decreased, and performance in dark current, light response, and noise has been significantly improved. Therefore, the research and development of TDI CMOS image sensors is in full swing.

[0004] Currently, the accumulation methods of TDI-type CMOS image sensors mainly include the following: charge domain accumulation, analog domain accumulation, digital domain accumulation, and hybrid domain accumulation. Charge domain accumulation is implemented within the pixel, characterized by low accumulation noise, but it is more complex to design. Analog domain accumulation is implemented at the front end of the readout circuit, characterized by simple circuit design, but circuit area and high-order parasitic limitations restrict the number of accumulation stages. Digital domain accumulation is implemented after the analog-to-digital converter, characterized by unlimited accumulation stages, but requiring a high-speed analog-to-digital converter and higher power consumption. Hybrid domain accumulation is based on any combination of the above three accumulation methods, characterized by having the advantages of multiple accumulation methods while also possessing their respective disadvantages. Therefore, to obtain images with higher signal-to-noise ratios, improvements to the above methods are needed. Summary of the Invention

[0005] The purpose of this invention is to provide an analog domain accumulator for TDI-type CMOS image sensors based on correlated multisampling, which can improve the signal-to-noise ratio of TDI-type CMOS image sensors with the same number of accumulation stages.

[0006] The present invention also aims to provide an application method for an analog domain accumulator of a TDI-type CMOS image sensor based on correlation multisampling.

[0007] The first technical solution adopted in this invention is: a TDI-type CMOS image sensor analog domain accumulator based on correlation multisampling, including a correlation multisampling circuit and a 32-level analog domain accumulator. The output terminal of the correlation multisampling circuit is connected to the input terminal of the 32-level analog domain accumulator. The correlation multisampling circuit is used to sample and average the input pixel signal multiple times. The 32-level analog domain accumulator is used to store the output signal after multiple sampling and averaging of the correlation multisampling circuit on the storage capacitor of the integrator. By repeating the operation multiple times, multi-level accumulation of the analog domain is realized.

[0008] The invention is further characterized in that,

[0009] The correlation multisampling circuit used in this invention can achieve averaging of eight samples of the same signal. This circuit includes nineteen CMOS switches N0~N4, N00~N44, R0~R4, Z0~Z3, and five sampling capacitors C0~C4. Pixel outputs are connected to the input terminals of switches N0~N4 respectively. The output terminal of switch N0 is connected to the upper stage board of capacitor C0, and the lower stage board of capacitor C0 is connected to the reference voltage Vref. The upper stage board of capacitor C0 is simultaneously connected to the output terminal of switch R0 and the input terminal of switch N00. The input terminal of switch R0 is connected to the reference voltage Vref. The output terminal of switch N1 is connected to the upper stage board of capacitor C1, and the lower stage board of capacitor C1 is connected to the reference voltage Vref. The upper stage board of capacitor C1 is simultaneously connected to the output terminal of switch R1 and the input terminal of switch N11. The input terminal is connected to the reference voltage Vref; the output terminal of switch N2 is connected to the upper stage board of capacitor C2, and the lower stage board of capacitor C2 is connected to the reference voltage Vref. The upper stage board of capacitor C2 is simultaneously connected to the output terminal of switch R2 and the input terminal of switch N22. The input terminal of switch R2 is connected to the reference voltage Vref; the output terminal of switch N3 is connected to the upper stage board of capacitor C3 and the input terminal of switch Z0. The lower stage board of capacitor C3 is connected to the reference voltage Vref, and the upper stage board of capacitor C3 is simultaneously connected to the output terminal of switch R3 and the input terminal of switch N33. The output terminal of switch Z0 is connected to switch L... 11 and switch L 21 The input terminals of switch R3 are connected to the reference voltage Vref; the output terminal of switch N4 is connected to the lower stage board of capacitor C4 and the input terminal of switch Z1, and the output terminal of switch Z1 is connected to the reference voltage Vref; the upper stage board of capacitor C4 is connected to the output terminal of switch Z2 and the input terminal of switch Z3, and the input terminal of switch Z2 is connected to the reference voltage Vref; the output terminal of switch Z3 is connected to switch L. 11 and switch L 21 The input terminal of capacitor C4 is connected to both the output terminal of switch R4 and the input terminal of switch N44. The input terminal of switch R4 is connected to the reference voltage Vref. The output terminals of switches N00 to N44 are also connected.

[0010] The 32-stage analog domain accumulator includes an operational amplifier, two sampling switches RST and RST', 33 integrators, sampling capacitor Cs, and four circuit switching switches L. 11 L 12 L 21 L 22 The output connection circuit of the related multi-sampling circuit switches L 11 L 21 Input terminal, circuit switching switch L 11 The output terminal is connected to the negative input terminal of the operational amplifier and the circuit switch L. 22 Output terminal, circuit switching switch L 21 The output terminal is connected to the positive input terminal of the operational amplifier and the circuit switch L.12 Output terminal, circuit switching switch L 22 The input terminal is connected to the upper plate of the sampling capacitor Cs and the circuit switching switch L. 12 At the input terminal, the lower plate of the sampling capacitor Cs is connected to the reference voltage V. R The input terminal of the sampling switch RST is connected to the negative input terminal of the operational amplifier and the input terminal of each stage integrator. The output terminal of the sampling switch RST is connected to the positive output terminal of the operational amplifier. The input terminal of the sampling switch RST' is connected to the positive input terminal of the operational amplifier and the input terminal of each stage integrator. The output terminal of the sampling switch RST' is connected to the negative output terminal of the operational amplifier.

[0011] Each integrator stage consists of four integrating switches. A I B I C I D Four circuit switching switches K A K B K C K D Two integrating capacitors C H C H It consists of ', and three reset switches Rs, Rs', and Rs"; and an integrating switch I. A Circuit switching switch K B The input terminals of both the reset switch Rs and the integrator I are connected to the negative input terminal of the operational amplifier. A The output terminal of the reset switch Rs is connected to the circuit switch K. A Input terminal and integrating capacitor C H Upper electrode plate, circuit switching switch K B The output terminal is connected to an integrating capacitor C. H Lower electrode plate and integral switch I B Input terminal, circuit switching switch K A and integral switch I B The output terminals of all terminals are connected to the positive output terminal of the operational amplifier, and the input terminal of the reset switch Rs' is connected to the integrating capacitor C. H The lower plate is connected to the integrating capacitor C at the output terminal. H The lower plate is connected to the circuit switch K at the positive input terminal of the operational amplifier. C Integral switch I D And the reset switch Rs” input terminal, circuit switching switch K C The output terminal is connected to an integral switch I. C Input terminal and integrating capacitor C H 'Lower electrode plate, integral switch I' D Output terminal connection circuit switch K D Input terminal, reset switch Rs” output terminal and integrating capacitor C H Upper plate, circuit switching switch K Dand integral switch I C The output terminal is connected to the negative output terminal of the operational amplifier.

[0012] The second technical solution adopted in this invention is an application method based on the analog domain accumulator of a correlated multisampling image sensor. The image is divided into 32 rows, represented by 32 symbols. During each drum exposure, only one new image signal enters the sensor. Pixels output a reset signal SET and an exposed image signal SIG. The correlated multisampling circuit samples and averages the reset signal and the exposed image signal multiple times, then outputs the averaged reset signal and image signal. Subsequently, a 32-stage analog domain accumulator acquires and accumulates the signal output by the correlated multisampling circuit. The circuit switching switch L in the 32-stage analog domain accumulator... 11 L 12 With circuit switching L 21 L 22 The integral switch I operates alternately during different duty cycles of the analog domain accumulator. A I B I C I D With circuit switching L 11 L 12 Operating within the same cycle, circuit switching switch K A K B K C K D With switch L 21 L 22 Operating in the same cycle, two positive image signals are accumulated in the same integrating capacitor, while a signal coupled to the integrating capacitor by a parasitic capacitor in the opposite direction and a signal coupled to the integrating capacitor by a parasitic capacitor in the positive direction will cancel each other out on the integrating capacitor.

[0013] When a pixel outputs a reset signal, switches R0-R3 are turned on, and the reference voltage Vref charges capacitors C0-C3, resetting them. After switches R0-R3 are turned off, switch N0 is turned on, and capacitor C0 begins to acquire the pixel output reset signal. After switch N0 is turned off, switch N1 is turned on, and capacitor C1 begins to acquire the pixel output reset signal. After switch N1 is turned off, switch N3 is turned on, and capacitor C3 begins to acquire the pixel output reset signal. Simultaneously, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, averaging the acquired reset signal twice. Then, switches N00 and N11 are turned off. After switch N3 is turned off, switch N2 is turned on, and capacitor... C2 begins acquiring the reset signal from the pixel output; after switch N2 is turned off, switch N0 turns on, and capacitor C0 begins acquiring the reset signal from the pixel output. Simultaneously, switches N22 and N33 turn on, and capacitors C2 and C3 share charge, averaging the acquired reset signal twice. Then, switches N22 and N33 are turned off. Afterward, switches N33 and N11 turn on, and capacitors C3 and C1 share charge, averaging the acquired reset signal four times. Then, switches N33 and N11 are turned off. After switch N0 is turned off, switch N1 turns on, and... Capacitor C1 begins acquiring the reset signal from the pixel output. After switch N1 is turned off, switch N2 turns on, and capacitor C2 begins acquiring the reset signal from the pixel output. Simultaneously, switches N00 and N11 turn on, and capacitors C0 and C1 share charge, averaging the acquired reset signal twice. Then, switches N00 and N11 are turned off. After switch N2 is turned off, switch N0 turns on, and capacitor C0 begins acquiring the reset signal from the pixel output. After switch N0 is turned off, switches N00 and N22 turn on, and capacitors C0 and C2 share charge, averaging the acquired reset signal twice. The reset signal is averaged twice, then switches N00 and N22 are turned off. After that, switches N11 and N22 are turned on, and capacitors C1 and C2 share the charge. The reset signal is averaged four times. Then switches N11 and N22 are turned off. Then switches N22 and N33 are turned on, and capacitors C2 and C3 share the charge. The reset signal is averaged eight times. Then switches N22 and N33 are turned off. After that, switches Z0 and Z2 are turned on, and the analog accumulator begins to acquire the reset signal averaged eight times by the relevant multisampling circuit.

[0014] After the pixel output reset signal is received, image signal output begins. Switches R0~R2 and R4 are turned on, and the reference voltage Vref charges capacitors C0~C2 and C4, resetting them. After switches R0~R2 and R4 are turned off, switch N0 is turned on, and capacitor C0 begins to acquire the pixel output image signal. After switch N0 is turned off, switch N1 is turned on, and capacitor C1 begins to acquire the pixel output image signal. After switch N1 is turned off, switch N4 is turned on, and capacitor C4 begins to acquire the pixel output image signal. Simultaneously, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, performing a second average of the acquired image signal. Then, switches N00 and N11 are turned off. After switch N4 is turned off, switch N2 is turned on, and capacitor C2... The process begins by acquiring image signals from the pixel output. After switch N2 is turned off, switch N0 turns on, and capacitor C0 begins acquiring image signals from the pixel output. Simultaneously, switches N22 and N44 turn on, and capacitors C2 and C4 share charge, averaging the acquired image signals twice. Then, switches N22 and N44 are turned off. Afterward, switches N44 and N11 turn on, and capacitors C4 and C1 share charge, averaging the acquired image signals four times. Then, switches N44 and N11 are turned off. After switch N0 is turned off, switch N1 turns on, and capacitor C1 begins acquiring image signals. The image signal output by the pixel; after switch N1 is turned off, switch N2 is turned on, and capacitor C2 begins to acquire the image signal output by the pixel. At the same time, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, averaging the acquired image signal twice. Then switches N00 and N11 are turned off. After switch N2 is turned off, switch N0 is turned on, and capacitor C0 begins to acquire the image signal output by the pixel. After switch N0 is turned off, switches N00 and N22 are turned on, and capacitors C0 and C2 share charge, averaging the acquired image signal twice. Then switches N00 and N22 are turned off. Switches N00 and N22 are turned on, then switches N11 and N22 are turned on, capacitors C1 and C2 share charge, and the acquired image signal is averaged four times. Switches N11 and N22 are then turned off, followed by switches N22 and N44, with capacitors C2 and C4 sharing charge, and the acquired image signal is averaged eight times. Switches N22 and N44 are then turned off, followed by switches Z0 and Z2. Switch Z1 is then turned on, followed by switch Z3. The analog accumulator begins acquiring the image signal averaged eight times by the correlated multisampling circuit. Before the reset signal of the next row of pixels is averaged eight times by the correlated multisampling circuit, switches Z1 and Z3 are turned off sequentially. After the reset signal of the next row of pixels is averaged eight times by the correlated multisampling circuit, the analog accumulator begins acquiring the reset signal output from the next row of pixels, which has been averaged eight times by the correlated multisampling circuit.

[0015] During the same duty cycle of the 32-level analog domain accumulator, the circuit switching switch L 11 L 12 and four integral switches I A I B IC I D Simultaneously, during the next 32-level analog domain accumulator duty cycle, the circuit switching switch L... 21 L 22 and four circuit switching switches K A K B K C K D Working simultaneously, the integrating capacitor stores a positive image signal and a signal coupled to the integrating capacitor by a parasitic capacitance in two working cycles, as well as a positive image signal and a signal coupled to the integrating capacitor by a positive parasitic capacitance. The two positive image signals are accumulated in the same integrating capacitor, while the signal coupled to the integrating capacitor by a parasitic capacitance in the reverse direction and the signal coupled to the integrating capacitor by a positive parasitic capacitance will cancel each other out in the integrating capacitor.

[0016] The beneficial effects of this invention are as follows: The TDI-type CMOS image sensor analog domain accumulator based on correlation multisampling proposed in this invention uses an image sensor composed of a correlation multisampling circuit and a 32-stage analog domain accumulator. The output of the correlation multisampling circuit is connected to the input of the 32-stage analog domain accumulator. The correlation multisampling circuit is used to average the signal output from the pixels multiple times. The 32-stage analog domain accumulator stores the output signal after multiple averages from the correlation multisampling circuit on the storage capacitor of the integrator. This process is repeated multiple times to achieve multi-stage accumulation in the analog domain. When the correlation multisampling circuit averages the signal output from the pixels multiple times, it reduces the noise of the signal, that is, it reduces the noise of each accumulated signal. Therefore, as the number of accumulation stages of the analog domain accumulator increases, the signal-to-noise ratio of the image sensor will continuously improve. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the analog domain accumulator for an image sensor based on correlation multisampling, as described in this invention.

[0018] Figure 2 This is a timing diagram of the correlation multiple sampling circuit in the analog domain accumulator of the image sensor based on correlation multiple sampling in this invention;

[0019] Figure 3 This is a timing diagram of the 32-level analog domain accumulator in the image sensor analog domain accumulator based on correlation multisampling of the present invention. Detailed Implementation

[0020] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments, so that the advantages and features of the present invention can be more readily understood by those skilled in the art.

[0021] Example 1

[0022] This invention is based on a correlated multisampling TDI type CMOS image sensor analog domain accumulator, with reference to... Figure 1 It includes a correlation multiple sampling circuit and a 32-level analog domain accumulator. The output of the correlation multiple sampling circuit is connected to the input of the 32-level analog domain accumulator. The correlation multiple sampling circuit is used to sample and average the signal output by the pixel multiple times. The 32-level analog domain accumulator is used to store the output signal after multiple sampling and averaging by the correlation multiple sampling circuit on the storage capacitor of the integrator. By repeating the operation multiple times, multi-level accumulation of the analog domain is realized.

[0023] Example 2

[0024] Based on Example 1, the related multisampling circuit includes nineteen CMOS switches N0~N4, N00~N44, R0~R4, Z0~Z3, and five sampling capacitors C0~C4. Pixel outputs are connected to the input terminals of switches N0~N4 respectively. The output terminal of switch N0 is connected to the upper-level board of capacitor C0, and the lower-level board of capacitor C0 is connected to the reference voltage Vref. The upper-level board of capacitor C0 is simultaneously connected to the output terminal of switch R0 and the input terminal of switch N00. The input terminal of switch R0 is connected to the reference voltage Vref. The output terminal of switch N1 is connected to the upper-level board of capacitor C1, and the lower-level board of capacitor C1 is connected to the reference voltage Vref. The upper-level board of capacitor C1 is simultaneously connected to the output terminal of switch R1 and the input terminal of switch N11. The input terminal is connected to the reference voltage Vref; the output terminal of switch N2 is connected to the upper stage board of capacitor C2, and the lower stage board of capacitor C2 is connected to the reference voltage Vref. The upper stage board of capacitor C2 is simultaneously connected to the output terminal of switch R2 and the input terminal of switch N22. The input terminal of switch R2 is connected to the reference voltage Vref; the output terminal of switch N3 is connected to the upper stage board of capacitor C3 and the input terminal of switch Z0. The lower stage board of capacitor C3 is connected to the reference voltage Vref, and the upper stage board of capacitor C3 is simultaneously connected to the output terminal of switch R3 and the input terminal of switch N33. The output terminal of switch Z0 is connected to switch L... 11 and switch L 21 The input terminals of switch R3 are connected to the reference voltage Vref; the output terminal of switch N4 is connected to the lower stage board of capacitor C4 and the input terminal of switch Z1, and the output terminal of switch Z1 is connected to the reference voltage Vref; the upper stage board of capacitor C4 is connected to the output terminal of switch Z2 and the input terminal of switch Z3, and the input terminal of switch Z2 is connected to the reference voltage Vref; the output terminal of switch Z3 is connected to switch L. 11 and switch L 21 The input terminal of capacitor C4 is connected to both the output terminal of switch R4 and the input terminal of switch N44. The input terminal of switch R4 is connected to the reference voltage Vref. Simultaneously, the output terminals of switches N00 to N44 are connected together.

[0025] Example 3

[0026] Based on Example 2, the 32-stage analog domain accumulator includes an operational amplifier, two sampling switches RST and RST', 33 integrators, a sampling capacitor Cs, and four circuit switching switches L. 11 L 12 L 21 L 22 The output connection circuit of the related multi-sampling circuit switches L. 11 L 21 Input terminal, circuit switching switch L 11 The output terminal is connected to the negative input terminal of the operational amplifier and the circuit switch L. 22 Output terminal, circuit switching switch L 21 The output terminal is connected to the positive input terminal of the operational amplifier and the circuit switch L. 12 Output terminal, circuit switching switch L 22 The input terminal is connected to the upper plate of the sampling capacitor Cs and the circuit switching switch L. 12 At the input terminal, the lower plate of the sampling capacitor Cs is connected to the reference voltage V. R The input terminal of the sampling switch RST is connected to the negative input terminal of the operational amplifier and the input terminal of each stage integrator. The output terminal of the sampling switch RST is connected to the positive output terminal of the operational amplifier. The input terminal of the sampling switch RST' is connected to the positive input terminal of the operational amplifier and the input terminal of each stage integrator. The output terminal of the sampling switch RST' is connected to the negative output terminal of the operational amplifier.

[0027] Example 4

[0028] Based on Example 3, each integrator consists of four integrating switches I. A I B I C I D Four circuit switching switches K A K B K C K D Two integrating capacitors C H C H It consists of ', and three reset switches Rs, Rs', and Rs"; and an integrating switch I. A Circuit switching switch K B The input terminals of both the reset switch Rs and the integrator I are connected to the negative input terminal of the operational amplifier. A The output terminal of the reset switch Rs is connected to the circuit switch K. A Input terminal and integrating capacitor C H Upper electrode plate, circuit switching switch K B The output terminal is connected to an integrating capacitor C. H Lower electrode plate and integral switch I B Input terminal, circuit switching switch K A and integral switch IB The output terminals of all terminals are connected to the positive output terminal of the operational amplifier, and the input terminal of the reset switch Rs' is connected to the integrating capacitor C. H The lower plate is connected to the integrating capacitor C at the output terminal. H The lower plate is connected to the circuit switch K at the positive input terminal of the operational amplifier. C Integral switch I D And the reset switch Rs” input terminal, circuit switching switch K C The output terminal is connected to an integral switch I. C Input terminal and integrating capacitor C H 'Lower electrode plate, integral switch I' D Output terminal connection circuit switch K D Input terminal, reset switch Rs” output terminal and integrating capacitor C H Upper plate, circuit switching switch K D and integral switch I C The output terminal is connected to the negative output terminal of the operational amplifier.

[0029] The output of the correlated multiple sampling circuit is connected to the input of the 32-level analog domain accumulator. The correlated multiple sampling circuit is used to sample and average the signal output by the pixel multiple times. The 32-level analog domain accumulator is used to store the output signal after multiple sampling and averaging by the correlated multiple sampling circuit on the storage capacitor of the integrator. By repeating the operation multiple times, multi-level accumulation in the analog domain is achieved.

[0030] Example 5

[0031] This invention relates to an application method of an analog domain accumulator for image sensors based on correlation multisampling, with reference to... Figure 2 and Figure 3 The image is divided into 32 rows, represented by 32 symbols: SIG(1), SIG(2), SIG(3), SIG(4), ..., SIG(32). During each drum exposure, only a new symbol image enters the sensor. A reset signal SET and an image signal SIG are output during each row exposure. The relevant multisampling circuit samples and averages these two signals, then outputs them to the analog domain accumulator. The circuit switching switch L in the 32-level analog domain accumulator... 11 L 12 With circuit switching L 21 L 22 The circuit switches L alternately operate during different duty cycles of the analog domain accumulator. Within the same duty cycle of the 32-level analog domain accumulator, the circuit switching switch L... 11 L 12 and four integral switches I A I B I C I DSimultaneously, during the next 32-level analog domain accumulator duty cycle, the circuit switching switch L... 21 L 22 and four circuit switching switches K A K B K C K D Operating simultaneously, the integrating capacitor stores, in two working cycles, a positive image signal and a signal coupled to the integrating capacitor by a negative parasitic capacitance, as well as a positive image signal and a signal coupled to the integrating capacitor by a positive parasitic capacitance. The two positive image signals are accumulated within the same integrating capacitor, while the signals coupled to the integrating capacitor by a negative parasitic capacitance and a signal coupled to the integrating capacitor by a positive parasitic capacitance cancel each other out, thus suppressing the influence of parasitic capacitance on the accumulation result and compensating for parasitic effects.

[0032] When a pixel outputs a reset signal, switches R0-R3 are turned on, and the reference voltage Vref charges capacitors C0-C3, resetting them. After switches R0-R3 are turned off, switch N0 is turned on, and capacitor C0 begins to acquire the pixel output reset signal. After switch N0 is turned off, switch N1 is turned on, and capacitor C1 begins to acquire the pixel output reset signal. After switch N1 is turned off, switch N3 is turned on, and capacitor C3 begins to acquire the pixel output reset signal. Simultaneously, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, averaging the acquired reset signal twice. Then, switches N00 and N11 are turned off. After switch N3 is turned off, switch N2 is turned on, and capacitor... C2 begins acquiring the reset signal from the pixel output; after switch N2 is turned off, switch N0 turns on, and capacitor C0 begins acquiring the reset signal from the pixel output. Simultaneously, switches N22 and N33 turn on, and capacitors C2 and C3 share charge, averaging the acquired reset signal twice. Then, switches N22 and N33 are turned off. Afterward, switches N33 and N11 turn on, and capacitors C3 and C1 share charge, averaging the acquired reset signal four times. Then, switches N33 and N11 are turned off. After switch N0 is turned off, switch N1 turns on, and... Capacitor C1 begins acquiring the reset signal from the pixel output. After switch N1 is turned off, switch N2 turns on, and capacitor C2 begins acquiring the reset signal from the pixel output. Simultaneously, switches N00 and N11 turn on, and capacitors C0 and C1 share charge, averaging the acquired reset signal twice. Then, switches N00 and N11 are turned off. After switch N2 is turned off, switch N0 turns on, and capacitor C0 begins acquiring the reset signal from the pixel output. After switch N0 is turned off, switches N00 and N22 turn on, and capacitors C0 and C2 share charge, averaging the acquired reset signal twice. The reset signal is averaged twice, then switches N00 and N22 are turned off. After that, switches N11 and N22 are turned on, and capacitors C1 and C2 share the charge. The reset signal is averaged four times. Then switches N11 and N22 are turned off. Then switches N22 and N33 are turned on, and capacitors C2 and C3 share the charge. The reset signal is averaged eight times. Then switches N22 and N33 are turned off. After that, switches Z0 and Z2 are turned on, and the analog accumulator begins to acquire the reset signal averaged eight times by the relevant multisampling circuit.

[0033] After the pixel output reset signal is received, image signal output begins. Switches R0~R2 and R4 are turned on, and the reference voltage Vref charges capacitors C0~C2 and C4, resetting them. After switches R0~R2 and R4 are turned off, switch N0 is turned on, and capacitor C0 begins to acquire the pixel output image signal. After switch N0 is turned off, switch N1 is turned on, and capacitor C1 begins to acquire the pixel output image signal. After switch N1 is turned off, switch N4 is turned on, and capacitor C4 begins to acquire the pixel output image signal. Simultaneously, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, performing a second average of the acquired image signal. Then, switches N00 and N11 are turned off. After switch N4 is turned off, switch N2 is turned on, and capacitor C2... The process begins by acquiring image signals from the pixel output. After switch N2 is turned off, switch N0 turns on, and capacitor C0 begins acquiring image signals from the pixel output. Simultaneously, switches N22 and N44 turn on, and capacitors C2 and C4 share charge, averaging the acquired image signals twice. Then, switches N22 and N44 are turned off. Afterward, switches N44 and N11 turn on, and capacitors C4 and C1 share charge, averaging the acquired image signals four times. Then, switches N44 and N11 are turned off. After switch N0 is turned off, switch N1 turns on, and capacitor C1 begins acquiring image signals. The image signal output by the pixel; after switch N1 is turned off, switch N2 is turned on, and capacitor C2 begins to acquire the image signal output by the pixel. At the same time, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, averaging the acquired image signal twice. Then switches N00 and N11 are turned off. After switch N2 is turned off, switch N0 is turned on, and capacitor C0 begins to acquire the image signal output by the pixel. After switch N0 is turned off, switches N00 and N22 are turned on, and capacitors C0 and C2 share charge, averaging the acquired image signal twice. Then switches N00 and N22 are turned off. Switches N00 and N22 are turned on, then switches N11 and N22 are turned on, capacitors C1 and C2 share charge, and the acquired image signal is averaged four times. Switches N11 and N22 are then turned off, followed by switches N22 and N44, with capacitors C2 and C4 sharing charge, and the acquired image signal is averaged eight times. Switches N22 and N44 are then turned off, followed by switches Z0 and Z2. Switch Z1 is then turned on, followed by switch Z3. The analog accumulator begins acquiring the image signal averaged eight times by the correlated multisampling circuit. Before the reset signal of the next row of pixels is averaged eight times by the correlated multisampling circuit, switches Z1 and Z3 are turned off sequentially. After the reset signal of the next row of pixels is averaged eight times by the correlated multisampling circuit, the analog accumulator begins acquiring the reset signal output from the next row of pixels, which has been averaged eight times by the correlated multisampling circuit.

[0034] Example 6

[0035] Based on Example 5, the related multisampling circuit averages the reset signal, and then the circuit switching switch L in the analog accumulator... 11 L 12Sampling switches RST and RST', as well as the three reset switches Rs1, Rs1', and Rs1" are turned on, and circuit switching switch L is turned on. 21 and L 22 Disconnect, then sampling switches RST and RST', as well as three reset switches Rs1, Rs1', and Rs1" are disconnected, and four integrating switches I A1 I B1 I C1 and I D1 When switch Z0 is turned on, capacitor C3 acquires the reset signal SET(1). When switch Z0 is turned off, switch Z3 is turned on, and the charge on capacitor C4, which acquired the image signal SIG(1), will be transferred to the integrating capacitor C. H1 and C H1 At this point, the integrating capacitor C H1 and C H1 'If a positive image SIG(1) signal is stored on the output, the output voltage will have a jump V SIG(1) Then the four integral switches I A1 I B1 I C1 and I D1 When switch Z3 is open, sampling switches RST and RST' are open, and the output voltage will have a reverse jump of -V. SIG(1) The parasitic capacitance in the integrator will cause this reverse transition -V SIG(1) Coupled to integrating capacitor C H1 and C H1 After the first exposure, the 32 image signals are stored in the 32 integrators as described above; during the second exposure, the timing of all switches in the correlated multisampling circuit remains unchanged, and the circuit switching switch L in the analog accumulator is switched. 21 L 22 Sampling switches RST and RST' are turned on, and circuit switching switch L... 11 L 12 After the circuit is disconnected, sampling switches RST and RST' are disconnected. After switch Z0 is turned on, capacitor C3 collects the reset signal SET(1). Switch Z0 is disconnected, switch Z3 is turned on, and the four circuit switching switches K A1 K B1 K C1 and K D1 When the circuit is turned on, the charge on capacitor C4, which acquired the image SIG(1) signal, will be transferred to the integrating capacitor C. H1 and C H1 At this point, the integrating capacitor C H1 and C H1 'If a positive image SIG(1) signal is stored on the output, the output voltage will have a jump V SIG(1) Then the four circuit switching switches KA1 K B1 K C1 and K D1 When switch Z3 is open, sampling switches RST and RST' are open, and the output voltage will have a positive jump V. SIG(1) The parasitic capacitance in the integrator will cause this positive jump V to be... SIG(1) Coupled to integrating capacitor C H1 and C H1 At this point, the integrating capacitor C H1 and C H1 There will be two positive image SIG(1) signals, and a negative parasitic capacitance coupled to the integrating capacitor C. H1 and C H1 The signal on the capacitor and a positive parasitic capacitance are coupled to the integrating capacitor C. H1 and C H1 The signals on the ' and parasitic capacitance coupling signals will cancel each other out, only at the integrating capacitor C H1 and C H1 The image SIG(1) signal is stored on the upper part. In addition, the two opposite output transitions of the first integrator in the second working cycle of the analog domain accumulator will also be coupled to the integrating capacitor C through the parasitic capacitance. H33 and C H33 However, the two can be directly canceled out. Working in this way, the circuit switching mechanism will suppress the effect of parasitic capacitance on the analog domain accumulation result.

Claims

1. An analog domain accumulator for a TDI-type CMOS image sensor based on correlation multisampling, characterized in that, It includes a correlated multiple sampling circuit and a 32-level analog domain accumulator. The output of the correlated multiple sampling circuit is connected to the input of the 32-level analog domain accumulator. The correlated multiple sampling circuit is used to sample and average the input pixel signal multiple times. The 32-level analog domain accumulator is used to store the output signal after multiple sampling and averaging of the correlated multiple sampling circuit on the storage capacitor of the integrator. By repeating the operation multiple times, multi-level accumulation of the analog domain is realized. The associated multisampling circuit includes CMOS switches N0~N4, N00~N44, R0~R4, Z0~Z3 and five sampling capacitors C0~C4; Specifically, the output terminal of switch N0 is connected to the upper board of capacitor C0, the lower board of capacitor C0 is connected to the reference voltage Vref, the upper board of capacitor C0 is connected to both the output terminal of switch R0 and the input terminal of switch N00, the input terminal of switch R0 is connected to the reference voltage Vref, and the output terminal of switch N1 is connected to the upper board of capacitor C1. The lower stage board of capacitor C1 is connected to the reference voltage Vref. The upper stage board of capacitor C1 is connected to both the output terminal of switch R1 and the input terminal of switch N11. The input terminal of switch R1 is connected to the reference voltage Vref. The output terminal of switch N2 is connected to the upper stage board of capacitor C2. The lower stage board of capacitor C2 is connected to the reference voltage Vref. The upper stage board of capacitor C2 is connected to both the output terminal of switch R2 and the input terminal of switch N22. The input terminal of switch R2 is connected to the reference voltage Vref. The output terminal of switch N3 is connected to the upper stage board of capacitor C3 and the input terminal of switch Z0. The lower stage board of capacitor C3 is connected to the reference voltage Vref, and the upper stage board of capacitor C3 is connected to both the output terminal of switch R3 and the input terminal of switch N33; the output terminal of switch Z0 is connected to the circuit switching switch L. 11 and L 21 The input terminal of switch R3 is connected to the reference voltage Vref. The output of switch N4 is connected to the lower stage board of capacitor C4 and the input of switch Z1. The output of switch Z1 is connected to the reference voltage Vref. The upper stage board of capacitor C4 is connected to the output of switch Z2 and the input of switch Z3. The input of switch Z2 is connected to the reference voltage Vref. The output of switch Z3 is connected to the circuit toggle switch L. 11 and L 21 The input terminal of capacitor C4 is connected to the output terminal of switch R4 and the input terminal of switch N44. The input terminal of switch R4 is connected to the reference voltage Vref, and the output terminals of switches N00~N44 are connected.

2. The analog domain accumulator for a TDI-type CMOS image sensor based on correlation multisampling according to claim 1, characterized in that, The 32-stage analog domain accumulator includes an operational amplifier, two sampling switches RST and RST', 33 integrators, a sampling capacitor Cs, and four circuit switching switches L. 11 L 12 L 21 L 22 The output connection circuit of the related multi-sampling circuit switches L. 11 L 21 Input terminal, circuit switching switch L 11 The output terminal is connected to the negative input terminal of the operational amplifier and the circuit switch L. 22 Output terminal, circuit switching switch L 21 The output terminal is connected to the positive input terminal of the operational amplifier and the circuit switch L. 12 Output terminal, circuit switching switch L 22 The input terminal is connected to the upper plate of the sampling capacitor Cs and the circuit switching switch L. 12 At the input terminal, the lower plate of the sampling capacitor Cs is connected to the reference voltage V. R The input terminal of the sampling switch RST is connected to the negative input terminal of the operational amplifier and the input terminal of each stage integrator. The output terminal of the sampling switch RST is connected to the positive output terminal of the operational amplifier. The input terminal of the sampling switch RST' is connected to the positive input terminal of the operational amplifier and the input terminal of each stage integrator. The output terminal of the sampling switch RST' is connected to the negative output terminal of the operational amplifier.

3. The analog domain accumulator for a TDI-type CMOS image sensor based on correlation multisampling according to claim 2, characterized in that, Each integrator stage consists of four integrating switches I A I B I C I D Four circuit switching switches K A K B K C K D Two integrating capacitors C H C H It consists of ', and three reset switches Rs, Rs', and Rs"; and an integrating switch I. A Circuit switching switch K B The input terminals of both the reset switch Rs and the integrator I are connected to the negative input terminal of the operational amplifier. A The output terminal of the reset switch Rs is connected to the circuit switch K. A Input terminal and integrating capacitor C H Upper electrode plate, circuit switching switch K B The output terminal is connected to an integrating capacitor C. H Lower electrode plate and integral switch I B Input terminal, circuit switching switch K A and integral switch I B The output terminals of all terminals are connected to the positive output terminal of the operational amplifier, and the input terminal of the reset switch Rs' is connected to the integrating capacitor C. H The lower plate is connected to the integrating capacitor C at the output terminal. H The lower plate is connected to the circuit switch K at the positive input terminal of the operational amplifier. C Integral switch I D And the reset switch Rs” input terminal, circuit switching switch K C The output terminal is connected to an integral switch I. C Input terminal and integrating capacitor C H 'Lower electrode plate, integral switch I' D Output terminal connection circuit switch K D Input terminal, reset switch Rs” output terminal and integrating capacitor C H Upper plate, circuit switching switch K D and integral switch I C The output terminal is connected to the negative output terminal of the operational amplifier.

4. An application method for an analog domain accumulator based on a correlated multisampling TDI-type CMOS image sensor, characterized in that, The analog domain accumulator of the TDI-type CMOS image sensor based on correlation multisampling as described in any one of claims 1-3 is specifically as follows: The image is divided into 32 rows of pixels. During each drum exposure, only a new image signal enters the sensor. During one row of exposure, a reset signal SET and an image signal SIG are output. The correlation multisampling circuit samples and averages these two signals respectively, and then outputs them to the 32-stage analog domain accumulator; the circuit switching switch L in the 32-stage analog domain accumulator... 11 L 12 With circuit switching L 21 L 22 The circuit switches L alternately operate during different duty cycles of the analog domain accumulator. Within the same duty cycle of the 32-level analog domain accumulator, the circuit switching switch L... 11 L 12 and four integral switches I A I B I C I D Simultaneously, during the next 32-level analog domain accumulator duty cycle, the circuit switching switch L... 21 L 22 and four circuit switching switches K A K B K C K D Working simultaneously, the integrating capacitor stores a positive image signal and a signal coupled to the integrating capacitor by a parasitic capacitance in opposite directions, as well as a positive image signal and a signal coupled to the integrating capacitor by a positive parasitic capacitance in two working cycles. The two positive image signals are accumulated in the same integrating capacitor, while the signal coupled to the integrating capacitor by a parasitic capacitance in opposite directions and the signal coupled to the integrating capacitor by a positive parasitic capacitance cancel each other out in the same integrating capacitor, thereby suppressing the influence of parasitic capacitance on the accumulation result and compensating for parasitic effects.

5. The application method of the analog domain accumulator of a TDI-type CMOS image sensor based on correlation multisampling according to claim 4, characterized in that, When a pixel outputs a reset signal, switches R0~R3 are turned on, and the reference voltage Vref charges capacitors C0~C3, resetting them. After switches R0~R3 are turned off, switch N0 is turned on, and capacitor C0 begins to acquire the pixel output reset signal. After switch N0 is turned off, switch N1 is turned on, and capacitor C1 begins to acquire the pixel output reset signal. After switch N1 is turned off, switch N3 is turned on, and capacitor C3 begins to acquire the pixel output reset signal. Simultaneously, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, processing the acquired reset signal. The signal is averaged twice, then switches N00 and N11 are turned off. After switch N3 is turned off, switch N2 turns on, and capacitor C2 begins to collect the reset signal from the pixel output. After switch N2 is turned off, switch N0 turns on, and capacitor C0 begins to collect the reset signal from the pixel output. At the same time, switches N22 and N33 turn on, and capacitors C2 and C3 share charge. The collected reset signal is averaged twice. Then switches N22 and N33 are turned off. After that, switches N33 and N11 turn on, and capacitors C3 and C1 share charge. The collected reset signal is averaged four times. Then the switches are turned off. N33, N11; After switch N0 is turned off, switch N1 is turned on, and capacitor C1 begins to collect the reset signal output by the pixel; After switch N1 is turned off, switch N2 is turned on, and capacitor C2 begins to collect the reset signal output by the pixel. At the same time, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, averaging the collected reset signal twice. Then switches N00 and N11 are turned off; After switch N2 is turned off, switch N0 is turned on, and capacitor C0 begins to collect the reset signal output by the pixel; After switch N0 is turned off, switches N00 and N22 are turned on, and capacitor C0... The reset signal is averaged twice with C2, then switches N00 and N22 are turned off. After that, switches N11 and N22 are turned on, and capacitors C1 and C2 share the charge, averaging the reset signal four times. Then switches N11 and N22 are turned off, then switches N22 and N33 are turned on, and capacitors C2 and C3 share the charge, averaging the reset signal eight times. After that, switches N22 and N33 are turned off, and switches Z0 and Z2 are turned on. The analog accumulator begins to acquire the reset signal averaged eight times by the relevant multisampling circuit.

6. The application method of the analog domain accumulator of a TDI-type CMOS image sensor based on correlation multisampling according to claim 5, characterized in that, After the current row pixel outputs a reset signal, image signal output begins. Switches R0~R2 and R4 are turned on, and the reference voltage Vref charges capacitors C0~C2 and C4, resetting them. After switches R0~R2 and R4 are turned off, switch N0 is turned on, and capacitor C0 begins to acquire the image signal from the pixel output. After switch N0 is turned off, switch N1 is turned on, and capacitor C1 begins to acquire the image signal from the pixel output. After switch N1 is turned off, switch N4 is turned on, and capacitor C4 begins to acquire the image signal from the pixel output. Simultaneously, switches N00 and N11 are turned on, and capacitors C0 and C1 share charge, performing a second averaging of the acquired image signal. Then, switches N00 and N11 are turned off. 11; After switch N4 is turned off, switch N2 is turned on, and capacitor C2 begins to acquire the image signal output by the pixel; After switch N2 is turned off, switch N0 is turned on, and capacitor C0 begins to acquire the image signal output by the pixel. At the same time, switches N22 and N44 are turned on, and capacitors C2 and C4 share charge, averaging the acquired image signal twice. Then switches N22 and N44 are turned off. After that, switches N44 and N11 are turned on, and capacitors C4 and C1 share charge, averaging the acquired image signal four times. Then switches N44 and N11 are turned off; After switch N0 is turned off, switch N1 is turned on, and capacitor C1 begins to acquire the image signal output by the pixel; After switch N1 is turned off, the switch... When N2 is turned on, capacitor C2 begins to acquire the image signal output from the pixel. Simultaneously, switches N00 and N11 are turned on, and capacitors C0 and C1 share the same charge, performing a second average of the acquired image signal. Then, switches N00 and N11 are turned off. After switch N2 is turned off, switch N0 is turned on, and capacitor C0 begins to acquire the image signal output from the pixel. After switch N0 is turned off, switches N00 and N22 are turned on, and capacitors C0 and C2 share the same charge, performing a second average of the acquired image signal. Then, switches N00 and N22 are turned off. Afterward, switches N11 and N22 are turned on, and capacitors C1 and C2 share the same charge, performing a fourth average of the acquired image signal. Finally, switch N11 is turned off. Switches N22 and N44 are turned on, and capacitors C2 and C4 share charge. The acquired image signal is averaged eight times. Then switches N22 and N44 are turned off. After that, switches Z0 and Z2 are turned off. Then switch Z1 is turned on, followed by switch Z3. The analog accumulator begins to acquire the image signal averaged eight times by the correlated multisampling circuit. Before the reset signal of the next row of pixels is averaged eight times by the correlated multisampling circuit, switches Z1 and Z3 are turned off one after the other. After the reset signal of the next row of pixels is averaged eight times by the correlated multisampling circuit, the analog accumulator begins to acquire the reset signal output of the next row of pixels, which has been averaged eight times by the correlated multisampling circuit.

7. The application method of the analog domain accumulator of a TDI-type CMOS image sensor based on correlation multisampling according to claim 5, characterized in that, After the relevant multisampling circuit averages the reset signal, the circuit switching switch L in the analog accumulator... 11 L 12 Sampling switches RST and RST', as well as the three reset switches Rs1, Rs1', and Rs1" are turned on, and circuit switching switch L is turned on. 21 and L 22 Disconnect, then sampling switches RST and RST', as well as three reset switches Rs1, Rs1', and Rs1" are disconnected, and four integrating switches I A1 I B1 I C1 and I D1 When switch Z0 is on, capacitor C3 acquires the reset signal. When switch Z0 is off, switch Z3 is on, and the charge on capacitor C4, which has acquired the image signal, is transferred to integrating capacitor C. H1 and C H1 At this point, the integrating capacitor C H1 and C H1 'If a positive image signal is stored on the output, the output voltage will have a jump V' SIG(1) Then the four integral switches I A1 I B1 I C1 and I D1 When switch Z3 is open, sampling switches RST and RST' are open, and the output voltage will have a reverse jump of -V. SIG(1) The parasitic capacitance in the integrator will cause this reverse transition -V SIG(1) Coupled to integrating capacitor C H1 and C H1 After the first exposure, the 32 image signals are stored in the 32 integrators as described above. During the second exposure, the timing of all switches in the relevant multisampling circuit remains unchanged, and the circuit switching switch L in the analog accumulator... 21 L 22 Sampling switches RST and RST' are turned on, and circuit switching switch L... 11 L 12 After the circuit is disconnected, sampling switches RST and RST' are disconnected. After switch Z0 is turned on, capacitor C3 collects the reset signal. Switch Z0 is then disconnected, switch Z3 is turned on, and the four circuit switching switches K... A1 K B1 K C1 and K D1 When the circuit is turned on, the charge on capacitor C4, which has acquired the image signal, will be transferred to the integrating capacitor C. H1 and C H1 At this point, the integrating capacitor C H1 and C H1 'If a positive image signal is stored on the output, the output voltage will have a jump V' SIG(1) Then the four circuit switching switches K A1 K B1 K C1 and K D1 When switch Z3 is open, sampling switches RST and RST' are open, and the output voltage will have a positive jump V. SIG(1) The parasitic capacitance in the integrator will cause this positive jump V to be... SIG(1) Coupled to integrating capacitor C H1 and C H1 At this point, the integrating capacitor C H1 and C H1 There will be two positive image signals, and a parasitic capacitance in the opposite direction coupled to the integrating capacitor C. H1 and C H1 The signal on the capacitor and a positive parasitic capacitance are coupled to the integrating capacitor C. H1 and C H1 The signals on the ' and parasitic capacitance coupling signals will cancel each other out, only at the integrating capacitor C H1 and C H1 The accumulator stores two positive image signals. In addition, the two opposite output transitions of the first integrator during the second operating cycle of the analog domain accumulator are also coupled to the integrating capacitor C via parasitic capacitance. H33 and C H33 However, the two can be directly canceled out; in this way, the circuit switching switch will suppress the influence of parasitic capacitance on the analog domain accumulation result.

Images