On-chip bias drive system for sensor pixel arrays

Abstract

The present invention provides an on-chip bias driving system for a sensor pixel array, which relates to the field of integrated circuit technology and image sensing. The on-chip bias driving system includes: a pixel array, including a plurality of pixel units, each pixel unit including a first transistor and a second transistor; a first voltage generator, configured to generate a first voltage according to a reference current, the first voltage is loaded to the gate of each first transistor, the magnitude of the first voltage is controlled by a first digital code to control the current magnitude of the first transistor; a second voltage generator, configured to generate a second voltage according to the reference voltage, the second voltage is loaded to the gate of each second transistor, the magnitude of the second voltage is controlled by a second digital code, so that the second transistor controls the DC operating point in the pixel unit or generates a comparison voltage inside the pixel unit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology and image sensing, and more specifically to an on-chip bias driving system applied to a high-resolution sensor pixel array. Background Art

[0002] As a result of the long-term development of microelectronics technology, CMOS image sensors have become an important tool for recording visual information. With the development of the times, the demand for high-quality imaging sensors in various scenarios has increased, and the imaging resolution of sensors has continued to improve. The pixel circuit structure of some sensors is complex, and there is a bias voltage of the transistor, so it is necessary to provide a shared analog bias bus to the pixel array externally. When the imaging resolution is large, the gate parasitic capacitance of all transistors in the pixel array often reaches the nanofarad level, which brings challenges to the design of the bias scheme. Many current bias schemes have the following disadvantages:

[0003] (1) Some solutions use off-chip independent amplifiers, linear regulators and other electronic components, which increases the size and power consumption of the system, while lengthening the analog routing and increasing noise.

[0004] (2) Some solutions use a two-stage amplifier on the chip as the driving stage, but set the bias output point as the main pole through a large capacitor outside the chip, which reduces the transient response speed of the bias bus.

[0005] (3) Some solutions use a two-stage amplifier on the chip as the driving stage and set the bias output point to the secondary pole. However, when the pixel array resolution increases, the load capacitance of all transistors in the array increases, and the power consumption proportional to the load will increase sharply.

[0006] (4) In some solutions, the reference voltage comes from outside the chip, and the bias voltage value is adjusted by a manual mechanical device. Summary of the invention

[0007] Based on the above problems, the present invention provides an on-chip bias driving system for a high-resolution pixel array, which can achieve intelligent regulation of the bias voltage using digital codes while maintaining microsecond transient response speed and low power consumption.

[0008] An embodiment of the present invention provides an on-chip bias driving system, comprising: a pixel array, comprising a plurality of pixel units, each pixel unit comprising a first transistor and a second transistor; a first voltage generator, configured to generate a first voltage according to a reference current, the first voltage being loaded to a gate of each first transistor, the magnitude of the first voltage being controlled by a first digital code to control the magnitude of the current of the first transistor; a second voltage generator, configured to generate a second voltage according to a reference voltage, the second voltage being loaded to a gate of each second transistor, the magnitude of the second voltage being controlled by a second digital code to enable the second transistor to control a DC operating point in the pixel unit or generate a comparison voltage inside the pixel unit.

[0009] According to an embodiment of the present invention, the first voltage generator includes: a current mirror, which is configured to copy a reference current and transmit it to an output electrode of the current mirror; K switches, each switch includes a first end and a second end, each first end is connected to the output electrode, and K is a positive integer greater than or equal to 1; K+1 N-type transistors, the source of each N-type transistor is connected to a fixed ground potential, the gate of each N-type transistor is connected to the output electrode, the drain of the first N-type transistor of the K+1 N-type transistors is connected to the output electrode, and the drains of the remaining K N-type transistors are respectively connected to the corresponding second ends; wherein the first digital code is set to act on the K switches, and by controlling the on and off of each switch, the drain of the current mirror generates a first voltage.

[0010] According to an embodiment of the present invention, the ratio of the width-to-length ratios of the remaining K N-type transistors is a geometric progression of 2, and the width-to-length ratio of the first N-type transistor is equal to the minimum width-to-length ratio of the remaining K N-type transistors.

[0011] According to an embodiment of the present invention, a width-to-length ratio of the first transistor is an integer multiple of that of the first N-type transistor.

[0012] According to an embodiment of the present invention, the current mirror includes: a first P-type transistor, the drain of the first P-type transistor flows into the reference current; a second P-type transistor, the drain of the second P-type transistor flows into the reference current; a third P-type transistor, the drain of the third P-type transistor is connected to the source of the first P-type transistor, the gate of the third P-type transistor is connected to the gate of the first P-type transistor, and the source of the third P-type transistor is connected to a fixed power supply potential; a fourth P-type transistor, the drain of the fourth P-type transistor is connected to the source of the second P-type transistor, the gate of the fourth P-type transistor is connected to the drain of the second P-type transistor, and the source of the fourth P-type transistor is connected to the fixed power supply potential; a fifth P-type transistor, the gate of the fifth P-type transistor is connected to the gate of the fourth P-type transistor, and the source of the fifth P-type transistor is connected to the fixed power supply potential; a sixth P-type transistor, the source of the sixth P-type transistor is connected to the drain of the fifth P-type transistor, and the gate of the sixth P-type transistor is connected to the gate of the first P-type transistor and the gate of the second P-type transistor, wherein the drain of the sixth P-type transistor is connected to the gate of each N-type transistor and each first end as the output electrode of the current mirror.

[0013] According to an embodiment of the present invention, the second P-type transistor and the first P-type transistor have the same width-to-length ratio, the width-to-length ratio of the first P-type transistor is an integer multiple of the third P-type transistor; the width-to-length ratio of the fifth P-type transistor is an integer multiple of the fourth P-type transistor, and the width-to-length ratio of the sixth P-type transistor is an integer multiple of the second P-type transistor.

[0014] According to an embodiment of the present invention, the second voltage generator includes: a first amplifier, including a first positive input terminal, a first negative input terminal and a first output terminal, the first negative input terminal is connected to the first output terminal, and the first positive input terminal is used to receive and input a reference voltage; a resistor string, composed of 2 T resistors are connected in series in sequence, one end of the resistor string is connected to the first output terminal, and the other end of the resistor string is connected to a fixed ground potential, and T is a positive integer greater than or equal to 1; a multiplexer includes 2 T A selection terminal, each of which is connected to a node of a corresponding resistor close to the first output terminal; wherein the second digital code is set to act on the multiplexer, by selecting 2 T The voltages at different nodes of the resistors are used as the second voltage.

[0015] According to an embodiment of the present invention, the on-chip bias driving system also includes: two second amplifiers, respectively connected to the first voltage generator and the second voltage generator, and the second amplifiers are configured to amplify the first voltage and the second voltage with a gain of 1 and input them to the first transistor and the second transistor respectively.

[0016] According to an embodiment of the present invention, the second amplifier includes: a first transconductance amplifier, a second transconductance amplifier, a third transconductance amplifier, a fourth transconductance amplifier, and a fifth transconductance amplifier, the input of the first transconductance amplifier is the input of the second amplifier, the output of the first transconductance amplifier is connected to the input of the second transconductance amplifier and the input of the fifth transconductance amplifier, the output of the second transconductance amplifier is connected to the input of the third transconductance amplifier and the output of the fourth transconductance amplifier, and the output of the third transconductance amplifier is connected to the output of the fifth transconductance amplifier; a first capacitor, one end of the first capacitor is connected to the output of the first transconductance amplifier, and the other end of the first capacitor is connected to the output of the third transconductance amplifier; a second capacitor, one end of the second capacitor is connected to the input of the fourth transconductance amplifier, and the other end of the second capacitor is connected to the output of the third transconductance amplifier, and the output of the third transconductance amplifier is the output of the second amplifier.

[0017] According to an embodiment of the present invention, the on-chip bias driving system further includes: a bandgap reference source configured to generate a reference voltage and a reference current; and a reference current generator configured to replicate the reference current to obtain at least one reference current.

[0018] It can be seen from the above technical solutions that the present invention proposes an on-chip bias driving system for a high-resolution pixel array, which has at least the following beneficial effects:

[0019] (1) The bias system proposed in the present invention uses an on-chip integrated analog circuit, which can reduce the size, power consumption and noise of the system.

[0020] (2) The bias system proposed in the present invention uses digital code configuration to generate bias voltage, which is conducive to integration with digital processing function modules to achieve an integrated intelligent system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram of a structure of an on-chip bias driving system according to an embodiment of the present invention is shown;

[0023] Figure 2 A schematic diagram of a structure of a first voltage generator according to an embodiment of the present invention is shown;

[0024] Figure 3 A schematic diagram of a structure of a second voltage generator according to an embodiment of the present invention is shown;

[0025] Figure 4 A schematic diagram showing a structure of a multiplexer according to an embodiment of the present invention;

[0026] Figure 5A schematic diagram of a structure of an on-chip bias driving system according to yet another embodiment of the present invention is shown;

[0027] Figure 6 A schematic diagram of the structure of a second amplifier according to an embodiment of the present invention is shown;

[0028] Figure 7 Schematically shows a structural diagram of a second amplifier according to yet another embodiment of the present invention;

[0029] Figure 8 A schematic diagram of a bandgap reference source according to an embodiment of the present invention is shown;

[0030] Fig. 9 The structure of a reference current generator according to an embodiment of the present invention is schematically shown. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0032] Embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which some but not all embodiments are shown. Indeed, various embodiments of the present invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure may satisfy applicable legal requirements.

[0033] Figure 1 The structure diagram of an on-chip bias driving system according to an embodiment of the present invention is schematically shown.

[0034] like Figure 1 As shown, the on-chip bias driving system may include: a pixel array, a first voltage generator and a second voltage generator.

[0035] The pixel array may include M×N pixel units, where M and N are positive integers. Each pixel unit includes a first transistor M1 and a second transistor M0. The present invention does not limit the number and specific arrangement of the pixel units.

[0036] The first voltage generator is configured to generate a voltage according to a reference current I ref A first voltage V1 is generated, and the first voltage V1 is applied to the gate of each first transistor M1. The magnitude of the first voltage V1 can be controlled by the first digital code K bit, thereby controlling the current magnitude of the first transistor M1. In other words, the first transistor M1 can be used as a current source capable of generating a specified current magnitude. The first voltage can be used as a bias voltage of an on-chip bias drive system. The first voltage generator can also be a current source bias voltage generator.

[0037] The second voltage generator is configured to generate a voltage according to the reference voltage V BG A second voltage V2 is generated, and the second voltage V2 is loaded to the gate of each second transistor M0. The magnitude of the second voltage V2 is controlled by the second digital code T bit, so that the second transistor M0 controls the DC operating point in the pixel unit or generates a comparison voltage inside the pixel unit. The second voltage can be used as a reference voltage for an on-chip bias drive system. The second voltage generator can be a reference voltage generator.

[0038] According to this embodiment, the bias voltage and the reference voltage can be intelligently controlled through digital codes, which is beneficial for integration with digital processing function modules to realize an integrated intelligent system.

[0039] Figure 2 The structure of a first voltage generator according to an embodiment of the present invention is schematically shown.

[0040] like Figure 2 As shown, the first voltage generator may include devices such as a current mirror, a plurality of switches, and a plurality of N-type transistors.

[0041] The current mirror may include an output stage. The current mirror is configured to replicate the reference current and transmit it to the output stage of the current mirror. Each switch S <1> , S <2> , … , S <k>It includes a first terminal and a second terminal, each of which is connected to an output terminal, and K is a positive integer greater than or equal to 1. K+1 N-type transistors M n0 、M n1 、M n2 , …, M nK The source of each N-type transistor in the K+1 N-type transistors is connected to a fixed ground potential, and the gate of each N-type transistor is connected to the output electrode of the current mirror. n0 The drain of the other K N-type transistors M n1 、M n2 , …, M nK The drains of the current mirror are connected to the corresponding second ends respectively. The first digital code K bit is set to act on K switches, and by controlling the on and off of each switch, the drain of the current mirror generates a first voltage V1.

[0042] In some embodiments, the remaining K N-type transistors M n1 、M n2 , …, M nK The ratio of the width to length ratio is a geometric progression of 2, and the first N-type transistor M n0 The width-to-length ratio of the remaining K N-type transistors M n1 、M n2 , …, M nK For example, K+1 N-type transistors M n0 、M n1 、M n2 ,… ,M nK The ratios of the width to length can be 1:1:2:4: …:2 K-1 .

[0043] In some embodiments, the width-to-length ratio of the first transistor M1 is n0 An integer multiple of .

[0044] Please continue reading Figure 2 The first voltage generator generates two bias voltages of the common-source and common-gate current sources by inputting two reference currents I1 and I2, and replicates the reference currents I1 and I2 to B times, and inputs them into the transistor array whose switches are controlled by the first digital code K bit. The reference current I1 is equal to the reference current I2. The switches with corresponding weight bits correspond to transistors of the same proportional size, where the switches S <k>The N-type transistor M controlled nK The width-to-length ratio is affected by the switch S <1> Controlled M n1 Aspect ratio of 2 K-1 times. Then when the width-to-length ratio of the first transistor M1 in the pixel unit is n0 When the first voltage V1 generated by the first voltage generator is loaded onto the gate of M1, the magnitude of the drain current I of the first transistor M1 generated can be expressed as:

[0045]

[0046] In the formula, represents the value of the reference current I1 or I2, which are equal. B, C, and K are all positive integers. It can be seen from the above formula that different drain currents I of the first transistor M1 can be obtained when different switches are turned on and off.

[0047] Please continue reading Figure 2 The current mirror in the first voltage generator may include six P-type transistors, namely, the first P-type transistor M p5 , the second P-type transistor M p2 , the third P-type transistor M p4 , the fourth P-type transistor M p0 , the fifth P-type transistor M p1 , the sixth P-type transistor M p3 The first P-type transistor M p5 The reference current I1 flows into the drain of the second P-type transistor M p2 The reference current I2 flows into the drain of the third P-type transistor M p4 The drain of the first P-type transistor M p5 The source of the third P-type transistor M p4 The gate and the first P-type transistor M p5 The gate of the third P-type transistor M p4 The source of the fourth P-type transistor M is connected to a fixed power supply potential. p0 The drain of the second P-type transistor M p2 The source of the fourth P-type transistor M p0 The gate of the second P-type transistor M p2 The drain of the fourth P-type transistor M p0 The source of the fifth P-type transistor M is connected to a fixed power supply potential. p1 The gate and the fourth P-type transistor M p0 The gate of the fifth P-type transistor M p1 The source of the sixth P-type transistor M is connected to a fixed power supply potential. p3 The source of the fifth P-type transistor M p1 The drain of the sixth P-type transistor M p3 The gate of the first P-type transistor M p5 The gate of the second P-type transistor M p2 The gate of the sixth P-type transistor M p3 The drain of the current mirror can be used as the output of the current mirror and the gate of each N-type transistor and each switch S <1> , S <2> , … , S <k>Each switch S is controlled by the first digital code K bit. <1> , S <2> ,…,S <k>The on and off of the sixth P-type transistor M p3 The drain of generates a first voltage V1.

[0048] In some embodiments, the second P-type transistor M p2 and the first P-type transistor M p5 The width-to-length ratio of the first P-type transistor M p5 The width-to-length ratio of the third P-type transistor M may be p4 The fifth P-type transistor M p1 The width-to-length ratio of the fourth P-type transistor M may be p0 The sixth P-type transistor M p3 The width-to-length ratio of the second P-type transistor M may be p2 An integer multiple of .

[0049] For example, the fifth P-type transistor M p1 The width-to-length ratio of the fourth P-type transistor M p0 The sixth P-type transistor M p3 The width-to-length ratio of the second P-type transistor M p2 An integer B times of the reference current I1 and I2 can be copied to B times.

[0050] Figure 3 The structure of a second voltage generator according to an embodiment of the present invention is schematically shown.

[0051] like Figure 3 As shown, the second voltage generator may include a first amplifier A1, a resistor string, and a multiplexer MUX.

[0052] The first amplifier A1 may include a first positive (+) input terminal, a first negative (-) input terminal and a first output terminal, wherein the first negative input terminal is connected to the first output terminal, and the first positive input terminal is used to receive and input a reference voltage V BG The first amplifier A1 forms a unit gain negative feedback, so that the reference voltage V BG With the output voltage V FB The resistor string consists of 2 T The resistors R are connected in series one after the other, and one end of the resistor string is connected to the first output terminal, that is, the output voltage V FB , the other end of the resistor string is connected to a fixed ground potential, and T is a positive integer greater than or equal to 1. Each resistor can be the same. The multiplexer MUX can include 2 T There are selection terminals, each of which is connected to a node of the corresponding resistor R close to the first output terminal, that is, a node far away from the fixed ground potential. The number of nodes is also 2. T The second digital code T bit can also be expressed as , is set to act on the multiplexer MUX, by selecting 2 T The voltages at different nodes of the resistors are used as the second voltage V2. The second voltage V2 can be obtained by the following formula:

[0053]

[0054] Figure 4 The structure of a multiplexer according to an embodiment of the present invention is schematically shown.

[0055] like Figure 4 As shown, in some embodiments, the circuit structure of the multiplexer MUX may have T stages, each stage having 2 parallel T Paths controlled by switches, 2 at each level T input and 2 from the previous level T The jth level can be connected by the digital code W <j>, that is, the second digital code T bit controls the switch, which consists of 2 from top to bottom. j-1 W <j>Control switch and 2 j-1 ~W <j>The controlled switching cycles are arranged alternately, so as to achieve the output of different second voltages V2. j is a positive integer.

[0056] Figure 5 The structure of an on-chip bias driving system according to yet another embodiment of the present invention is schematically shown.

[0057] like Figure 5 As shown, based on the above embodiment, the on-chip bias driving system may further include two second amplifiers A2 and A3. The second amplifiers A2 and A3 are connected to the first voltage generator and the second voltage generator, respectively, and the second amplifiers A2 and A3 are configured to amplify the first voltage V1 and the second voltage V2 with a gain of 1 and then input them to the first transistor and the second transistor, respectively. Figure 5 As shown, the output of the second amplifier A2, A3 can be connected to the inverting input (-) terminal, so that the amplification gain of the output to the positive input (+) of the amplifier is 1. Then, the first voltage V1 generated by the first voltage generator or the second voltage V2 generated by the second voltage generator is amplified to the output voltage V with a gain of 1. B1 Or output voltage V B2 , used to drive the bias bus shared by the pixel array.

[0058] Figure 6 The structure of a second amplifier according to an embodiment of the present invention is schematically shown.

[0059] like Figure 6 As shown, in this embodiment, the second amplifier A2 may be a three-stage amplifier. For example, it may include: a first transconductance amplifier g m1 , the second transconductance amplifier g m2 , the third transconductance amplifier g m3 , the fourth transconductance amplifier g mt , the fifth transconductance amplifier g mf and two capacitors C m1 , C m2 The first transconductance amplifier g m1 The input of the second amplifier A2 is the input of the first transconductance amplifier g m1 The output of the second transconductance amplifier g m2 The input of the fifth transconductance amplifier g mf The input connection of the second transconductance amplifier g m2 The output of the third transconductance amplifier g m3 The input of the fourth transconductance amplifier g mt The output of the third transconductance amplifier g m3 The output of the fifth transconductance amplifier g mf Output connection. First capacitor C m1 One end of the first transconductance amplifier g m1 The output of the first capacitor C m1 The other end is connected to the third transconductance amplifier g m3 The output of the second capacitor C m2 One end of the fourth transconductance amplifier g mt The second capacitor C m2 The other end is connected to the third transconductance amplifier g m3 The output of the third transconductance amplifier g m3 The output of is the output of the second amplifier A2. In this embodiment, the second amplifier A2 adopts transconductance feedback compensation, which can reduce the number and power consumption of the last stage transistors in the case of high load capacitance.

[0060] The structure of the second amplifier A3 may be the same as that of the second amplifier A2, and will not be described in detail herein.

[0061] Figure 7 The structure of a second amplifier according to another embodiment of the present invention is schematically shown.

[0062] like Figure 7 As shown, it can be Figure 6 The circuit of the second amplifier A2 is further refined. Compared with the traditional three-stage amplifier structure of nested Miller compensation, a reverse transconductance amplifier is inserted between the second and third stages of the amplifier in this embodiment, thereby increasing the overall equivalent transconductance of the third stage by a fixed coefficient, so that the third transconductance amplifier g m3 The requirement reduces the corresponding coefficient, thereby greatly reducing the power consumption and hardware overhead of the second amplifier A2.

[0063] As shown in FIG. 7 , the input stage of the second amplifier A2 can adopt a transconductance enhancement complementary structure, that is, through the transistor M 77 、M 86 、M 93 、M 94 、M 101 、M 102 、M 80 、M 89 The current mirror formed by the circuit makes the tail current of the lower N transistor differential input double when the input common mode is too high and the upper P transistor differential input tube is cut off; or makes the tail current of the upper P transistor differential input double when the input common mode is too low and the lower N transistor differential input tube is cut off. In this way, the first stage amplifier g is kept within a relatively wide input common mode range. m1 The relative constancy of the input voltage increases the bandwidth when the input voltage is too high or too low. Figure 7 As shown, the bias circuit generates all bias signals of the amplifier through two input reference currents to ensure that the circuit nodes are at a suitable DC potential.

[0064] See also Figure 5 The on-chip bias drive system may further include: a bandgap reference source and a reference current generator. The bandgap reference source is configured to generate a reference voltage and a reference current; the reference current generator is configured to replicate the reference current to obtain at least one reference current.

[0065] For example, a bandgap reference source can generate a reference voltage and a reference current based on the bandgap voltage characteristics of silicon materials by using a plurality of bipolar transistors of different sizes, a current mirror network, and a resistor network.

[0066] Figure 8 The structure of a bandgap reference source according to an embodiment of the present invention is schematically shown.

[0067] like Figure 8 As shown, well-matched transistors pnp1, pnp2, pnp3, pnp4, pnp5 and amplifier A can be used. v The virtual short characteristic generates a voltage with a positive temperature coefficient across resistor R1. After the current mirror copies the current flowing through R1 to the branch where resistor R2 is located, a voltage with a positive temperature coefficient is generated across resistor R2. This voltage is superimposed on the collector voltage of transistor pnp5 with a negative temperature coefficient to obtain an output reference voltage V with a very low temperature coefficient. BG At the same time, the current of resistor R1 is copied into two output reference currents I PTAT1 and I PTAT2 .

[0068] Fig. 9 The structure of a reference current generator according to an embodiment of the present invention is schematically shown.

[0069] like Fig. 9 As shown, the reference current I PTAT1 and I PTAT2 Generates a cascode current mirror (by transistor M 42 、M 53 、M 43 、M 52 、M 44 、M 51 、M 45 、M 50 、M 46 、M 49 、M 47 、M 48 The two bias voltages are composed of multiple reference currents I1, I2, ..., I E-1 ,I E E is the number of reference currents generated. The reference currents I1 and I2 can be used as reference currents of the first voltage generator.

[0070] It should be noted that, among the multiple reference currents generated by the reference current generator, a part can be used as the source reference current of the first amplifier A1 in the first voltage generator, and a part can also be used as the source reference current of the second amplifiers A2 and A3 in the second voltage generator. Inputting the source reference current into the amplifier is a general operation in the amplifier circuit, so it will not be described in detail.

[0071] So far, the present embodiment has been described in detail in conjunction with the accompanying drawings. Based on the above description, those skilled in the art should have a clear understanding of an on-chip bias drive system for a high-resolution pixel array proposed by the present invention. According to the above-mentioned multiple embodiments, the on-chip bias drive system for a high-resolution pixel array proposed by the present invention reduces the volume, power consumption and noise of the system, achieves a microsecond transient response speed under large load capacitance conditions brought by a high-resolution pixel array with lower power consumption, and the voltage generated by the digital code configuration is conducive to integration with the digital processing function module to realize an integrated intelligent system.

[0072] It should be noted that the implementation methods not shown or described in the drawings or the text of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of various elements and methods are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them, such as: bandgap reference source, amplifier, multiplexer, etc.

[0073] It should also be noted that the present invention may provide demonstrations of parameters containing specific values, but these parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint. Directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only referenced to the directions of the accompanying drawings and are not intended to limit the scope of protection of the present invention.

[0074] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.< / j> < / j> < / j> < / k> < / k> < / k> < / k>

Claims

1. An on-chip bias drive system for a sensor pixel array, characterized in that: include: A pixel array, comprising a plurality of pixel units, each of the pixel units comprising a first transistor and a second transistor; A first voltage generator is configured to generate a first voltage according to a reference current, wherein the first voltage is applied to a gate of each of the first transistors, and the magnitude of the first voltage is controlled by a first digital code to control the magnitude of the current of the first transistor; The first voltage generator includes: a current mirror configured to copy the reference current and transmit it to the output electrode of the current mirror; K switches, each of which includes a first end and a second end, each of which is connected to the output electrode, and K is a positive integer greater than or equal to 1; K+1 N-type transistors, each of which has a source connected to a fixed ground potential, a gate connected to the output electrode, a drain of a first N-type transistor of the K+1 N-type transistors connected to the output electrode, and drains of the remaining K N-type transistors are respectively connected to the corresponding second ends; wherein the first digital code is set to act on the K switches, and by controlling the on and off of each switch, the drain of the current mirror generates the first voltage; The second voltage generator is configured to generate a second voltage according to a reference voltage, the second voltage is loaded to the gate of each second transistor, and the magnitude of the second voltage is controlled by a second digital code, so that the second transistor controls the DC operating point in the pixel unit or generates a comparison voltage inside the pixel unit; the second voltage generator includes: a first amplifier, including a first positive input terminal, a first reverse input terminal and a first output terminal, the first reverse input terminal is connected to the first output terminal, and the first positive input terminal is used to receive and input the reference voltage; a resistor string, consisting of 2 T resistors are connected in series in sequence, one end of the resistor string is connected to the first output end, the other end of the resistor string is connected to a fixed ground potential, and T is a positive integer greater than or equal to 1; a multiplexer includes 2 T selection terminals, each of which is connected to a node of the corresponding resistor close to the first output terminal; wherein the second digital code is set to act on the multiplexer, by selecting the 2 T The voltages at different nodes of the resistors are used as the second voltage.

2. The on-chip bias driving system according to claim 1, characterized in that: The ratio of the width-to-length ratios of the remaining K N-type transistors is a geometric progression of 2, and the width-to-length ratio of the first N-type transistor is equal to the minimum width-to-length ratio of the remaining K N-type transistors.

3. The on-chip bias driving system according to claim 1, characterized in that: The width-to-length ratio of the first transistor is an integer multiple of that of the first N-type transistor.

4. The on-chip bias driving system according to claim 1, characterized in that: The current mirror comprises: a first P-type transistor, wherein a drain of the first P-type transistor flows the reference current; a second P-type transistor, wherein a drain of the second P-type transistor flows the reference current; a third P-type transistor, wherein a drain of the third P-type transistor is connected to a source of the first P-type transistor, a gate of the third P-type transistor is connected to a gate of the first P-type transistor, and a source of the third P-type transistor is connected to a fixed power supply potential; a fourth P-type transistor, wherein a drain of the fourth P-type transistor is connected to a source of the second P-type transistor, a gate of the fourth P-type transistor is connected to a drain of the second P-type transistor, and a source of the fourth P-type transistor is connected to a fixed power supply potential; a fifth P-type transistor, wherein a gate of the fifth P-type transistor is connected to a gate of the fourth P-type transistor, and a source of the fifth P-type transistor is connected to a fixed power supply potential; a sixth P-type transistor, wherein a source of the sixth P-type transistor is connected to a drain of the fifth P-type transistor, and a gate of the sixth P-type transistor is connected to a gate of the first P-type transistor and a gate of the second P-type transistor, The drain of the sixth P-type transistor is connected to the gate of each of the N-type transistors and each of the first ends as the output electrode of the current mirror.

5. The on-chip bias driving system according to claim 4, characterized in that: The second P-type transistor and the first P-type transistor have the same width-to-length ratio, and the width-to-length ratio of the first P-type transistor is an integer multiple of the third P-type transistor; the width-to-length ratio of the fifth P-type transistor is an integer multiple of the fourth P-type transistor, and the width-to-length ratio of the sixth P-type transistor is an integer multiple of the second P-type transistor.

6. The on-chip bias driving system according to claim 1, characterized in that: Also includes: Two second amplifiers are connected to the first voltage generator and the second voltage generator respectively, and the second amplifiers are configured to amplify the first voltage and the second voltage with a gain of 1 and then input them to the first transistor and the second transistor respectively.

7. The on-chip bias driving system according to claim 6, characterized in that: The second amplifier comprises: a first transconductance amplifier, a second transconductance amplifier, a third transconductance amplifier, a fourth transconductance amplifier, and a fifth transconductance amplifier, wherein the input of the first transconductance amplifier is the input of the second amplifier, the output of the first transconductance amplifier is connected to the input of the second transconductance amplifier and the input of the fifth transconductance amplifier, the output of the second transconductance amplifier is connected to the input of the third transconductance amplifier and the output of the fourth transconductance amplifier, and the output of the third transconductance amplifier is connected to the output of the fifth transconductance amplifier; A first capacitor, one end of the first capacitor is connected to the output of the first transconductance amplifier, and the other end of the first capacitor is connected to the output of the third transconductance amplifier; A second capacitor, one end of the second capacitor is connected to the input of the fourth transconductance amplifier, the other end of the second capacitor is connected to the output of the third transconductance amplifier, and the output of the third transconductance amplifier is the output of the second amplifier.

8. The on-chip bias driving system according to claim 1, characterized in that: Also includes: A bandgap reference source, configured to generate the reference voltage and reference current; The reference current generator is configured to replicate the reference current to obtain at least one reference current.

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