Method of manufacturing a semiconductor device
By using wet cleaning processes, especially acid and alkali cleaning steps, in semiconductor device fabrication, the overlay deviation problem caused by wafer exposure defects in metal zero-layer lithography was solved, improving device yield and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2024-10-31
- Publication Date
- 2026-05-22
AI Technical Summary
In the metal-zero layer photolithography process of field-effect transistors, a large number of exposure defects appear on the wafer, resulting in large overlay deviations, affecting the etching window of the metal-zero layer vias, increasing the risk of etching errors in the vias, and reducing the yield and reliability of the devices.
Wet cleaning process is used to remove the natural oxide layer on the surface of the semiconductor structure, including acid washing and alkaline washing steps. Hydrofluoric acid solution is used to clean the front side and deionized water is used to clean the back side. The back dielectric layer is kept away from hydrofluoric acid to prevent damage to the back side. Cleaning is performed by stacking multiple wafers to reduce contamination and damage.
It improves the overlay accuracy of metal zero-layer via etching, increases device yield and reliability, avoids wafer damage and contamination caused by exposure defects, and enhances the stability of subsequent processes.
Smart Images
Figure CN119421441B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for preparing a semiconductor device. Background Technology
[0002] In the fabrication process of the metal zero layer in the middle section of the field-effect transistor, a large number of exposure defects were found on the wafer during the metal zero layer photolithography process. Exposure defects will seriously affect the overlay of the metal zero layer, resulting in a large overlay deviation error, which in turn leads to a smaller etching window for the metal zero layer vias and a higher risk of etching errors in the vias.
[0003] During yield diagnosis, HVS (High Voltage Stress) failure caused by overlay misalignment of the metal zero layer was also detected. The large overlay misalignment error and the numerous exposure defects observed in the electron microscope images matched perfectly, both being in-plane MAP (patterns). This confirmed that exposure defects suffered by the wafer in the metal zero layer lithography process severely impact the overlay of the metal zero layer vias. The inventors found that over three consecutive months, the total number of exposure defects on the wafers in the metal zero layer lithography process reached as high as 1564 or more, which had a significant negative impact on the yield and reliability of field-effect transistor devices. Summary of the Invention
[0004] This application provides a method for fabricating semiconductor devices, which can solve the problem that exposure defects suffered by the wafer in the metal zero-layer photolithography process affect the overlay of metal zero-layer vias, thereby affecting the yield and reliability of the devices.
[0005] This application provides a method for fabricating a semiconductor device, including:
[0006] A substrate is provided, wherein a gate structure and a first hard mask layer are formed on the front side of the substrate, the first hard mask layer covering the gate structure and the front side of the substrate; a source region and a drain region are formed in the substrate, the source region and the drain region being located on opposite sides of the gate structure, and a back dielectric layer is formed on the back side of the semiconductor structure.
[0007] A first photoresist layer is coated on the first hard mask layer;
[0008] A gate ionization window pattern is defined on the first photoresist layer using a photolithography process to form a patterned first photoresist layer.
[0009] Using a patterned first photoresist layer as a mask, the first hard mask layer is etched up to the top of the gate structure;
[0010] The gate structure is subjected to an ion implantation process;
[0011] Remove the patterned first photoresist layer;
[0012] Remove the first hard mask layer;
[0013] A wet cleaning process is used to clean the semiconductor structure after the removal of the first hard mask layer in order to remove the natural oxide layer on the surface of the semiconductor structure. The wet cleaning process includes an acid cleaning step and an alkaline cleaning step. In the acid cleaning step, hydrofluoric acid solution is used to clean the front side of the semiconductor structure and deionized water is used to clean the back side of the semiconductor structure.
[0014] An interlayer dielectric layer is formed, which covers the front side of the gate structure and the substrate.
[0015] Optionally, in the method for fabricating the semiconductor device, the step of using a wet cleaning process to clean the semiconductor structure after removing the first hard mask layer to remove the native oxide layer on the surface of the semiconductor structure includes:
[0016] A pickling process is performed, in which hydrofluoric acid solution is used to clean the front side of the semiconductor structure for 150 seconds, and deionized water is used to clean the back side of the semiconductor structure for 150 seconds.
[0017] An alkaline cleaning process is performed, in which the front side of the semiconductor structure is cleaned with ammonia water while the back side of the semiconductor structure is purged with nitrogen gas.
[0018] Optionally, in the method for fabricating the semiconductor device, the step of performing the alkaline washing process includes:
[0019] The front side of the semiconductor structure was cleaned with ammonia for the first time, while the back side of the semiconductor structure was purged with nitrogen for 70 seconds.
[0020] The semiconductor structure was dried using isopropanol;
[0021] The front side of the semiconductor structure was cleaned a second time with ammonia, while the back side of the semiconductor structure was purged with nitrogen for 40 seconds.
[0022] The semiconductor structure was dried using isopropanol;
[0023] The front side of the semiconductor structure was cleaned with ammonia for the third time, while the back side of the semiconductor structure was purged with nitrogen for 40 seconds.
[0024] The semiconductor structure was dried using isopropanol.
[0025] Optionally, in the method for preparing the semiconductor device, in the acid washing step, the ratio of HF to water in the hydrofluoric acid solution is 1:200.
[0026] Optionally, in the method for fabricating the semiconductor device, after forming the interlayer dielectric layer, the method further includes:
[0027] A second hard mask layer is formed, which covers the interlayer dielectric layer;
[0028] A second photoresist layer is coated on the second hard mask layer;
[0029] Through a photolithography process, through-hole patterns are defined on the second photoresist layer to form a patterned second photoresist layer;
[0030] Using a patterned second photoresist layer as a mask, the second hard mask layer is etched to the top of the gate structure, and the second hard mask layer and the interlayer dielectric layer are etched to the surfaces of the source region and the drain region to form a plurality of vias;
[0031] The through-hole is filled with metallic material to form a metal zero layer;
[0032] Remove the patterned second photoresist layer;
[0033] Remove the second hard mask layer.
[0034] Optionally, in the method for fabricating the semiconductor device, hot sulfuric acid is used to remove the patterned first photoresist layer.
[0035] Optionally, in the method for fabricating the semiconductor device, the material of the first hard mask layer is silicon nitride.
[0036] Optionally, in the method for fabricating the semiconductor device, the material of the back dielectric layer is silicon nitride.
[0037] Optionally, in the method for fabricating the semiconductor device, the material of the second hard mask layer is silicon nitride.
[0038] The technical solution of this application has at least the following advantages:
[0039] After removing the patterned first photoresist layer used for ion implantation of the gate structure, this application employs a wet cleaning process to clean the semiconductor structure after the removal of the first hard mask layer, thereby removing the natural oxide layer on the surface of the semiconductor structure. The wet cleaning process includes an acid cleaning step and an alkaline cleaning step. In the acid cleaning step, hydrofluoric acid solution is used to clean the front side of the semiconductor structure, and deionized water is used to clean the back side. By using deionized water to clean the back side of the semiconductor structure, this application avoids the back dielectric layer of the substrate coming into contact with the hydrofluoric acid solution, thus preventing the back dielectric layer surface from becoming pitted and uneven. This avoids exposure defects in the subsequent photolithography process, improves the overlay accuracy of subsequent metal zero-layer via etching, and enhances the device yield and reliability.
[0040] Furthermore, in the acid cleaning and alkaline cleaning processes of this application, multiple semiconductor structures (wafers) are stacked and maintained at a certain interval, and the acid cleaning and alkaline cleaning processes are performed together in the process cavity. In the acid cleaning process, hydrofluoric acid solution is used to clean the front side of the semiconductor structure and deionized water is used to clean the back side of the semiconductor structure. This can prevent the back dielectric layer on the back side of the substrate from contacting the hydrofluoric acid solution, thereby preventing the back dielectric layer on the back side of the substrate from peeling off and falling down to contaminate and / or damage the front side of the underlying wafer.
[0041] In summary, this application uses deionized water to clean the back side of the semiconductor structure, which can remove impurities (such as polymers) on the back side of the wafer without damaging the back dielectric layer. This can improve the exposure defects of the current wafer and reduce the contamination and / or damage defects on the front side of the lower wafer caused by the corrosion and fall-off of the back dielectric layer of the upper wafer. Attached Figure Description
[0042] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0043] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;
[0044] Figures 2-10 This is a schematic diagram of the semiconductor structure in each process step of the semiconductor device fabrication according to an embodiment of the present invention;
[0045] The reference numerals in the attached figures are explained as follows:
[0046] 10-Substrate, 11-Source region, 12-Drain region, 21-Gate oxide layer, 22-Gate, 23-Sidewall, 31-First hard mask layer, 40-Back dielectric layer, 51-First photoresist layer, 52-Patterned first photoresist layer, 53-Gate ionization window, 60-Interlayer dielectric layer, 71-Metal zero layer one, 72-Metal zero layer two, 73-Metal zero layer three. Detailed Implementation
[0047] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0048] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0049] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0050] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0051] This application provides a method for fabricating a semiconductor device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The method for fabricating the semiconductor device includes:
[0052] First, perform step S1: Refer to Figure 2 , Figure 2This is a schematic diagram of a semiconductor structure after the formation of a back dielectric layer and a first hard mask layer according to an embodiment of this application. A substrate 10 is provided, and a gate structure and a first hard mask layer 31 are formed on the front side of the substrate 10. The first hard mask layer 31 covers the gate structure and the front side of the substrate 10. A source region 11 and a drain region 12 are formed in the substrate 10. The source region 11 and the drain region 12 are respectively located on both sides of the gate structure. A back dielectric layer 40 is formed on the back side of the semiconductor structure.
[0053] In step S1, the formation of source region 11 and drain region 12 is a conventional device source and drain region ion implantation process. Specifically, in the process of forming source region 11 and drain region 12, a photoresist layer is usually used as a mask, and then the barrier layer at the top of the source region 11 and drain region 12 is opened by photolithography, etching and other processes. Then, ion implantation processes are performed on the substrates on both sides of the gate structure to form source region 11 and drain region 12 respectively. Finally, the photoresist layer and barrier layer are removed.
[0054] In this embodiment, the gate structure includes at least: a gate oxide layer 21, a gate 22, and sidewalls 23. The gate oxide layer 21 is located on the front side of the substrate 10, the gate 22 covers the gate oxide layer 21, and the sidewalls 23 are located on both sides of the gate 22.
[0055] In this embodiment, the sidewall 23 is a combination of a silicon oxide layer and a silicon nitride layer.
[0056] Preferably, the first hard mask layer 31 is made of silicon nitride.
[0057] In this embodiment, the material of the back dielectric layer 40 is silicon nitride.
[0058] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the first photoresist layer is coated on the first hard mask layer according to an embodiment of this application. The first photoresist layer 51 is coated on the first hard mask layer 31.
[0059] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of a patterned first photoresist layer according to an embodiment of this application. The gate ionization window 53 pattern is defined on the first photoresist layer 51 by photolithography to form a patterned first photoresist layer 52.
[0060] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5This is a schematic diagram of the semiconductor structure after etching the first hard mask layer to the top of the gate structure according to an embodiment of this application. The patterned first photoresist layer 52 is used as a mask to etch the first hard mask layer 31 to the top of the gate 22.
[0061] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of a semiconductor structure for performing an ion implantation process on the gate according to an embodiment of this application, wherein the gate 22 is subjected to an ion implantation process.
[0062] Further, step S6 is performed: the patterned first photoresist layer 52 is removed.
[0063] In this embodiment, hot sulfuric acid is used to remove the patterned first photoresist layer 52.
[0064] Next, step S7 is performed: the first hard mask layer 31 is removed.
[0065] In this embodiment, the first hard mask layer 31 can be removed using a dry etching process or a wet etching process.
[0066] Further, proceed to step S8: (Refer to...) Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of the semiconductor structure performing the pickling process according to an embodiment of this application. Figure 8 This is a schematic diagram of a semiconductor structure performing an alkaline cleaning process according to an embodiment of this application. The semiconductor structure after the removal of the first hard mask layer is cleaned using a wet cleaning process to remove the natural oxide layer on the surface of the semiconductor structure. The wet cleaning process includes an acid cleaning process and an alkaline cleaning process.
[0067] Preferably, the step of using a wet cleaning process to clean the semiconductor structure after removing the first hard mask layer, in order to remove the native oxide layer on the surface of the semiconductor structure, may specifically include:
[0068] Step S8.1: Reference Figure 7 A pickling process is performed, in which hydrofluoric acid solution is used to clean the front side of the semiconductor structure for 150 seconds, and deionized water is used to clean the back dielectric layer 40 on the back side of the semiconductor structure for 150 seconds.
[0069] Step S8.2: Reference Figure 8 An alkaline cleaning process is performed, in which the front side of the semiconductor structure is cleaned with ammonia water, while the back dielectric layer 40 on the back side of the semiconductor structure is purged with nitrogen gas.
[0070] Preferably, in the pickling process, the ratio of HF to water in the hydrofluoric acid solution is 1:200.
[0071] The process involves using hydrofluoric acid for pickling to remove the native oxide layer on the front side of the semiconductor structure. Furthermore, using deionized water to clean the back side of the semiconductor structure removes impurities (such as polymers) without damaging the back dielectric layer. During the pickling process, the hydrofluoric acid solution used to clean the front side of the semiconductor structure does not flow to the back side of the wafer. As the stage rotates at high speed, the hydrofluoric acid solution used to clean the front side of the wafer flies out from the edge of the front side and falls into a collection device.
[0072] Preferably, the steps of performing the alkaline washing process may specifically include:
[0073] Step S8.21: First, clean the front side of the semiconductor structure with ammonia water, and at the same time, blow the back dielectric layer 40 on the back side of the semiconductor structure with nitrogen gas for 70 seconds.
[0074] Step S8.22: Dry the semiconductor structure using isopropanol;
[0075] Step S8.23: Clean the front side of the semiconductor structure with ammonia for the second time, and simultaneously purge the back dielectric layer 40 on the back side of the semiconductor structure with nitrogen for 40 seconds.
[0076] Step S8.24: Dry the semiconductor structure using isopropanol;
[0077] Step S8.25: Clean the front side of the semiconductor structure with ammonia for the third time, and simultaneously purge the back dielectric layer 40 on the back side of the semiconductor structure with nitrogen for 40 seconds.
[0078] Step S8.26: Dry the semiconductor structure using isopropanol.
[0079] The process of cleaning the front side of the semiconductor structure with ammonia while simultaneously purging the back dielectric layer 40 on the back side with nitrogen can further remove impurities from the front side of the semiconductor structure. The cleaning principle of cleaning the front side of the semiconductor structure with ammonia and purging the back dielectric layer 40 with nitrogen can be based on Bernoulli's principle. During the nitrogen purging process, the ammonia used to clean the front side of the wafer will not flow to the back side. Instead, as the stage rotates at high speed, the ammonia used to clean the front side of the wafer flies out from the edge of the front side and falls into a collection device.
[0080] In the wet cleaning process of this application, multiple semiconductor structures (wafers) are stacked and maintained at a certain interval, and together they undergo acid cleaning and alkaline cleaning processes in the process cavity. The acid cleaning and alkaline cleaning processes are used to clean the semiconductor structure after the removal of the first hard mask layer, so as to remove the natural oxide layer on the surface of the semiconductor structure. In the acid cleaning process, hydrofluoric acid solution is used to clean the front side of the semiconductor structure and deionized water is used to clean the back side of the semiconductor structure. By using deionized water to clean the back side of the semiconductor structure, this application can avoid the back dielectric layer of the substrate from contacting the hydrofluoric acid solution, thereby avoiding the pitting and unevenness of the back dielectric layer surface after washing. This avoids the exposure defects of the wafer in the subsequent photolithography process, improves the overlay accuracy of the subsequent metal zero layer via etching, and improves the yield and reliability of the device.
[0081] Furthermore, in the pickling process, using hydrofluoric acid solution to clean the front side of the semiconductor structure and using deionized water to clean the back side of the semiconductor structure can prevent the back dielectric layer on the back side of the substrate from coming into contact with the hydrofluoric acid solution. This can prevent the back dielectric layer on the back side of the substrate from peeling off and falling down to contaminate and / or damage the front side of the lower wafer. In other words, it avoids the situation where the front side of multiple lower wafers in a stacked wafer is contaminated and / or damaged by the back dielectric layer falling from the upper wafer, further improving the yield and reliability of the device.
[0082] Finally, proceed to step S9: (Refer to...) Figure 9 , Figure 9 This is a schematic diagram of a semiconductor structure forming an interlayer dielectric layer according to an embodiment of this application. An interlayer dielectric layer 60 is formed, which covers the front side of the gate structure and the substrate 10.
[0083] Further reference Figure 10 , Figure 10 This is a schematic diagram of a semiconductor structure forming a metal zero layer according to an embodiment of this application. After forming the interlayer dielectric layer 60, the method for fabricating the semiconductor device may further include:
[0084] Step S10: Form a second hard mask layer (not shown), the second hard mask layer covering the interlayer dielectric layer;
[0085] Step S11: Coat a second photoresist layer (not shown) on the second hard mask layer;
[0086] Step S12: Define via patterns on the second photoresist layer using photolithography to form a patterned second photoresist layer (not shown);
[0087] Step S13: Using the patterned second photoresist layer as a mask, etch the second hard mask layer to the top of the gate structure, and etch the second hard mask layer and the interlayer dielectric layer to the surface of the source region and the drain region to form a plurality of vias (not shown);
[0088] Step S14: Reference Figure 10 Metal material is filled into the via to form metal zero layer 1 71, metal zero layer 2 72 and metal zero layer 3 73; wherein, metal zero layer 1 71 penetrates the interlayer dielectric layer 60 and contacts the source region 11, metal zero layer 2 72 penetrates the interlayer dielectric layer 60 and contacts the drain region 12, and metal zero layer 3 73 penetrates the interlayer dielectric layer 60 and contacts the gate 22.
[0089] Step S15: Remove the patterned second photoresist layer (not shown);
[0090] Step S16: Remove the second hard mask layer (not shown).
[0091] In this embodiment, the material of the second hard mask layer can be silicon nitride.
[0092] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, wherein a gate structure and a first hard mask layer are formed on the front side of the substrate, and the first hard mask layer covers the gate structure and the front side of the substrate; An active region and a drain region are formed in the substrate, the active region and the drain region are respectively located on both sides of the gate structure, and a back dielectric layer is formed on the back side of the semiconductor structure; A first photoresist layer is coated on the first hard mask layer; A gate ionization window pattern is defined on the first photoresist layer using a photolithography process to form a patterned first photoresist layer. Using a patterned first photoresist layer as a mask, the first hard mask layer is etched up to the top of the gate structure; The gate structure is subjected to an ion implantation process; Remove the patterned first photoresist layer; Remove the first hard mask layer; A wet cleaning process is used to clean the semiconductor structure after the removal of the first hard mask layer in order to remove the natural oxide layer on the surface of the semiconductor structure. The wet cleaning process includes an acid cleaning step and an alkaline cleaning step. In the acid cleaning step, hydrofluoric acid solution is used to clean the front side of the semiconductor structure and deionized water is used to clean the back side of the semiconductor structure. An interlayer dielectric layer is formed, which covers the front side of the gate structure and the substrate.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of cleaning the semiconductor structure after removing the first hard mask layer using a wet cleaning process to remove the native oxide layer on the surface of the semiconductor structure includes: A pickling process is performed, in which hydrofluoric acid solution is used to clean the front side of the semiconductor structure for 150 seconds, and deionized water is used to clean the back side of the semiconductor structure for 150 seconds. An alkaline cleaning process is performed, in which the front side of the semiconductor structure is cleaned with ammonia water while the back side of the semiconductor structure is purged with nitrogen gas.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The steps for performing the alkaline washing process include: The front side of the semiconductor structure was cleaned with ammonia for the first time, while the back side of the semiconductor structure was purged with nitrogen for 70 seconds. The semiconductor structure was dried using isopropanol; The front side of the semiconductor structure was cleaned a second time with ammonia, while the back side of the semiconductor structure was purged with nitrogen for 40 seconds. The semiconductor structure was dried using isopropanol; The front side of the semiconductor structure was cleaned with ammonia for the third time, while the back side of the semiconductor structure was purged with nitrogen for 40 seconds. The semiconductor structure was dried using isopropanol.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, In the pickling process, the ratio of HF to water in the hydrofluoric acid solution is 1:
200.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the interlayer dielectric layer, the method for fabricating the semiconductor device further includes: A second hard mask layer is formed, which covers the interlayer dielectric layer; A second photoresist layer is coated on the second hard mask layer; Through a photolithography process, through-hole patterns are defined on the second photoresist layer to form a patterned second photoresist layer; Using a patterned second photoresist layer as a mask, the second hard mask layer is etched to the top of the gate structure, and the second hard mask layer and the interlayer dielectric layer are etched to the surfaces of the source region and the drain region to form a plurality of vias; The through-hole is filled with metallic material to form a metal zero layer; Remove the patterned second photoresist layer; Remove the second hard mask layer.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The patterned first photoresist layer was removed using hot sulfuric acid.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first hard mask layer is made of silicon nitride.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the back dielectric layer is silicon nitride.
9. The method for fabricating a semiconductor device according to claim 5, characterized in that, The material of the second hard mask layer is silicon nitride.