Semiconductor structure and method of forming the same

Abstract

A semiconductor structure according to the present disclosure includes a substrate; a through substrate via (TSV) unit disposed over the substrate; and a TSV extending through the TSV cell and the substrate. The TSV cell includes a guard ring structure extending around a perimeter of the TSV cell and a buffer surrounded by the guard ring structure. The buffer includes a first dummy transistor and a second dummy transistor. Each of the first dummy transistors includes two first type epitaxial features, a first plurality of nanostructures extending between the two first type epitaxial features, and a first isolation gate structure wrapped over the first plurality of nanostructures. Each of the second dummy transistors includes two second type epitaxial features, a second plurality of nanostructures extending between the two first type epitaxial features, and a second isolation gate structure wrapped over the second plurality of nanostructures. The embodiment of the invention also provides a method for forming the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming semiconductor structures. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Through silicon vias or through substrate vias (TSVs) have been employed in three-dimensional (3D) ICs to route electrical signals from one side of an IC substrate to the other side thereof. Typically, TSVs are formed by etching vertical via openings through a substrate and filling the via openings with a conductive material, such as copper. Summary of the invention

[0004] Some embodiments of the present disclosure provide a semiconductor structure comprising: a substrate; a through substrate via (TSV) unit disposed above the substrate; and a substrate through via extending through the substrate through via unit and the substrate, wherein the substrate through via unit comprises: a guard ring structure extending continuously around the periphery of the substrate through via unit, and a buffer zone surrounded by the guard ring structure, wherein the buffer zone comprises: a plurality of first pseudo-transistors, and a plurality of second pseudo-transistors, wherein each of the plurality of first pseudo-transistors comprises: two first type epitaxial components, a first plurality of nanostructures extending between the two first type epitaxial components, and a first isolation gate structure extending through the first plurality of nanostructures, wherein each of the plurality of second pseudo-transistors comprises: two second type epitaxial components, a second plurality of nanostructures extending between the two second type epitaxial components, and a second isolation gate structure extending through the second plurality of nanostructures.

[0005] Some other embodiments of the present disclosure provide a semiconductor structure, which includes: a substrate, including a first region and a second region; a plurality of n-type transistors and a plurality of p-type transistors, located in the first region; and a plurality of first-type pseudo-transistors and a plurality of second-type pseudo-transistors, located in the second region, wherein each of the plurality of n-type transistors includes: two n-type source / drain components, a first plurality of nanostructures, extending between the two n-type source / drain components, and a first gate structure, surrounding each of the first plurality of nanostructures, wherein each of the plurality of p-type transistors includes: two p-type source / a drain feature, a second plurality of nanostructures extending between the two p-type source / drain features, and a second gate structure surrounding each of the second plurality of nanostructures, wherein each of the plurality of first type pseudo-transistors comprises: two n-type epitaxial features, a third plurality of nanostructures extending between the two n-type epitaxial features, and a first dielectric gate structure extending through the third plurality of nanostructures, wherein each of the plurality of second type pseudo-transistors comprises: two p-type epitaxial features, a fourth plurality of nanostructures extending between the two p-type epitaxial features, and a second dielectric gate structure extending through the fourth plurality of nanostructures.

[0006] Another embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising: receiving an intermediate structure, the intermediate structure comprising: a substrate, comprising a first region and a second region, and a stack, located above the first region and the second region, the stack comprising a plurality of channel layers interlaced by a plurality of sacrificial layers; patterning portions of the stack and the substrate to form a first fin structure above the first region and a second fin structure above the second region; forming a first dummy gate stack above the channel region of the first fin structure, and forming a second dummy gate stack above the channel region of the second fin structure; etching the source / drain regions of the first fin structure and the second fin structure to form source / drain grooves; forming epitaxial components in the source / drain grooves; selectively removing a plurality of sacrificial layers in the channel regions of the first fin structure and the second fin structure to form a first channel component above the first region and a second channel component above the second region; selectively forming a gate structure to surround each of the first channel components; and selectively forming a dielectric gate structure to wrap around each of the second channel components. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, for clarity of discussion, the sizes of the various components may be arbitrarily increased or reduced.

[0008] Figure 1A schematic top view of an integrated circuit (IC) die including TSV cells and device regions according to various aspects of the present disclosure is shown.

[0009] Figure 2 Magnified partial cross-sectional views of TSV cells and device regions according to various aspects of the present disclosure are provided.

[0010] Figure 3 is a flow chart illustrating an embodiment of a method of forming a device structure and a buffer zone in a TSV cell according to various aspects of the present disclosure.

[0011] Figures 4 to 18 According to the experience of various aspects of this disclosure Figure 3 A partial cross-sectional view of a work-in-process (WIP) structure of the method of operation.

[0012] Figures 19 to 22 Exemplary embodiments of TSV cells according to various aspects of the present disclosure are shown.

[0013] Fig.23 A first IC package having TSV cells according to various aspects of the present disclosure is shown.

[0014] Fig.24 A second IC package having TSV cells according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different components of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0016] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] In addition, when "about," "approximately," or the like is used to describe a value or range of values, the term is intended to encompass values ​​within a reasonable range as understood by a person of ordinary skill in the art to take into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value, the value or range of values ​​encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers is known to a person of ordinary skill in the art to be + / - 15%. Depending on the context, the source / drain regions may refer to the source or drain individually or collectively.

[0018] Through silicon vias or through substrate vias (TSVs) have been developed to provide vertical interconnects extending through portions of substrates and interconnect structures to facilitate various device structures, such as CMOS image sensors (CIS), three-dimensional integrated circuits (3DICs), MEMS devices, radio frequency (RF) devices, wafer-on-wafer (WoW) devices, system-on-integrated circuit (SoIC) devices, etc. The term TSV in the present disclosure broadly covers through-hole structures that provide direct signal routing from the front side of the substrate and the back side of the substrate (or vice versa). During the formation of the TSV, water vapor may corrode the metal material in the area that accommodates the TSV. Protective structures such as guard rings and buffers have been developed to protect the TSV from water vapor during manufacturing. In addition, the guard ring can also provide an electrical barrier to protect nearby components from electrical interference from the current carried by the TSV. In addition to the guard ring, a buffer or enhanced buffer can be formed between the TSV and the guard ring to provide additional protection to prevent stress from the TSV from damaging the surrounding devices. The structure in the buffer and its formation have been studied to minimize the impact on the devices in the device area.

[0019] The present disclosure provides a TSV cell with a buffer zone, which includes epitaxial components similar to their corresponding components in the device region outside the TSV cell. The present disclosure also provides a method for forming a TSV cell. In an exemplary process, a work-in-process (WIP) structure including a TSV cell region and a device region is received. A fin structure including a plurality of first semiconductor layers interlaced by a plurality of second semiconductor layers is formed above the TSV cell region and the device region. A pseudo gate stack is formed above the channel region of the fin structure. A top gate spacer layer is deposited above the WIP structure (including above the pseudo gate stack). Subsequently, the source / drain region of the fin structure is etched. After partially etching the plurality of second semiconductor layers to form an internal spacer groove, an internal spacer layer is deposited and etched back to form an internal spacer component. A bottom epitaxial layer is deposited above the source / drain region of the TSV cell region. Then an n-type source / drain component and a p-type source / drain component are selectively formed above the n-type region and the p-type region. The pseudo gate stack is removed to expose the sidewall of the second semiconductor layer. After selectively removing the second semiconductor layer, the first semiconductor layer is released as a channel member. After releasing the channel member, the exemplary process is split into two branches to form a gate structure to surround the channel member in the device region and to form a dielectric gate structure to wrap over the channel member in the buffer region.

[0020] Figure 1 1 shows a schematic top view of an integrated circuit (IC) die 10 including TSV cells 11 and a device region 12 located above a substrate 202. Each TSV cell 11 includes a guard ring 14 extending continuously around a buffer region 15. The buffer region 15 is configured to receive a TSV 16. More specifically, when the TSV 16 is formed, the TSV 16 extends through the buffer region 15, as shown in FIG. Figure 1 To prevent stress associated with TSV 16, device region 12 is placed outside exclusion zone (KOZ) 20. The size of KOZ 20 is determined by the device structure in device region 12 and the size of TSV 16. As the name implies, TSV 16 extends through buffer zone 15 and continues through substrate 202. Figure 2 A partial cross-sectional view of the TSV unit 11 and the device region 12 is provided. The front-side interconnect structure 30 is disposed above the substrate 202, including above the TSV unit 11 and the device region 12. The guard ring 14 extending along the periphery of the buffer zone 15 may include a fin structure, a gate ring structure, and a contact ring structure located above the substrate. In addition, as shown in FIG. Figure 2 As shown, the guard ring 14 may also include a metal via tower extending through the front side interconnect structure 30. The TSV 16 extends completely through the substrate 202, the buffer region 15, and at least partially through the front side interconnect structure 30. The device region 12 is disposed outside the KOZ 20.

[0021] Figure 3 1 is a flow chart illustrating a method 100 for forming a device structure or a dummy device structure in a TSV cell 11 and a device region 12 on a substrate 202. Because different operations of the method 100 add different structural features to the substrate 202, the substrate 202 and the structure formed thereon may be collectively referred to as a work-in-progress (WIP) structure 200. The method 100 is merely an example and is not intended to limit the present disclosure to that explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Figures 4 to 22 Describing method 100, Figures 4 to 22 1 is a partial cross-sectional view of a WIP structure 200 at different manufacturing stages according to various embodiments of the method 100. Because the WIP structure 200 will be manufactured into a device structure, the WIP structure 200 may be referred to as a device structure 200 herein as the context requires. To avoid ambiguity, Figures 4 to 22 The X, Y and Z directions in FIG. 1 are perpendicular to each other. Throughout the present disclosure, similar reference numerals refer to similar components unless otherwise explicitly stated.

[0022] refer to Figure 3 and Figure 1 , the method 100 includes a frame 102, in which a substrate 202 is received. The substrate 202 includes a TSV cell 11 (or a TSV cell region 11) and a device region 12. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 202 may include various doping configurations known in the art, depending on the design requirements. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on the substrate 202. In some embodiments, an n-type dopant for forming an n-type well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on the substrate 202. In some embodiments, a p-type dopant for forming a p-type well may include boron (B) or gallium (Ga). Appropriate doping may be performed using ion implantation and / or diffusion processes of dopants. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. In addition, the substrate 202 may optionally include an epitaxial layer (epi layer), the substrate 202 may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement components. Figure 1 As shown, depending on the location of the TSV in the design, the substrate 202 may include a TSV cell region 11 and a device region 12. As described above, the device region 12 is set outside the exclusion zone relative to the boundary of the planned TSV. The TSV cell region 11 includes a guard ring 14, a buffer zone 15, and a TSV 16 (or a site of the TSV 16).

[0023] Still refer to Figure 3 and Figure 4 , the method 100 includes block 104, wherein the fin structure 210 is located above the buffer region 15 and the device region 12. Figure 4 As shown, each fin structure 210 includes a channel layer 208 interleaved with a sacrificial layer 206. Figure 4 Although the details are not explicitly shown in FIG. 2 , the fin structures 210 are patterned from a stack deposited on the substrate 202. The stack includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206. Each fin structure 210 is patterned from a portion of the stack and the substrate 202. Figure 4 As shown, each fin structure 210 includes a base fin 202B formed by a substrate 202. Figure 4 Although not explicitly shown, the fin structure 210 is similarly formed in the buffer region 15 and the device region 12. Similar sizes help maintain a uniform process environment when forming functional devices in the device region 12. The size of the front end of line (FEOL) structure in the guard ring 14 can be large compared to the structure in the buffer region 15 or the device region 12.

[0024] In some embodiments, the sacrificial layer 206 has a first semiconductor composition and the channel layer 208 has a second semiconductor composition. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layer 206 includes silicon germanium (SiGe) and the channel layer 208 includes silicon (Si). Figure 4 As shown, three (3) layers of sacrificial layers 206 and three (3) layers of channel layers 208 are arranged alternately, which is for illustrative purposes only and is not intended to limit the specific references in the claims. It is understood that any number of epitaxial layers can be formed in the stack. The number of layers depends on the number of channel components required for the device structure 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0025] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness, and all channel layers 208 may have a substantially uniform second thickness. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion thereof may serve as a channel member for a subsequently formed multi-gate device, and the thickness of each channel layer 208 is selected based on device performance considerations. The sacrificial layer 206 in the channel region may eventually be removed, and the sacrificial layer 206 is used to define the vertical distance (along the Z direction) between adjacent channel regions of the subsequently formed multi-gate device, and the thickness of each sacrificial layer 206 is selected based on device performance considerations.

[0026] The layers in the stack may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. As described above, in at least some examples, sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants (i.e., have a dopant content of from about 0 cm -3 To about 1x10 17 cm -3 extrinsic dopant concentration), wherein, for example, no intentional doping is performed during the epitaxial growth process of the stack.

[0027] In order to pattern the stack and the substrate 202 to form a fin structure, a hard mask layer may be deposited over the stack to form an etching mask. The hard mask layer may be a single layer or a multilayer. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer located above the pad oxide layer. The fin structure 210 may be patterned from a portion of the stack and the substrate 202 using a lithography process and an etching process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. As Figure 4 As shown, the etching process at box 104 forms a trench through the stack and a portion of the substrate 202. The trench defines a fin structure 210. In some embodiments, a double patterning or multiple patterning process can be used to define, for example, a fin structure having a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a material layer is formed above a substrate, and the material layer is patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the fin structure 210 can then be patterned by etching the stack using the remaining spacers or mandrels. As shown in FIG. Figure 3 As shown, the fin structure 210 together with the sacrificial layer 206 and the channel layer 208 therein extends vertically along the Z direction and longitudinally along the X direction.

[0028] The isolation component 204 is formed adjacent to the fin structure 210. In some embodiments, the isolation component 204 may be formed in a trench to isolate the fin structure 210 from an adjacent active area. The isolation component 204 may also be referred to as a shallow trench isolation (STI) component 204. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form the STI component 204. After being recessed, the fin structure 210 is elevated above the STI feature 204 .

[0029] refer to Figure 3 and Figure 4 The method 100 includes a block 106 in which a dummy gate stack 230 is formed above the channel region of the fin structure 210. In some embodiments, a gate replacement process (or a gate-last process) is used. In the gate replacement process, the dummy gate stack 230 (eg, Figure 4 and Fig.13 ) as a placeholder to go through various processes, and the dummy gate stack 230 will be removed and replaced by a functional gate structure. Other processes and configurations are possible. Figure 4 The fin structure 210 in the embodiment extends longitudinally and parallel to the Y direction, while the dummy gate stack 230 extends longitudinally and parallel to the X direction. Figure 4 In some embodiments shown, the dummy gate stack 230 is formed above the fin structure 210, and the fin structure 210 can be divided into a channel region located below the dummy gate stack 230 and a source / drain region not located below the dummy gate stack 230. In the embodiment shown, the fin structure 210 serves as an active region of an n-type device or a p-type device. The N-type source / drain region is denoted as NSD, and the p-type source / drain region is denoted as PSD. In addition, because Figure 4 The cross section in FIG. 1 is cut through the source / drain region of the fin structure 210 , so the dummy gate stack 230 is not on a plane, and the outline of the dummy gate stack 230 is shown with a dotted line.

[0030] The formation of the dummy gate stack 230 may include depositing the layers in the dummy gate stack 230 and patterning the layers. Fig.13 In the example shown, the pseudo gate stack 230 may include a pseudo dielectric layer and a pseudo electrode layer. For patterning purposes, the pseudo gate stack 230 may be covered by a first gate top hard mask layer 232 and a second gate top hard mask layer 234. These layers may be blanket deposited over the WIP structure 200. In some embodiments, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an oxygen plasma oxidation process, or other suitable processes may be used to deposit a pseudo dielectric layer on the fin structure 210. In some examples, the pseudo dielectric layer may include silicon oxide. Subsequently, a pseudo electrode layer may be deposited over the pseudo dielectric layer using a CVD process, an ALD process, or other suitable processes. In some examples, the pseudo electrode layer may include polysilicon (poli-Si). For patterning purposes, a first gate top hard mask layer 232 and a second gate top hard mask layer 234 may be deposited on the pseudo electrode layer using a CVD process, an ALD process, or other suitable processes. Then, the second gate top hard mask layer 234, the first gate top hard mask layer 232, the dummy electrode layer, and the dummy dielectric layer may be patterned to form the dummy gate stack 230. For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the first gate top hard mask layer 232 may include silicon oxide, and the second gate top hard mask layer 234 may include silicon nitride.

[0031] refer to Figure 3 and Figure 4 , the method 100 includes box 108, in which a top spacer layer 212 is deposited over the dummy gate stack 230. In some embodiments, the top spacer layer 212 is conformally deposited over the WIP structure 200, including being deposited over the top surface and sidewalls of the dummy gate stack 230. The term "conformally" may be used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The top spacer layer 212 may be a single layer or a multilayer. The top spacer layer 212 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. In some embodiments, the top spacer layer 212 may be deposited over the dummy gate stack 230 using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, an ALD process, or other suitable process. As Figure 4 As shown, at block 108 , a top spacer layer 212 is also conformally deposited over the n-type source / drain regions NSD and the p-type source / drain regions PSD of the fin structure 210 .

[0032] refer to Figure 3 and Figure 5 The method 100 includes block 110, where the source / drain region of the fin structure 210 is recessed to form a source / drain recess. Figure 5 As shown, the source / drain region (NSD or PSD) not covered by the dummy gate stack 230 is anisotropically etched by dry etching or a suitable etching process to form a source / drain trench 228. For example, the dry etching process may be performed with an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 and / or C 2 F 6 ), chlorine-containing gases (such as Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing gases (such as HBr and / or CHBr 3 ), iodine-containing gases, other suitable gases and / or plasmas, and / or combinations thereof. The source / drain regions (NSD or PSD) of the fin structure 210 are recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, the source / drain trenches 228 may extend below the stack into the substrate 202. Figure 5 As shown, the sacrificial layer 206 and the channel layer 208 in the source / drain region (NSD or PSD) are removed at block 110, thereby exposing the substrate 202 and the sidewalls of the sacrificial layer 206 and the channel layer 208 in the channel region. In the process of forming the source / drain recesses, the anisotropic dry etch at block 110 also removes the top-facing portion of the top spacer layer 212 and creates recesses in the STI features 204. Figure 5 In the embodiment of the present invention, the remaining portion of the top spacer layer 212 may remain on the WIP structure 200. Because the remaining portion of the top spacer layer 212 blocks the travel of the anisotropic etch, portions of the STI features 204 under the remaining portion of the top spacer layer 212 may remain after forming the source / drain recesses.

[0033] refer to Figure 3 and Figure 6, the method 100 includes block 112, where an inner spacer feature 214 is formed. Although not explicitly shown, the operations at block 112 may include selectively and partially removing the sacrificial layer 206 to form an inner spacer recess, depositing an inner spacer material over the WIP structure 200, and etching back the inner spacer material to form the inner spacer feature 214 in the inner spacer recess (e.g., Fig.13 20). The sacrificial layer 206 exposed to the source / drain trench 228 is selectively and partially recessed to form an inner spacer recess, while the top spacer layer 212, the exposed portion of the substrate 202, and the channel layer 208 are substantially unetched. In embodiments where the channel layer 208 is substantially composed of silicon (Si) and the sacrificial layer 206 is substantially composed of silicon germanium (SiGe), the selective recessing of the sacrificial layer 206 may be performed using a selective wet etching process or a selective dry etching process. The selective and partial recessing of the sacrificial layer 206 may include a SiGe oxidation process followed by removal of the SiGe oxide. In this embodiment, the SiGe oxidation process may include the use of ozone. In some other embodiments, the selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0034] See also Figure 6 , after forming the internal spacer recess, an internal spacer material 214 is deposited over the WIP structure 200 (including over the internal spacer recess). The internal spacer material 214 may include a metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly shown, the internal spacer material 214 may be a single layer or multiple layers. In some embodiments, the internal spacer material 214 may be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The internal spacer material 214 is deposited in the internal spacer recess and over the sidewalls of the channel layer 208 exposed in the source / drain trench 228. Reference Figure 7 , and then etching back the deposited inner spacer material 214 to remove the inner spacer material 214 from the sidewalls of the channel layer 208, thereby forming the inner spacer features 214. At block 112, the inner spacer material 214 may also be removed from the top surface and / or sidewalls of the top spacer layer 212. In some embodiments, the etching back operation performed at block 112 may include using hydrogen fluoride (HF), fluorine gas (F 2 ), hydrogen (H 2 ), ammonia (NH 3), nitrogen trifluoride (NF 3 ) or other fluorine-based etchants. Fig.13 As shown, each inner spacer component 214 is in direct contact with the recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208. That is, the inner spacer components 214 are interleaved with the channel layers 208.

[0035] refer to Figure 3 and Figure 7 , the method 100 includes a frame 114, in which a bottom epitaxial layer 216 is deposited over the source / drain regions in the buffer region 15 and the device region 12. In some embodiments, the bottom epitaxial layer 216 includes an undoped semiconductor layer, such as an undoped silicon (Si) layer, an undoped silicon germanium (SiGe) layer, or an undoped germanium (Ge) layer. In one embodiment, the bottom epitaxial layer 216 includes an undoped silicon layer. As used herein, an undoped semiconductor layer refers to a semiconductor layer that is not intentionally doped. In an exemplary process, the bottom epitaxial layer 216 is epitaxially deposited over the WIP structure 200 using an MBE, a VPE process, and / or other suitable epitaxial growth process. Due to the crystal orientation, the bottom epitaxial layer 216 deposited on the exposed top surface of the substrate 202 has fewer defects. This allows the bottom epitaxial layer 216 to be selectively removed from surfaces other than the exposed top surface of the substrate 202.

[0036] refer to Figure 3 and Figures 8 to 13 The method 100 includes a block 116 in which a p-type source / drain feature 220P and an n-type source / drain feature 220N are formed. The operations in block 116 may include selectively depositing a first pattern film 218 (eg, Figure 8 ), depositing a p-type source / drain feature 220P (as shown) above the p-type source / drain region PSD Fig. 9 ), selectively depositing a second pattern film 222 (as shown) on the p-type source / drain feature 220P Fig.10 ), depositing n-type source / drain features 220N (as shown) above the n-type source / drain regions NSD Fig.11 ), remove the second pattern film 222 (as shown Fig.12 shown).

[0037] refer to Figure 8When the first pattern film 218 is deposited over the n-type source / drain region NSD, a photolithography process may be used to cover the p-type source / drain region PSD with a patterned photoresist. In some examples, the first pattern film 218 may include aluminum oxide, which allows it to be selectively removed without significantly damaging structures formed with silicon oxide, silicon nitride, or semiconductor materials. In the case where the first pattern film 218 covers the n-type source / drain region NSD, the p-type source / drain feature 220P is selectively deposited over the bottom epitaxial layer 216 in the p-type source / drain region PSD, as shown in FIG. Fig. 9 As shown. The p-type source / drain feature 220P may include silicon germanium (SiGe) and a p-type dopant, such as boron (B). Suitable epitaxial processes for the p-type source / drain feature 220P include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. After forming the p-type source / drain feature 220P, the first pattern film 218 may be removed from the n-type source / drain region NSD.

[0038] refer to Fig.10 After removing the first pattern film 218, a second pattern film 222 is selectively formed to cover the p-type source / drain region PSD, including the p-type source / drain feature 220P formed thereon. In some examples, the second pattern film 222 may include aluminum oxide, which allows it to be selectively removed without significantly damaging structures formed with silicon oxide, silicon nitride, or semiconductor materials. In the case where the second pattern film 222 covers the p-type source / drain region PSD, an n-type source / drain feature 220N is selectively deposited over the bottom epitaxial layer 216 in the n-type source / drain region NSD, as shown in FIG. Fig.11 As shown. The n-type source / drain feature 220N may include silicon (Si) and an n-type dopant, such as phosphorus (P) or arsenic (As). Suitable epitaxial processes for the n-type source / drain feature 220N include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. After forming the n-type source / drain feature 220N, the second pattern film 222 may be removed from the p-type source / drain region PSD, as shown. Fig.12 shown.

[0039] In some embodiments, an annealing process may be performed to anneal the p-type source / drain component 220P and the n-type source / drain component 220N. The annealing process may include a rapid thermal annealing (RTA) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. In some examples, the annealing process may include a peak annealing temperature between about 900°C and about 1000°C. In these embodiments, the peak annealing temperature may be maintained for a duration in seconds or microseconds. Throughout the annealing process, a desired electron distribution of a dopant (such as a p-type dopant boron (B) or an n-type dopant phosphorus (P)) in a semiconductor body (such as silicon (Si) or silicon germanium (SiGe)) may be obtained. The annealing process may generate vacancies that promote the movement of p-type dopants from interstitial positions to alternative lattice positions, and reduce damage or defects in the lattice of the semiconductor body.

[0040] Fig.13 A Y-direction cross-sectional view across the n-type device region N and the p-type device region P is provided. After the operation at box 116, each p-type source / drain component 220P is sandwiched between two p-type channel regions PC. Each p-type channel region PC includes a channel layer 208 interleaved by a sacrificial layer 206 and an internal spacer component 214. Similarly, each n-type source / drain component 220N is sandwiched between two n-type channel regions NC. Each n-type channel region NC includes a channel layer 208 interleaved by a sacrificial layer 206 and an internal spacer component 214. Note that the same precursor structure is also formed in the buffer region 15. As will be described in further detail below, the buffer region 15 may include corresponding components of the p-type source / drain component 220P and the n-type source / drain component 220N. Because these corresponding components in the buffer region 15 do not function as a source and a drain, they may be referred to as n-type epitaxial components 220N or p-type epitaxial components 220P.

[0041] refer to Figure 3 , Fig.14 and Fig.15 , the method 100 includes block 118, where the dummy gate stack 230 is removed. The operation at block 118 may include depositing a contact etch stop layer (CESL) 242 (eg, Fig.14 ), depositing an interlayer dielectric layer (ILD) 244 (as shown) on the CESL 242 Fig.14 ), and removing the dummy gate stack 230 (as shown Fig.15 Now refer to Fig.15, before depositing the ILD layer 244, the CESL 242 is deposited. In some examples, the CESL 242 includes silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 242 can be formed by ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition processes. The ILD layer 244 is then deposited over the CESL 242. In some embodiments, the ILD layer 244 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials). The ILD layer 244 can be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after forming the ILD layer 244, the WIP structure 200 can be annealed to improve the integrity of the ILD layer 244. As Fig.14 As shown, the CES L 242 may be disposed directly on top surfaces of the p-type source / drain features 220P in the p-type device region P and the n-type source / drain features 220N in the n-type device region N.

[0042] Still refer to Fig.14 After depositing the CESL 242 and the ILD layer 244, the WIP structure 200 may be planarized by a planarization process to expose the dummy gate stack 230. For example, the planarization process may include a chemical mechanical planarization (CMP) process. The exposure of the dummy gate stack 230 allows the dummy gate stack 230 to be removed, such as Fig.15 As shown. In some embodiments, removing the dummy gate stack 230 generates a gate trench 246 above the n-type channel region NC and the p-type channel region PC. Removing the dummy gate stack 230 may include one or more etching processes that are selective to the material of the dummy gate stack 230. For example, the dummy gate stack 230 may be removed using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 230. After removing the dummy gate stack 230, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel regions NC and PC are exposed in the gate trench 246.

[0043] refer to Figure 3 and Fig.16 , the method 100 includes block 120, wherein the channel layer 208 above the buffer region 15 and the device region 12 is released as a channel member 2080. Fig.16After removing the dummy gate stack 230 to form the gate trench 246, the method 100 selectively removes the sacrificial layer 206 between the channel layer 208 in the n-type channel region NC and the p-type channel region PC. Selectively removing the sacrificial layer 206 releases Fig.15 The channel layer 208 in the Fig.16 248 between the channel members 2080. Selectively removing the sacrificial layer 206 also leaves a space 248 between the channel members 2080. The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching or other selective etching processes. An exemplary selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., ammonium hydroxide-hydrogen peroxide-water mixture).

[0044] Until block 120, the operations of method 100 are performed differently between buffer region 15 and device region 12. This means that the structures formed as a result of the operations at block 120 are generally the same across buffer region 15 and device region 12. For example, n-type source / drain features 220N in device region 12 can be similar in composition and size to n-type epitaxial features 220N in buffer region 15, and p-type source / drain features 220P in device region 12 can be similar in composition and size to p-type epitaxial features 220P in buffer region 15. The same is true for channel member 2080. Channel members 2080 in device region 12 and buffer region 15 can have the same composition or size. After block 120, method 100 branches into two branches and performs different operations on structures in device region 12 and structures in buffer region 15. As will be further described below, block 122 forms a gate structure 250 to surround the channel member 2080 in the device region 12 , and block 124 forms a dielectric gate structure 260 to cut through the channel member 2080 in the buffer region 15 .

[0045] refer to Figure 3 and Fig.17, the method 100 includes a frame 122, wherein a gate structure 250 is selectively formed over the device region 12. In order to achieve differentiated processing of the device region 12, a mask layer may be deposited over the buffer region 15. The mask layer may include a bottom anti-reflective coating (BARC) layer, a photoresist layer, or a combination thereof. The mask layer may first be blanket deposited over the WIP structure 200, and then the mask layer may be photolithographically patterned to selectively cover the buffer region 15. The gate structure 250 includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer disposed on the channel member 2080 and a high-K gate dielectric layer over the interface layer. As used and described herein, a high-K dielectric material includes a dielectric material having a high dielectric constant (e.g., a dielectric constant greater than that of thermal silicon oxide (~3.9)). The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer may include hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 5 ), Hafnium Silicon Oxide (HfSiO 4 )、ZrO 2 ), zirconium oxide silicon (ZrSiO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 )、ZrO、Yttrium oxide (Y 2 O 3 )、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, Hafnium Lanthanum Oxide (HfLaO), Lanthanum Silicon Oxide (LaSiO), Aluminum Silicon Oxide (AlSiO), Hafnium Tantalum Oxide (HfTaO), Hafnium Titanium Oxide (HfTiO), (Ba, Sr)TiO 3 The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0046] The gate electrode layer of the gate structure 250 may include a single layer structure or an alternative multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or a combination of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), aluminum titanium (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure 250. Because the gate structure 250 includes the high-k gate dielectric layer and the various metal layers in the gate electrode layer, the gate structure 250 may be referred to as a high-k metal gate or a high-k metal gate structure. After the gate structure 250 is formed, the mask layer covering the buffer region 15 may be removed. Fig.17 As shown, the gate structure 250 is formed in the n-type device region 12N and the p-type device region 12P in the device region 12. At the end of block 122, Fig.17 In the embodiment shown, the gate structures 250 in the p-type device region 12P and the n-type device region 12N have a gate pitch P.

[0047] refer to Figure 3 and Fig.18, the method 100 includes a block 124, in which a dielectric gate structure 260 is formed over the buffer region 15. As will be further described below, the buffer region 15 may include a p-type buffer region 15P and / or an n-type buffer region 15N. The p-type source / drain feature 220P may be located in the p-type buffer region 15P, and the n-type source / drain feature 220N may be located in the n-type buffer region 15N. Although forming the gate structure 250 over the buffer region 15 appears to be a cost-effective option, it may result in defects when forming a TSV opening through the buffer region 15. Experimental and simulation data indicate that when the gate structure 250 is formed over the buffer region 15, the high-k dielectric layer in the gate structure 250 and the metal layer in the gate electrode layer may slow down the etching process. Etching processes designed to remove these features that slow down etching may cause over-etching and defects in surrounding structures. Etching processes that fail to satisfactorily remove these features that slow down etching may leave conductive residues, which may result in undesirable leakage or unsatisfactory TSV formation. In addition, etching of gate structure 250 tends to create metal fragments that may contaminate the process chamber and reduce yield. For these reasons, frame 124 forms a dielectric gate structure 260 formed above buffer 15 separately. In some embodiments, dielectric gate structure 260 may include silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride oxide. In one embodiment, dielectric gate structure 260 includes silicon nitride. According to the present disclosure, dielectric gate structure 260 does not contain a dielectric material having a dielectric constant greater than 7 (approximately the dielectric constant of silicon nitride). In addition, dielectric gate structure 260 is non-conductive and does not contain any metal.

[0048] Box 124 includes an etching process to form an extended opening through the channel region in the p-type buffer 15P and the n-type buffer 15N, and then depositing a dielectric material over the extended opening to form a dielectric gate structure 260. In the illustrated embodiment, the formation of the extended opening includes using an anisotropic etching process, and the extended opening extends through all of the channel members 2080. In some embodiments, because the dielectric gate structure 260 is formed with isolation structures to divide active areas, such as continuous polysilicon on diffusion edge (CPODE) features, the extended opening extends into the substrate 202. Thereafter, the dielectric gate structure 260 may be deposited using CVD or ALD. The dielectric gate structure 260 wraps over the edge sidewalls of the severed channel members 2080. In some embodiments, the dielectric gate structure 260 may not completely fill the extended opening and may leave a void 270. As shown in FIG. Fig.18 As shown, the dielectric gate structure 260 is formed in the n-type buffer region 15N and the p-type buffer region 15P in the buffer region 15. The transistor-like structure having the dielectric gate structure 260 is not functional and may be referred to as a pseudo transistor or a pseudo transistor structure.

[0049] refer to Figure 3 The method 100 includes block 126 , where further processing is performed. For example, block 126 may include forming a front-side interconnect structure 30 over the WIP structure 200 , and forming TSVs 16 through the front-side interconnect structure 30 and the substrate 202 .

[0050] The N-type source / drain component 220N (or the n-type epitaxial component 220N) and the p-type source / drain component 220P (or the p-type epitaxial component 220P) apply different stresses to the surrounding structures. For example, the p-type source / drain component 220P (or the p-type epitaxial component 220P) can apply compressive stress to the channel member 2080. According to the present disclosure, because the device region 12 includes the N-type source / drain component 220N and the p-type source / drain component 220P, the buffer region 15 should also include the n-type epitaxial component 220N and the p-type epitaxial component 220P to provide a similar environment. In addition, the present disclosure aims to provide a relatively stress-free buffer region 15 for forming the TSV 16. Based on these premises, the present disclosure provides Figures 19 to 22 Four (4) exemplary arrangements are shown in .

[0051] Fig.19 A first exemplary arrangement 300 is shown. In the first exemplary arrangement 300, the buffer region 15 includes a stripe-shaped n-type buffer region 15N and a stripe-shaped p-type buffer region 15P. The stripe-shaped n-type buffer region 15N includes Fig.18 The strip-shaped p-type buffer 15P includes Fig.18 The strip n-type buffer 15N and the strip p-type buffer 15P are arranged along a direction parallel to the edge of the TSV unit 11 ( Fig.19 16 ). In some embodiments, the guard ring 14 and the buffer zone 15 may each have a rectangular shape when viewed along the Z direction. In the illustrated embodiment, the guard ring 14 and the buffer zone 15 are square in shape when viewed from a top view, and the guard ring 14 and the buffer zone 15 are concentric with respect to the center of the circular cross section of the TSV 16. The circular cross section of the TSV 16 has a diameter D. In some examples, the ratio of the diameter D to the gate pitch P may be between about 10 and about 400.

[0052] Fig. 20 A second exemplary arrangement 302 is shown. The second exemplary arrangement 302 is similar to the first exemplary arrangement 300, except that the strip-shaped buffers in the buffer 15 may have different widths. Fig. 20, the buffer zone 15 includes a wide n-type buffer zone 15NW, a narrow n-type buffer zone 15NN, a wide p-type buffer zone 15PW, and a narrow p-type buffer zone 15PN. The wide strip-shaped region and the narrow strip-shaped region may be arranged to maximize the stress relief of the TSV 16. In some embodiments, the guard ring 14 and the buffer zone 15 may each have a rectangular shape when viewed along the Z direction. In the illustrated embodiment, the guard ring 14 and the buffer zone 15 are square in shape when viewed from a top view, and the guard ring 14 and the buffer zone 15 are concentric with respect to the center of the circular cross section of the TSV 16. The circular cross section of the TSV 16 has a diameter D. In some examples, the ratio of the diameter D to the gate pitch P may be between about 10 and about 400.

[0053] Fig.21 A third exemplary arrangement 304 is shown. The third exemplary arrangement 304 is similar to the first exemplary arrangement 300, except that the guard ring 14 includes n-type regions 14N and p-type regions 14P arranged alternately around the buffer region 15. In the exemplary process, in order to form a continuous epitaxial structure in the guard ring 14, n-type epitaxial components and p-type epitaxial components are sequentially and individually formed in the n-type region 14N and the p-type region 14P using a masking layer and a photolithography technique. The separately formed n-type epitaxial components and p-type epitaxial components are physically connected to stretch around the guard ring 14. In some embodiments, the n-type regions 14N and p-type regions 14P that alternately step in the guard ring 14 are rectangular in shape and have the same size. In some embodiments, when viewed along the Z direction, the guard ring 14 and the buffer region 15 can each have a rectangular shape. In the illustrated embodiment, the guard ring 14 and the buffer region 15 are square in shape when viewed from a top view, and the guard ring 14 and the buffer region 15 are concentric with respect to the center of the circular cross section of the TSV 16. The circular cross-section of TSV 16 has a diameter D. In some examples, a ratio of diameter D to gate pitch P may be between about 10 and about 400.

[0054] Fig. 22A fourth exemplary arrangement 306 is shown. The fourth exemplary arrangement 306 is similar to the third exemplary arrangement 304, except that the buffer area 15 includes block n-type buffer areas 15N and block p-type buffer areas 15P arranged in a checkerboard manner. That is, each block n-type buffer area 15N is bordered by four (4) block p-type buffer areas 15P along its four straight sides, and each block p-type buffer area 15P is bordered by four (4) block n-type buffer areas 15N along its four straight sides. In some embodiments, the guard ring 14 and the buffer area 15 may each have a rectangular shape when viewed along the Z direction. In the illustrated embodiment, the guard ring 14 and the buffer area 15 are square in shape when viewed from a top view, and the guard ring 14 and the buffer area 15 are concentric with respect to the center of the circular cross-section of the TSV 16. The circular cross-section of the TSV 16 has a diameter D. In some examples, the ratio of the diameter D to the gate pitch P may be between about 10 and about 400.

[0055] Fig.23 and Fig.24 It schematically shows how the TSV cell region 11 of the present disclosure is presented in a face-to-face (F2F) stacking structure 400 and a face-to-back (F2B) stacking structure 500 .

[0056] First reference Fig.23 . The F2F stacked structure 400 includes a first substrate 402 and a second substrate 404. Wiring for the first substrate 402 is provided through a first front-side interconnect structure 412F above a first front side 402F and a first back-side interconnect structure 412B above a first back side 402B. Wiring for the second substrate 404 is provided through a second front-side interconnect structure 414F above a second front side 404F, the second front side 404F being opposite to the second back side 404B. The first front-side interconnect structure 412F is bonded to the second front-side interconnect structure 414F via a first bonding layer 422 and a second bonding layer 424. Each of the first bonding layer 422 and the second bonding layer 424 includes a metal pad embedded in a dielectric layer. As shown Fig.23 As shown, when the metal pad in the first bonding layer 422 is directly bonded to the metal pad in the second bonding layer 424, the metal pad in the first bonding layer 422 is aligned with the metal pad in the second bonding layer 424. The device region 12 on the first substrate 402 is located outside the KOZ 20 of the TSV 16. Fig.23 The TSV 16 in FIG. 4 extends completely through the first substrate 402 and partially extends into the first front-side interconnect structure 412F and the first back-side interconnect structure 412B. Fig.23 The buffer indicated by the arrow in the middle is found as Figures 19 to 22 The transistor-like structure shown.

[0057] Then refer to Fig.24. The F2B stacked structure 500 includes a lower substrate 502 and an upper substrate 504. Wiring for the lower substrate 502 is provided through a lower front side interconnect structure 512F above a lower front side 502F, the lower front side 502F being opposite to a lower back side 502B. Wiring for the upper substrate 504 is provided through an upper front side interconnect structure 514F above an upper front side 504F, the upper front side 504F being opposite to an upper back side 504B. The lower front side interconnect structure 512F is bonded to the upper front side interconnect structure 514F via a lower bonding layer 522 and an upper bonding layer 524. Each of the lower bonding layer 522 and the upper bonding layer 524 includes a metal pad embedded in a dielectric layer. As Fig.24 As shown, when the metal pads in the lower bonding layer 522 and the metal pads in the upper bonding layer 524 are directly bonded, the metal pads in the lower bonding layer 522 are aligned with the metal pads in the upper bonding layer 524. The device region 12 on the lower substrate 502 is located outside the KOZ 20 of the TSV 16. Fig.24 The TSV 16 in FIG. 1 extends completely through the lower substrate 502 and partially into the lower front side interconnect structure 512F. Fig.24 The arrow indicates the buffer 15. Figures 19 to 22 The transistor-like structure shown.

[0058] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate, a through substrate via (TSV) unit disposed above the substrate, and a TSV extending through the TSV unit and the substrate. The TSV unit includes a guard ring structure extending continuously around the periphery of the TSV unit and a buffer zone surrounded by the guard ring structure. The buffer zone includes a plurality of first pseudo-transistors and a plurality of second pseudo-transistors. Each of the plurality of first pseudo-transistors includes two first type epitaxial components, a first plurality of nanostructures extending between the two first type epitaxial components, and a first isolation gate structure extending through the first plurality of nanostructures. Each of the plurality of second pseudo-transistors includes two second type epitaxial components, a second plurality of nanostructures extending between the two second type epitaxial components, and a second isolation gate structure extending through the second plurality of nanostructures.

[0059] In some embodiments, the two first type epitaxial components include silicon (Si) and an n-type dopant. The two second type epitaxial components include silicon germanium (SiGe) and a p-type dopant. The substrate includes silicon (Si), and the TSV includes copper (Cu), aluminum (Al), cobalt (Co), a copper alloy, tantalum (Ta), titanium (Ti) or tungsten (W). In some embodiments, the first isolation gate structure and the second isolation gate structure include silicon nitride. In some examples, a portion of the first isolation gate structure extends into the substrate, and a portion of the second isolation gate structure extends into the substrate. In some embodiments, the semiconductor structure also includes a first gap disposed between the first plurality of nanostructures and a second gap disposed between the second plurality of nanostructures. In some examples, the TSV unit includes a square shape when viewed from a top view. In some embodiments, the TSV includes a circular shape when viewed from a top view.

[0060] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate including a first region and a second region, a plurality of n-type transistors and a plurality of p-type transistors located in the first region, and a plurality of first-type pseudo-transistors and a plurality of second-type pseudo-transistors located in the second region. Each of the plurality of n-type transistors includes two n-type source / drain components, a first plurality of nanostructures extending between the two n-type source / drain components, and a first gate structure surrounding each of the first plurality of nanostructures. Each of the plurality of p-type transistors includes two p-type source / drain components, a second plurality of nanostructures extending between the two p-type source / drain components, and a second gate structure surrounding each of the second plurality of nanostructures. Each of the plurality of first-type pseudo-transistors includes two n-type epitaxial components, a third plurality of nanostructures extending between the two n-type epitaxial components, and a first dielectric gate structure extending through the third plurality of nanostructures. Each of the plurality of second-type pseudo-transistors includes two p-type epitaxial components, a fourth plurality of nanostructures extending between the two p-type epitaxial components, and a second dielectric gate structure extending through the fourth plurality of nanostructures.

[0061] In some embodiments, the second region further includes a guard ring structure extending continuously around the periphery of the second region. In some examples, the semiconductor structure further includes a through hole extending through the second region and the substrate. In some embodiments, the first gate structure and the second gate structure include a metal, and the first dielectric gate structure and the second dielectric gate structure do not contain any metal. In some embodiments, the first dielectric gate structure and the second dielectric gate structure include silicon nitride. In some embodiments, the size of the first plurality of nanostructures is substantially the same as the size of the third plurality of nanostructures. In some embodiments, the two n-type epitaxial components include silicon (Si) and an n-type dopant, and the two p-type epitaxial components include silicon germanium (SiGe) and a p-type dopant. In some embodiments, a portion of the first dielectric gate structure is disposed between the third plurality of nanostructures, and a portion of the second dielectric gate structure is disposed between the fourth plurality of nanostructures. In some embodiments, the semiconductor structure further includes a first gap disposed between the third plurality of nanostructures, and a second gap disposed among the fourth plurality of nanostructures.

[0062] In yet another exemplary aspect, the present disclosure is directed to a method. The method includes receiving an intermediate structure, the intermediate structure including: a substrate including a first region and a second region, and a stack located above the first region and the second region, the stack including a plurality of channel layers interleaved by a plurality of sacrificial layers, patterning portions of the stack and the substrate to form a first fin structure above the first region and a second fin structure above the second region, forming a first dummy gate stack above a channel region of the first fin structure, and forming a second dummy gate stack above a channel region of the second fin structure, etching source / drain regions of the first fin structure and the second fin structure to form source / drain recesses, forming epitaxial features in the source / drain recesses, selectively removing a plurality of sacrificial layers in the channel regions of the first fin structure and the second fin structure to form a first channel member above the first region and a second channel member above the second region, selectively forming a gate structure to surround each of the first channel members, and selectively forming a dielectric gate structure to wrap around each of the second channel members.

[0063] In some embodiments, the dielectric gate structure does not contain any metal. In some embodiments, the dielectric gate structure consists essentially of silicon nitride.

[0064] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: substrate; A substrate through hole unit is arranged above the substrate; as well as a through-substrate via extending through the through-substrate via unit and the substrate, Wherein, the substrate through hole unit comprises: a guard ring structure extending continuously around the periphery of the through substrate via unit, and A buffer zone, surrounded by the guard ring structure, Wherein, the buffer zone includes: a plurality of first dummy transistors, and a plurality of second dummy transistors, Wherein, each of the plurality of first dummy transistors comprises: two first type epitaxial components, a first plurality of nanostructures extending between the two first type epitaxial features, and a first isolation gate structure extending through the first plurality of nanostructures, Wherein, each of the plurality of second dummy transistors comprises: two second type epitaxial components, a second plurality of nanostructures extending between the two second type epitaxial features, and A second isolation gate structure extends through the second plurality of nanostructures.

2. The semiconductor structure according to claim 1, in, The two first type epitaxial components include silicon (Si) and an n-type dopant, Wherein, the two second type epitaxial components include silicon germanium (SiGe) and p-type dopants.

3. The semiconductor structure according to claim 1, in, The substrate includes silicon (Si), Wherein, the substrate through hole includes copper (Cu), aluminum (Al), cobalt (Co), copper alloy, tantalum (Ta), titanium (Ti) or tungsten (W).

4. The semiconductor structure according to claim 1, wherein: The first isolation gate structure and the second isolation gate structure include silicon nitride.

5. The semiconductor structure according to claim 1, wherein: A portion of the first isolation gate structure extends into the substrate, Part of the second isolation gate structure extends into the substrate.

6. The semiconductor structure according to claim 1, further comprising: a first gap disposed between the first plurality of nanostructures; as well as The second gaps are arranged between the second plurality of nanostructures.

7. The semiconductor structure according to claim 1, wherein: The through substrate via unit comprises a square shape when viewed from a top view.

8. The semiconductor structure according to claim 1, wherein: The through substrate via comprises a circular shape when viewed from a top view.

9. A semiconductor structure comprising: A substrate including a first region and a second region; A plurality of n-type transistors and a plurality of p-type transistors, located in the first region; as well as A plurality of first type pseudo transistors and a plurality of second type pseudo transistors are located in the second region, Wherein, each of the plurality of n-type transistors comprises: Two n-type source / drain components, a first plurality of nanostructures extending between the two n-type source / drain features, and a first gate structure surrounding each of the first plurality of nanostructures, Wherein, each of the plurality of p-type transistors comprises: Two p-type source / drain components, a second plurality of nanostructures extending between the two p-type source / drain features, and a second gate structure surrounding each of the second plurality of nanostructures, Wherein, each of the plurality of first type dummy transistors comprises: Two n-type epitaxial components, a third plurality of nanostructures extending between the two n-type epitaxial components, and a first dielectric gate structure extending through the third plurality of nanostructures, Wherein, each of the plurality of second type dummy transistors comprises: Two p-type epitaxial components, a fourth plurality of nanostructures extending between the two p-type epitaxial components, and A second dielectric gate structure extends through the fourth plurality of nanostructures.

10. A method of forming a semiconductor structure, comprising: An intermediate structure is received, the intermediate structure comprising: A substrate including a first region and a second region, and a stack located above the first region and the second region, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers; patterning the stack and portions of the substrate to form a first fin structure over the first region and a second fin structure over the second region; forming a first dummy gate stack over the channel region of the first fin structure, and forming a second dummy gate stack over the channel region of the second fin structure; Etching source / drain regions of the first fin structure and the second fin structure to form source / drain recesses; forming an epitaxial component in the source / drain recess; selectively removing the plurality of sacrificial layers in the channel regions of the first fin structure and the second fin structure to form a first channel member over the first region and a second channel member over the second region; selectively forming a gate structure to surround each of the first channel members; and A dielectric gate structure is selectively formed to wrap over each of the second channel members.

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