Display substrate, manufacturing method thereof, and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes a substrate, a first conductive layer disposed on one side of the substrate, the first conductive layer including a first electrode, a second conductive layer disposed on a side of the first conductive layer away from the substrate, the second conductive layer including a gate electrode, a semiconductor layer disposed on a side of the second conductive layer away from the substrate, a projection of the semiconductor layer on the substrate being within a projection of the second conductive layer on the substrate, a third conductive layer disposed on a side of the semiconductor layer away from the substrate, the third conductive layer including a transfer portion whose projection on the substrate is within a projection of the first electrode on the substrate, a passivation layer, a first electrode via penetrating through the passivation layer, an opening area of the first electrode via gradually decreasing from a direction away from the substrate to a direction close to the substrate, and the exposed transfer portion constituting part of a via sidewall of the first electrode via.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display substrate, a method for manufacturing the same, and a display device. Background Technology

[0002] With the development of display technology, display devices are being used more and more widely in various fields, and the requirements for display technology are also becoming increasingly stringent. In the manufacturing process of display devices, there are multiple metal traces and vias used to connect metal traces located in different film layers. Electrical connections between metal traces in different film layers are achieved by filling the vias with conductive material. However, in the manufacturing process of existing vias, the etching process of metal traces in different film layers has a certain impact. For example, when a via is close to a metal trace, the metal trace collects charged particles generated during etching, leading to defects at the via location and consequently reducing product yield. Summary of the Invention

[0003] To address at least one aspect of the aforementioned problems, embodiments of this disclosure provide a display substrate, a method for manufacturing the same, and a display device, which can at least avoid defects caused by vias near metal traces, improve product yield, and enhance the display effect of the display substrate.

[0004] In one aspect, a display substrate is provided, including but not limited to: a substrate having a plurality of sub-pixels disposed thereon, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting, each sub-pixel including at least one control transistor; a first conductive layer disposed on one side of the substrate, the first conductive layer including first electrodes arranged at intervals along the second direction to form the sub-pixels; a second conductive layer disposed on the side of the first conductive layer away from the substrate, the second conductive layer including electrodes arranged at intervals along the second direction and extending along the first direction to form the gate electrodes of the control transistors; and a semiconductor layer disposed on the side of the second conductive layer away from the substrate, the semiconductor layer being disposed on the substrate... The projection is located within the orthographic projection of the second conductive layer on the substrate; a third conductive layer is disposed on the side of the semiconductor layer away from the substrate, the third conductive layer including a transition portion whose orthographic projection on the substrate is located within the orthographic projection of the first electrode on the substrate; a passivation layer is disposed on the side of the third conductive layer away from the substrate; a first electrode via penetrates the passivation layer and exposes the first electrode and a portion of the transition portion, the opening area of ​​the first electrode via gradually decreasing from the direction away from the substrate towards the direction closer to the substrate, the exposed transition portion forming a portion of the via sidewall of the first electrode via; and a fourth conductive layer is disposed in the first electrode via, electrically connecting the first electrode to the transition portion.

[0005] In some exemplary embodiments of this disclosure, the via sidewall of the first electrode via includes a stepped portion; the stepped portion includes: a stepped top surface formed by the surface of the exposed transition portion away from the substrate; and a stepped side surface formed by the surface of the exposed transition portion facing into the first electrode via; wherein the opening area of ​​the first electrode via corresponding to the stepped side surface is greater than or equal to the opening area of ​​the first electrode via on the side of the stepped portion closer to the substrate.

[0006] In some exemplary embodiments of this disclosure, the surface roughness of the side of the unexposed transition portion away from the substrate is less than the surface roughness of the top surface of the step.

[0007] In some exemplary embodiments of this disclosure, the angle between the top surface of the step and the side surface of the step is θ, where 90° < θ < 180°.

[0008] In some exemplary embodiments of this disclosure, the first electrode via exposes a portion of the semiconductor layer, and the exposed semiconductor layer constitutes a portion of the via sidewall of the first electrode via; the opening area of ​​the first electrode via corresponding to the semiconductor layer is less than or equal to the opening area of ​​the first electrode via corresponding to the step portion.

[0009] In some exemplary embodiments of this disclosure, the first electrode includes pixel electrodes, which are spaced apart in a first direction, with each pixel electrode corresponding to each sub-pixel; the third conductive layer further includes: data signal lines spaced apart in the first direction and extending along the second direction; and a first electrode and a second electrode constituting the control transistor; the first electrode is electrically connected to the data signal lines, and the second electrode is electrically connected to the adapter.

[0010] In some exemplary embodiments of this disclosure, the third conductive layer further includes: voltage signal lines spaced apart in the first direction and extending along the second direction; the voltage signal lines are located between adjacent data signal lines; and the sub-pixels are located between adjacent voltage signal lines and data signal lines.

[0011] In some exemplary embodiments of this disclosure, the voltage signal line is electrically connected to the common electrode through a second electrode via.

[0012] In some exemplary embodiments of this disclosure, the gate electrode is located between adjacent pixel electrodes; the orthographic projections of the first electrode and the second electrode on the substrate are located within the orthographic projection of the semiconductor layer on the substrate, and the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the gate electrode on the substrate; the gate electrode is configured to transmit control data signals from the data signal line to the pixel electrode via the control transistor, the adapter, and the fourth conductive layer.

[0013] In some exemplary embodiments of this disclosure, the sub-pixel includes a first sub-pixel and a second sub-pixel adjacent in the first direction, the first sub-pixel and the second sub-pixel being located between adjacent data signal lines, and the voltage signal line being located between the first sub-pixel and the second sub-pixel; the gate electrode includes a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode being disposed adjacent to each other in the second direction; the first gate electrode is configured to control a control transistor of the first sub-pixel adjacent to the first gate electrode; the second gate electrode is configured to control a control transistor of the second sub-pixel adjacent to the second gate electrode.

[0014] In some exemplary embodiments of this disclosure, the first electrode includes a common electrode, and a plurality of first electrode vias are provided on the side of each common electrode away from the substrate; the third conductive layer further includes a connection portion, the connection portion electrically connecting the transition portions of the common electrodes adjacent in a second direction, wherein the connection portion is configured to electrically connect the common electrodes adjacent in the second direction through a fourth conductive layer located within the first electrode vias.

[0015] In some exemplary embodiments of this disclosure, the second conductive layer further includes voltage signal lines arranged at intervals in the second direction and extending along the first direction; the voltage signal lines are electrically connected to the common electrode.

[0016] In some exemplary embodiments of this disclosure, the gate electrode is disposed adjacent to the voltage signal line, and the gate electrode and the voltage signal line are located between adjacent common electrodes.

[0017] In some exemplary embodiments of this disclosure, the third conductive layer further includes: data signal lines spaced apart in a first direction and extending along a second direction; and a first electrode and a second electrode constituting the control transistor; the first electrode is electrically connected to the data signal lines, and the second electrode is electrically connected to a pixel electrode through a third electrode via.

[0018] In another aspect, this disclosure provides a method for manufacturing a display substrate, comprising: forming a first conductive layer on one side of a substrate, the first conductive layer including first electrodes spaced apart in a second direction to form sub-pixels on the substrate, the sub-pixels on the substrate being arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting; forming a second conductive layer on the side of the first conductive layer away from the substrate, the second conductive layer including first electrodes spaced apart in the second direction and extending along the first direction to form gate electrodes of control transistors; forming a semiconductor layer on the side of the second conductive layer away from the substrate, the orthographic projection of the semiconductor layer on the substrate being located within the orthographic projection of the second conductive layer on the substrate; and ... semiconductor layer being located within the orthographic projection of the second conductive layer on the substrate; and forming a semiconductor layer on the side of the second conductive layer away from the substrate, the semiconductor layer being located within the orthographic projection of the second conductive layer on the substrate; and forming a semiconductor layer on the side of the second conductive layer away from the substrate. A third conductive layer is formed on the side of the semiconductor layer away from the substrate. The third conductive layer includes a transition portion whose orthogonal projection on the substrate lies within the orthogonal projection of the first electrode on the substrate. A passivation layer is formed on the side of the third conductive layer away from the substrate. A first electrode via is formed, penetrating the passivation layer and exposing the first electrode and a portion of the transition portion. The opening area of ​​the first electrode via gradually decreases from the direction away from the substrate toward the direction closer to the substrate. The exposed transition portion constitutes a portion of the via sidewall of the first electrode via. A fourth conductive layer is formed in the first electrode via, which electrically connects the first electrode to the transition portion.

[0019] In some exemplary embodiments of this disclosure, forming the first electrode via includes forming a first sub-via and forming a second sub-via, wherein the first sub-via exposes a portion of the first electrode and the orthographic projection of the first sub-via on the substrate does not overlap with the orthographic projection of the transition portion on the substrate, and the second sub-via exposes a portion of the transition portion and the orthographic projection of the second sub-via on the substrate overlaps with the orthographic projection of the transition portion on the substrate.

[0020] In some exemplary embodiments of this disclosure, forming a first sub-via and forming a second sub-via include: coating a photoresist on the side of the passivation layer away from the substrate; fully exposing the photoresist region corresponding to the first sub-via and partially exposing the photoresist region corresponding to the second sub-via; etching a film material in the region corresponding to the first sub-via to expose the first electrode; and etching a film material in the region corresponding to the second sub-via to expose the transition portion, wherein the exposed transition portion constitutes a via sidewall of the first electrode via.

[0021] In some exemplary embodiments of this disclosure, etching the film material corresponding to the region of the first sub-via includes: etching the passivation layer corresponding to the region of the first sub-via using a first dry etching medium, and etching an insulating layer corresponding to the region of the first sub-via and located between the passivation layer and the first electrode.

[0022] In some exemplary embodiments of this disclosure, etching the film material corresponding to the region of the second sub-via includes: etching the photoresist material corresponding to the region of the second sub-via using a second dry etching medium; and etching the passivation layer material corresponding to the region of the second sub-via using a first dry etching medium.

[0023] In some exemplary embodiments of this disclosure, the method further includes etching photoresist located on the passivation layer using a second dry etching medium.

[0024] In some exemplary embodiments of this disclosure, forming a first sub-via and forming a second sub-via include: coating a first photoresist on the side of the passivation layer away from the substrate; fully exposing the first photoresist region corresponding to the first sub-via; etching the film material in the region corresponding to the first sub-via to expose the first electrode; stripping the first photoresist; coating a second photoresist on the side of the passivation layer away from the substrate so that a portion of the second photoresist fills the first sub-via; fully exposing the second photoresist region corresponding to the second sub-via; etching the film material in the region corresponding to the second sub-via to expose the transition portion, the exposed transition portion constituting the via sidewall of the first electrode via; and stripping the second photoresist.

[0025] In another aspect of this disclosure, a display device is provided, comprising: a display substrate as described above. Attached Figure Description

[0026] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0027] Figure 1 This is a plan view of a display substrate according to an exemplary embodiment of the present disclosure;

[0028] Figure 2 This is a schematic diagram of the planar structure of a display substrate according to an embodiment of the present disclosure;

[0029] Figure 3 According to the embodiments of this disclosure Figure 2 A magnified schematic diagram of a portion of region A;

[0030] Figure 4 According to the embodiments of this disclosure Figure 3 A schematic diagram of the cross-sectional structure of line B-B' in the diagram;

[0031] Figure 5 This is a schematic diagram of the planar structure of a display substrate according to another embodiment of the present disclosure;

[0032] Figure 6 According to the embodiments of this disclosure Figure 5 A magnified schematic diagram of the local structure of region C;

[0033] Figure 7 This is a flowchart of a method for manufacturing a display substrate according to exemplary embodiments of the present disclosure;

[0034] Figures 8A to 8L This is a cross-sectional structural schematic diagram of a method for manufacturing a display substrate according to an exemplary embodiment of the present disclosure during the manufacturing process;

[0035] Figures 9A to 9G This is a cross-sectional structural schematic diagram of a method for manufacturing a display substrate according to another exemplary embodiment of the present disclosure during the manufacturing process;

[0036] Figure 10A This is a planar schematic diagram of the first electrode via manufactured using existing manufacturing methods;

[0037] Figure 10B It is along Figure 10A The actual cross-sectional structure diagram with dashed lines;

[0038] Figure 10C This is a plan view of a first electrode via manufactured according to a manufacturing method of an exemplary embodiment of the present disclosure;

[0039] Figure 10D It is along Figure 10C The actual cross-sectional structure diagram with dashed lines.

[0040] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0041] The technical solutions of this disclosure will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of this disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of this disclosure and should not be construed as a limitation thereof.

[0042] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0043] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0044] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0045] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0046] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0047] Those skilled in the art will understand that, unless otherwise stated herein, the expressions “continuous extension,” “monolithic structure,” “integral structure,” or similar expressions mean that multiple elements, components, structures, and / or portions are located on the same layer and are typically formed during manufacturing by the same patterning process, and that these elements, components, structures, and / or portions are continuous extensions without gaps or breaks between them.

[0048] In this document, the directional terms "first direction" and "second direction" are used to describe different directions along a pixel region, such as the vertical and horizontal directions of the pixel region. It should be understood that such representations are merely exemplary descriptions and not limitations of this disclosure.

[0049] In this document, the term "control transistor" refers to a transistor in a sub-pixel used to control the transmission of data signals within the sub-pixel. A sub-pixel may include one or more transistors, and one or more transistors may include one or more control transistors.

[0050] In this paper, the term "aperture area" refers to the area of ​​the orthogonal projection of the opening onto a plane parallel to the plane where the electrode via opening is located. The opening area varies at different locations of the electrode via as the distance from the substrate changes.

[0051] In related technologies, different display panel structures correspond to different display modes, such as ADS display mode and iADS display mode. Since display panels consist of multiple different film layers, including multiple insulating layers and multiple metal wires, even with different display panel structures, electrode vias are generally manufactured using an exposure process to electrically connect the metal wires in these different film layers. However, when electrode vias are close to metal wires, the metal wires are prone to inducing plasma effects during dry etching, resulting in a higher etching rate for the insulating layer near the metal. This leads to more defects in the electrode vias, easily causing product defects, reducing both product yield and display performance.

[0052] To address the aforementioned problems, embodiments of this disclosure provide a display substrate, which includes, but is not limited to: a substrate having a plurality of sub-pixels arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting, each sub-pixel including at least one control transistor; a first conductive layer disposed on one side of the substrate, the first conductive layer including first electrodes arranged at intervals along the second direction to form the sub-pixels; a second conductive layer disposed on the side of the first conductive layer away from the substrate, the second conductive layer including first electrodes arranged at intervals along the second direction and extending along the first direction to form the gate electrodes of the control transistors; and a semiconductor layer disposed on the side of the second conductive layer away from the substrate, the semiconductor layer being disposed on the side of the second conductive layer away from the substrate. The orthographic projection on the substrate lies within the orthographic projection of the second conductive layer on the substrate; a third conductive layer is disposed on the side of the semiconductor layer away from the substrate, the third conductive layer including a transition portion whose orthographic projection on the substrate lies within the orthographic projection of the first electrode on the substrate; a passivation layer is disposed on the side of the third conductive layer away from the substrate; a first electrode via penetrates the passivation layer and exposes the first electrode and a portion of the transition portion, the opening area of ​​the first electrode via gradually decreases from the direction away from the substrate towards the direction closer to the substrate, the exposed transition portion constitutes a portion of the via sidewall of the first electrode via; and a fourth conductive layer is disposed in the first electrode via, electrically connecting the first electrode to the transition portion.

[0053] According to embodiments of this disclosure, by providing a first electrode via through the passivation layer and exposing a portion of the transition portion in the first electrode and the third conductive layer, the first electrode is electrically connected to the transition portion. By setting the opening area of ​​the first electrode via to gradually decrease from the direction away from the substrate to the direction closer to the substrate, the exposed transition portion is prevented from causing defects in subsequent manufacturing processes, thereby improving the yield of the display substrate and the display effect.

[0054] The following is combined with Figures 1 to 8L The structure of the display substrate according to the embodiments of this disclosure will be described in detail.

[0055] Figure 1 This is a plan view of a display substrate according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 1 According to embodiments of the present disclosure, the display substrate may include a substrate 10 and pixel units PX disposed on the substrate 10.

[0056] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel units PX are disposed to display images. Each pixel unit PX will be described later. The non-display area NA is an area where no pixel units PX are disposed, that is, an area where no images are displayed. The non-display area NA corresponds to the bezel in the final display device, and the width of the bezel can be determined based on the width of the non-display area NA.

[0057] The display area AA can have various shapes. For example, the display area AA can be set in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with both straight and curved edges. In the embodiments of this disclosure, the display area AA is set as an area having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof.

[0058] A non-display area NA may be disposed on at least one side of the display area AA. In embodiments of this disclosure, the non-display area NA may surround the outer periphery of the display area AA. In embodiments of this disclosure, the non-display area NA may include a lateral portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0059] Pixel units (PX) are disposed within the display area (AA). A pixel unit (PX) is the smallest unit used to display an image, and multiple units can be configured. For example, a pixel unit (PX) may include a light-emitting device that emits white light and / or colored light.

[0060] Pixel units PX can be configured in multiples, arranged in a matrix form along rows extending in the first direction X and columns extending in the first direction Y. However, embodiments of this disclosure do not specifically limit the arrangement of pixel units PX, and pixel units PX can be arranged in various forms. For example, pixel units PX can be arranged such that the direction inclined relative to the first direction X and the first direction Y is the column direction, and the direction intersecting the column direction is the row direction.

[0061] In other words, multiple pixel units PX are arranged in an array along the first direction X and the second direction Y to form multiple rows of pixel units and multiple columns of pixel units.

[0062] A pixel unit PX can include multiple sub-pixels. For example, a pixel unit PX can include three sub-pixels: a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, the first sub-pixel SP1 can be a red sub-pixel, the second sub-pixel SP2 can be a green sub-pixel, and the third sub-pixel SP3 can be a blue sub-pixel.

[0063] It should be noted that in the embodiments of this disclosure, the number of sub-pixels included in a pixel unit is not particularly limited and is not limited to the above-mentioned three.

[0064] For example, in Figure 1 In the exemplary embodiment shown, signal lines 11 and data lines 12 are schematically illustrated. That is, the display substrate may further include: a plurality of signal lines 11 and a plurality of data lines 12 disposed on the substrate, wherein the plurality of signal lines 11 supply, for example, scan control signals to multiple rows of pixel units, and the plurality of data lines 12 supply data signals to multiple columns of pixel units. The signal lines 11 extend along a first direction X, and the plurality of signal lines 11 are arranged at intervals along a second direction Y. The data lines 12 extend along the second direction Y, and the plurality of data lines 12 are arranged at intervals along the first direction X.

[0065] For example, signal line 11 can be representative of horizontal routing, and data line 12 can be representative of vertical routing. It should be understood that horizontal routing may also include other types of routing or routing used to supply other signals, and vertical routing may also include other types of routing or routing used to supply other signals.

[0066] Each subpixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, in an OLED display substrate or display panel, the light-emitting element of a subpixel may include an anode, a light-emitting material layer, and a cathode stacked together. The anodes of the light-emitting elements of each subpixel are spaced apart and arranged in a matrix form along rows extending in a first direction X and columns extending in a second direction Y.

[0067] Figure 2 This is a schematic diagram of the planar structure of a display substrate according to an embodiment of the present disclosure.

[0068] Figure 3 According to the embodiments of this disclosure Figure 2 A magnified schematic diagram of a portion of region A.

[0069] Figure 4 According to the embodiments of this disclosure Figure 3 A schematic diagram of the cross-sectional structure of line B-B' in the diagram.

[0070] The following is combined with Figures 2 to 4 The structure of a display substrate according to one embodiment of the present disclosure will be described in detail.

[0071] like Figures 2 to 4 As shown, the display substrate 100 includes a substrate 10, a first conductive layer 20, a second conductive layer 30, a semiconductor layer 40, a third conductive layer 50, a passivation layer 60, and a fourth conductive layer 70.

[0072] like Figure 2 As shown, a plurality of sub-pixels px are disposed on the substrate 10. The plurality of sub-pixels px are arranged in an array along the first direction X and the second direction Y. The first direction X and the second direction Y intersect. Each sub-pixel px includes at least one control transistor TFT.

[0073] For example, subpixels arranged in an array can emit light of different colors. For instance, three subpixels can also be called a pixel unit. The first direction X refers to the horizontal direction of the display substrate, and the second direction Y is, for example, the vertical direction perpendicular to the horizontal direction of the display substrate. In optional embodiments, the first direction X and the second direction Y can be set to have a certain angle, thereby achieving different pixel arrangements and display effects.

[0074] A control transistor TFT can refer to one of the transistors in one or more transistors included in each sub-pixel that is used to implement a specific control function. For example, the control transistor TFT of each sub-pixel is used to control the transmission of data signals to the pixel electrode of each sub-pixel.

[0075] like Figure 4 As shown, a first conductive layer 20 is disposed on one side of the substrate 10. The first conductive layer 20 includes first electrodes arranged at intervals in a second direction to form the sub-pixels. In this embodiment, the first electrodes include pixel electrodes 21, each pixel electrode 21 corresponding to each sub-pixel, that is, the pixel electrodes 21 are arranged at intervals in the first direction X and the second direction Y. For example, the pixel electrodes 21 are rectangular, and the length direction of the rectangle is parallel to the second direction Y. In other alternative embodiments, the first electrode may also include a common electrode, which will be described in detail below.

[0076] The second conductive layer 30 is disposed on the side of the first conductive layer 20 away from the substrate. The second conductive layer 30 includes components spaced apart in the second direction Y and extending along the first direction X, forming the gate electrode G30 of the control transistor TFT.

[0077] In some embodiments, the first conductive layer 20 may overlap with the orthographic projection of the gate electrode G30 on the substrate. The portion of the first conductive layer 20 that overlaps with the gate electrode G30 is insulated from and separated from the pixel electrode 21 in the first conductive layer 20, that is, the portion of the first conductive layer 20 that overlaps with the gate electrode G30 has no electrical connection with the pixel electrode 21 in the first conductive layer 20.

[0078] like Figure 4 As shown, the semiconductor layer 40 is disposed on the side of the second conductive layer 30 away from the substrate 10, and the orthographic projection of the semiconductor layer 40 on the substrate lies within the orthographic projection of the second conductive layer 30 on the substrate. Specifically, the orthographic projection of the semiconductor layer 40 on the substrate overlaps with the orthographic projection of the gate electrode G30 of the second conductive layer 30 on the substrate, that is, the conduction state of the semiconductor layer 40 is controlled by the gate electrode G30.

[0079] like Figure 4 As shown, the third conductive layer 50 is disposed on the side of the semiconductor layer 40 away from the substrate 10, and the third conductive layer 50 includes a transition portion 51 whose orthogonal projection on the substrate 10 is located within the orthogonal projection of the first electrode on the substrate.

[0080] When a third conductive layer 50 is formed on the side of the semiconductor layer 40 away from the substrate 10, a portion of the formed third conductive layer 50 is a transition portion 51, and other portions of the third conductive layer 50 can be structures such as data signal lines or voltage signal lines, which will be described in detail below.

[0081] like Figure 4 As shown, a passivation layer 60 is disposed on the side of the third conductive layer 50 away from the substrate 10. A first electrode via VH1 penetrates the passivation layer 60 and exposes the first electrode 21 and a portion of the transition portion 51. The opening area of ​​the first electrode via VH1 gradually decreases from the direction away from the substrate 10 toward the direction closer to the substrate 10. The exposed transition portion 51 constitutes a portion of the via sidewall of the first electrode via. A fourth conductive layer 70 is disposed in the first electrode via VH1, electrically connecting the first electrode 21 to the transition portion 51.

[0082] In some embodiments of this disclosure, one or more insulating layers are disposed between the first conductive layer 20 and the semiconductor layer 40, and one or more insulating layers are disposed between the second conductive layer 30 and the semiconductor layer 40. For example, the insulating layer may include a gate insulating layer 101.

[0083] like Figure 3 and Figure 4 As shown, a semiconductor layer 40 is further included between the transition portion 51 in the third conductive layer 50 and the first electrode 21. In some optional embodiments, the semiconductor layer may not be provided between the transition portion in the third conductive layer and the first electrode.

[0084] For example, the first electrode via VH1 penetrates the passivation layer 60 and the gate insulating layer 101.

[0085] like Figure 4 As shown, the opening area of ​​the first electrode via VH1 refers to the orthogonal projection area of ​​the opening of the first electrode via on a plane parallel to the upper surface of the substrate. The first electrode via VH1 has a via sidewall jointly formed by the passivation layer 60, the transition portion 51 in the third conductive layer 50, the semiconductor layer 40, and the gate insulating layer 101. A portion of the exposed pixel electrode 21 forms the bottom wall of the first electrode via VH1, and a portion of the exposed transition portion 51 forms a portion of the via sidewall of the first electrode via VH1.

[0086] The fourth conductive layer 70 located in the first electrode via VH1 is electrically connected to the exposed portion of the adapter 51 in the first electrode via VH1. At the same time, the fourth conductive layer 70 is also electrically connected to the exposed portion of the pixel electrode 21 in the electrode via VH1, so that the fourth conductive layer 70 can electrically connect the pixel electrode 21 in the first electrode to the adapter 51.

[0087] like Figure 4 As shown, the via sidewall of the first electrode via VH1 includes a step portion S1, which includes a top surface S11 and a side surface S12.

[0088] The top surface S11 of the step is formed by the surface of the exposed transition portion 51 away from the substrate 10. The side surface S12 of the step is formed by the surface of the exposed transition portion 51 facing into the first electrode via. The opening area of ​​the first electrode via corresponding to the side surface S12 of the step is greater than or equal to the opening area of ​​the first electrode via on the side of the step portion S1 closer to the substrate.

[0089] That is, the closer the opening area of ​​the first electrode via VH1 is to the substrate, the smaller the opening area. For example, the opening area of ​​the first electrode via located on the top surface S11 of the step is larger than the opening area of ​​the first electrode via located on the side surface S12 of the step, and the opening area of ​​the first electrode via corresponding to the side surface S12 of the step is larger than the opening area of ​​the first electrode via closer to the substrate than the step S1.

[0090] According to an embodiment of this disclosure, the opening area of ​​the first electrode via VH1 gradually decreases from the direction away from the substrate to the direction closer to the substrate, thereby avoiding the presence of gaps in the transition portion in the direction close to the substrate, further avoiding the problem of reduced product yield caused by residual stripping fluid in the gaps during processing, and improving the display effect of the display substrate.

[0091] In the embodiments of this disclosure, the transition portion 51 in the first electrode via VH1 includes an exposed portion and a non-exposed portion. During the formation of the first electrode via VH1, it is formed by dry etching. During etching, the surface of the transition portion 51 on the side away from the substrate 10 is bombarded by plasma, thereby increasing its surface roughness. The non-exposed portion is not bombarded by plasma and is unaffected. That is, the surface roughness of the non-exposed transition portion on the side away from the substrate 10 is less than the surface roughness of the top surface of the step.

[0092] like Figure 4 As shown, the angle between the top surface S11 and the side surface S12 of the step portion is θ, where 90° < θ < 180°. By setting a certain angle between the top surface S11 and the side surface S12 of the step, the opening area of ​​the first electrode via VH1 gradually decreases from the direction away from the substrate towards the direction closer to the substrate.

[0093] In some embodiments, a semiconductor layer 40 is further provided on the side of the transition portion 51 near the substrate 10, and a portion of the semiconductor layer 40 is exposed by the first electrode via VH1, the exposed semiconductor layer 40 constituting a portion of the via sidewall of the first electrode via VH1. The opening area of ​​the first electrode via corresponding to the exposed semiconductor layer 40 is less than or equal to the opening area of ​​the first electrode via corresponding to the step portion S12.

[0094] exist Figures 2 to 4 In the illustrated embodiment, the first electrode includes a pixel electrode that provides a data signal for each sub-pixel.

[0095] like Figures 2 to 3 As shown, the third conductive layer 50 includes data signal lines 52 and voltage signal lines 53.

[0096] Data signal lines 52 are spaced apart in the first direction X and extend along the second direction Y. Data signal lines 52 are used to transmit data signal VDD. Voltage signal lines 53 are spaced apart in the first direction X and extend along the second direction Y. Voltage signal lines 53 are used to transmit voltage signal Vcom.

[0097] The third conductive layer 50 includes a first electrode T1 and a second electrode T2 constituting a control transistor TFT. The first electrode T1 is electrically connected to the data signal line 52, and the second electrode T2 is electrically connected to the adapter 51.

[0098] One or more sub-pixels are set between the data signal lines 52. For example, two sub-pixels are set between the data signal lines 52, that is, one sub-pixel is set on each side of each data signal line 52.

[0099] The voltage signal line 53 is located between adjacent data signal lines 52, that is, it is arranged in a way that alternates between voltage signal line 53 and data signal line 52.

[0100] A second electrode via VH2 is provided at the gap position between the pixel electrodes 21 on the voltage signal line 53, and the voltage signal line 53 is electrically connected to the common electrode through the second electrode via VH2.

[0101] like Figure 2 and Figure 3 As shown, the gate electrode G30 is located between adjacent pixel electrodes 21, and the gate electrode G30 extends along a first direction.

[0102] like Figure 3 As shown, the orthographic projections of the first electrode T1 and the second electrode T2 on the substrate 10 lie within the orthographic projection of the semiconductor layer 40 on the substrate 10, meaning that the first electrode T1 and the second electrode T2 are electrically connected to the semiconductor layer 40. The orthographic projection of the semiconductor layer 40 on the substrate 10 lies within the orthographic projection of the gate electrode G30 on the substrate 10. The gate electrode G30 and the semiconductor layer 40 are insulated and separated by the gate insulating layer 101. By setting the orthographic projection relationship between the gate electrode G30 and the semiconductor layer 40, the gate electrode G30 controls the semiconductor layer of the control transistor TFT.

[0103] For example, the gate electrode G30 is configured to control the transmission of data signals from the data signal line 52 via the control transistor TFT, the adapter 51, and the fourth conductive layer 70 to the pixel electrode 21.

[0104] In some embodiments of this disclosure, such as Figure 2 and Figure 3As shown, the sub-pixel includes a first sub-pixel PX1 and a second sub-pixel PX2 that are adjacent in the first direction X. The first sub-pixel PX1 and the second sub-pixel PX2 are located between adjacent data signal lines 52, and the voltage signal line 53 is located between the first sub-pixel PX1 and the second sub-pixel PX2.

[0105] The gate electrode G30 includes a first gate electrode G301 and a second gate electrode G302, which are disposed adjacent to each other in the second direction Y. The first gate electrode G301 is configured to control a control transistor of the first sub-pixel PX1 located near the first gate electrode G301. The second gate electrode G302 is configured to control a control transistor of the second sub-pixel PX2 located near the second gate electrode G302.

[0106] For example, such as Figure 3 As shown, data signal line 52 provides data signal lines for the upper second sub-pixel PX2 and the lower first sub-pixel PX1. Specifically, data signal line 52 is electrically connected to the first electrode T1 of the control transistor TFT of the upper second sub-pixel PX2 and the first electrode T1 of the control transistor TFT of the lower first sub-pixel PX1, respectively. The first gate electrode G301 controls the conduction state of the control transistor of the lower first sub-pixel PX1, and the second gate electrode G302 controls the conduction state of the control transistor of the upper second sub-pixel PX2.

[0107] Figure 5 This is a schematic diagram of the planar structure of a display substrate according to another embodiment of the present disclosure. Figure 6 According to the embodiments of this disclosure Figure 5 A magnified schematic diagram of the local structure of region C.

[0108] like Figure 5 and Figure 6 As shown, the first electrode includes a common electrode 21' for the sub-pixel, and each common electrode 21' has a plurality of first electrode vias VH1' on the side away from the substrate 10.

[0109] For example, a column of sub-pixels arranged along a first direction X can share a common electrode 21'. The common electrodes 21' are spaced apart along a second direction Y. A second conductive layer 30 is disposed between adjacent common electrodes 21' in the second direction Y. The second conductive layer 30 includes a gate electrode G30' and a voltage signal line 31. The voltage signal line 31 is spaced apart along the second direction Y and extends along the first direction X. The voltage signal line is electrically connected to the common electrode 21'. The voltage signal line 31 is used to transmit a voltage signal Vcom to the common electrode 21'.

[0110] The portion of the third conductive layer 50 projected onto the substrate 10 and falling within the projected portion of the common electrode 21' onto the substrate 10 constitutes a transition portion 51'. Each common electrode has a plurality of corresponding transition portions 51', which are used to electrically connect adjacent common electrodes in the second direction Y. For example, adjacent common electrodes in the second direction each have a transition portion 51' at a corresponding position, and the transition portion 51' is electrically connected to the common electrode 21' through the fourth conductive layer in the first electrode via VH1'. Adjacent transition portions 51' are connected by a connecting portion.

[0111] For example, the third conductive layer also includes a connection portion 511, which electrically connects to the transition portion 51' of the common electrode adjacent in the second direction Y. The connection portion 511 is configured to electrically connect to the common electrode 21' adjacent in the second direction Y through a fourth conductive layer 70 located in the first electrode via VH1'.

[0112] The gate electrode G30' is disposed adjacent to the voltage signal line 31, and the gate electrode G30' and the voltage signal line 31 are located between the adjacent common electrode 21'.

[0113] In one embodiment of this disclosure, the voltage signal line 31 is electrically connected to the common electrode 21' to provide a voltage signal to the common electrode. Since the common electrodes 21' are spaced apart in the second direction Y, there is a voltage difference between the spaced common electrodes 21' due to resistance, etc., which can easily cause inconsistent display effects on the display substrate during display. By providing the connecting part 511 to electrically connect the common electrodes 21' spaced apart in the second direction through the adapter part 51' and the fourth conductive layer 70 in the first electrode via VH1', the voltage difference caused by resistance and other problems between the common electrodes is avoided, thereby improving the display uniformity of the display substrate and improving the display effect.

[0114] like Figure 6 As shown, the third conductive layer 50 further includes data signal lines 52', which are spaced apart in the first direction X and extend along the second direction Y. The third conductive layer 50 also includes a first electrode T1' and a second electrode T2' constituting the control transistor TFT.

[0115] The first electrode T1' is electrically connected to the data signal line 52', and the second electrode T2' is electrically connected to the pixel electrode through the third electrode via VH3.

[0116] In the embodiments of this disclosure, the second electrode via VH2 and the third electrode via VH3 are different from the first electrode via VH1, and no metal-containing film layer is exposed on the via sidewalls of the second electrode via VH2 and the third electrode via VH3.

[0117] In embodiments of this disclosure, such as Figure 4 As shown, the opening area of ​​the first electrode via VH1 gradually decreases from the direction away from the substrate to the direction closer to the substrate. For example, the opening area of ​​the first electrode via in the passivation layer 60 is greater than the opening area of ​​the first electrode via in the gate insulating layer 101.

[0118] For example, the orthographic projection of the opening of the first electrode via of the gate insulating layer 101 onto the substrate lies within the orthographic projection of the opening of the first electrode via of the passivation layer 60 onto the substrate.

[0119] The first electrode via VH1 includes a via sidewall formed by a passivation layer 60 and a gate insulating layer 101. The cross-sectional line of the via sidewall formed by the passivation layer 60 and the gate insulating layer 101 is obtuse, meaning that there are via sidewalls with different angles formed between the passivation layer 60 and the gate insulating layer 101 due to different etching rates. For example, the via sidewall formed by the gate insulating layer 101 has an included angle α with the upper surface of the substrate, and 35°≤α≤45°. Compared to the process of forming the first electrode via in a single exposure, this disclosure adopts a process of first forming the first sub-via and then forming the second sub-via to form the first electrode via, as detailed in the display substrate manufacturing method below. This avoids the step formed by the surface of the gate insulating layer away from the substrate during the formation of the first electrode via due to the different etching rates of the passivation layer and the gate insulating layer in the single exposure process. In other words, when the first electrode via is formed by the manufacturing process of this disclosure, the connection between the passivation layer and the gate insulating layer is an obtuse angled zigzag transition, instead of a stepped platform.

[0120] Figure 7 This is a flowchart of a method for manufacturing a display substrate according to an exemplary embodiment of the present disclosure.

[0121] like Figure 7 As shown, the manufacturing method of the display substrate includes operations S1 to S7.

[0122] In operation S1, a first conductive layer is formed on one side of the substrate. The first conductive layer includes first electrodes arranged at intervals in a second direction to form sub-pixels on the substrate. The sub-pixels on the substrate are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.

[0123] In operation S2, a second conductive layer is formed on the side of the first conductive layer away from the substrate. The second conductive layer includes components spaced apart in a second direction and extending along the first direction to form the gate electrode of the control transistor.

[0124] In operation S3, a semiconductor layer is formed on the side of the second conductive layer away from the substrate, and the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate.

[0125] In operation S4, a third conductive layer is formed on the side of the semiconductor layer away from the substrate. The third conductive layer includes a transition portion whose orthogonal projection on the substrate is located within the orthogonal projection of the first electrode on the substrate.

[0126] In operation S5, a passivation layer is formed on the side of the third conductive layer away from the substrate.

[0127] In operation S6, a first electrode via is formed, which penetrates the passivation layer and exposes the first electrode and a portion of the transition portion. The opening area of ​​the first electrode via gradually decreases from the direction away from the substrate towards the direction closer to the substrate, and the exposed transition portion constitutes a portion of the via sidewall of the first electrode via.

[0128] In operation S7, a fourth conductive layer is formed in the first electrode via, the fourth conductive layer electrically connecting the first electrode to the adapter.

[0129] Figures 8A to 8L This is a cross-sectional structural schematic diagram of a method for manufacturing a display substrate according to an exemplary embodiment of the present disclosure during the manufacturing process.

[0130] The following is combined with Figures 8A to 8L The manufacturing method of the display substrate according to the embodiments of this disclosure will be described in detail.

[0131] like Figure 8A As shown, a first conductive layer 20 is formed on one side of the display substrate 10. The first conductive layer 20 includes first electrodes that are arranged at intervals in a second direction to form sub-pixels on the substrate. The first electrodes can be pixel electrodes or common electrodes.

[0132] like Figure 8B As shown, a second conductive layer 30 is formed on the side of the first conductive layer 20 away from the substrate 10. The second conductive layer 30 includes gate electrodes that are spaced apart in a second direction and extend along the first direction to form a control transistor.

[0133] like Figure 8CAs shown, a gate insulating layer 101 is formed on the second conductive layer 20, and a semiconductor layer 40 is formed on the side of the gate insulating layer 101 away from the substrate 10. The semiconductor layer 40 includes a portion whose orthogonal projection on the substrate overlaps with the orthogonal projection of the second conductive layer 30 forming the gate electrode on the substrate, and this portion serves as the active layer for controlling the transistor.

[0134] like Figure 8D As shown, a third conductive layer 50 is formed on the side of the semiconductor layer 40 away from the substrate 10. The third conductive layer 50 includes a transition portion 51 whose orthogonal projection on the substrate 10 is located within the orthogonal projection of the first electrode on the substrate. That is, the transition portion 51 is part of the third conductive layer 50.

[0135] like Figure 8E As shown, a passivation layer 60 is formed on the side of the third conductive layer 50 away from the substrate 10.

[0136] Next, a first electrode via is formed, wherein forming the first electrode via includes forming a first sub-via and forming a second sub-via, wherein the first sub-via exposes a portion of the first electrode, and the orthographic projection of the first sub-via on the substrate does not overlap with the orthographic projection of the transition portion on the substrate, and the second sub-via exposes a portion of the transition portion, and the orthographic projection of the second sub-via on the substrate overlaps with the orthographic projection of the transition portion on the substrate.

[0137] like Figure 8F As shown, photoresist 80 is first coated on the passivation layer 60.

[0138] like Figure 8G As shown, the coated photoresist 80 is exposed in segments, the photoresist area corresponding to the first sub-via is fully exposed, and the photoresist area corresponding to the second sub-via is partially exposed.

[0139] For example, a full-transparency exposure process is used to expose region Q1, and a semi-transparency exposure process is used to expose region Q2. Region Q1 is the photoresist region corresponding to the first sub-via, and region Q2 is the photoresist region corresponding to the second sub-via. This forms a... Figure 8G The structure of the photoresist film layer is shown.

[0140] like Figure 8H As shown, the film material in the region of the first sub-via is etched to expose the first electrode in the first conductive layer 20. The passivation layer corresponding to the region of the first sub-via and the insulating layer located between the passivation layer and the first electrode in the region corresponding to the first sub-via are etched using a first dry etching medium.

[0141] For example, a dry etching process is used, and the etching medium is a first etching medium, such as N2. The passivation layer material and gate insulating layer material of the first sub-via region are etched, and finally the first electrode in the first conductive layer 20 is exposed to form the bottom wall of the first sub-via.

[0142] like Figure 8I As shown, the photoresist material corresponding to the second sub-hole area is further etched. For example, the same dry etching process is used, and the etching medium is the second etching medium, such as O2, to etch away the photoresist material corresponding to the second sub-hole area.

[0143] like Figure 8J As shown, the passivation layer material corresponding to the second sub-hole region is etched again using the first dry etching medium. For example, O2 is used to etch away the passivation layer material corresponding to the second sub-hole region, exposing the transition portion 51 in the third conductive layer.

[0144] like Figure 8K As shown, the photoresist 80 located on the passivation layer is etched by the second dry etching medium to finally form the first electrode via VH1, which facilitates subsequent processes.

[0145] In one embodiment of this disclosure, by using a second dry etching medium to etch the photoresist on the passivation layer, the wet photoresist stripping process can be eliminated, simplifying the production steps and improving production efficiency. At the same time, it can solve the problem of excessive corrosion of the via caused by residual etching solution in the first electrode via.

[0146] In another embodiment of this disclosure, the photoresist 80 on the passivation layer 60 can be removed by a wet stripping process.

[0147] like Figure 8L As shown, a fourth conductive layer material 70 is formed in the first electrode via VH1, and the fourth conductive layer material electrically connects the first electrode to the transition portion 51 in the third conductive layer.

[0148] Figures 9A to 9G This is a cross-sectional structural schematic diagram of a method for manufacturing a display substrate according to another exemplary embodiment of the present disclosure.

[0149] Forming a first sub-via and forming a second sub-via includes: coating a first photoresist on the side of the passivation layer away from the substrate; fully exposing the first photoresist region corresponding to the first sub-via; etching the film material in the region corresponding to the first sub-via to expose the first electrode; stripping the first photoresist; coating a second photoresist on the side of the passivation layer away from the substrate so that a portion of the second photoresist fills the first sub-via; fully exposing the second photoresist region corresponding to the second sub-via; etching the film material in the region corresponding to the second sub-via to expose the transition portion, the exposed transition portion constituting the via sidewall of the first electrode via; and stripping the second photoresist. For example, the first and second photoresists can be the same photoresist.

[0150] The following is combined with Figures 9A to 9G A detailed explanation of the aforementioned process and Figures 8A to 8E The process is the same.

[0151] like Figure 9A As shown, after forming the passivation layer 60, photoresist 80 is coated on the passivation layer 60, and the first photoresist area corresponding to the first sub-via is fully exposed, thereby determining the area Q1 corresponding to the first sub-via.

[0152] like Figure 9B As shown, the film material corresponding to the region Q1 of the first sub-via is etched to expose the first electrode, for example, by etching the passivation layer 60 and the gate insulating layer 101, thereby exposing the first electrode in the first conductive layer 20.

[0153] like Figure 9C As shown, 80% of the photoresist is stripped off.

[0154] like Figure 9D As shown, photoresist 80 is coated on the side of passivation layer 60 away from the substrate, so that a portion of photoresist 80 fills the first sub-via.

[0155] like Figure 9E As shown, the region Q2 corresponding to the second sub-via is fully exposed, that is, the photoresist corresponding to the region of the second sub-via is exposed.

[0156] like Figure 9F As shown, the film material corresponding to region Q2 of the second sub-via is etched to expose the transition portion, which constitutes the via sidewall of the first electrode via. For example, a passivation layer is etched to form the second sub-via.

[0157] like Figure 9G As shown, the photoresist 80 is stripped to form a first electrode via VH1, which is composed of a first sub-via and a second sub-via.

[0158] Figure 10A This is a planar schematic diagram of the first electrode via manufactured using existing manufacturing methods. Figure 10B It is along Figure 10A The actual cross-sectional structure diagram with dashed lines. Figure 9C This is a plan view of a first electrode via manufactured according to a manufacturing method of an exemplary embodiment of the present disclosure. Figure 9D It is along Figure 10C The actual cross-sectional structure diagram with dashed lines.

[0159] like Figure 10A and Figure 10B As shown in the actual cross-sectional structure diagram of the first electrode via manufactured by the existing manufacturing method, in the existing manufacturing method, during the formation of the first electrode via, the area of ​​the first electrode via is fully exposed. After the material of the passivation layer is etched away, the transition portion 51 of the third conductive layer located below the passivation layer is exposed. At this time, the first electrode is not yet exposed, and the gate insulating layer needs to be etched further. Due to the "antenna effect" of the exposed third conductive layer, that is, the metal of the exposed transition portion will attract plasma, which will accelerate the etching rate near the lower side of the transition portion, thereby further etching the gate insulating layer on the lower side of the bottom of the transition portion. That is, the transition portion 51 extends into the first electrode via relative to the sidewall of the first electrode via to form a protrusion, and a defect D with a void is formed at the bottom, as shown. Figure 10B As shown, further etching of the gate insulating layer on the side of the transition near the substrate will expose the transition to prolonged plasma bombardment, posing a risk of surface oxidation and potentially causing poor contact. In subsequent processes, such as wet stripping of the photoresist on the passivation layer, defect D can leave stripping solution residue, leading to electrode via corrosion or poor overlap, thus reducing product yield.

[0160] In comparison, the manufacturing method of the display substrate according to the embodiments of this disclosure, such as Figure 10C and Figure 10D As shown, the portion of the transition portion 51 in the third conductive layer exposed in the first electrode via forms the via sidewall of the first electrode via, and the transition portion 51 does not protrude relative to the via sidewall. As a result, the opening area of ​​the first electrode via gradually decreases from the direction away from the substrate to the direction closer to the substrate. That is, there is no defect D in the first electrode via as in the existing manufacturing method. On the one hand, the problem of oxidation caused by long-term plasma bombardment of the exposed transition portion 51 is avoided, and on the other hand, the problem of electrode via corrosion caused by defect D is also avoided, thereby effectively improving the product yield of the display substrate.

[0161] Another aspect of this disclosure provides a display device including the display substrate described above, which is manufactured according to the manufacturing method described above.

[0162] The beneficial effects that the display device in the above embodiments of this disclosure can achieve are the same as the beneficial effects that the display substrate can achieve, and will not be repeated here.

[0163] The aforementioned display device can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it contains text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0164] While some embodiments of the general concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, include: A substrate having multiple sub-pixels arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect, and each sub-pixel includes at least one control transistor. A first conductive layer is disposed on one side of the substrate, and the first conductive layer includes first electrodes arranged at intervals in a second direction to form the sub-pixels. A second conductive layer is disposed on the side of the first conductive layer away from the substrate. The second conductive layer includes components spaced apart in a second direction and extending along the first direction to form the gate electrode of the control transistor. A semiconductor layer is disposed on the side of the second conductive layer away from the substrate, and the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate. A third conductive layer is disposed on the side of the semiconductor layer away from the substrate, and the third conductive layer includes a transition portion whose orthogonal projection on the substrate is located within the orthogonal projection of the first electrode on the substrate. A passivation layer is disposed on the side of the third conductive layer away from the substrate. A first electrode via penetrates the passivation layer and exposes the first electrode and a portion of the transition portion. The opening area of ​​the first electrode via gradually decreases from the direction away from the substrate towards the direction closer to the substrate. The exposed transition portion constitutes a portion of the via sidewall of the first electrode via. as well as A fourth conductive layer is disposed in the first electrode via, which electrically connects the first electrode to the adapter. The first electrode includes a common electrode, and each common electrode has a plurality of first electrode vias on the side away from the substrate. The third conductive layer further includes a connecting portion that electrically connects the transition portions of the adjacent common electrodes in the second direction. The connection portion is configured to electrically connect adjacent common electrodes in the second direction via a fourth conductive layer located within the first electrode via.

2. The display substrate according to claim 1, wherein, The via sidewall of the first electrode via includes a stepped portion; The stepped portion includes: a stepped top surface formed by the exposed surface of the transition portion away from the substrate; and The stepped side surface formed by the exposed transition portion facing the surface inside the first electrode via; Wherein, the opening area of ​​the first electrode via corresponding to the side of the step is greater than or equal to the opening area of ​​the first electrode via on the side of the step closer to the substrate.

3. The display substrate according to claim 2, wherein, The surface roughness of the side of the unexposed transition portion away from the substrate is less than the surface roughness of the top surface of the step.

4. The display substrate according to claim 2, wherein, The angle between the top surface of the step and the side surface of the step is ɵ, where 90° < ɵ < 180°.

5. The display substrate according to claim 2, wherein, The first electrode via exposes a portion of the semiconductor layer, and the exposed semiconductor layer constitutes part of the via sidewall of the first electrode via; The opening area of ​​the first electrode via corresponding to the semiconductor layer is less than or equal to the opening area of ​​the first electrode via corresponding to the step portion.

6. The display substrate according to any one of claims 1 to 5, wherein, The first electrode includes pixel electrodes, which are arranged at intervals in a first direction, with each pixel electrode corresponding to each sub-pixel; The third conductive layer further includes: Data signal lines are arranged at intervals in the first direction and extended along the second direction; and the first and second terminals constituting the control transistor; The first pole is electrically connected to the data signal line, and the second pole is electrically connected to the adapter.

7. The display substrate according to claim 6, wherein, The third conductive layer further includes: Voltage signal lines are arranged at intervals in the first direction and extended along the second direction; The voltage signal line is located between adjacent data signal lines; The sub-pixel is located between adjacent voltage signal lines and data signal lines.

8. The display substrate according to claim 7, wherein, The voltage signal line is electrically connected to the common electrode through the second electrode via.

9. The display substrate according to claim 8, wherein, The gate electrode is located between adjacent pixel electrodes; The orthographic projections of the first electrode and the second electrode on the substrate are located within the orthographic projection of the semiconductor layer on the substrate, and the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the gate electrode on the substrate; The gate electrode is configured to control the transmission of data signals from the data signal line through the control transistor, the adapter, and the fourth conductive layer to the pixel electrode.

10. The display substrate according to claim 9, wherein, The sub-pixel includes a first sub-pixel and a second sub-pixel that are adjacent in the first direction, the first sub-pixel and the second sub-pixel are located between adjacent data signal lines, and the voltage signal line is located between the first sub-pixel and the second sub-pixel; The gate electrode includes a first gate electrode and a second gate electrode, which are arranged adjacent to each other in the second direction. The first gate electrode is configured to control a control transistor of the first sub-pixel that is close to the first gate electrode; The second gate electrode is configured to control a control transistor of the second sub-pixel that is close to the second gate electrode.

11. The display substrate according to claim 1, wherein, The second conductive layer also includes voltage signal lines that are spaced apart in the second direction and extend along the first direction; The voltage signal line is electrically connected to the common electrode.

12. The display substrate according to claim 11, wherein, The gate electrode is disposed adjacent to the voltage signal line, and the gate electrode and the voltage signal line are located between adjacent common electrodes.

13. The display substrate according to claim 12, wherein, The third conductive layer also includes: Data signal lines are arranged at intervals in the first direction and extended along the second direction; and the first and second terminals constituting the control transistor; The first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the pixel electrode through a third electrode via.

14. A method for manufacturing a display substrate, wherein, include: A first conductive layer is formed on one side of a substrate. The first conductive layer includes first electrodes arranged at intervals in a second direction to form sub-pixels on the substrate. The sub-pixels on the substrate are arranged in an array along the first and second directions, and the first and second directions intersect. A second conductive layer is formed on the side of the first conductive layer away from the substrate. The second conductive layer includes components spaced apart in a second direction and extending along the first direction to form the gate electrode of a control transistor. A semiconductor layer is formed on the side of the second conductive layer away from the substrate, and the orthographic projection of the semiconductor layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate. A third conductive layer is formed on the side of the semiconductor layer away from the substrate, and the third conductive layer includes a transition portion whose orthogonal projection on the substrate is located within the orthogonal projection of the first electrode on the substrate. A passivation layer is formed on the side of the third conductive layer away from the substrate. A first electrode via is formed, which penetrates the passivation layer and exposes the first electrode and a portion of the transition portion. The opening area of ​​the first electrode via gradually decreases from the direction away from the substrate towards the direction closer to the substrate. The exposed transition portion constitutes a portion of the via sidewall of the first electrode via. as well as A fourth conductive layer is formed in the first electrode via, and the fourth conductive layer electrically connects the first electrode to the adapter. The first electrode includes a common electrode, and each common electrode has a plurality of first electrode vias on the side away from the substrate. The third conductive layer further includes a connecting portion that electrically connects the transition portions of the adjacent common electrodes in the second direction. The connection portion is configured to electrically connect adjacent common electrodes in the second direction via a fourth conductive layer located within the first electrode via.

15. The method according to claim 14, wherein, Forming the first electrode via includes: forming a first sub-via and forming a second sub-via. The first sub-via exposes a portion of the first electrode, and the orthographic projection of the first sub-via on the substrate does not overlap with the orthographic projection of the transition portion on the substrate. The second sub-via exposes a portion of the adapter portion, and the orthographic projection of the second sub-via on the substrate overlaps with the orthographic projection of the adapter portion on the substrate.

16. The method according to claim 15, wherein, The formation of the first sub-via and the formation of the second sub-via include: Photoresist is coated on the side of the passivation layer away from the substrate. The photoresist area corresponding to the first sub-via is fully exposed, and the photoresist area corresponding to the second sub-via is partially exposed. Etch the film material in the region corresponding to the first sub-via to expose the first electrode; Etch the film material in the region corresponding to the second sub-via to expose the transition portion. The exposed transition portion constitutes the via sidewall of the first electrode via.

17. The method according to claim 16, wherein, Etching the film material in the region corresponding to the first sub-via includes: The passivation layer corresponding to the first sub-via and the insulating layer located between the passivation layer and the first electrode are etched using a first dry etching medium.

18. The method according to claim 16, wherein, Etching the film material in the region corresponding to the second sub-via includes: The photoresist material corresponding to the second sub-via region is etched using a second dry etching medium. The passivation layer material corresponding to the second sub-via region is etched using a first dry etching medium.

19. The method of claim 16, wherein, Also includes: The photoresist located on the passivation layer is etched using a second dry etching medium.

20. The method of claim 15, wherein, The formation of the first sub-via and the formation of the second sub-via include: A first photoresist is coated on the side of the passivation layer away from the substrate. The first photoresist area corresponding to the first sub-via is fully exposed; Etch the film material in the region corresponding to the first sub-via to expose the first electrode; The first photoresist is peeled off; A second photoresist is coated on the side of the passivation layer away from the substrate, so that a portion of the second photoresist fills the first sub-via. The second photoresist region corresponding to the second sub-via is fully exposed; Etch the film material in the region corresponding to the second sub-via to expose the transition portion, the exposed transition portion forming the via sidewall of the first electrode via; The second photoresist is peeled off.

21. A display device, wherein, include: The display substrate according to any one of claims 1 to 13.

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