Vertically stacked full-color Micro-LED chips and display modules

Abstract

This application proposes a vertically stacked full-color Micro-LED chip and display module, comprising a first sub-chip, a second sub-chip, and a third sub-chip. The first, second, and third sub-chips are each provided with an insulating layer on their sidewalls and upper and lower surfaces. Each of the first, second, and third sub-chips comprises an n-type electrode, an n-type semiconductor layer, a multi-quantum well light-emitting layer, a p-type semiconductor layer, and a p-type electrode, with the multi-quantum well light-emitting layer located between the n-type and p-type semiconductor layers. The first sub-chip emits blue light, the second sub-chip emits green light, and the third sub-chip emits red light, with the three stacked vertically. The second sub-chip is located between the first and third sub-chips. The p-type semiconductor layer of the first sub-chip faces the p-type semiconductor layer of the second sub-chip, while the n-type semiconductor layer of the first sub-chip is spaced apart from the n-type semiconductor layer of the second sub-chip. This achieves a highly reliable vertically stacked full-color Micro-LED chip.

Description

Technical Field

[0001] The present application relates to the field of Micro-LED display technology, and specifically to vertically stacked full-color Micro-LED chips and display modules. Background Art

[0002] Micro-LED display is a highly competitive next-generation display technology. Full-color display is an essential feature of display products. Liquid crystal displays use color filters corresponding to each pixel to convert the white light emitted by the backlight into monochromatic light of the three primary colors of red, green, and blue (RGB), achieving full-color display; each pixel of OLED displays uses RGB three primary colors of luminescent materials, thereby achieving self-luminous full-color display. At present, the technical routes of Micro-LED full-color display are divided into three categories: (1) Three-primary color Micro-LED chip array, using RGB three primary colors Micro-LED chips to be arranged into a pixel array at intervals to achieve full-color display. The characteristic of this solution is that all Micro-LED chips are used as light-emitting units, and no other light-emitting materials are required. This solution is mainly for large-size, medium-resolution display applications such as televisions; (2) Blue light Micro-LED chip array combined with red and green light fluorescence conversion. Blue light Micro-LED chips are arranged into an array, and then according to the red, green, and blue pixel points, red and green light fluorescent materials are coated on the surface of the Micro-LED chips corresponding to the red and green light pixels respectively. The fluorescent material absorbs the blue light emitted by the chip below it and converts it into red and green light in the form of photoluminescence. The pixel positions not coated with fluorescent material serve as blue light pixels, thereby realizing RGB full-color display. The main technical challenge of this solution lies in how to realize a high-reliability and low-cost fluorescent conversion layer; (3) The three primary color Micro-LEDs are vertically stacked to form a single-chip full-color Micro-LED with a laminated structure. The advantage is that the area of ​​a single pixel in the Micro-LED display can be reduced to achieve high-resolution display, which is particularly suitable for near-eye display applications such as AR display.

[0003] In recent years, with the continuous development of Micro-LED technology, the path to industrialization of Micro-LED displays has gradually become clearer. The industry generally believes that near-eye displays, such as AR displays, will be the first mass-produced applications for Micro-LED displays. However, vertically stacking full-color Micro-LED chips still faces serious process challenges. The three epitaxial layers are grown separately on their own substrates, and then the red, green, and blue epitaxial layers, peeled from the substrate, are bonded together, presenting serious challenges such as stress mismatch and workability. Summary of the Invention

[0004] In order to solve the above technical problems, the first aspect of the present application proposes a vertically stacked full-color Micro-LED chip, which is provided with a first sub-chip, a second sub-chip, and a third sub-chip. The side walls and upper and lower surfaces of the first sub-chip, the second sub-chip and the third sub-chip are provided with an insulating layer, and the first sub-chip, the second sub-chip and the third sub-chip are provided with an n-type electrode, an n-type semiconductor layer, a multi-quantum well light-emitting layer, a p-type semiconductor layer and a p-type electrode. The multi-quantum well light-emitting layer is located between the n-type semiconductor layer and the p-type semiconductor layer; the first sub-chip emits blue light, the second sub-chip emits green light, and the third sub-chip emits red light, and the three are stacked vertically; the second sub-chip is located between the first sub-chip and the third sub-chip; the p-type semiconductor layer of the first sub-chip and the p-type semiconductor layer of the second sub-chip are arranged face to face, and the n-type semiconductor layer of the first sub-chip and the n-type semiconductor layer of the second sub-chip are far away from each other.

[0005] The above technical solution provides a vertically stacked full-color Micro-LED chip structure. By arranging three sub-chips, each emitting blue, green, and red light, and stacking them vertically, full-color display is achieved. The insulating layers on the sidewalls and upper and lower surfaces of the sub-chips, along with the specific layout of each layer, ensure the proper operation and luminous effect of the chip.

[0006] Specifically, a carrier medium layer is arranged between the first sub-chip and the second sub-chip, and a first metal wiring layer and a second metal wiring layer are arranged on the upper and lower surfaces of the carrier medium layer respectively; the p-type electrode of the first sub-chip is bonded to the first metal wiring layer; the p-type electrode of the second sub-chip is bonded to the second metal wiring layer; the first metal wiring layer is connected to the lower surface of the carrier medium layer through a metallized via.

[0007] The above technical solution sets a carrier medium layer and a metal wiring layer between the first sub-chip and the second sub-chip, realizes the bonding and electrical connection between the sub-chips, ensures the transmission of signals, solves the connection and electrical conduction problems between the sub-chips, and ensures the normal operation of the chips.

[0008] Specifically, an adhesive layer is provided between the second sub-chip and the third sub-chip; the n-type semiconductor layer of the second sub-chip and the n-type semiconductor layer of the third sub-chip are bonded back to back on upper and lower sides of the adhesive layer.

[0009] The above technical solution bonds the second sub-chip and the third sub-chip back to back together through the bonding layer, thereby achieving stable stacking of the chips and stable connection between the second sub-chip and the third sub-chip.

[0010] Specifically, a first filling layer is provided above the carrier medium layer to cover the first sub-chip; a second filling layer is provided between the carrier medium layer and the adhesive layer to cover the second sub-chip; and a third filling layer is provided below the adhesive layer to cover the third sub-chip.

[0011] The above technical solution sets a first filling layer, a second filling layer and a third filling layer to respectively cover the corresponding sub-chips, play a role in protection and fixation, protect the sub-chips, and improve the stability and reliability of the chip.

[0012] Specifically, a deep blind hole is provided, which passes through the first filling layer, the supporting medium layer, the second filling layer and the bonding layer in sequence. A metal film layer is provided inside the deep blind hole, and the metal film layer connects the first sub-chip n-type electrode, the second sub-chip n-type electrode and the third sub-chip n-type electrode together in sequence to achieve electrical conduction.

[0013] The above technical solution connects the n-type electrode of the first sub-chip, the n-type electrode of the second sub-chip and the n-type electrode of the third sub-chip in sequence through deep blind holes and the internal metal film layer, thereby achieving electrical conductivity, ensuring the normal operation of the chip, and solving the problem of electrical conductivity of the n-type electrodes between the sub-chips.

[0014] Specifically, the light in the first sub-chip's light-emitting band cannot pass through the carrying medium layer, and the light in the first sub-chip's light-emitting band and the light in the second sub-chip's light-emitting band cannot pass through the adhesive layer; the light in the second sub-chip's light-emitting band and the light in the third sub-chip's light-emitting band pass through the carrying medium layer, and the light in the third sub-chip's light-emitting band passes through the adhesive layer.

[0015] The above technical solution stipulates the conditions under which light in the luminous band of each sub-chip passes through different dielectric layers, ensuring the normal emission and display effect of light, ensuring that the emission and transmission of light meet the design requirements, and achieving good display effects.

[0016] Specifically, vertical symmetry center lines of the first sub-chip, the second sub-chip, and the third sub-chip coincide with each other.

[0017] The above technical solution enables the vertical symmetry center lines of the first sub-chip, the second sub-chip and the third sub-chip to coincide, thereby improving the stability and symmetry of the chip.

[0018] Specifically, the bottom of the p-type electrode of the third sub-chip is exposed outside the third filling layer; a first electrode and a second electrode are also provided, the first electrode passes through the third filling layer, the adhesive layer and the second filling layer to be connected to the metallized via, and the second electrode passes through the third filling layer, the adhesive layer and the second filling layer to be connected to the second metal wiring layer.

[0019] The above technical solution provides the first electrode and the second electrode, thereby achieving the bonding of the p-type electrode of the third sub-chip and the pixel driving pad, and the connection of the second metal wiring layer with other parts.

[0020] It solves the connection problem between the chip and the external circuit, ensuring signal transmission and control.

[0021] In the second aspect of the present application, a vertically stacked full-color Micro-LED display module is provided, including the above-mentioned vertically stacked full-color Micro-LED chip, as well as a CMOS driving backplane and a common electrode; the CMOS driving backplane is provided with a pixel driving pad and a common electrode pad; the pixel driving pad is arranged in an array, and multiple vertically stacked full-color Micro-LED chips are arranged in an array, and the metal film layers of the vertically stacked full-color Micro-LED chips in the array are connected and share a first filling layer, a carrying medium layer, a second filling layer, an adhesive layer and a third filling layer; the p-type electrode, the second electrode and the third electrode of the third sub-chip are respectively bonded to the corresponding pixel driving pad; the common electrode passes through the first filling layer, the carrying medium layer, the second filling layer, the adhesive layer and the third filling layer, and the common electrode is bonded to the common electrode pad.

[0022] The above technical solution combines vertically stacked full-color Micro-LED chips with a CMOS driver backplane and common electrodes to form a display module, realizing the driving and control of the chips. Multiple chips are arranged into an array and share related layers, thereby improving the integration and performance of the display module.

[0023] Specifically, a light extraction lens is further provided, and the light extraction lens corresponds one-to-one to the first sub-chip, the second sub-chip, and the third sub-chip.

[0024] The above technical solution sets a light extraction lens, which corresponds one-to-one with the sub-chip, thereby improving the light extraction efficiency and display effect.

[0025] Compared with the prior art, the beneficial results of this application are:

[0026] 1. It achieves full-color display of Micro-LED chips by vertically stacking three sub-chips, emitting blue, green, and red light respectively, providing an effective full-color display solution;

[0027] 2. Ensure the connection and electrical conduction of each part of the chip, and ensure stable signal transmission through the structure of the carrier dielectric layer, metal wiring layer, adhesive layer, deep blind hole and metal film layer;

[0028] 3. It plays a good role in protecting and fixing the sub-chip, and the setting of the filling layer improves the stability and reliability of the chip;

[0029] 4. It specifies the light transmittance, ensures the normal emission and display effect of light, and helps to achieve good image display;

[0030] 5. Make the chip more stable and symmetrical, and improve the performance and reliability of the chip;

[0031] 6. A display module is formed, which realizes the driving and control of the chip and improves the integration and performance of the display module;

[0032] 7. Setting a light extraction lens improves the light extraction efficiency and the brightness and clarity of the display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and, together with the description, serve to explain the principles of the present application. Other embodiments and many of the expected advantages of the embodiments will be readily apparent as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals designate corresponding similar parts.

[0034] Figure 1 2. This is a schematic diagram of the structure of a vertically stacked full-color Micro-LED chip according to an embodiment of the present application;

[0035] Figure 2 2 is a schematic structural diagram of a vertically stacked full-color Micro-LED display module according to an embodiment of the present application;

[0036] Figure 3 This is a structural diagram of a vertically stacked full-color Micro-LED display module according to the second embodiment of the present application. Description of the drawings:

[0038] 1. First sub-chip; 2. Second sub-chip; 3. Third sub-chip; 4. Carrying dielectric layer; 5. Adhesive layer; 6. First filling layer; 7. Second filling layer; 8. Third filling layer; 9. Deep blind hole; 10. Metal film layer; 11. P-type semiconductor layer of the first sub-chip; 12. N-type semiconductor layer of the first sub-chip; 13. P-type electrode of the first sub-chip; 14. N-type electrode of the first sub-chip; 21. P-type semiconductor layer of the second sub-chip; 22. N-type semiconductor layer of the second sub-chip; 23. P-type electrode of the second sub-chip; 32. N-type semiconductor layer of the third sub-chip; 33. N-type electrode of the second sub-chip; 34. N-type electrode of the third sub-chip; 41. First metal wiring layer; 42. Second metal wiring layer; 101. First electrode; 102. Second electrode; 111. CMOS driver backplane; 112. Pixel driver pad; 113. Common electrode pad; 114. Common electrode; 120. Light extraction lens. DETAILED DESCRIPTION

[0039] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and are shown by illustrative specific embodiments in which the present application can be practiced. In this regard, directional terms, such as "top", "bottom", "left", "right", "up", "down", etc., are used with reference to the orientation of the figures being described. Because the components of the embodiments can be positioned in several different orientations, directional terms are used for illustrative purposes and are in no way limiting. It should be understood that other embodiments can be utilized or logical changes can be made without departing from the scope of the present application. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

[0040] like Figure 1 As shown, a vertically stacked full-color Micro-LED chip is provided with a first sub-chip 1, a second sub-chip 2, and a third sub-chip 3. The side walls and upper and lower surfaces of the first sub-chip 1, the second sub-chip 2, and the third sub-chip 3 are provided with an insulating layer. The first sub-chip 1, the second sub-chip 2, and the third sub-chip 3 are all provided with an n-type electrode, an n-type semiconductor layer, a multi-quantum well light-emitting layer, a p-type semiconductor layer, and a p-type electrode. The multi-quantum well light-emitting layer is located between the n-type semiconductor layer and the p-type semiconductor layer; the first sub-chip 1 emits blue light, the second sub-chip 2 emits green light, and the third sub-chip 3 emits red light, and the three are stacked vertically; the second sub-chip 2 is located between the first sub-chip 1 and the third sub-chip 3; the p-type semiconductor layer of the first sub-chip 1 and the p-type semiconductor layer of the second sub-chip 2 are arranged face to face, and the n-type semiconductor layer of the first sub-chip 1 and the n-type semiconductor layer of the second sub-chip 2 are far away from each other.

[0041] Specifically, a carrier dielectric layer 4 is arranged between the first sub-chip 1 and the second sub-chip 2, and a first metal wiring layer 41 and a second metal wiring layer 42 are respectively arranged on the upper and lower surfaces of the carrier dielectric layer 4; the p-type electrode of the first sub-chip 1 is bonded to the first metal wiring layer 41; the p-type electrode of the second sub-chip 2 is bonded to the second metal wiring layer 42; the first metal wiring layer 41 is connected to the lower surface of the carrier dielectric layer 4 through metallized vias.

[0042] Specifically, an adhesive layer 5 is provided between the second sub-chip 2 and the third sub-chip 3 ; the n-type semiconductor layer of the second sub-chip 2 and the n-type semiconductor layer of the third sub-chip 3 are bonded back to back on upper and lower sides of the adhesive layer 5 .

[0043] Specifically, a first filling layer 6 is provided above the carrier medium layer 4 to cover the first sub-chip 1; a second filling layer 7 is provided between the carrier medium layer 4 and the adhesive layer 5 to cover the second sub-chip 2; and a third filling layer 8 is provided below the adhesive layer 5 to cover the third sub-chip 3.

[0044] Specifically, a deep blind hole 9 is also provided, which passes through the first filling layer 6, the supporting medium layer 4, the second filling layer 7 and the bonding layer 5 in sequence. A metal film layer 10 is provided inside the deep blind hole 9. The metal film layer 10 connects the first sub-chip 1n-type electrode, the second sub-chip 2n-type electrode and the third sub-chip 3n-type electrode in sequence to achieve electrical conduction.

[0045] Specifically, the light in the light-emitting band of the first sub-chip 1 cannot pass through the carrying medium layer 4, and the light in the light-emitting band of the first sub-chip 1 and the light in the light-emitting band of the second sub-chip 2 cannot pass through the adhesive layer 5; the light in the light-emitting band of the second sub-chip 2 and the light in the light-emitting band of the third sub-chip 3 pass through the carrying medium layer 4, and the light in the light-emitting band of the third sub-chip 3 passes through the adhesive layer 5.

[0046] Specifically, the vertical symmetry center lines of the first sub-chip 1 , the second sub-chip 2 , and the third sub-chip 3 coincide with each other.

[0047] Specifically, the bottom of the p-type electrode of the third sub-chip 3 is exposed outside the third filling layer 8; a first electrode 101 and a second electrode 102 are also provided. The first electrode 101 passes through the third filling layer 8, the adhesive layer 5 and the second filling layer 7 to be connected to the metallized via, and the second electrode 102 passes through the third filling layer 8, the adhesive layer 5 and the second filling layer 7 to be connected to the second metal wiring layer 42.

[0048] like Figure 2-Figure 3 As shown, the vertically stacked full-color Micro-LED display module includes the above-mentioned vertically stacked full-color Micro-LED chips, as well as a CMOS driving backplane 111 and a common electrode 114; the CMOS driving backplane 111 is provided with a pixel driving pad 112 and a common electrode 114 pad 113; the pixel driving pad 112 is arranged in an array, and multiple vertically stacked full-color Micro-LED chips are arranged in an array, and the metal film layer 10 of the vertically stacked full-color Micro-LED chips in the array is connected and shares the first filling layer 6, the carrying medium layer 4, the second filling layer 7, the bonding layer 5 and the third filling layer 8; the third sub-chip 3p-type electrode, the second electrode 102 and the third electrode are respectively bonded to the corresponding pixel driving pad 112; the common electrode 114 passes through the first filling layer 6, the carrying medium layer 4, the second filling layer 7, the bonding layer 5 and the third filling layer 8, and the common electrode 114 is bonded to the common electrode 114 pad 113.

[0049] Specifically, a light extraction lens 120 is further provided, and the light extraction lens 120 corresponds one-to-one to the first sub-chip 1 , the second sub-chip 2 , and the third sub-chip 3 .

[0050] In a specific embodiment,

[0051] A vertically stacked full-color Micro-LED chip is provided with a first sub-chip 1, a second sub-chip 2, and a third sub-chip 3. The first sub-chip 1, the first sub-chip 1, the second sub-chip 2, and the third sub-chip 3 are all provided with an n-type electrode, an n-type semiconductor layer, a multi-quantum well light-emitting layer, a p-type semiconductor layer, and a p-type electrode. The multi-quantum well light-emitting layer is located between the n-type semiconductor layer and the p-type semiconductor layer. The first sub-chip 1 emits blue light, the second sub-chip 2 emits green light, and the third sub-chip 3 emits red light. The three are stacked vertically longitudinally, and the second sub-chip 2 is located between the first sub-chip 1 and the third sub-chip 3. It is characterized in that the p-type semiconductor layer of the first sub-chip 1 and the p-type semiconductor layer of the second sub-chip 2 are arranged face to face, and the n-type semiconductor layer of the first sub-chip 1 and the n-type semiconductor layer of the second sub-chip 2 are far away from each other.

[0052] The n-type semiconductor layer of the first sub-chip 1 and the second sub-chip 2 also includes a buffer layer, and the multi-quantum well light-emitting layer is composed of a chemical formula of Al x In y Ga z The chip is composed of two semiconductor layers of different compositions, each with a thickness of nanometers, stacked alternately. The p-type semiconductor layer also includes an electron blocking layer. The first sub-chip 1 emits light in the blue band, with a typical peak wavelength of 467 nm. The second sub-chip 2 emits light in the green band, with a typical peak wavelength of 532 nm.

[0053] The n-type semiconductor layer of the third sub-chip 3 contains at least one layer of doped AlGaAs, and the multi-quantum well light-emitting layer is composed of a chemical formula of Al x Ga y In z The third sub-chip 3 emits light in the red band, with a typical peak wavelength of 625 nm.

[0054] A carrier dielectric layer 4 is arranged between the first sub-chip 1 and the second sub-chip 2, and a first metal wiring layer 41 and a second metal wiring layer 42 are respectively arranged on the upper and lower surfaces of the carrier dielectric layer 4. The p-type electrode of the first sub-chip 1 is bonded to the first metal wiring layer 41, and the p-type electrode of the second sub-chip 2 is bonded to the second metal wiring layer 42. The first metal wiring layer 41 is connected to the lower surface of the carrier dielectric layer 4 through metallized vias.

[0055] An adhesive layer 5 is provided between the second sub-chip 2 and the third sub-chip 3. The n-type semiconductor layer of the second sub-chip 2 and the n-type semiconductor layer of the third sub-chip 3 are bonded back to back on the upper and lower sides of the adhesive layer 5.

[0056] A first filling layer 6 is provided above the carrier dielectric layer 4, covering the first sub-chip 1. A second filling layer 7 is provided between the carrier dielectric layer 4 and the adhesive layer 5, covering the second sub-chip 2. A third filling layer 8 is provided below the adhesive layer 5, covering the third sub-chip 3.

[0057] The vertically stacked full-color Micro-LED chip is provided with a deep blind hole 9, which passes through the first filling layer 6, the carrying medium layer 4, the second filling layer 7, and the bonding layer 5 in sequence. A metal film layer 10 is provided inside the deep blind hole 9. The metal film layer 10 connects the n-type electrode of the first sub-chip 1, the n-type electrode of the second sub-chip 2, and the n-type electrode of the third sub-chip 3 together to achieve electrical conduction.

[0058] The light in the emission band of the first sub-chip 1 cannot pass through the carrying medium layer 4, the light in the emission band of the first sub-chip 1 and the light in the emission band of the second sub-chip 2 cannot pass through the adhesive layer 5, the light in the emission band of the second sub-chip 2 and the light in the emission band of the third sub-chip 3 can pass through the carrying medium layer 4, and the light in the emission band of the third sub-chip 3 can pass through the adhesive layer 5.

[0059] The vertical symmetry center lines of the first sub-chip 1 , the second sub-chip 2 , and the third sub-chip 3 coincide with each other.

[0060] The bottom of the p-type electrode of the third sub-chip is exposed outside the third filling layer 8. The vertically stacked full-color Micro-LED chip is provided with a first electrode 101 and a second electrode 102. The first electrode 101 passes through the third filling layer 8, the adhesive layer 5, and the second filling layer 7 to be connected to the metallized via. The second electrode 102 passes through the third filling layer 8, the adhesive layer 5, and the second filling layer 7 to be connected to the second metal wiring layer 42.

[0061] A display module based on vertically stacked full-color Micro-LED chips is provided with a CMOS driving backplane 111, and the CMOS driving backplane 111 is provided with pixel driving pads 112 and common electrode 114 pads 113. The pixel driving pads 112 are arranged in an array, and multiple vertically stacked full-color Micro-LED chips are arranged in an array. The metal film layers 10 of the vertically stacked full-color Micro-LED chips in the array are connected and share the first filling layer 6, the carrying medium layer 4, the second filling layer 7, the bonding layer 5, and the third filling layer 8. The p-type electrode, the first electrode 101, and the second electrode 102 of the third sub-chip are respectively bonded to the corresponding pixel driving pads 112, and a common electrode 114 is provided. The common electrode 114 passes through the first filling layer 6, the carrying medium layer 4, the second filling layer 7, the bonding layer 5, and the third filling layer 8, and the common electrode 114 is bonded to the common electrode 114 pad 113.

[0062] In another embodiment,

[0063] A light extraction lens 120 is further provided above the vertically stacked full-color Micro-LED chip in the display module based on the vertically stacked full-color Micro-LED chip, and the light extraction lens 120 corresponds one-to-one to the vertically stacked full-color Micro-LED chip.

[0064] The rest is the same as the previous embodiment.

[0065] This instance has the following advantages:

[0066] (1) With this structure, the first and second sub-chips can be processed on the epitaxial substrate respectively, and then the two can be bonded to the carrier dielectric layer. Then, the substrates of the two can be peeled off, and the third sub-chip can be bonded under the support of the carrier dielectric layer, thus avoiding the stress mismatch problem in the traditional technical solution of first bonding the epitaxial layer and then processing the chip;

[0067] (2) The carrier medium layer and the adhesive layer can shield the light from passing through from above and avoid optical crosstalk.

[0068] Obviously, those skilled in the art can make various modifications and changes to the embodiments of the present application without departing from the spirit and scope of the present application. In this way, if these modifications and changes are within the scope of the claims of the present application and their equivalents, the present application is also intended to cover these modifications and changes. The word "comprising" does not exclude the presence of other elements or steps not listed in the claims. The simple fact that certain measures are recited in mutually different dependent claims does not indicate that the combination of these measures cannot be used to advantage. Any reference signs in the claims should not be considered as limiting the scope.

Claims

1. A vertically stacked full-color Micro-LED chip, comprising a first sub-chip, a second sub-chip, and a third sub-chip, characterized in that: The side walls and upper and lower surfaces of the first sub-chip, the second sub-chip and the third sub-chip are all provided with an insulating layer. The first sub-chip, the second sub-chip and the third sub-chip are all provided with an n-type electrode, an n-type semiconductor layer, a multi-quantum well light-emitting layer, a p-type semiconductor layer and a p-type electrode. The multi-quantum well light-emitting layer is located between the n-type semiconductor layer and the p-type semiconductor layer; the first sub-chip emits blue light, the second sub-chip emits green light, and the third sub-chip emits red light, and the three are stacked vertically; the second sub-chip is located between the first sub-chip and the third sub-chip; the p-type semiconductor layer of the first sub-chip and the p-type semiconductor layer of the second sub-chip are arranged face to face, and the n-type semiconductor layer of the first sub-chip and the n-type semiconductor layer of the second sub-chip are far away from each other.

2. The vertically stacked full-color Micro-LED chip according to claim 1, wherein: A carrier dielectric layer is arranged between the first sub-chip and the second sub-chip, and a first metal wiring layer and a second metal wiring layer are arranged on the upper and lower surfaces of the carrier dielectric layer respectively; the p-type electrode of the first sub-chip is bonded to the first metal wiring layer; the p-type electrode of the second sub-chip is bonded to the second metal wiring layer; the first metal wiring layer is connected to the lower surface of the carrier dielectric layer through a metallized via.

3. The vertically stacked full-color Micro-LED chip according to claim 2, wherein: An adhesive layer is provided between the second sub-chip and the third sub-chip; the n-type semiconductor layer of the second sub-chip and the n-type semiconductor layer of the third sub-chip are bonded back to back on upper and lower sides of the adhesive layer.

4. The vertically stacked full-color Micro-LED chip according to claim 3, wherein: A first filling layer is provided above the carrier medium layer to cover the first sub-chip; a second filling layer is provided between the carrier medium layer and the adhesive layer to cover the second sub-chip; and a third filling layer is provided below the adhesive layer to cover the third sub-chip.

5. The vertically stacked full-color Micro-LED chip according to claim 4, wherein: A deep blind hole is also provided, which passes through the first filling layer, the supporting medium layer, the second filling layer and the bonding layer in sequence. A metal film layer is provided inside the deep blind hole, and the metal film layer connects the first sub-chip n-type electrode, the second sub-chip n-type electrode and the third sub-chip n-type electrode together in sequence to achieve electrical conduction.

6. The vertically stacked full-color Micro-LED chip according to claim 5, wherein: The light in the light-emitting band of the first sub-chip cannot pass through the carrying medium layer, and the light in the light-emitting band of the first sub-chip and the light in the light-emitting band of the second sub-chip cannot pass through the adhesive layer; the light in the light-emitting band of the second sub-chip and the light in the light-emitting band of the third sub-chip pass through the carrying medium layer, and the light in the light-emitting band of the third sub-chip passes through the adhesive layer.

7. The vertically stacked full-color Micro-LED chip according to claim 1, wherein: The vertical symmetry center lines of the first sub-chip, the second sub-chip and the third sub-chip coincide with each other.

8. The vertically stacked full-color Micro-LED chip according to claim 6, wherein: The bottom of the p-type electrode of the third sub-chip is exposed outside the third filling layer; a first electrode and a second electrode are also provided, the first electrode passes through the third filling layer, the adhesive layer and the second filling layer to be connected to the metallized via, and the second electrode passes through the third filling layer, the adhesive layer and the second filling layer to be connected to the second metal wiring layer.

9. Vertically stacked full-color Micro-LED display module, characterized by: It comprises a vertically stacked full-color Micro-LED chip as described in any one of claims 1 to 8, as well as a CMOS driving backplane and a common electrode; the CMOS driving backplane is provided with a pixel driving pad and a common electrode pad; the pixel driving pad is arranged in an array, and a plurality of the vertically stacked full-color Micro-LED chips are arranged in an array, and the metal film layers of the vertically stacked full-color Micro-LED chips in the array are connected and share a first filling layer, a carrying medium layer, a second filling layer, an adhesive layer and a third filling layer; the p-type electrode, the second electrode and the third electrode of the third sub-chip are respectively bonded to the corresponding pixel driving pad; the common electrode passes through the first filling layer, the carrying medium layer, the second filling layer, the adhesive layer and the third filling layer, and the common electrode is bonded to the common electrode pad.

10. The vertically stacked full-color Micro-LED display module according to claim 9, wherein: A light extraction lens is also provided, and the light extraction lens corresponds one-to-one to the first sub-chip, the second sub-chip and the third sub-chip.

Images