Array substrate, display panel, driving method of display panel and display device

Abstract

The invention discloses an array substrate, a display panel, a driving method of the display panel and a display device. The array substrate comprises a substrate body, a plurality of sub-pixels, a plurality of grid lines and a plurality of data lines, wherein the sub-pixels, the grid lines and the data lines are arranged on the substrate body. The plurality of sub-pixels are arranged on the substrate in an array manner, the plurality of sub-pixels form a plurality of pixel groups, each pixel group comprises a first sub-pixel and a second sub-pixel, the first sub-pixel comprises a first transistor and a first electrode group which are connected with each other, and the second sub-pixel comprises a second transistor and a second electrode group which are connected with each other; the first transistor and the second transistor are both located between the first electrode group and the second electrode group and located at the two ends of the pixel group in the column direction respectively; the first electrode group comprises a first pixel electrode and a first common electrode, and the second electrode group comprises a second pixel electrode and a second common electrode. Wherein the overlapping area of the first pixel electrode and the first common electrode is equal to the overlapping area of the second pixel electrode and the second common electrode.

Description

Array substrate, display panel, display panel driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a driving method for a display panel, and a display device. Background Art

[0002] In the field of display technology, display panels and display devices are typically driven by thin-film transistors. With the advancement of display technology, dual-gate drive is often used to drive pixel arrays to reduce costs. This dual-gate drive method can halve the number of data lines compared to traditional drive methods, thereby reducing the number of source driver circuits, and thus the number of driver chips, thereby lowering costs.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate includes a base substrate, a plurality of sub-pixels disposed on the base substrate, a plurality of gate lines, and a plurality of data lines. The plurality of sub-pixels are arranged in an array on the base substrate, the plurality of sub-pixels being arranged in E rows and F columns; the plurality of sub-pixels form a plurality of pixel groups, each of the pixel groups including a first sub-pixel and a second sub-pixel, the first sub-pixel including a first transistor and a first electrode group connected thereto, the second sub-pixel including a second transistor and a second electrode group connected thereto; the first electrode group and the second electrode group are arranged sequentially along the row direction; the first transistor and the second transistor are both located between the first electrode group and the second electrode group, and are respectively located at both ends of the pixel group along the column direction; the first electrode group includes a first pixel electrode and a first common electrode, the second electrode group includes a second pixel electrode and a second common electrode. The plurality of gate lines form a plurality of gate line groups, each of the plurality of gate line groups including a first gate line and a second gate line, and the first sub-pixel and the second sub-pixel of each pixel group are respectively connected to the first gate line and the second gate line of a gate line group. A plurality of data lines are arranged on the base substrate, and the first sub-pixel and the second sub-pixel of each pixel group are connected to one of the data lines; at least some of the plurality of data lines include a third data segment extending in the row direction, a first data segment and a second data segment extending in the column direction, the third data segment connects the first data segment and the second data segment, the first data segment is arranged between the sub-pixel in the i-th column and the sub-pixel in the (i+1)-th column, and the second data segment is arranged between the sub-pixel in the (ij)-th column and the sub-pixel in the (ij-1)-th column, where j is greater than or equal to 1; i+1≤F; wherein an overlapping area between the first pixel electrode and the first common electrode is equal to an overlapping area between the second pixel electrode and the second common electrode.

[0005] In some embodiments, j=1; the two outermost data lines in the row direction are the first data line and the second data line, the first data segment of the first data line is set between the first column sub-pixel and the second column sub-pixel, and the second data segment of the first data line is set on the side of the first column sub-pixel away from the multiple columns of sub-pixels; the first data segment of the second data line is set on the side of the F column sub-pixel away from the multiple columns of sub-pixels, and the second data segment of the first data line is set between the (F-1) column sub-pixel and the F column sub-pixel.

[0006] In some embodiments, at least a portion of the data line connected to the pixel group is located between the first electrode group and the second electrode group of the pixel group; at least a portion of the data line is the first data segment or the second data segment; the first electrode of the first transistor and the first electrode of the second transistor are both connected to the data line, the second electrode of the first transistor is connected to the first pixel electrode, and the second electrode of the second transistor is connected to the second pixel electrode; the first electrode of the first transistor points to the second electrode, and the direction parallel to the row direction is the first direction, the first electrode of the second transistor points to the second electrode, and the direction parallel to the row direction is the second direction, and the first direction is opposite to the second direction.

[0007] In some embodiments, the first transistor and the second transistor both include a gate, an active layer, and a source and drain that are stacked in sequence, the source and drain include a first pole and a second pole, the orthographic projection of the active layer on the base substrate falls within the orthographic projection of the gate on the base substrate, and at least part of the orthographic projections of the first pole and the second pole on the base substrate falls within the orthographic projection of the active layer on the base substrate; the orthographic projection of the first pole is U-shaped, and the opening of the first pole faces the second pole.

[0008] In some embodiments, the first pixel electrode and the second pixel electrode are block electrodes, the first common electrode and the second common electrode are strip electrodes, and the first common electrode and the second common electrode each include a plurality of slits; the aperture ratio of the first sub-pixel is equal to the aperture ratio of the second sub-pixel; the first electrode group includes a first domain region and a second domain region arranged along the column direction, and the second electrode group includes a third domain region and a fourth domain region arranged along the column direction, and the aperture ratios of the first domain region, the second domain region, the third domain region and the fourth domain region are equal.

[0009] In some embodiments, the array substrate further includes: a first spacer arranged on the side of the first transistor away from the base substrate, and a second spacer arranged on the side of the second transistor away from the base substrate; the center of the positive projection of the first spacer on the base substrate is offset by a first distance toward a third direction relative to the center of the positive projection of the first transistor on the base substrate, and the third direction is the direction in which the first transistor points to the second transistor; the center of the positive projection of the second spacer on the base substrate is offset by a second distance toward a fourth direction relative to the center of the positive projection of the second transistor on the base substrate, and the fourth direction is the direction in which the second transistor points to the first transistor.

[0010] In some embodiments, the first distance is equal to the second distance.

[0011] In some embodiments, the orthographic projection of the first spacer on the base substrate overlaps with the orthographic projections of the first pixel electrode and the second pixel electrode on the base substrate; the orthographic projection of the second spacer on the base substrate overlaps with the orthographic projections of the first pixel electrode and the second pixel electrode on the base substrate.

[0012] On the other hand, a display panel is provided, comprising a display area and a peripheral area. The display panel comprises: an array substrate as described in any of the above embodiments; the plurality of pixel groups are located in the display area; at least one gate drive circuit is provided on the base substrate, the gate drive circuit is located in the peripheral area; the gate drive circuit comprises N cascaded shift registers; wherein the output end of the i-th shift register is connected to the input end of the i+n-th shift register; the output end of the i+n+2j-th shift register is connected to the reset end of the i-th shift register; j is greater than or equal to 1; the plurality of gate lines are arranged in sequence along a column direction, and the plurality of first gate lines and the plurality of second gate lines are arranged alternately; each of the N cascaded shift registers is electrically connected to a gate line.

[0013] In some embodiments, the multiple shift registers are arranged along the column direction; the display panel also includes: a first voltage signal line arranged on one side of the gate drive circuit along the row direction; each level of the shift register includes multiple transistors, at least one of the multiple transistors is electrically connected to the first voltage signal line; the multiple transistors include a reset transistor and multiple noise reduction transistors, and the shift register also includes an input transistor, and the input transistor and the reset transistor are away from the first voltage signal line relative to the noise reduction transistor; the display panel also includes an auxiliary first voltage signal line located on the other side of the gate drive circuit, and the first voltage signal line is connected to the auxiliary first voltage signal line; the input transistor and the reset transistor are close to the auxiliary first voltage signal line relative to the noise reduction transistor; at least part of the reset transistors of the shift register are connected to the auxiliary first voltage signal line through a first lead line.

[0014] In some embodiments, the display panel also includes: a connecting voltage signal line arranged on the side of the last-stage shift register of the gate drive circuit away from other shift registers, the first voltage signal line and the auxiliary first voltage signal line are connected through the connecting voltage signal line, and the connecting voltage signal line extends along the row direction; the connecting voltage signal line includes a plurality of electrically connected sub-signal lines.

[0015] In some embodiments, the noise reduction transistor of the shift register is connected to the first voltage signal line through a second lead line.

[0016] In some embodiments, the plurality of noise reduction transistors include multiple groups of transistors, each group of transistors includes two transistors; the second lead is located between the two transistors in each group of transistors; and the two transistors in at least one group of transistors are staggered in the column direction.

[0017] In some embodiments, the size of the region where each stage of the shift register is located in the column direction is 60 μm to 100 μm.

[0018] In some embodiments, the display panel also includes: M clock signal lines arranged on the side of the gate drive circuit away from the display area, the clock signal lines being electrically connected to the gate drive circuit, wherein the i-th clock signal line is connected to the (Mm+i)-th level shift register, wherein 1≤i≤M, and i is a positive integer, 0≤m, and m is a positive integer; (Mm+i)≤N; the starting position of the valid clock signal transmitted by the i-th clock signal line is earlier than the starting position of the valid clock signal transmitted by the i+1-th clock signal line, i+1≤M.

[0019] In some embodiments, starting from the first clock signal line, every two adjacent clock signal lines form a group, and the starting position of the valid clock signal output by the second clock signal line in each group of clock signal lines is earlier than the starting position of the valid clock signal output by the first clock signal line; the starting position of the valid clock signal transmitted by the i-th clock signal line is earlier than the starting position of the valid clock signal transmitted by the i+2-th clock signal line; i+2≤M.

[0020] In another aspect, a method for driving a display panel is provided. The method for driving a display panel is applied to a display panel as described in any of the above embodiments, wherein the plurality of pixel groups include a plurality of row pixel groups arranged along a column direction, each row pixel group includes at least two pixel groups arranged along a row direction; each row pixel group is disposed between a first gate line and a second gate line of a gate line group and is electrically connected to the gate line group; the driving method comprises: when the display panel displays a first setting screen, the gate drive circuit outputs a first set of gate drive signals, the plurality of row pixel groups are activated row by row under the scanning of the plurality of gate line groups, and in each row pixel, a first sub-pixel electrically connected to the first gate line is turned on before a second sub-pixel electrically connected to the second gate line.

[0021] In some embodiments, when the display panel displays a second setting screen, the gate drive circuit outputs a second gate drive signal, the multiple row pixel groups are activated row by row under the scanning of the multiple gate line groups, and in each row pixel, the second sub-pixel electrically connected to the second gate line is turned on before the first sub-pixel electrically connected to the first gate line.

[0022] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments.

[0023] In some embodiments, the display device further includes M clock signal lines, the i-th clock signal line is connected to the (Mm+i)-th level shift register, wherein 1≤i≤M, and i is a positive integer, 0≤m, and m is a positive integer; (Mm+i)≤N; the display device further includes a control chip, the control chip is connected to the M clock signal lines, and outputs clock signals to the M clock signal lines; the control chip is configured to, when it is detected that the display panel displays a first setting screen, output valid clock signals to the M clock signal lines in a first order in sequence, wherein the first order is 1, 2, 3, 4...M-1, M; when it is detected that the display panel displays a second setting screen, output valid clock signals to the M clock signal lines in a second order in sequence, wherein the second order is 2, 1, 4, 3...M, M-1. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] FIG1 is a structural diagram of an array substrate according to some embodiments;

[0026] FIG2A is another structural diagram of an array substrate according to some embodiments;

[0027] FIG2B is a structural diagram of gate lines of an array substrate according to some embodiments;

[0028] FIG2C is a structural diagram of an active layer of an array substrate according to some embodiments;

[0029] FIG2D is a structural diagram of a pixel electrode of an array substrate according to some embodiments;

[0030] FIG2E is a structural diagram of a data line of an array substrate according to some embodiments;

[0031] FIG2F is a structural diagram of a common electrode of an array substrate according to some embodiments;

[0032] 3A is a structural diagram of an array substrate where a pixel electrode and a common electrode overlap according to some embodiments;

[0033] FIG3B is a partial enlarged view of point A according to FIG3A ;

[0034] FIG4 is a structural diagram of a pixel group of an array substrate according to some embodiments;

[0035] FIG5 is a cross-sectional structural diagram obtained by making a cross section along the cross-sectional line CC in FIG4;

[0036] FIG6 is another structural diagram of a pixel group of an array substrate according to some embodiments;

[0037] FIG7 is a diagram illustrating a pixel opening structure of a pixel group of an array substrate according to some embodiments;

[0038] FIG8 is a diagram illustrating a domain area structure of a pixel group of an array substrate according to some embodiments;

[0039] FIG9A is another structural diagram of a pixel group of an array substrate according to some embodiments;

[0040] FIG9B is a partially enlarged structural diagram at point B in FIG9A ;

[0041] FIG9C is a cross-sectional structural diagram obtained by making a cross section along the cross-sectional line EE of the first spacer in FIG9B ;

[0042] FIG10 is a structural diagram of a display panel according to some embodiments;

[0043] FIG11A is another structural diagram of a display panel according to some embodiments;

[0044] FIG11B is an enlarged view obtained based on FIG11A ;

[0045] FIG11C is a timing diagram of FIG11A according to some embodiments;

[0046] FIG11D is a timing diagram of FIG11A according to some embodiments;

[0047] FIG11E is a circuit diagram of a shift register according to some embodiments;

[0048] FIG11F is a timing diagram of a gate driving circuit and a reset relationship diagram according to some embodiments;

[0049] FIG12A is another structural diagram of an array substrate according to some embodiments;

[0050] FIG12B is another structural diagram of an array substrate according to some embodiments;

[0051] FIG13 is a connection structure diagram of a gate driving circuit according to some embodiments;

[0052] FIG14A is a connection structure diagram of a shift register according to some embodiments;

[0053] FIG14B is a partial enlarged structural diagram obtained according to FIG14A;

[0054] FIG14C is a partial enlarged structural diagram obtained according to FIG14A;

[0055] FIG15A is a partial enlarged structural diagram obtained at point D according to FIG14A;

[0056] FIG15B is a partial enlarged structural diagram obtained at point E according to FIG14A;

[0057] FIG16 is a structural diagram of a display device according to some embodiments;

[0058] FIG. 17 is a diagram illustrating a connection structure of a control chip of a display device according to some embodiments. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0060] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0061] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0062] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0063] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0064] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0065] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0066] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0067] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0068] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0069] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0070] Currently, low-cost display products typically use a dual-gate drive method to drive the pixel array. This reduces the number of data line channels, thereby reducing the number of driver chips and ultimately lowering costs. However, in existing display panels using this method, the layout of different thin-film transistors varies. This leads to misalignment between different film layers during the manufacturing process, resulting in differences in parasitic capacitance. This can lead to poor display performance, such as vertical streaks, flickering, and image sticking.

[0071] Based on this, some embodiments of the present disclosure provide an array substrate, a display panel, a driving method for a display panel, and a display device to solve the problem of poor picture display (for example, flickering, afterimages, vertical stripes, etc.), while ensuring uniform light effects, thereby improving product yield and quality.

[0072] The array substrate, display panel, display panel driving method and display device provided by the present disclosure are respectively introduced below.

[0073] Some embodiments of the present invention provide an array substrate 10, as shown in Figures 1 and 2A . The array substrate 10 includes a base substrate 1 and a plurality of sub-pixels 2', a plurality of gate lines 3', and a plurality of data lines 4 disposed on the base substrate 1. The plurality of sub-pixels 2' are arranged in an array on the base substrate 1, with the plurality of sub-pixels arranged in E rows and F columns; the plurality of sub-pixels form a plurality of pixel groups 2.

[0074] 2A and 4 , a plurality of sub-pixels 2′ are divided into a plurality of pixel groups. Each pixel group 2 includes two adjacent sub-pixels 2′ arranged along a row direction X. Each sub-pixel 2′ includes a transistor and an electrode group, wherein the electrode group is an overlapping pixel electrode and a common electrode. Each pixel group 2 includes a first sub-pixel 21 and a second sub-pixel 22. The first sub-pixel 21 includes a first transistor 211 and a first electrode group 212 connected thereto, and the second sub-pixel 22 includes a second transistor 221 and a second electrode group 222 connected thereto. The first electrode group 212 and the second electrode group 222 are sequentially arranged along the row direction X. The first transistor 211 and the second transistor 221 are both located between the first electrode group 212 and the second electrode group 222, and are respectively located at opposite ends of the pixel group 2 along the column direction Y. The first electrode group 212 includes a first pixel electrode 2121 and a first common electrode 2122, and the second electrode group 222 includes a second pixel electrode 2221 and a second common electrode 2222.

[0075] The multiple gate lines 3' constitute a plurality of gate line groups 3, each of the multiple gate line groups 3 includes a first gate line 31 and a second gate line 32, and the first sub-pixel 21 and the second sub-pixel 22 of each pixel group 2 are respectively connected to the first gate line 31 and the second gate line 32 of a gate line group 3, that is, the gate of the first transistor 211 included in the first sub-pixel 21 is electrically connected to the first gate line 31, that is, the gate of the second transistor 221 included in the second sub-pixel 22 is electrically connected to the second gate line 32.

[0076] Exemplarily, a plurality of gate lines 3' extend along the row direction X and are arranged along the column direction Y, and every two adjacent gate lines 3' constitute a gate line group 3, and the gate line group 3 is electrically connected to a row of sub-pixels 2'. The two gate lines of each gate line group 3 are respectively located on both sides of a row of sub-pixels 2', and the first gate line 31 is electrically connected to the first sub-pixel 21 of each pixel group 2 in the row of sub-pixels 2', and the second gate line 32 is electrically connected to the second sub-pixel 2 of each pixel group 2 in the row of sub-pixels 2'.

[0077] It should be noted that, in each pixel group 2, the relative positions of the first sub-pixel 21 and the second sub-pixel 22 are not fixed. For example, in a row of sub-pixels 2' and the corresponding gate line group 3, the sub-pixels electrically connected to the first gate line 31 are all first sub-pixels 21, and the sub-pixels electrically connected to the second gate line 32 are all second sub-pixels 22. For example, as shown in FIG2A , in a pixel group 2 in the upper left corner, the first sub-pixel 21 is located to the left of the second sub-pixel 22, and the first sub-pixel 21 is the odd-numbered sub-pixel in this row of sub-pixels. In a pixel group 2 in the upper right corner, the first sub-pixel 21 is located to the right of the second sub-pixel 22, and the first sub-pixel 21 is the even-numbered sub-pixel in this row of sub-pixels.

[0078] As shown in FIG1 , the first subpixel 21 and the second subpixel 22 of each pixel group 2 are connected to a data line 4, that is, the two subpixels in a pixel group 2 are controlled by the same data line. Multiple data lines 4 are arranged along a row direction X. At least some of the data lines 4 include a third data segment 43 extending along the row direction X, a first data segment 41 and a second data segment 42 extending along the column direction Y. The third data segment 43 connects the first data segment 41 and the second data segment 42. The first data segment 41 is arranged between the subpixel in the i-th column and the (i+1)-th column, and the second data segment 42 is arranged between the subpixel in the (ij)-th column and the subpixel in the (ij-1)-th column, where j is greater than or equal to 1 and i+1≤F.

[0079] It should be noted that, the at least part of the data lines here refers to the remaining data lines except the two data lines located at the outermost sides along the row direction X.

[0080] For example, referring to FIG. 1 , the arrangement of at least some of the data lines 4 when j is equal to 1 is shown. The at least some of the data lines include a third data segment 43 extending along the row direction X, and a first data segment 41 and a second data segment 42 extending along the column direction Y. FIG. 1 shows that the first data segment 41 is disposed between the i-th column of sub-pixels and the (i+1)-th column of sub-pixels, and is electrically connected to the sub-pixels on either side of the first data segment 41. The second data segment 42 is disposed between the (i-1)-th column of sub-pixels and the (i-2)-th column of sub-pixels, and is electrically connected to the sub-pixels on either side of the second data segment 42. In other words, two columns of sub-pixels separate the first data segment 41 and the second data segment 42 of the same data line 4. The arrangement of the data lines 4 shown in FIG. 1 is merely an example, and corresponds to the arrangement of the data lines when j is equal to 1. When j is greater than 1, three columns of sub-pixels, four columns of sub-pixels, and so on, separate the first data segment 41 and the second data segment 42 of the same data line 4.

[0081] It can be understood that in the above-mentioned setting, the same data line 4 can be electrically connected to two adjacent columns of pixel groups 2, wherein each first data segment 41 of the data line is electrically connected to each odd-numbered pixel group 2 (or even-numbered pixel group 2) of one column of pixel groups, and each second data segment 42 of the data line 4 is electrically connected to each even-numbered pixel group 2 (or odd-numbered pixel group 2) of the other column of pixel groups.

[0082] In some embodiments, referring to Figure 1 again, j=1; the two outermost data lines 4 in the row direction X are the first data line 401 and the second data line 402, the first data segment 41 of the first data line 401 is set between the first column sub-pixel and the second column sub-pixel, and the second data segment 42 of the first data line 401 is set on the side of the first column sub-pixel away from the multiple columns of sub-pixels; the first data segment 41 of the second data line 402 is set on the side of the F column sub-pixel away from the multiple columns of sub-pixels, and the second data segment 42 of the second data line 402 is set between the (F-1) column sub-pixel and the F column sub-pixel.

[0083] For example, as shown in FIG1 , the sub-pixel columns arranged from left to right in FIG1 are the first column of sub-pixels, the second column of sub-pixels...the Fth column of sub-pixels, wherein the first data line 401 and the second data line 402 are respectively located at the leftmost and rightmost sides of the multiple data lines 4, and the second data segment 42 of the first data line 401 is set on the side of the first column of sub-pixels away from the multiple columns of sub-pixels, that is, the second data segment 42 is located on the left side of the first column of sub-pixels; the first data segment 41 of the second data line 402 is set on the side of the Fth column of sub-pixels away from the multiple columns of sub-pixels, that is, the first data segment 41 is located on the right side of the Fth column of sub-pixels.

[0084] Illustratively, the base substrate 1 has a supporting and protective function and can be a rigid substrate, such as a glass substrate or a silicon substrate; or a flexible substrate, such as a polyimide substrate, etc., which is not limited here.

[0085] In some embodiments, as shown in Figure 2A, multiple pixel groups 2 are arranged into multiple rows and columns, and each row of pixel groups 2 is arranged between the first gate line 31 and the second gate line 32 of a gate line group 3; multiple data lines 4 are arranged along the row direction, and each data line 4 includes a plurality of first data segments 41 and a plurality of second data segments 42 that are alternately arranged. Except for the two outermost data lines 4 in the row direction, the plurality of first data segments 41 of the data lines 4 are respectively located between the first electrode group 212 and the second electrode group 222 of the odd-numbered row pixel groups in the first column of pixel groups, and the plurality of second data segments 42 of the data lines 4 are respectively located between the first electrode group 212 and the second electrode group 222 of the even-numbered row pixel groups in the second column of pixel groups, and the first column of pixel groups and the second column of pixel groups are adjacent; the data lines 4 also include a plurality of third data segments 43, and the third data segments 43 connect the adjacent first data segments 41 and the second data segments 42.

[0086] Exemplarily, referring to Figure 2A, the multiple pixel groups 2 shown in the figure are arranged into four rows and six columns, and each row of pixel groups 2 is arranged between the first gate line 31 and the second gate line 32 of a gate line group 3, that is, in the same row of pixel groups 2, the first sub-pixel 21 and the second sub-pixel 22 included in each pixel group 2 are respectively electrically connected to the same gate line group 3; multiple data lines 4 are arranged along the row direction X, and the multiple data lines 4 include multiple first data segments 41 and multiple second data segments 42 extending along the column direction Y, wherein the first data segment 41 is located between the first electrode group 212 and the second electrode group 222 of the odd-numbered row pixel group in the first column pixel group 2a, and the second data segment 42 is located between the first electrode group 212 and the second electrode group 222 of the even-numbered row pixel group in the second column pixel group 2b. It should be noted that the first column pixel group is adjacent to the second column pixel group here, but their specific positional relationship is not limited. The multiple pixel groups 2 shown in Figure 2A are only an example, wherein the first column pixel group is located to the right of the second column pixel group and the two are adjacent. The third data segments 43 of the plurality of data lines 4 extend along the row direction X and connect the first data segment 41 and the second data segment 42. As can be seen from the above, each data line 4 is distributed in a bow shape.

[0087] As shown in FIG1 , the dual-gate-line + zigzag pixel architecture employs the above-described structure. Each subpixel in each row of subpixels is electrically connected to two gate lines in an alternating pattern of odd and even. Multiple data lines are arranged in a zigzag pattern. The first data segment 41 of each data line 4 is located between two adjacent columns of subpixels, and the second data segment is located between two other adjacent columns of subpixels. This arrangement reduces the number of data lines 4 and the number of source drive channels for transmitting data signals. Furthermore, due to the zigzag data line design, the two subpixels in each pixel group are electrically connected to the same data line, while adjacent pixel groups are electrically connected to different data lines. The "+" and "-" in FIG1 represent opposite polarities. Given that the polarities of the multiple data lines alternate in an odd-even pattern along the row direction, the polarities of the multiple subpixels can be flipped by 2 dots (pixel points) per pixel group. This means that the two subpixels in each pixel group have the same polarity, while adjacent pixel groups have opposite polarities. This, to a certain extent, can shield most vertical streaks from the image, improving display issues such as vertical streaks.

[0088] As shown in Figures 2B to 2F, Figures 2B to 2F are schematic diagrams of each film layer of multiple pixel groups. The array substrate includes a base substrate, a gate layer 101, a semiconductor layer 103, a pixel electrode layer 104, a source-drain metal layer 105 and a common electrode layer 107 (collectively referred to as functional layers) arranged in sequence on the base substrate. Exemplarily, the semiconductor layer 103 and the pixel electrode layer 104 are located in the same layer; optionally, the gate layer 101, the semiconductor layer 103, the source-drain metal layer 105, the pixel electrode layer 104 and the common electrode layer 107 (collectively referred to as functional layers) may be arranged in sequence on the base substrate; optionally, the gate layer 101, the pixel electrode layer 104, the semiconductor layer 103, the source-drain metal layer 105 and the common electrode layer 107 (collectively referred to as functional layers) may be arranged in sequence on the base substrate; the array substrate also includes an insulating layer arranged between two adjacent functional layers. 2B is a structural diagram of the layout of multiple gate lines, wherein multiple gate lines 3' are arranged in multiple gate line groups 3, each gate line group 3 includes a first gate line 31 and a second gate line 32, and each gate line 3' is evenly connected to the gates of multiple transistors. FIG2C is a structural diagram of the semiconductor layer 103, wherein the semiconductor layer 103 includes an active layer 12 of multiple transistors, and the material of the semiconductor layer can be, for example, amorphous silicon, low-temperature polysilicon, metal oxide semiconductor, etc., which are not limited here. FIG2D is a structural diagram of the pixel electrode layer, wherein the pixel electrode layer 104 includes a plurality of pixel electrodes, and the plurality of pixel electrodes are arranged in an array, and the first pixel electrode 2121 and the second pixel electrode 2221 in each pixel group 2 extend in the same direction; along the row direction X, a spare data line (as indicated by the arrow) is provided between two adjacent pixel electrodes, the spare data line being electrically connected to the data line and configured to assist in transmitting data signals, or to transmit data signals as a spare data line when a data line fails. Optionally, the lengths of the spare data lines can be set differently, for example, the lengths of adjacent spare data lines are different along the X direction. Figure 2E is a structural diagram of the source-drain metal layer. The source-drain metal layer includes multiple data lines. As can be seen from the figure, each data line 4 is arranged in a bow shape. Each data line 4 includes a first data segment 41 and a second data segment 42 extending along the column direction Y, and a third data segment 43 extending along the row direction X. The third data segment 43 electrically connects the first data segment 41 and the second data segment 42. In addition, the source-drain metal layer also includes the first and second electrodes of multiple transistors, wherein the first electrodes of the transistors are connected to the data lines. Figure 2F is a structural diagram of the common electrode layer. In the figure, the common electrodes are arranged in a mesh structure, and the common electrodes of each sub-pixel are electrically connected to form a whole. It can be understood that the common electrode in a sub-pixel is the portion of the common electrode layer that overlaps with the pixel electrode of the sub-pixel.

[0089] In some embodiments, referring to FIG. 3A , an overlapping area between the first pixel electrode 2121 and the first common electrode 2122 is equal to an overlapping area between the second pixel electrode 2221 and the second common electrode 2222 .

[0090] For example, as shown in Figure 4, since in a pixel group 2, the first transistor 211 and the second transistor 221 are located between the two first electrode groups and the second electrode group, the shapes, settings and placement positions of the first transistor 211 and the second transistor 221 are not completely consistent. Therefore, the shapes of the first pixel electrode 2121 and the second pixel electrode 2221 close to the boundaries of the two transistors are different, resulting in differences in the areas of the first pixel electrode 2121 and the second pixel electrode 2221. Therefore, the overlapping area of ​​the first pixel electrode 2121 and the first common electrode 2122 and the overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222 are different, that is, the capacitance generated by the first sub-pixel 21 and the second sub-pixel 22 is different, which will cause deviations in the sub-pixel display and affect the display effect.

[0091] 3A , by setting the overlapping area of ​​the first pixel electrode 2121 and the first common electrode 2122 to be equal to the overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222, it is possible to ensure that the capacitance generated between the first pixel electrode 2121 and the first common electrode 2122 is consistent with the capacitance generated between the second pixel electrode 2221 and the second common electrode 2222. In this way, the electric field strengths generated by the first electrode group and the second electrode group are consistent, driving the deflection of the liquid crystal layer to be consistent, and the light transmitted through the liquid crystal layer to be consistent, thereby avoiding poor display phenomena such as flickering, vertical stripes, etc.

[0092] Since the common electrode layer is a whole layer structure laid on the display area, and the common electrodes of multiple sub-pixels are connected, the main way to adjust the overlapping area between the pixel electrode and the common electrode is to adjust the shape of the pixel electrode. As shown in Figure 3A, the dotted box is the outline of the pixel electrode, wherein the pixel group 2 includes a first electrode group 212 and a second electrode group 222, and the second electrode group 222' on the right is a structural diagram before adjustment. For example, before the adjustment, the area of ​​the second pixel electrode 2221' is larger than the area of ​​the first pixel electrode 2121, so that the capacitance formed by the first electrode group 212 and the capacitance formed by the second electrode group 222' differ by 1.6%, and the △Vp differs by 1.2%, which makes flickering easy to occur. Referring to Figure 3B, Figure 3B is an enlarged view of Figure 3A at point A, wherein the area of ​​the dotted box area S is s. The area S of the second pixel electrode 2221' in Figure 3A is partially removed, and the second pixel electrode 2221 on the left side of Figure 3A is obtained. For example, the size of area S in the row direction X is 5.24um, and the overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222 is also reduced accordingly. By adjusting the overlapping area of ​​the second pixel electrode and the second common electrode in the second electrode group, the first electrode group is not adjusted, so that the overlapping area of ​​the first pixel electrode 2121 and the first common electrode 2122 is equal to the overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222. The capacitance generated by the second electrode group is consistent with the capacitance generated by the first electrode group, thereby avoiding poor display phenomena such as flickering, vertical stripes, etc.

[0093] In some embodiments, as shown in Figure 4, at least a portion of the data line 4 connected to the pixel group 2 is located between the first electrode group 212 and the second electrode group 222 of the pixel group 2; at least a portion of the data line 4 is the first data segment 41 or the second data segment 42; the first electrode 211a of the first transistor 211 and the first electrode 221a of the second transistor 221 are both connected to the data line 4, the second electrode 211b of the first transistor 211 is connected to the first pixel electrode 2121, and the second electrode 221b of the second transistor 221 is connected to the second pixel electrode 2221; the first electrode 211a of the first transistor 211 points to the second electrode 211b, and the direction parallel to the row direction X is the first direction F1, the first electrode 221a of the second transistor 221 points to the second electrode 221b, and the direction parallel to the row direction X is the second direction F2, and the first direction F1 is opposite to the second direction F2.

[0094] For example, referring to Figure 4, the first direction F1 and the second direction F2 introduced above are both for the direction in which the first pole of the transistor points to the second pole in a pixel group 2. The pixel group shown in Figure 4 is only one example. The specific direction needs to be determined based on the positions of the first pole and the second pole of the transistor. The first direction F1 and the second direction F2 here are not fixed, but it can be understood that the first pole 211a of the first transistor 211 points to the second pole 211b and is parallel to the first direction F1 of the row direction X, and is set opposite to the second direction F2 of the first pole 221a of the second transistor 221 pointing to the second pole 221b and parallel to the row direction X. This is beneficial to the spatial arrangement of other structures in the pixel group 2, and thus makes it easier to make the overlapping area of ​​the first pixel electrode 2121 and the first common electrode 2122 equal to the overlapping area of ​​the second pixel electrode 2221 and the second common electrode 2222.

[0095] It should be noted that at least a portion of the data line 4 connected to the pixel group 2 is located between the first electrode group 212 and the second electrode group 222 of the pixel group 2. As shown in Figure 4, at least a portion of the data line 4 extends along the column direction Y and is located between the first electrode group 212 and the second electrode group 222. At least a portion of the data line 4 is configured to provide a data signal to the first pixel electrode 2121 and the second pixel electrode 2221 through the first transistor 211 and the second transistor 221, respectively. The data signal can be a voltage signal, and its size corresponds to the brightness of the display brightness of the sub-pixel.

[0096] In some embodiments, the first transistor 211 and the second transistor 221 are centrally symmetrically arranged.

[0097] It should be noted that, continuing to refer to Figure 4, in the area where a pixel group 2 is located, the central symmetry point is O, the first transistor 211 and the second transistor 221 are symmetrical relative to the central symmetry point O, and the line segment formed by connecting the center of the first transistor 211 and the center of the second transistor 221 passes through the central symmetry point O.

[0098] In some embodiments, referring to Figures 4 and 5, the first transistor 211 and the second transistor 221 are bottom-gate transistors. The first transistor 211 and the second transistor 221 both include a gate 11, an active layer 12, and a source and drain 13 stacked in sequence. The source and drain 13 include a first electrode 131 and a second electrode 132. The orthographic projection of the active layer 12 on the base substrate 1 falls within the orthographic projection of the gate 11 on the base substrate 1. At least part of the orthographic projections of the first electrode 131 and the second electrode 132 on the base substrate 1 falls within the orthographic projection of the active layer 12 on the base substrate 1. The orthographic projection shape of the first electrode 131 (for example, the first electrode 221a of the second transistor 221) is U-shaped, and the opening of the first electrode 131 faces the second electrode 132.

[0099] Exemplarily, the orthographic projections of the active layers 12 of the first transistor 211 and the second transistor 221 on the substrate 1 fall within the orthographic projections of the gate 11 on the substrate 1, that is, the areas of the active layer 12 of the first transistor 211 and the active layer 12 of the second transistor 221 are both smaller than the areas of the gates 11 of the corresponding first transistor 211 and the gates 11 of the second transistor 221, and at least part of the orthographic projections of the first electrode 131 and the second electrode 132 on the substrate 1 fall within the orthographic projections of the active layer 12 on the substrate 1.

[0100] It should be noted that, as shown in Figure 5, in combination with Figures 2B to 2F, a gate layer 101, a gate insulating layer 102, a semiconductor layer 103, a pixel electrode layer 104, a source-drain metal layer 105, a passivation layer 106, and a common electrode layer 107 are sequentially provided on the base substrate 1, wherein the semiconductor layer 103 and the pixel electrode layer 104 are located on the same layer, and the source-drain metal layer 105 is provided on the side of the semiconductor layer 103 and the pixel electrode layer 104 away from the base substrate 1; the gate layer 101 includes a gate 11 of the transistor, the semiconductor layer 103 includes an active layer 12 of the transistor, and the pixel electrode layer 104 is provided with a plurality of pixel electrodes (for example, a second pixel electrode 2221). As shown in Figures 2C and 2D, the shapes of the two pixel electrodes in a pixel group 2, which are respectively close to the boundaries of the two transistors, correspond to the shape of the active layer 12, so as to achieve a reasonable spatial layout of the multiple pixel electrodes and the multiple active layers located on the same layer. The source-drain metal layer 105 includes a first electrode 131 and a second electrode 132 of the transistor, the second electrode 132 of the transistor contacts the pixel electrode to achieve electrical connection, and the first electrode 131 and the second electrode 132 of the transistor are respectively in contact with the two ends of the active layer 12 of the transistor to achieve electrical connection, and the common electrode layer 107 includes multiple common electrodes.

[0101] The following takes the second transistor as an example to introduce the relationship between the gate, active layer, source and drain of the transistor.

[0102] As shown in Figure 5, Figure 5 is a cross-sectional view of the second transistor 221 obtained by making a cross-section along the cross-sectional line CC in Figure 4, wherein, it can be seen from Figure 5 that the orthographic projection of the active layer 12 of the second transistor 221 on the substrate 1 falls within the orthographic projection of the gate 11 on the substrate 1, and at least part of the orthographic projections of the first electrode 131 and the second electrode 132 of the second transistor 221 on the substrate 1 fall within the orthographic projection of the active layer 12 on the substrate 1, the first electrode 131 and the second electrode 132 of the second transistor 221 are electrically connected to its active layer, at least part of the orthographic projection of the second electrode 132 of the second transistor 221 on the substrate 1 falls within the orthographic projection of the pixel electrode layer 104 on the substrate 1, and the second electrode 132 of the second transistor 221 is electrically connected to the pixel electrode on the pixel electrode layer 104.

[0103] In some embodiments, referring to Figures 2D, 2F, 6 and 7, the first pixel electrode 2121 and the second pixel electrode 2221 are block electrodes, and the first common electrode 2122 and the second common electrode 2222 are strip electrodes. As shown in Figure 3A, the first common electrode 2122 and the second common electrode 2222 both include multiple slits f; the aperture ratio of the first sub-pixel 21 is equal to the aperture ratio of the second sub-pixel 22.

[0104] For example, as shown in FIG6 , the first pixel electrode 2121 and the second pixel electrode 2221 are arranged in parallel, and the first common electrode 2122 and the second common electrode 2222 include a plurality of slits f, wherein each slit f extends entirely in the column direction. A black matrix layer 110 is disposed above the pixel group 2. The black matrix layer 110 is used for light shielding. The actual light-transmitting area in the sub-pixel is the area not blocked by the black matrix layer 110. The aperture ratio of the first sub-pixel 21 is equal to the aperture ratio of the second sub-pixel 22. In other words, the ratio of the actual light-transmitting area of ​​the first sub-pixel 21 to the total area is equal to the ratio of the actual light-transmitting area of ​​the second sub-pixel 22 to the total area, thereby ensuring light extraction efficiency. Referring to FIG7 , FIG7 is a diagram of the pixel opening structure of the first sub-pixel and the second sub-pixel, wherein the pixel opening of the first sub-pixel is referred to as the first pixel opening K1, and the pixel opening of the second sub-pixel is referred to as the second pixel opening K2. The area of ​​the first pixel opening K1 is equal to the area of ​​the second pixel opening K2.

[0105] In some embodiments, referring to Figure 8, the first electrode group 212 includes a first domain region 212m and a second domain region 212n arranged along the column direction Y, and the second electrode group 222 includes a third domain region 222m and a fourth domain region 222n arranged along the column direction, and the aperture ratios of the first domain region 212m, the second domain region 212n, the third domain region 222m and the fourth domain region 222n are equal.

[0106] Exemplarily, the first domain region 212m and the second domain region 212n are connected, the third domain region 222m and the fourth domain region 222n are connected, and the areas of the first domain region 212m, the second domain region 212n, the third domain region 222m and the fourth domain region 222n are equal, that is, the aperture ratios of the domain regions where the first electrode group 212 and the second electrode group 222 are located are equal, which can ensure that the light extraction efficiency of each domain region of the first electrode group 212 and the second electrode group 222 is the same and the light is uniform.

[0107] In some embodiments, as shown in Figures 9A to 9C, the array substrate 10 further includes: a first spacer 51 disposed on the side of the first transistor 211 away from the base substrate 1, and a second spacer 52 disposed on the side of the second transistor 221 away from the base substrate 1; the first spacer 51 and the second spacer 52 play a supporting role to form a space for placing the liquid crystal layer of the display panel.

[0108] In some examples, due to the placement of the transistor, the black matrix layer 110 near the transistor may have insufficient light shielding, resulting in abnormal lighting effects. The first spacer 51 and the second spacer 52 can play a light shielding role, which has an impact on the aperture ratio of the sub-pixel. By adjusting the position of the first spacer 51 and the second spacer 52, the light shielding ability can be ensured while the impact on the aperture ratio of the two sub-pixels can be kept consistent.

[0109] As shown in FIG9C , taking the first spacer 51 as an example, the first spacer 51 includes a first portion 511, a second portion 512, and a third portion 513 stacked in sequence. The first portion 511 is closer to the substrate than the second portion 512, and the orthographic projection of the first portion 511 on the substrate falls within the orthographic projection of the second portion 512 on the substrate. The orthographic projection of the second portion 512 on the substrate falls within the orthographic projection of the third portion 513 on the substrate. As shown in FIG9B , the orthographic projection boundary 51c of the third portion 513 on the substrate surrounds the orthographic projection boundary 51b of the second portion 512 on the substrate, and the orthographic projection boundary 51b of the second portion 512 on the substrate surrounds the orthographic projection boundary 51a of the first portion 511 on the substrate. The third portion 513 is located in the same layer as the black matrix layer 110. It can be considered that the third portions of the first and second spacers belong to the black matrix layer.

[0110] The center G1 of the orthographic projection of the first spacer 51 on the base substrate 1 is offset by a first distance H1 toward a third direction F3 relative to the center J1 of the orthographic projection of the first transistor 211 on the base substrate 1, and the third direction F3 is the direction from the first transistor 211 to the second transistor 221; the center G2 of the orthographic projection of the second spacer 52 on the base substrate 1 is offset by a second distance H2 toward a fourth direction F4 relative to the center J2 of the orthographic projection of the second transistor 221 on the base substrate 1, and the fourth direction F4 is the direction from the second transistor 221 to the first transistor 211.

[0111] It should be noted that the first transistor 211 and the second transistor 221 are transistors in the same pixel group, and the third direction F3 and the fourth direction F4 are also directions determined based on the two transistors in one pixel group.

[0112] As shown in FIG9A , the side of the black matrix layer 110 close to the first transistor and the side close to the second transistor may leak light. Here, the first spacer is offset by a first distance H1 toward the third direction F3 to block the position of the black matrix layer 110 close to the first transistor 211. The second spacer 52 is offset by a second distance H2 toward the fourth direction F4 to block the position of the black matrix layer 110 close to the second transistor 221 to compensate for the problem of insufficient light shielding of the black matrix layer and ensure that display abnormalities caused by light leakage will not occur. In addition, the spacer offset design can also prevent the problem of adhesion between two spacers that are close to each other.

[0113] In some embodiments, as shown in FIG. 9B , the first distance H1 is equal to the second distance H2 .

[0114] It should be noted that to clearly illustrate the offset distance, the first and second transistors in FIG9B are illustrated as the first and second transistors of adjacent pixel groups. Furthermore, the offset distances of the first spacer 51 and the second spacer 52 are set equal. This is primarily to ensure that the aperture ratios of the first domain region 212m, the second domain region 212n, the third domain region 222m, and the fourth domain region 222n are equal, thereby ensuring light extraction efficiency. Furthermore, referring to FIG9B and FIG9C , since the first and second spacers 51, 52 are columnar structures, the surrounding liquid crystal deflection is disrupted, making light leakage more likely. Setting the offset distance can prevent this light leakage.

[0115] In some embodiments, continuing to refer to Figure 9B, the orthographic projection of the first spacer 51 on the base substrate 1 overlaps with the orthographic projections of the first pixel electrode 2121 and the second pixel electrode 2221 on the base substrate 1; the orthographic projection of the second spacer 52 on the base substrate 1 overlaps with the orthographic projections of the first pixel electrode 2121 and the second pixel electrode 2221 on the base substrate 1.

[0116] It should be noted that the above-mentioned overlap means that the orthographic projection of the first spacer 51 on the base substrate 1 at least partially covers the orthographic projection of the first pixel electrode 2121 on the base substrate 1, and at the same time, the orthographic projection of the first spacer 51 on the base substrate 1 at least partially covers the orthographic projection of the second pixel electrode 2221 on the base substrate 1. As shown in FIG9B , the outermost boundary 51 c of the orthographic projection of the first spacer 51 on the base substrate 1 overlaps with the boundary of the orthographic projection of the first pixel electrode 2121 and the boundary of the orthographic projection of the second pixel electrode 2221. Similarly, the orthographic projection of the second spacer 52 on the base substrate 1 at least partially covers the orthographic projection of the first pixel electrode 2121 on the base substrate 1, and at the same time, the orthographic projection of the second spacer 52 on the base substrate 1 at least partially covers the orthographic projection of the second pixel electrode 2221 on the base substrate 1. As shown in FIG9B , the outermost boundary 52c of the orthographic projection of the second spacer 52 on the base substrate 1 intersects the boundary of the orthographic projection of the first pixel electrode 2121 and the boundary of the orthographic projection of the second pixel electrode 2221. The overlapping design ensures that the area between the transistor and the pixel electrode is shielded, effectively preventing light leakage.

[0117] For example, the first spacer 51 and the second spacer 52 can be disposed on a color filter substrate (CF) or an array substrate. The color filter substrate, also known as an opposing substrate, has a liquid crystal layer disposed between the color filter substrate and the array substrate. A black matrix layer and a color filter layer can be disposed on the color filter substrate. The color filter layer includes multiple filter units of different colors, such as red, green, and blue filter units formed using red, green, and blue photosensitive resins. Each filter unit corresponds to a sub-pixel. The black matrix layer is used to define the boundaries between the filter units to prevent light leakage between adjacent filter units.

[0118] As shown in Figure 10, some embodiments of the present disclosure also provide a display panel 100, including a display area AA and a peripheral area BB arranged outside the display area AA; the display panel includes the array substrate 10 provided by any of the above embodiments and at least one gate driving circuit 20 arranged on the base substrate 1; the multiple pixel groups 2 are located in the display area AA; the gate driving circuit 20 is arranged in the peripheral area BB, and the gate driving circuit 20 includes N cascaded shift registers 30.

[0119] The gate drive circuit 20 is used to output gate signals to the display area to control the opening of each sub-pixel and input data signals. The plurality of gate lines 3' are arranged in a column direction, and the plurality of first gate lines 31 and the plurality of second gate lines 32 are arranged alternately. The N cascaded shift registers 30 are electrically connected to the gate lines 3' and output gate scanning signals to the gate lines 3'.

[0120] Exemplarily, referring to FIG10 , the display panel includes two gate drive circuits 20, and the two gate drive circuits 20 are respectively located on both sides of the display area. In the two gate drive circuits 20, the same-level shift register is electrically connected to the same gate line. For example, the first-level shift registers of the two gate drive circuits are both electrically connected to the first gate line, and the gate scan signal is output to the gate line at the same time. In this way, the driving efficiency can be improved, the scanning time can be saved, and multiple sub-pixels can be turned on faster to write data signals and improve the display effect. Optionally, the present invention can also support unilateral drive, that is, a gate drive circuit is set on one side of the non-display area, which is not limited here.

[0121] The shift register 30 includes an input terminal, an output terminal, and a reset terminal. In some examples, the cascade connection of N shift registers 30 is as follows: the output terminal of the i-th shift register is connected to the input terminal of the i+n-th shift register; and the output terminal of the i+n-th shift register is connected to the reset terminal of the i-th shift register. This cascade connection is called a conventional reset cascade connection, whereby a shift register carries a bit into the n-th shift register that is arranged next to it and is reset by the n-th shift register.

[0122] It should be noted that the output end of the shift register can be an output end responsible for outputting a gate scanning signal, electrically connected to a gate line, and outputting a gate scanning signal to the gate line, or an output end responsible for cascading, which plays the role of cascade carry and reset and is not electrically connected to the gate line of the display area. In other words, the shift register has two output ends with different functions. In some examples, the shift register has one output end, which is both connected to the gate line and responsible for cascading.

[0123] In other embodiments of the present application, the cascade relationship of N shift registers 30 is as follows: the output of the i-th shift register is connected to the input of the i+n-th shift register; the output of the i+n+2j-th shift register is connected to the reset terminal of the i-th shift register; and j is greater than or equal to 1. This cascade connection is called a delayed reset cascade connection, where a shift register outputs a carry signal to the n-th shift register (called a carry shift register) arranged after it, and is then reset by the 2j-th shift register arranged after it, which is equivalent to a delay of 2j rows before resetting.

[0124] For example, as shown in FIG11A , FIG11A shows the first eight cascaded shift registers 30 included in the gate drive circuit 20, wherein, when i=1, n=4, j=1 and i, n and j are all positive integers greater than 0, i+n=5, i+n+2j=7, that is, the output end of the first-stage shift register is connected to the input end of the fifth-stage shift register, and the output end of the seventh-stage shift register is connected to the reset end of the first-stage shift register. When i=2, the output end of the second-stage shift register is connected to the input end of the sixth-stage shift register; the output end of the eighth-stage shift register is connected to the reset end of the second-stage shift register, and so on. No further details are given.

[0125] In some examples, the input terminals of the first n stages of the N shift registers are connected to the initialization signal line STV, and the reset terminals of the last n+2j stages of the shift registers are connected to the initialization signal line. The last n+2j stages of the shift registers are, for example, dummy shift registers. For example, with continued reference to FIG. 11A , the input terminals of the first four stages of the N shift registers are connected to the initialization signal line STV, and the reset terminals of the last six stages of the shift registers are connected to the initialization signal line.

[0126] It should be noted that the above cascade relationship uses a reset delay of 2j rows. For example, the reset is delayed by two rows, and the reset method of delaying even rows is used to support the implementation of parity swapping of timing signals, which is described in detail below.

[0127] In some embodiments, as shown in Figure 11E, the shift register includes multiple transistors, the multiple transistors include an input transistor M1, a reset transistor M2, an output transistor M3, a storage capacitor C1 and a plurality of noise reduction transistors M, the multiple noise reduction transistors include a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16 and a seventeenth transistor M17. Among them, the gate and first electrode of the input transistor M1 are electrically connected to the input terminal Input, and the second electrode is electrically connected to the pull-up node PU; the gate of the reset transistor M2 is electrically connected to the reset terminal Reset, the first electrode of the reset transistor is electrically connected to the pull-up node PU, and the second electrode is electrically connected to the first voltage signal line VGL; the gate of the output transistor M3 is electrically connected to the pull-up node PU, the first electrode of the output transistor M3 is electrically connected to the clock signal line CLK, and the second electrode is electrically connected to the output terminal Output; the storage capacitor C1 is electrically connected between the pull-up node PU and the output terminal Output.

[0128] The fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13, the fourteenth transistor M14, the sixteenth transistor M16 and the seventeenth transistor M17 of the plurality of noise reduction transistors M are all electrically connected to the first voltage signal line VGL, wherein the fifth transistor M5, the sixth transistor M6, the eighth transistor M8 and the ninth transistor M9 constitute a first pull-down node control subcircuit, and the first pull-down node control subcircuit is electrically connected to the second voltage signal line VDDO and the first pull-down node PD1. The first pull-down node PD1 controls the gate of the tenth transistor M10 and the gate of the eleventh transistor M11, and is used to reduce noise for the pull-up node and the output end; the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 constitute a second pull-down node control sub-circuit, the second pull-down node control sub-circuit is electrically connected to the third voltage signal line VDDE and the second pull-down node PD2, the second pull-down node PD2 controls the gate of the sixteenth transistor M16 and the gate of the seventeenth transistor M17, and is used to reduce noise for the pull-up node and the output end. The level of the signal transmitted by the second voltage signal line VDDO and the third voltage signal line VDDE is greater than the level of the signal transmitted by the first voltage signal line VGL. The first pull-down node control subcircuit and the second pull-down node control subcircuit can work alternately to improve the service life of the shift register; the initialization signal bus STV0 controls the gate of the seventh transistor M7 and the fourth transistor M4, and is used to reset the pull-up nodes and output terminals of all shift registers in the gate drive circuit before the start of a frame. Optionally, each stage of the shift register is connected to the initialization signal bus STV0 signal. The connection relationship of the specific transistors in this case is shown in Figure 11E. For example, the gate and the first electrode of the input transistor M1 are electrically connected (optionally, the gate and the first electrode of the input transistor M1 can also be given signals separately, which is not limited here), the second electrode of the input transistor M1 is electrically connected to the pull-up node PU, the gate and the pull-up node of the output transistor M3 are electrically connected, the first electrode of the output transistor M3 is electrically connected to the clock signal line CLK, and the second electrode of the output transistor M3 is electrically connected to the output terminal Output. Other transistor connection methods are specifically shown in Figure 11E and will not be repeated here.

[0129] When the voltage of the pull-up node PU is the turn-on voltage, the output transistor M3 is turned on, and the effective clock signal from the clock signal line is transmitted to the output terminal Output. The effective clock signal is used as a gate scan signal and is output from the output terminal Output to the connected gate line. The gate scan signal is transmitted to the sub-pixel to which it is connected via the gate line, controlling the transistor in the sub-pixel to be turned on; at the same time, the effective clock signal is used as a cascade output signal and is output to the input or output end of the cascaded shift register. The cascade output signal is transmitted to the input end of the shift register, controlling the input transistor M1 to be turned on, and realizing charging of the pull-up node PU, or the cascade output signal is transmitted to the reset end of the shift register, controlling the reset transistor M2 to be turned on, realizing resetting of the pull-up node PU. Among them, the effective clock signal is a signal that can turn on the transistor it controls. For example, when the transistor in the sub-pixel, or the input transistor M1, and the reset transistor M2 are N-type transistors, the level of the effective clock signal is a high level. When the transistor in the sub-pixel, or the input transistor M1, and the reset transistor M2 are P-type transistors, the level of the effective clock signal is a low level.

[0130] In some embodiments, referring to Figure 11A, the display panel 100 also includes: M clock signal lines CLK arranged on the side of the gate driving circuit 20 away from the display area, the clock signal line CLK is electrically connected to the gate driving circuit 20, wherein the i-th clock signal line is connected to the (Mm+i)-th level shift register, wherein 1≤i≤M, and i is a positive integer, 0≤m, and m is a positive integer; (Mm+i)≤N.

[0131] For example, referring to Figure 11B, there are eight clock signal lines CLK shown in Figure 11B, namely the first clock signal line CLK1 to the eighth clock signal line CLK8, that is, M is equal to 8. When m=0 and i=1~8, the first clock signal line CLK1 is connected to the first-stage shift register, the second clock signal line CLK2 is connected to the second-stage shift register, and the eighth clock signal line CLK8 is connected to the eighth-stage shift register. When m=1 and i=1~8, the first clock signal line CLK1 is connected to the ninth-stage shift register, and so on. Multiple shift registers are grouped in eight adjacent groups, and each shift register in each group is connected to a corresponding clock signal line in turn.

[0132] In some examples, the signal transmission mode of the multiple clock signal lines CLK is such that the starting position of the valid clock signal transmitted by the i-th clock signal line is earlier than the starting position of the valid clock signal transmitted by the i+1-th clock signal line, where i+1≤M. Taking the valid clock signal as an example of a high level (when the valid level is high, the output transistor M3 is an N-type transistor; when the valid level is low, the output transistor M3 is a P-type transistor, and in this case, the transistor is an N-type transistor for illustration), the rising edge position of the i-th clock signal line is earlier than the rising edge position of the valid clock signal transmitted by the i+1-th clock signal line.

[0133] Referring to Figure 11C, the starting position of the effective clock signal transmitted by the first clock signal line CLK1 is earlier than the starting position of the effective clock signal transmitted by the second clock signal line CLK2, the starting position of the effective clock signal transmitted by the second clock signal line CLK2 is earlier than the starting position of the effective clock signal transmitted by the third clock signal line CLK3, and the starting positions of the effective clock signals transmitted by the first clock signal line CLK1 to the eighth clock signal line CLK8 are successively delayed, and the effective clock signals transmitted by the eight clock signal lines are output in a first sequence, i.e., CLK1→CLK2→CLK3→CLK4→CLK5→CLK6→CLK7→CLK8, so that the first-stage shift register to the N-th stage shift register output gate scan signals to the connected gate lines in sequence.

[0134] In some embodiments, another transmission method for the signals of multiple clock signal lines CLK is that, starting from the first clock signal line, every two adjacent clock signal lines form a group, and the starting position of the valid clock signal transmitted by the second clock signal line in each group of clock signal lines is earlier than the starting position of the valid clock signal transmitted by the first clock signal line; the starting position of the valid clock signal output by the i-th clock signal line is earlier than the starting position of the valid clock signal output by the i+2-th clock signal line; i+2≤M.

[0135] For example, referring to Figure 11D, there are eight clock signal lines CLK shown in Figure 11D. Starting from the first clock signal line, every two adjacent clock signal lines form a group, that is, the first clock signal line CLK1 and the second clock signal line CLK2 form a group, the third clock signal line CLK3 and the fourth clock signal line CLK4 form a group, the fifth clock signal line CLK5 and the sixth clock signal line CLK6 form a group, and the seventh clock signal line CLK7 and the eighth clock signal line CLK8 form a group; the starting position of the valid clock signal transmitted by the second clock signal line CLK2 in each group of clock signal lines is earlier than the starting position of the valid clock signal transmitted by the first clock signal line CLK1, that is, the starting positions of the valid clock signals transmitted by the eighth clock signal line CLK8, the sixth clock signal line CLK6, the fourth clock signal line CLK4 and the second clock signal line CLK2 are earlier than the starting positions of the valid clock signals transmitted by the seventh clock signal line CLK7, the fifth clock signal line CLK5, the third clock signal line CLK3 and the first clock signal line CLK1, respectively. The effective clock signals of the eight clock signal lines are output in a second sequential manner, i.e., CLK2→CLK1→CLK4→CLK3→CLK6→CLK5→CLK8→CLK7, so that the order in which the first-stage shift register to the N-stage shift register output gate scanning signals is parity-even swapped relative to the first sequential output manner, i.e., the second-stage shift register outputs the gate scanning signal before the first-stage shift register.

[0136] In the gate drive circuit provided by the above embodiment of the present application, the cascade relationship of each shift register is to use a delay of 2j rows for reset, and the use of a delayed even-row reset method can support the implementation of odd-even swapping of timing signals, which is described in detail below. As shown in Figure 11F, for example, taking eight clock signal lines and eight shift registers, and delaying the reset of two rows as an example, the cascade mode of the shift registers is that the first shift register RS1 carries to the fifth shift register RS5, the second shift register RS2 carries to the sixth shift register RS6, the seventh shift register RS7 resets to the first shift register RS1, and the eighth shift register RS8 resets to the second shift register RS2. In the upper figure in Figure 11F, the effective clock signals of the eight clock signal lines are output in a first sequence, that is, CLK1→CLK2→CLK3→CLK4→CLK5→CLK6→CLK7→CLK8. According to the cascade mode of delaying the reset of the even rows, CLK1 corresponds to CLK5 and CLK2 corresponds to CLK6 during the carry, and CLK7 corresponds to CLK1 and CLK8 corresponds to CLK2 during the reset. In the lower figure of Figure 11F, the effective clock signals of the eight clock signal lines are output in the second sequence, namely CLK2→CLK1→CLK4→CLK3→CLK6→CLK5→CLK8→CLK7. According to the cascade method of delayed even-numbered row reset, CLK1 corresponds to CLK5 and CLK2 corresponds to CLK6 during carry, and CLK7 corresponds to CLK1 and CLK8 corresponds to CLK2 during reset. It can be seen that no matter which output method is adopted for the effective clock signal of the clock signal line, the corresponding relationship of the clock signal line is consistent when the shift register carries and resets. Therefore, the timing of the clock signal line can be converted between the two methods, the carry and reset of each shift register of the gate drive circuit can be carried out normally, and each shift register can output the gate scan signal / cascade signal normally, and there will be no situation where the clock signal disorder causes the normal operation to fail.

[0137] In some embodiments, based on the dual-gate-line + bow-shaped pixel architecture shown in Figures 1 and 2A, the same data line connects two columns of sub-pixels, meaning the same data signal drives both odd and even columns. Under the premise of pre-charging the sub-pixels, there are differences in the charging process between the odd- and even-numbered columns. Insufficient pixel charging rates can result in vertical streaks. This risk is particularly high for blue mixed-color images.

[0138] In some embodiments, referring to Figure 12A, Figure 12A is an arrangement diagram of sub-pixels, wherein the plurality of sub-pixels 2' include red sub-pixels r, green sub-pixels g, and blue sub-pixels b. For example, along the row direction X, the plurality of sub-pixels are arranged in sequence as a column of red sub-pixels r, a column of green sub-pixels g, and a column of blue sub-pixels b. The sub-pixels arranged along the column direction Y are sub-pixels of the same color, and one gate line group 3 is electrically connected to a row of sub-pixels.

[0139] In this pixel architecture, under a sky-blue screen, the grayscale voltage of the blue subpixel is inconsistent with the grayscale voltage of the red subpixel and the grayscale voltage of the green subpixel. The blue subpixel has a larger grayscale voltage, which causes the voltage on the data line transmitting the signal to fluctuate. This leads to insufficient charging when the data signal is transmitted from blue subpixel b to red subpixel r, from blue subpixel b to green subpixel, from red subpixel to blue subpixel, and from green subpixel to blue subpixel. Due to insufficient charging, some red subpixels, green subpixels, and blue subpixels will appear brighter or darker. Since the human eye is most sensitive to green subpixels, the brightness and darkness distribution of green subpixels has the greatest impact on visual effects. As a result, the green subpixels will appear periodically brighter, ultimately leading to the poor display problem of vertical stripes.

[0140] FIG12B illustrates the colors of the sub-pixels written in sequence by each data line in FIG12A. Taking data line D4 as an example, data line D4 is electrically connected to each pixel group circled by frame line Q, and the order in which each sub-pixel is turned on to write data signals is: red, green, red, blue, red, green, red, blue. As shown in FIG12B , for example, under a sky blue screen, the grayscale voltage of the blue sub-pixel is greater than the grayscale voltage of the red sub-pixel and the grayscale voltage of the green sub-pixel, and the grayscale voltage of the red sub-pixel is consistent with the grayscale voltage of the green sub-pixel. When the grayscale voltage suddenly changes, the grayscale voltage of the blue sub-pixel is greater than the grayscale voltage of the red sub-pixel and the grayscale voltage of the green sub-pixel. Pixel undercharging is prone to occur. The voltage suddenly changes at position ①, but there's no pre-charging process at position ②, resulting in a short charging time. The pixel at position ③ undergoes a pre-charging process, but the charging time is longer. As a result, the blue subpixel corresponding to position ① appears darker (from a low grayscale voltage to a high grayscale voltage), while the red subpixel corresponding to position ② appears brighter (from a high grayscale voltage to a low grayscale voltage). The brightness of other subpixels remains normal. Throughout the entire display area, subpixels at various positions will appear darker or brighter. Because the human eye is most sensitive to green subpixels, the brightness distribution of green subpixels has the greatest impact on visual effects. Consequently, the green subpixels will appear periodically brighter, ultimately leading to the display's poor quality, resulting in vertical streaks.

[0141] It is understandable that in the above-mentioned gate drive circuit, the input signal of the reset signal end of the shift register has been delayed, and then when timing control, it is possible to support the timing signal to be output in the first sequence output mode and the second sequence output mode. As shown in Figure 12A, in the figure, red sub-pixel and blue sub-pixel connect the odd-numbered row grid lines, and green sub-pixel and blue sub-pixel connect the even-numbered row grid lines. After being adjusted to the clock signal corresponding to the generation of the clock signal line as shown in Figure 11C, it is possible to realize that the starting position of the effective clock signal of the second clock signal line transmission in each group of clock signal lines is earlier than the starting position of the effective clock signal of the first clock signal line transmission, that is to say, it is possible to realize that the signal received by the green sub-pixel and blue sub-pixel connected with the even-numbered row grid lines is prior to the signal received by the red sub-pixel and blue sub-pixel connected with the odd-numbered row grid lines, and then change the opening sequence of each sub-pixel, alleviate the situation that the grayscale voltage of the sub-pixel that is turned on successively occurs sudden change, improve the dark or bright display caused by insufficient or sufficient sub-pixel charging, thereby avoid the bad problem of vertical stripes caused by charging difference, especially solve the vertical stripe problem that occurs in display panel when displaying sky blue picture.

[0142] In some embodiments, the duty cycle of the effective clock signal of each clock signal line is 50%, which can achieve charge sharing of the clock signal, thereby reducing the power consumption of the gate drive circuit. Referring to Figures 11C and 11D, Figures 11C and 11D are timing diagrams corresponding to the gate drive circuit in Figure 11A. The falling edge of the timing signal received by the first clock signal line shown in Figures 11C and 11D is at the same time as the rising edge of the timing signal received by the fifth clock signal line, and the falling edge of the timing signal received by the second clock signal line is at the same time as the rising edge of the timing signal received by the sixth clock signal line. In other words, the CLK duty (clock control signal duty cycle) can be set to 50%, achieving charge sharing and reducing power consumption.

[0143] In some embodiments, referring to Figure 13, multiple shift registers 30 are arranged along the column direction Y; the display panel also includes: a first voltage signal line 61 (VGL) arranged on one side of the gate driving circuit 20 along the row direction X; each level of the shift register 30 includes multiple transistors 40, and at least one of the multiple transistors 40 is electrically connected to the voltage signal line 61; the transistor 40 includes multiple reset transistors M2 and multiple noise reduction transistors M, and the shift register 30 also includes an input transistor M1, as shown in Figure 11E. As described above, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13, the fourteenth transistor M14, the sixteenth transistor M16 and the seventeenth transistor M17 of the multiple noise reduction transistors M are all electrically connected to the first voltage signal line VGL, and the reset transistor M2 is electrically connected to the first voltage signal line 61.

[0144] As shown in Figures 13 and 14A, the peripheral area of ​​the display panel is also provided with a second voltage signal line VDDO and a third voltage signal line VDDE. The first voltage signal line 61 (VGL), the second voltage signal line VDDO and the third voltage signal line VDDE all extend along the column direction Y and are all arranged on the side of the gate drive circuit 20 away from the display area AA.

[0145] The input transistor M1 and the reset transistor M2 are far away from the first voltage signal line 61 (VGL) relative to the noise reduction transistor M; that is, the input transistor M1 and the reset transistor M2 are closer to the display area AA. Since the reset transistor M2 is connected to the reset terminal Reset and the input transistor M1 is connected to the input terminal Input, the reset terminal Reset and the input terminal Input need to be cascaded. The reset terminal Reset and the input terminal Input of a certain level of shift register are connected to the output terminal Output of other levels of shift register, and the output terminal Output of the shift register is connected to the gate line. The output terminal Output of the shift register is set close to the display area. Therefore, the input transistor M1 and the reset transistor M2 are set at a position close to the display area AA to facilitate connection. In this way, the input transistor M1 and the reset transistor M2 will be far away from the first voltage signal line 61, resulting in problems in the connection between the reset transistor M2 and the first voltage signal line 61. If a lead is added in each stage of the shift register to connect the first voltage signal line 61 and the reset transistor M2, the lead is long. Considering the spacing between each stage and the via and transistor design, it will make the shift register layout design difficult, the occupied space will increase, and the area of ​​the peripheral area will be indirectly increased, which will increase the border of the display panel.

[0146] Based on this, the display panel 100 also includes an auxiliary first voltage signal line 62 located on the other side of the gate drive circuit 20, and the first voltage signal line 61 is electrically connected to the auxiliary first voltage signal line 62; the input transistor M1 and the reset transistor M2 are close to the auxiliary first voltage signal line 62 relative to the noise reduction transistor M; at least part of the reset transistor M2 of the shift register 30 is electrically connected to the auxiliary first voltage signal line 62 through the first lead line 71.

[0147] Exemplarily, as shown in Figures 13 and 14A, the first voltage signal line 61 and the auxiliary first voltage signal line 62 are respectively arranged on both sides of the gate drive circuit 20 along the row direction X, and the first voltage signal line 61 and the auxiliary first voltage signal line 62 both extend along the column direction Y, that is, the auxiliary first voltage signal line 62 is close to the display area AA and is close to the reset transistor M2. At least part of the shift register 30 can electrically connect the reset transistor M2 and the auxiliary first voltage signal line 62 through their respective first lead-out lines 71, and the first voltage signal line 61 and the auxiliary first voltage signal line 62 are electrically connected, thereby realizing the electrical connection between the reset transistor M2 and the first voltage signal line 61.

[0148] By setting an auxiliary first voltage signal line 62, the reset transistor M2 and the auxiliary first voltage signal line 62 are connected with a first lead line 71. Since the auxiliary first voltage signal line 62 is closer to the reset transistor M2, compared with leading the line from the first voltage signal line 61 to connect to the reset transistor M2, the length of the first lead line 71 is shortened, the connection difficulty is reduced, the connection reliability is improved, the spatial layout of the gate drive circuit is optimized, the narrow frame of the display panel is achieved, and the signal transmission efficiency is improved.

[0149] In some embodiments, the display panel also includes: a connecting voltage signal line 63 arranged on the side of the last-stage shift register of the gate drive circuit 20 away from other shift registers 30, the voltage signal line 61 and the auxiliary voltage signal line 62 are connected through the connecting voltage signal line 63; the connecting voltage signal line 63 extends along the row direction X; the connecting voltage signal line 63 includes a plurality of electrically connected sub-signal lines 631.

[0150] For example, continuing to refer to Figures 13 and 14A, the connecting voltage signal line 63 extends along the row direction X and includes multiple electrically connected sub-signal lines 631. The sub-signal lines 631 here are connected in parallel, which can reduce the resistance of the connecting voltage signal line 63 and reduce the signal transmission loss. By setting the connecting voltage signal line 63, the penetration of ultraviolet light and the occurrence of electrostatic breakdown can be reduced.

[0151] In some embodiments, the noise reduction transistor of the shift register 30 is connected to the voltage signal line 61 via a second lead line 72 .

[0152] Exemplarily, referring to Figures 13 and 14A and 14B, the second lead line 72 is electrically connected to the first voltage signal line 61, the second lead line 72 is interspersed between multiple noise reduction transistors M, and the second lead line 72 is electrically connected to the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13, the fourteenth transistor M14, the sixteenth transistor M16 and the seventeenth transistor M17 of the multiple noise reduction transistors M, and the second lead line 72 is configured to transmit the first voltage signal to some transistors in the shift register 30 at this level.

[0153] The following describes the film layer positions of each signal line located in the peripheral area.

[0154] It should be noted that, referring to Figures 14A to 14C, optionally, the first voltage signal line 61 can be set in the same layer and material as the gate of the transistor, and the auxiliary first voltage signal line 62 and the second lead line 72 can be set in the same layer and material as the source and drain of the transistor. The second lead line 72 is electrically connected to the first voltage signal line 61 through a via (the via is filled with a transfer electrode, and the optional transfer electrode is in the same layer as the common electrode layer of the display area AA), and multiple transistors are electrically connected to other signal lines through vias.

[0155] The connecting voltage signal line 63 and the auxiliary first voltage signal line 62 are set in the same layer and material. Optionally, the two are set in the same layer and material as the source and drain of the transistor. One end of the connecting voltage signal line 63 is electrically connected to the first voltage signal line 61 through a via (the via is filled with a transfer electrode, and the optional transfer electrode is in the same layer as the common electrode layer of the display area AA), and the other end is electrically connected to the auxiliary first voltage signal line 62.

[0156] Optionally, the auxiliary first voltage signal line 62, the connecting voltage signal line 63 and the first lead line 71 are formed in the same layer and material as an integral structure, and are provided in the same layer and material as the source and drain of the transistor. One of the source and drain of the reset transistor M2 is electrically connected to the first voltage signal line 61 through the first lead line 71.

[0157] Exemplarily, referring to Figures 14A and 14B, in combination with Figure 5, the first voltage signal line 61 is located in the gate layer 101, the auxiliary first voltage signal line 62, the connecting voltage signal line 63, the first lead line 71 and the second lead line 72 are located in the source and drain metal 105, and a transfer electrode layer 108 is stacked on the source and drain metal layer. Exemplarily, the transfer electrode layer 108 is in the same layer and material as the common electrode layer 107, and the transfer electrode layer 108 includes a plurality of transfer electrodes, and vias are provided between the transfer electrodes and the gate layer and the source and drain metal layer. The transfer electrodes are used to electrically connect the signal line located in the gate layer 101 and the signal line located in the source and drain metal layer 105. The first voltage signal line 61 is connected to the second lead line 72 through the corresponding transfer electrode, and the first voltage signal line 61 is connected to the connecting voltage signal line 63 through the corresponding transfer electrode.

[0158] In some examples, the second voltage signal line VDDO and the third voltage signal line VDDE are both set in the same layer and material as the gate of the transistor, the second voltage signal line VDDO and the third voltage signal line VDDE are located in the gate layer 101, the second voltage signal line VDDO is connected to the lead line in the shift register through the corresponding switching electrode, and the third voltage signal line VDDE is connected to the lead line in the shift register through the corresponding switching electrode.

[0159] In some embodiments, the plurality of noise reduction transistors M include a plurality of groups of transistors, each group of transistors includes two transistors; the second lead line 72 is located between the two transistors in each group of transistors, and the two transistors are staggered in the column direction.

[0160] For example, referring to Figure 15A, a group of transistors includes two transistors T and T', for example, a ninth transistor M9 and a fifteenth transistor M15, and the two transistors are staggered in the column direction Y. In combination with Figure 11E and Figure 14B, the gate of the ninth transistor M9 is electrically connected to the third lead line 73, and one of the source and drain of the ninth transistor M9 is electrically connected to the third lead line 73 through the first switching electrode 1081 and the corresponding via hole. The third lead line 73 is electrically connected to the second voltage signal line VDDO through the switching electrode and the corresponding via hole. The gate of the fifteenth transistor M15 is electrically connected to the fourth lead line 74, and one of the source and drain of the fifteenth transistor M15 is electrically connected to the fourth lead line 74 through the first switching electrode 1082 and the corresponding via hole. The fourth lead line 74 is electrically connected to the third voltage signal line VDDE through the switching electrode and the corresponding via hole. It can be seen that the ninth transistor M9 and the fifteenth transistor M15 are located on either side of the second lead line 72 and are staggered in the column direction Y. That is, they are not arranged in a straight line in the column direction. The first transfer electrode 1081 and its via hole, and the first transfer electrode 1082 and its via hole corresponding to the ninth transistor M9 and the fifteenth transistor M15 are also staggered in the column direction. Correspondingly, the shape of the second lead line 72 is slightly curved along the row direction X to match the spatial positions of the transistors arranged on either side of it.

[0161] For example, referring to FIG. 15B , the third switching electrode 1083 and the fourth switching electrode 1084 are located on both sides of the second lead line, and the third switching electrode 1083 and the fourth switching electrode 1084 are staggered in the column direction.

[0162] The above-mentioned group of transistors and group of transfer electrodes are all arranged in a staggered manner in the column direction. On the one hand, this can compress the space in the column direction Y and reduce the height of each level of shift register (that is, the size of the area where each level of shift register 30 is located in the column direction). In high-resolution products, this is beneficial to the arrangement of shift registers. On the other hand, it can increase the life of the gate drive circuit.

[0163] In some embodiments, as shown in FIG. 14A , a size L of a region where each stage of the shift register 30 is located in the column direction is 60 μm to 100 μm.

[0164] Exemplarily, the size L of the region where each stage of the shift register 30 is located in the column direction is 60 μm, 80 μm or 100 μm.

[0165] As shown in Figures 2A and 10, some embodiments of the present disclosure also provide a driving method for a display panel, including a display panel provided by any of the above embodiments, wherein the multiple pixel groups 2 include multiple row pixel groups arranged along the column direction Y, and each row pixel group includes at least two pixel groups 2 arranged along the row direction; each row pixel group is arranged between a first gate line 31 and a second gate line 32 of a gate line group 3, and is electrically connected to the gate line group 3; the driving method includes: when the display panel 100 displays a first setting screen, the gate drive circuit 20 outputs a first group of gate drive signals, and the multiple row pixel groups 2 are started row by row under the scanning of the multiple gate line groups 3, and in each row pixel, the first sub-pixel electrically connected to the first gate line 31 is turned on before the second sub-pixel electrically connected to the second gate line 32.

[0166] Exemplarily, the above-mentioned first setting picture is a picture other than sky blue, which can be a pink picture, or an uncommon picture such as a yellow picture, or an ordinary picture. At this time, the grayscale voltage difference of each sub-pixel is small, which will not affect the fluctuation of the voltage transmission signal, thereby ensuring that the brightness difference of the sub-pixels is not obvious, and the display panel can display normally. The first group of gate drive signals output by the gate drive circuit 20 can drive each row of pixels to turn on row by row. At the same time, the first sub-pixel electrically connected to the first gate line 31 turns on before the second sub-pixel electrically connected to the second gate line 32. Referring to Figure 12A, the first sub-pixel in Figure 12A is a blue sub-pixel and a red sub-pixel, and the second sub-pixel is a blue sub-pixel and a green sub-pixel, wherein, under the control of the first group of gate drive signals, the first sub-pixel turns on before the second sub-pixel.

[0167] In some embodiments, referring to Figure 10, when the display panel 100 displays the second setting screen, the gate drive circuit 20 outputs a second gate drive signal, and the multiple row pixel groups are started row by row under the scanning of the multiple gate line groups 3, and in each row pixel, the second sub-pixel electrically connected to the second gate line is turned on before the first sub-pixel electrically connected to the first gate line.

[0168] Exemplarily, the above-mentioned second setting screen is a sky blue screen. At this time, the grayscale voltage difference of each sub-pixel is large, which will affect the fluctuation of the voltage transmission signal. The sub-pixel light and dark difference is obvious, and it is easy to have a situation where the vertical stripes are not good, causing the display panel screen to not display normally. The second group of gate drive signals output by the gate drive circuit 20 can drive each row of pixels to turn on row by row. At the same time, the first sub-pixel electrically connected to the second gate line 32 turns on before the second sub-pixel electrically connected to the first gate line 31. In this way, changing the turn-on order of the driven sub-pixels can improve the undercharging phenomenon between the sub-pixels, thereby reducing the voltage difference and improving the problem of poor vertical stripes displayed on the screen. Referring to Figure 12A, the first sub-pixel in Figure 12A is a blue sub-pixel and a red sub-pixel, and the second sub-pixel is a blue sub-pixel and a green sub-pixel. Wherein, under the control of the second group of gate drive signals, the second sub-pixel turns on before the first sub-pixel, that is, the second sub-pixel electrically connected to the even-numbered row gate lines is electrically connected before the odd-numbered row gate lines.

[0169] As shown in FIG16 , some embodiments of the present disclosure further provide a display device 1000 , comprising the display panel 100 provided by any of the above embodiments.

[0170] Exemplarily, the display device 1000 may be a Mini LED (Mini Light Emitting Diode) display device, or the display device 1000 may be a Micro LED (Micro Light-Emitting Diode) display device.

[0171] In some examples, mini light-emitting diodes or micro light-emitting diodes are used as light-emitting devices. Compared with traditional LEDs, they occupy a smaller volume and have smaller particles. Within the same screen size, the light source density per unit area is higher and the unit size of the light source is smaller. Therefore, more precise local control of the light-emitting device can be achieved, and the uniformity of the display brightness can be guaranteed, thereby ensuring the display quality of the display device 1000.

[0172] Some embodiments of the present disclosure provide a display device 1000, which can be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or electronic. More specifically, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0173] The embodiments of the present disclosure do not impose any special restrictions on the specific form of the above-mentioned display device. The display device 1000 adopts the display panel 100 provided by the above-mentioned embodiments. Therefore, the display device 1000 provided by the present disclosure has all the beneficial effects of the display panel 100 provided by any of the above embodiments, which will not be repeated here.

[0174] Exemplarily, as shown in FIG16 , the display device 1000 is, for example, rectangular.

[0175] In some embodiments, referring to Figures 17 and 11A, the display device 1000 further includes M clock signal lines, the i-th clock signal line is connected to the (Mm+i)-th stage shift register, wherein 1≤i≤M, and i is a positive integer, 0≤m, and m is a positive integer; (Mm+i)≤N; the display device 1000 further includes a control chip 50, the control chip 50 is connected to the M clock signal lines, and outputs clock signals to the M clock signal lines; the control chip 50 is configured to, when detecting that the display panel displays the first setting screen, output valid clock signals to the M clock signal lines in a first order in sequence, wherein the first order is 1, 2, 3, 4...M-1, M; when detecting that the display panel displays the second setting screen, output valid clock signals to the M clock signal lines in a second order in sequence, wherein the second order is 2, 1, 4, 3...M, M-1.

[0176] For example, FIG17 shows eight clock signal lines, i.e., M is equal to eight. When m is equal to 0, the first clock signal line is connected to the first-stage shift register. The display device 1000 includes a control chip 50, which is connected to the eight clock signal lines and outputs timing signals to the eight clock signal lines. When the control chip 50 detects that the display panel displays the first setting screen, it sequentially outputs valid clock signals to the eight clock signal lines in a first order, wherein the first order is 1, 2, 3, 4, 5, 6, 7, and 8. When the control chip 50 detects that the display panel displays the second setting screen, it sequentially outputs valid clock signals to the eight clock signal lines in a second order, wherein the second order is 2, 1, 4, 3, 6, 5, 8, and 7. FIG17 shows only one example. For other numbers of clock signal lines, the order of the clock signals output in the corresponding setting screen can be calculated by referring to the above formula and is not described in detail here.

[0177] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate substrate; A plurality of sub-pixels arranged in an array on the substrate, the plurality of sub-pixels are arranged into E rows and F columns; the plurality of sub-pixels form a plurality of pixel groups, each of the pixel groups includes a first sub-pixel and a second sub-pixel, the first sub-pixel includes a first transistor and a first electrode group connected to each other, and the second sub-pixel includes a second transistor and a second electrode group; the first electrode group and the second electrode group are sequentially arranged along the row direction; the first transistor and the second transistor are both located between the first electrode group and the second electrode group, and are respectively located at two ends of the pixel group along the column direction; the first electrode group includes a first pixel electrode and a first common electrode, and the second electrode group includes a second pixel electrode and a second common electrode; A plurality of gate lines are arranged on the substrate, the plurality of gate lines form a plurality of gate line groups, each of the plurality of gate line groups comprises a first gate line and a second gate line, and the first sub-pixel and the second sub-pixel of each pixel group are respectively connected to the first gate line and the second gate line of one gate line group; A plurality of data lines are arranged on the substrate, the first sub-pixel and the second sub-pixel of each pixel group are connected to one of the data lines; at least part of the plurality of data lines include a third data segment extending in a row direction, a first data segment and a second data segment extending in a column direction, the third data segment connects the first data segment and the second data segment, the first data segment is arranged between the sub-pixel in the i-th column and the sub-pixel in the (i+1)-th column, the second data segment is arranged between the sub-pixel in the (ij)-th column and the sub-pixel in the (ij-1)-th column, j is greater than or equal to 1; i+1≤F; The overlapping area between the first pixel electrode and the first common electrode is equal to the overlapping area between the second pixel electrode and the second common electrode.

2. The array substrate according to claim 1, wherein: j＝1； The two outermost data lines in the row direction are the first data line and the second data line, the first data segment of the first data line is arranged between the first column of sub-pixels and the second column of sub-pixels, and the second data segment of the first data line is arranged on a side of the first column of sub-pixels away from the plurality of columns of sub-pixels; The first data segment of the second data line is arranged at a side of the Fth column sub-pixel away from the multiple columns of sub-pixels, and the second data segment of the first data line is arranged between the (F-1)th column sub-pixel and the Fth column sub-pixel.

3. The array substrate according to claim 1 or 2, wherein: At least a portion of the data line connected to the pixel group is located between the first electrode group and the second electrode group of the pixel group; at least a portion of the data line is the first data segment or the second data segment; The first electrode of the first transistor and the first electrode of the second transistor are both connected to the data line, the second electrode of the first transistor is connected to the first pixel electrode, and the second electrode of the second transistor is connected to the second pixel electrode; The first electrode of the first transistor points to the second electrode, and the direction parallel to the row direction is the first direction, the first electrode of the second transistor points to the second electrode, and the direction parallel to the row direction is the second direction, and the first direction is The second direction is opposite.

4. The array substrate according to claim 3, wherein: The first transistor and the second transistor each include a gate, an active layer, and a source and drain electrode stacked in sequence, the source and drain electrode include a first electrode and a second electrode, the orthographic projection of the active layer on the substrate falls within the orthographic projection of the gate electrode on the substrate, and at least part of the orthographic projections of the first electrode and the second electrode on the substrate fall within the orthographic projection of the active layer on the substrate; The orthographic projection shape of the first pole is U-shaped, and the opening of the first pole faces the second pole.

5. The array substrate according to any one of claims 1 to 4, wherein: The first pixel electrode and the second pixel electrode are block electrodes, the first common electrode and the second common electrode are strip electrodes, and the first common electrode and the second common electrode each include a plurality of slits; The aperture ratio of the first sub-pixel is equal to the aperture ratio of the second sub-pixel; The first electrode group includes a first domain region and a second domain region arranged along a column direction, the second electrode group includes a third domain region and a fourth domain region arranged along a column direction, and the aperture ratios of the first domain region, the second domain region, the third domain region and the fourth domain region are equal.

6. The array substrate according to any one of claims 1 to 5, wherein: The array substrate further comprises: a first spacer disposed on a side of the first transistor away from the base substrate, and a second spacer disposed on a side of the second transistor away from the base substrate; The center of the orthographic projection of the first spacer on the substrate is offset by a first distance toward a third direction relative to the center of the orthographic projection of the first transistor on the substrate, and the third direction is a direction from the first transistor to the second transistor; The center of the orthographic projection of the second spacer on the base substrate is offset by a second distance toward a fourth direction relative to the center of the orthographic projection of the second transistor on the base substrate. The fourth direction is the direction from the second transistor to the first transistor.

7. The array substrate according to claim 6, wherein: The first distance is equal to the second distance.

8. The array substrate according to claim 7, wherein: The orthographic projection of the first spacer on the base substrate overlaps with the orthographic projections of the first pixel electrode and the second pixel electrode on the base substrate; The orthographic projection of the second spacer on the base substrate overlaps with the orthographic projections of the first pixel electrode and the second pixel electrode on the base substrate.

9. A display panel, comprising: Display area and peripheral area; The display panel comprises: The array substrate according to any one of claims 1 to 8 above, wherein the plurality of pixel groups are located in the display area; At least one gate driving circuit is disposed on the substrate, the gate driving circuit is located in the peripheral area; the gate driving circuit includes N cascaded shift registers; The output end of the i-th shift register is connected to the input end of the i+n-th shift register; the output end of the i+n+2j-th shift register is connected to the reset end of the i-th shift register; j is greater than or equal to 1; The plurality of gate lines are arranged in sequence along a column direction, and the plurality of first gate lines and the plurality of second gate lines are arranged alternately; In the N cascaded shift registers, the shift register is electrically connected to the gate line.

10. The display panel according to claim 9, wherein: The plurality of shift registers are arranged along a column direction; The display panel further comprises: a first voltage signal line arranged on one side of the gate driving circuit along the row direction; Each stage of the shift register includes a plurality of transistors, at least one of the plurality of transistors is electrically connected to the first voltage signal line; The plurality of transistors include a reset transistor and a plurality of noise reduction transistors, the shift register further includes an input transistor, the input transistor and the reset transistor are away from the first voltage signal line relative to the noise reduction transistor; The display panel further includes an auxiliary first voltage signal line located at the other side of the gate driving circuit, the first voltage signal line is connected to the auxiliary first voltage signal line; the input transistor and the reset transistor are close to the auxiliary first voltage signal line relative to the noise reduction transistor; At least part of the reset transistors of the shift register are connected to the first auxiliary voltage signal line through a first lead line.

11. The display panel according to claim 10, wherein: The display panel further comprises: a connection voltage signal line arranged at a side of the last stage shift register of the gate driving circuit away from other shift registers, the first voltage signal line and the auxiliary first voltage signal line are connected through the connection voltage signal line, and the connection voltage signal line extends along the row direction; The connection voltage signal line includes a plurality of electrically connected sub-signal lines.

12. The display panel according to claim 11, wherein: The noise reduction transistor of the shift register is connected to the first voltage signal line through a second lead line.

13. The display panel according to claim 12, wherein: The plurality of noise reduction transistors include a plurality of groups of transistors, each group of transistors includes two transistors; the second lead wire is located between the two transistors in each group of transistors; The two transistors in at least one group of transistors are arranged with an offset in a column direction.

14. The display panel according to any one of claims 9 to 13, wherein: The size of the area where each stage of the shift register is located in the column direction is 60 μm to 100 μm.

15. The display panel according to any one of claims 9 to 14, wherein: The display panel further includes: M clock signal lines are arranged on a side of the gate driving circuit away from the display area, the clock signal lines are electrically connected to the gate driving circuit, wherein the i-th clock signal line is connected to the (Mm+i)-th shift register, wherein 1≤i≤M, and i is a positive integer, 0≤m, and m is a positive integer; (Mm+i)≤N; The starting position of the valid clock signal output by the i-th clock signal line is earlier than the starting position of the valid clock signal output by the i+1-th clock signal line, i+1≤M.

16. The display panel according to claim 15, wherein: Starting from the first clock signal line, every two adjacent clock signal lines form a group. The second clock signal line in each group The starting position of the valid clock signal transmitted by the first clock signal line is earlier than the starting position of the valid clock signal transmitted by the first clock signal line; A starting position of a valid clock signal transmitted by the i-th clock signal line is earlier than a starting position of a valid clock signal transmitted by the i+2-th clock signal line; i+2≤M.

17. A method for driving a display panel, applied to the display panel according to any one of claims 9 to 16, wherein: The plurality of pixel groups include a plurality of row pixel groups arranged along a column direction, and each row pixel group includes at least two pixel groups arranged along a row direction; Each row of pixel groups is arranged between a first gate line and a second gate line of a gate line group and is electrically connected to the gate line group; the driving method comprises: When the display panel displays a first setting screen, the gate drive circuit outputs a first set of gate drive signals, the multiple row pixel groups are activated row by row under the scanning of the multiple gate line groups, and in each row pixel, the first sub-pixel electrically connected to the first gate line is turned on before the second sub-pixel electrically connected to the second gate line.

18. The method for driving a display panel according to claim 17, wherein: Also includes: When the display panel displays a second setting screen, the gate driving circuit outputs a second gate driving signal, the multiple row pixel groups are started row by row under the scanning of the multiple gate line groups, and in each row pixel, the second sub-pixel electrically connected to the second gate line is turned on before the first sub-pixel electrically connected to the first gate line.

19. A display device comprising: A display panel as claimed in claims 9 to 16.

20. The display device according to claim 19, wherein: The display device further includes M clock signal lines, the i-th clock signal line is connected to the (Mm+i)-th shift register, wherein 1≤i≤M, and i is a positive integer, 0≤m, and m is a positive integer; (Mm+i)≤N; The display device further includes a control chip, the control chip being connected to the M clock signal lines and outputting clock signals to the M clock signal lines; The control chip is configured to, when detecting that the display panel displays a first setting screen, output valid clock signals to the M clock signal lines in sequence in a first order, wherein the first order is 1, 2, 3, 4...M-1, M; and when detecting that the display panel displays a second setting screen, output valid clock signals to the M clock signal lines in sequence in a second order, wherein the second order is 2, 1, 4, 3...M, M-1.

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