Split register list for renaming

Abstract

The disclosed system may include a processor configured to detect that a data unit size of an instruction is less than a register. The processor may assign a first portion of the register to an instruction to enable a second portion of the register to be used for assignment to an additional instruction. The processor may also track registers that are split registers. Various other methods, systems, and computer readable media are also disclosed.

Description

Background Art

[0001] Modern processor architectures may incorporate various features to improve performance. For example, a processor may be able to execute instructions decoded from program code, such as processor-level micro-operations (uops or μops), non-sequentially or out of order. Instructions may access registers (e.g., fast local storage in the processor that may hold data for the instruction operation), and more specifically may access architectural registers (e.g., registers defined by the instruction architecture that may be visible to software and may be abstracted from physical registers in the processor) to perform operations.

[0002] Because instructions may be executed out of order, an instruction may modify an architectural register in a way that may change another instruction. For example, a first instruction may need to store the result of a second instruction in an architectural register, while another instruction may load a value into an architectural register. Loading the value into an architectural register may prevent the first instruction from operating on the correct value. To prevent this, during the renaming stage of the processor's instruction pipeline, the processor may map an architectural register or other logical register (e.g., a register abstracted from a physical register) to a different physical register. The processor may include more physical registers than the number of architectural registers defined in the instruction architecture.

[0003] During the renaming phase, the processor may select free physical registers for mapping. Thus, the processor may keep track of which of its physical registers are free. In some architectures, the processor may support instructions of different register sizes. For example, some instructions may use architectural registers that each correspond to two physical registers, while other instructions may use architectural registers that each correspond to one physical register. To simplify register management, the processor may manage physical registers based on the maximum architectural register size supported. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The accompanying drawings illustrate several exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

[0005] Figure 1 is a block diagram of an exemplary system for managing free registers for renaming using a split register list.

[0006] Figure 2 is a flow chart of an exemplary renaming workflow.

[0007] Figure 3 is a block diagram of the register.

[0008] Figure 4 is a diagram of an exemplary list for managing split registers.

[0009] Figure 5 is a simplified circuit diagram for deriving a free list.

[0010] Figure 6 is a flow chart of an exemplary method for managing free registers for renaming using a split register list.

[0011] Figure 7 is a simplified top-level view of an exemplary split-register renaming workflow.

[0012] Figure 8 is a flow chart of an exemplary return workflow.

[0013] Fig. 9 is a flow chart of an exemplary list update workflow.

[0014] FIG. 10A to FIG. 10B is a flow chart of an exemplary workflow for picking a register.

[0015] FIG. 11A to FIG. 11B is a flow chart of an exemplary workflow for renaming.

[0016] Throughout the drawings, the same reference numerals and descriptions represent similar but not necessarily identical elements. Although the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been illustrated by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the specific forms disclosed. On the contrary, the present disclosure covers all modifications, equivalents, and alternatives that fall within the scope of the appended claims. DETAILED DESCRIPTION

[0017] As will be described in more detail below, the present disclosure describes various systems and methods for managing split registers in a split register list for renaming. In order to simplify the management of registers, the processor can manage physical registers based on the maximum architectural register size supported. However, such a scheme may cause physical registers to be unused, for example when supporting instructions of smaller sizes. Therefore, in one example, a method for managing split registers for renaming may include detecting that the data unit size of an instruction is smaller than a register, and allocating a first portion of a register to an instruction so that a second portion of the register can be used to allocate to additional instructions. The method may also include tracking registers that are split registers.

[0018] In some examples, tracking registers may include marking the registers in a split register list. The split register list may track the split registers based on one of an even address value or an odd address value so that the corresponding second portion has the other of an even address value or an odd address value. In some examples, the method may further include unmarking the register in the split register list when the first portion and the second portion are free.

[0019] In some examples, the method may include selecting a register from a free register list. The free registers each being a pair of register portions may be tracked in the free register list. In addition, the method may include tracking the second portion of the register in the free register portion list.

[0020] In some examples, the method may include marking the first portion as free when the instruction is completed. In some examples, the method may also include allocating the second portion to the second instruction. In some examples, the data unit size may correspond to the instruction width of the instruction. In some examples, the size of the register may correspond to the wide instruction width.

[0021] In one example, a method for managing split registers for renaming may include detecting that a data unit size of an instruction is less than a register size, and selecting a free register having the register size for the instruction from a free register list. The method may also include assigning a first portion of the selected register to the instruction so that a second portion of the selected register can be used for assignment to additional instructions, and tracking the selected register as a split register in the split register list.

[0022] In one specific implementation, a system for managing split registers for renaming may include a physical memory and at least one physical processor, the at least one physical processor including a plurality of registers and a control circuit for managing register allocation for instructions. The control circuit is configured to select a free register from a free register list for an instruction having a data unit size smaller than the register. The control circuit may be further configured to allocate a first portion of the selected register to the instruction so that a second portion of the selected register can be used for allocation to additional instructions, and to track the selected register as a split register in the split register list.

[0023] Features from any of the above-described implementations may be used in combination with each other according to the general principles described herein. These and other implementations, features and advantages will be more fully understood after reading the following detailed description in conjunction with the accompanying drawings and claims.

[0024] The present disclosure as a whole relates to splitting registers during the renaming stage of an instruction pipeline of a processor. As will be explained in more detail below, the present disclosure provides systems and methods for splitting and tracking registers, which may be combinations of physical registers. Instead of tracking a single physical register, the processor may track combinations of physical registers (as registers) and split the combination when an instruction does not require the combined register. The processor may use a bit vector to track whether a register is a split register to avoid the need to make significant changes to the processor's renaming scheme.

[0025] For example, a specific implementation of the present disclosure may detect that the data unit size of an instruction is smaller than a register. In response, a specific implementation of the present disclosure may allocate a first portion of the register to the instruction so that a second portion of the register can be used to allocate to additional instructions. The register may be tracked as a split register.

[0026] According to the general principles described herein, the features of any specific implementation described herein can be used in combination with each other. These and other specific implementations, features and advantages will be more fully understood after reading the following detailed description in conjunction with the accompanying drawings and claims.

[0027] The following will refer to Figures 1 to 6 Provides detailed descriptions of various implementations of split register renaming. Figure 1 A detailed description of an example system for managing split registers is provided. Figure 2 A detailed description of the example renaming workflow is provided. Figure 3 and Figure 4 Provides detailed descriptions of registers and split register lists. Figure 6 A detailed description of an example method for managing split registers for renaming is provided.

[0028] Figure 1 1 is a block diagram of an example system 100 for managing split registers for renaming. The system 100 may correspond to a computing device such as a desktop computer, a laptop computer, a server, a tablet device, a mobile device, a smartphone, a wearable device, an augmented reality device, a virtual reality device, a network device, and / or an electronic device. Figure 1As illustrated, system 100 may include one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical drive, cache, variations or combinations of one or more of the foregoing, and / or any other suitable memory.

[0029] like Figure 1 As illustrated, the example system 100 may include one or more physical processors, such as processor 110. Processor 110 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 may access and / or modify data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system on a chip (SoC), a portion of one or more of the above components, a variation or combination of one or more of the above components, and / or any other suitable physical processor.

[0030] In some implementations, the term "instruction" may refer to computer code that can be read and executed by a processor. Examples of instructions may include, but are not limited to, macroinstructions (e.g., program code that may need to be decoded by a processor into processor instructions that the processor can directly execute) and micro-operations (e.g., low-level processor instructions that can be decoded from macroinstructions and form part of the macroinstructions).

[0031] like Figure 1 As further illustrated in , processor 110 may include control circuitry 112, registers 130, register list 140, and split register list 150. Control circuitry 112 may correspond to a rename unit or other similar control unit, and may include circuitry and / or instructions for allocating and / or assigning registers to instructions. Register 130 may correspond to one or more registers of processor 110. Register list 140 may correspond to a free list that may track which of registers 130 are free (e.g., not used) and / or which of registers 130 are unavailable. Split register list 150 may correspond to one or more lists that may track which of registers 130 have been split into register portions.

[0032] In some implementations, the term "register" may refer to a fast local storage of a processor that can be used to store operating data. Examples of registers may include, but are not limited to, physical registers (e.g., physical storage units in a processor), logical registers (e.g., registers that can be referenced by instructions and dynamically mapped to physical registers), and architectural registers (e.g., registers defined by an architecture that is visible to software and dynamically mapped to physical registers). In some examples, a register (e.g., a dual register) may refer to more than one physical register. In some examples, the size or number of bits of a physical register may be defined by the hardware architecture of the processor.

[0033] Figure 2 An exemplary pipeline 200 of a processor (such as processor 110 (and / or its functional units)) for executing instructions is illustrated. During the fetch stage 202, the processor 110 can read program instructions from the memory 120. The processor 110 can fetch based on active threads or other criteria. At the decode stage 204, the processor 110 can decode the read program instructions into micro-operations. The processor 110 (and / or its functional units) can forward the newly decoded micro-operations to the scheduler, which can queue the micro-operations until they are ready to be dispatched. At the dispatch stage 206, the scheduler can dispatch one or more micro-operations ready for dispatch. When the dependencies of the micro-operation (e.g., resources that may depend on other instructions to complete execution) have been resolved, the micro-operation can be ready to be dispatched. In some examples, the scheduler can select a ready micro-operation in response to the execution unit of the processor 110 becoming available.

[0034] At the renaming stage 208, the control circuit 112 may assign registers to the dispatched micro-operations as needed. The control circuit 112 may access one or more of the following: a register file 230 (which may correspond to and / or represent registers 130), a free list 240 (which may correspond to the register list 140), and a split register list 250 (which may correspond to the split register list 150). The register file 230 may correspond to the register array of the processor 110. Figure 3 Register file 330 is illustrated (which may correspond to register file 230 ).

[0035] like Figure 3As illustrated, register file 330 may include dual register 332, dual register 334, and dual register 336. In some examples, processor 110 implements an architecture that may support wide instructions that may operate with a data unit size that is larger than the register size of a physical register. For example, a wide instruction or special instruction may operate with a data unit size that is twice the size of a physical register. The data unit size may correspond to the bit size of the data unit operated by the instruction. In some examples, the data unit size also corresponds to the instruction width (e.g., the bit size of the instruction). To support wide instructions, processor 110 manages registers and physical register pairs so that the dual register size may be twice the size of the physical register. Thus, as shown in FIG. Figure 3 As shown, the double register 332 includes a physical register 333A (having an address of "00") and a physical register 333B (having an address of "01"), the double register 334 includes a physical register 335A (having an address of "02") and a physical register 335B (having an address of "03"), and the double register 336 includes a physical register 337A (having an address of "04") and a physical register 337B (having an address of "05"). Although the double register described herein includes a pair of physical registers, in other specific implementations, the double register may include a different number (e.g., three, four, etc.) of physical registers.

[0036] The physical registers of each register may be contiguous, such that the register may include two contiguous physical registers, but in other examples, the physical registers may not be contiguous. Figure 3 As shown, because each double register includes a pair of consecutive physical registers, each double register is associated with an even address value. For example, double register 332 has address 00 (because address 01 is considered part of double register 332). Similarly, double register 334 has address 02, and double register 336 has address 04. In other specific implementations, a register may have an odd address value, while the associated second physical register has an even address value.

[0037] During the renaming stage 208, the processor 110 may allocate one of the dual register 332, dual register 334, or dual register 336 based on availability. In other words, the processor 110 may allocate two physical registers to the instruction. However, in some examples, the instruction may have a data unit size and / or instruction width that may be smaller than the size of the dual register. The instruction may not require two physical registers. The systems and methods described herein allow for splitting the dual register into portions that may correspond to physical registers.

[0038] Figure 4A register list 440, a split register list 450 (which may correspond to the split register list 150 and / or the split register list 250), a derived dual register list 460, and a derived single register list 461 (which may correspond to the free list 240 and / or the register list 140) are illustrated. In some examples, the register list 440 includes a register list 442A and a register list 442B. The register list 442A tracks the availability of physical registers corresponding to the first portion of the dual registers, and the register list 442B tracks the availability of physical registers corresponding to the second portion of the dual registers. In some examples, the register list 442A may track even physical registers (e.g., physical registers with even addresses), and the register list 442B may track odd physical registers (e.g., physical registers with odd addresses). To avoid the use of a rename table or other complex structures, vectors are used to track the availability of dual registers and single registers (including the derived dual register list 460 and the derived single register list 461).

[0039] Figure 4 The size of the various register lists shown can be N / L, where N is the maximum or total number of single physical registers available in the processor. In the example described herein, N is 384 (e.g., 384 physical registers). L corresponds to the number of physical registers that can be combined as described herein, such as 2 physical registers combined into a double register. L also corresponds to the number of lists, and N is a multiple of L. In the example described herein, L is 2, corresponding to 2 register lists (e.g., register list 442A and register list 442B), and further corresponds to a double register including 2 physical registers (e.g., even registers and odd registers). Each of the lists (e.g., register list 442A, register list 442B, split register list 450, derived double register list 460 and / or derived single register list 461) is indexed from [0...N / L-1] and each stores data corresponding to different aspects of the register. For example, register list 442A is implemented as a 192-bit vector (e.g., 384 / 2) that holds information about even addressable registers, while register list 442B is implemented as a 192-bit vector that holds information about odd addressable registers. In other examples, L can be a different value. In one particular example, if the physical registers are 128-bit size registers, it may be desirable to be able to assign one physical register to a 128-bit micro-operation, two physical registers to a 256-bit micro-operation, and four physical registers to a 512-bit micro-operation, so that L can be 4 in this particular example.

[0040] Because the double registers are managed as pairs of physical registers (e.g., L=2), each double register has an address with an even value (e.g., corresponding to a physical register number or PRN), such as Figure 3 442A and 442B. As further illustrated in FIG. 442A , derived double register list 460 corresponds to a free double register list (indicating which double registers are free), and derived single register list 461 corresponds to a free single register list (indicating which single registers are free). Derived double register list 460 (also stored in registers) is a list derived from an AND combination of register list 442A and register list 442B. Derived single register list 461 (also stored in registers) is a list derived from an XOR combination of register list 442A and register list 442B. Figure 5 An example simplified circuit 500 for deriving dual register and single register lists is illustrated.

[0041] Figure 5 The even list 542A may correspond to the register list 442A, the odd list 542B may correspond to the register list 442B, the split vector 550 may correspond to the split register list 150, the AND gate 544, the XOR gate 546, the dual list 560 may correspond to the derived dual register list 460, the single list 561 may correspond to the derived single register list 461, and the rename block 582 may correspond to the rename stage 208. Each of the split vector 550, the even list 542A, and the odd list 542B has the same size N / 2 (e.g., 384 / 2=192 bit vector). Since each mark bit in the even list 542A and the odd list 542B indicates a free part of a double register (e.g., a physical register), both the even part and the odd part are free, indicating a free double register, while only one of the even part and the odd part is free, indicating a free single register. Therefore, the double list 560 is derived using the AND gate 544, and the single list 561 is derived using the XOR gate 546. For each index value, if both the even list 542A and the odd list 542B have a mark bit, the AND gate 544 marks the corresponding bit in the double list 560. In addition, for each index value, if a bit in the even list 542A or the odd list 542B is marked, but not both bits, the XOR gate 546 marks the corresponding bit in the single list 561.

[0042] Back to Figure 4 In some examples, the derived dual register list 460 and the derived single register list 461 include 192-bit vectors. Figure 4In the example shown, the double register (e.g., paired portion) is identified by an even address value, so that the derived double register list 460 tracks the even address value. Therefore, the double register from the derived double register list 460 has an even address value and includes 2 consecutive free portions (e.g., an even address PRN and a subsequent odd address PRN). The derived single register list 461 also tracks the even address value, including the most significant bit (MSB) data of the address value, but there may be no least significant bit (LSB) information of the address value. In order to specifically identify that the even portion or odd portion of the double register is free, the LSB data can be queried for one of the register lists 442A and / or register lists 442B to determine the LSB data. For example, query register list 442B (e.g., odd address) to determine the LSB state. For an index marked as free in the derived single register list 461, if the corresponding index in register list 442B is free, the LSB data indicates that the odd portion is free. Otherwise, if the corresponding index in register list 442B is not free, the LSB data indicates that the even portion is free. As described herein, the derived single register list 461 is derived from an XOR operation. The flag bit also indicates that a portion of the corresponding double register is not free in register list 442A or register list 442B.

[0043] When a new double register is being formed (e.g., both parts of the double register are freed), the corresponding address / bit in register list 442A and register list 442B is marked and propagated to the derived double register list 460. When only one of the addresses / bits in register list 442A and register list 442B is set (e.g., only a portion of the double register is free), the corresponding even address value is set in the derived single register list 461 to store the MSB data of the address value. Optionally, in some examples, to reduce power consumption, new pairs may not be tracked (e.g., updated / derived derived double register list 460) unless the number of free pairs in derived double register list 460 becomes small, such as below a threshold number of free double registers required for renaming iterations.

[0044] In some examples, split register list 450 tracks which of the registers have been split. Split register list 450 is implemented using a 192-bit vector. For example, Figure 4 As shown, split register list 450 can track even-addressed physical registers. A flag bit in split register list 450 for a register (indexed based on an even-address value) indicates that the corresponding dual register is split.

[0045] Back to Figure 2In some examples, during the renaming stage 208, the control circuitry 112 selects free dual registers (e.g., physical register pairs) for the instruction from the derived dual register list 460. If the instruction has a data unit width that matches the dual register size, or the instruction has other architectural signals (such as whether the instruction is a special instruction, the type of operation, etc.), the control circuitry 112 allocates all selected dual registers (e.g., both parts) to the instruction and indicates that the corresponding entry is not free in the derived dual register list 460 (e.g., by unmarking the corresponding bits in register list 442A and register list 442B and updating the derived dual register list 460 as described herein).

[0046] If the data unit width of the instruction is less than the register size, and there are no other architectural signals (e.g., whether the instruction is a special instruction, the type of operation, etc.), the control circuit 112 continues to allocate only the free portion of the selected double register (e.g., the free single physical register) to the instruction. If the selected double register has not been split, the control circuit 112 allocates the even portion of the selected double register to the instruction and unmarks the corresponding bit in the register list 442A. The control circuit 112 splits the selected double register (making the odd portion available) by marking the appropriate bit in the split register list 450 (e.g., marking the even address entry as split) and unmarking the appropriate bit in the derived double register list 460 (e.g., by updating / deriving the derived register list 460 as described herein). Therefore, the even portion of the selected double register is allocated to the instruction, and the odd portion is available for later allocation. Furthermore, in some examples, control circuitry 112 may proactively mark appropriate bits of a single free register portion (e.g., in register list 442B and updating derived single register list 461) as free if an instruction was previously allocated due to an architectural signal override in register list 442A and / or register list 442B (e.g., registers allocated in an earlier stage of the pipeline).

[0047] If the selected double register has been previously split (e.g., the exported single register list 461 is providing a free register and / or the exported double register list 460 has not been updated / exported), the control circuit 112 assigns an even address value to the instruction if free, or assigns a corresponding odd address value to the instruction if free, and updates the entry to non-free in the register list 440 (e.g., register list 442A or register list 442B and the exported single register list 461) accordingly. In some examples, if the instruction has a data unit width that is less than the register size, the control circuit 112 may first check the free register portion in the exported single register list 461 before selecting and splitting another free double register.

[0048] In some examples, the rename stage 208 may obtain only certain (e.g., P=6, S=6) selected register lists of dual registers or single registers. In some examples, when the selected register lists are passed to the rename stage 208, the rename stage 208 may preemptively update the entries in the register list 440 and / or the derived dual register list 460 to be not free, rather than marking the entries as free or non-free later. When the rename stage 208 is given the free list block, these selected register lists may be designated as non-free. The dual selected register lists of #P may be designated as not released from the derived dual register list 460. The single selected register list of #S may be designated as not released from the derived single register list 461 and register list 442A or register list 442B, depending on the selected LSB bit.

[0049] When a physical register is retired or returned after the instruction is completed or due to any other circumstances (e.g., clearing, etc.), the control circuit 112 updates the relevant list (e.g., one or more of the register list 140, the split register list 150, the free list 240, the split register list 250, the split register list 450, etc.) accordingly. For example, if the returned physical register has an even address value, the control circuit 112 identifies whether it is a split register (by checking the split register list 450). If the returned even physical register corresponds to a split register, the control circuit 112 marks the corresponding entry in the register list 442A as free. If the control circuit 112 determines that the returned even physical register is not a split register marked in the split register list 450, the control circuit 112 marks the appropriate entry in the register list 442A and the register list 442B for the appropriate address as free. If the returned physical register has an odd address value, the control circuit 112 marks the corresponding entry in the register list 442B as free.

[0050] In some examples, the control circuit 112 creates / derives a new dual register list and / or a new single register list (e.g., by updating / deriving as described herein), and writes the derived dual register list 460 and the derived single register list 461. The control circuit 112 unmarks the appropriate bits of the newly created dual registers in the split register list 450. In some examples, the control circuit 112 may supplement the derived dual register list 460 with the new dual register list, and the control circuit 112 may write all bits into the bit vector of the derived single register list 461.

[0051] Back to Figure 2 At the issue / execute stage 210, the processor 110 and / or its execution units execute the dispatched micro-operations. Figure 2 A basic example pipeline 200 is illustrated, but in other examples, the processor 110 may perform the stages in various orders, in repeated iterations, and / or in parallel.

[0052] Figure 6 is a flow chart of an exemplary computer-implemented method 600 for managing split registers for renaming. Figure 6 The steps shown may be implemented by any suitable computer executable code and / or computing system (including Figure 1 In one example, Figure 6 Each of the steps shown in may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in more detail below.

[0053] like Figure 6 As illustrated, at step 602, one or more of the systems described herein may detect that the data unit size of the instruction is smaller than the double register. For example, the control circuit 112 detects that the data unit size of the instruction is smaller than the double register that the control circuit 112 has selected.

[0054] The systems described herein may perform step 602 in various ways. As described herein, the data unit size corresponds to the instruction width of the instruction, and the size of the double register may correspond to the wide instruction width (e.g., a physical register pair). In some examples, the control circuitry 112 may detect the data unit size from the instruction width of the instruction or other architectural signals (e.g., whether the instruction is a special instruction, operation type, etc.).

[0055] As further described herein, free registers are tracked in the free register list as a pair of register parts or as a single part free list. For example, register list 140 tracks free registers as a pair of physical registers. In some examples, derived double register list 460 tracks available double registers, and derived single register list 461 tracks available single registers. In some examples, control circuit 112 selects double registers from the free register list (e.g., from register list 140, derived double register list 460, and / or derived single register list 461). Once the selected register is given to the rename block, the corresponding bit of the selected register from derived double register list 460 or derived single register list 461 is marked as non-free.

[0056] At step 604, one or more of the systems described herein may allocate a first portion of the dual register to the instruction to enable a second portion of the dual register to be available for allocation to an additional instruction. For example, after selecting a free register for the instruction, control circuitry 112 splits the selected dual register as described herein, allocates a first portion of the dual register to the instruction to enable a second portion of the dual register to be available for allocation to an additional instruction.

[0057] The systems described herein may perform step 604 in various ways. In one example, the control circuit 112 splits the selected dual register (which has an even address value, although it may have an odd address value in other specific implementations) by marking the corresponding entry in the split register list 450 as split. The control circuit 112 assigns the second portion of the split register to another instruction in the cycle. If it cannot assign the second portion to another instruction, the control circuit 112 saves the second portion in a register in the rename block. The save register prevents the second portion from being returned to the free list. Before interrupting the dual register, the control circuit 112 may also decide to assign the previously saved second portion of the register (e.g., from a previous cycle) to an appropriate new instruction in the cycle (e.g., an instruction that satisfies the condition that it is not a wide instruction and has no other architectural signals to override). The control circuit 112 may continue to clear the save registers in the rename block.

[0058] As described above, if the selected register has been split, control circuit 112 may allocate the first portion to the instruction. In another iteration, control circuit 112 may then allocate the second portion to the second instruction as needed.

[0059] Returning to method 600, at step 606, one or more of the systems described herein may track the dual register as a split register. For example, control circuitry 112 tracks the dual register as a split register by updating a relevant list (e.g., one or more of register list 140, split register list 150, free list 240, split register list 250, split register list 450, etc.).

[0060] The systems described herein can perform step 606 in various ways. In one example, tracking registers includes marking the registers in a split register list (e.g., split register list 250 and / or split register list 450). The split register list tracks the split registers based on one of an even address value or an odd address value, such that the corresponding second portion has the other of an even address value or an odd address value. In some examples, control circuitry 112 further tracks the second portion of the registers in a free register portion list (e.g., register list 442B and / or derived register list 461).

[0061] In some examples, when the instruction is completed, the control circuit 112 marks the first portion as free (e.g., by updating register list 442A). In some examples, when the corresponding instruction is completed, the control circuit 112 marks the second portion as free (e.g., by updating register list 442B). In some examples, when the corresponding instruction is completed, the control circuit 112 marks the first portion and the second portion as free (e.g., by updating register lists 442A and 442B, which may further update / derive the derived dual register list 460 and / or the derived single register list 461 in some examples). When the first portion and the second portion are free, the control circuit 112 may also unmark the registers in the split register list (e.g., split register list 450) to indicate that the first portion and the second portion have reorganized the dual registers.

[0062] Figure 7A simplified top-level view of a split register renaming process 700 as described herein is illustrated. The purge block 772, rename block 774, and retire block 776 return physical register numbers at 778 for updating the free list 741 (which may correspond to the register list 440), which may include updating one or more of the following: free register list 742A (which may correspond to the register list 442A), free register list 742B (which may correspond to the register list 442B), split register list 750 (which may correspond to the split register list 450), dual list 760 (which may correspond to the derived dual register list 460), and single list 761 (which may correspond to the derived single register list 461). At 780, additional PRNs (e.g., 6, although other numbers of PRNs may be used in other examples) are read from the updated free list 741 for the rename block 782.

[0063] refer to Figure 7 , Figure 8 A simplified flow chart of a return process 800 is illustrated, such as that performed at 778. At 802, a free list (e.g., free list 741) receives a returned PRN, such as an address returned to be released. At 804, a given address of each PRN is evaluated as even or odd. If it is odd, which in some examples indicates that a single PRN is released, at 808, the corresponding bit in the free register list 742B is marked as free.

[0064] If at 804, the address is even, which in some examples indicates that a pair of registers are freed, then at 806, the corresponding bit in the free register list 742A is marked. At 810, a check is made to see if the bit in the split vector (e.g., split register list 750) is marked as a double register. If the bit is not marked as a double register, then at 814, the process completes the current iteration. If the bit is marked as a double register, then at 812, the corresponding bit in the free register list 742B is marked as free to indicate that both the even and odd parts of the double register are free.

[0065] In one example of returning a PRN, for example Figure 4In the example, regarding address 04 corresponding to index 2 shown in register list 442A, register list 442A is updated at index 2 to mark PRN 04 as free. Split register list 450 is checked to determine whether index 2 is split or double register. If split register list 450 indicates double register, register list 442B is also updated at index 2 to be free to indicate that the double register (e.g., two parts) is free. If the returned PRN is not a double register, register list 442B may not need to be updated. In another example, for an odd address such as 01, register list 442B is updated at index 0.

[0066] Fig. 9 Reference Figure 7 800. At 902, the dual table 760 is evaluated to determine whether the number of available dual registers is low (e.g., below a threshold number of dual registers for the current iteration), which indicates that the dual table 760 needs to be updated. If the number of available dual registers is not low, the process 900 completes the current iteration at 904.

[0067] If the number of dual registers is low at 902, process 900 proceeds to 906 to update dual table 760 and single table 761. Using an AND operation (see also Figure 5 ) Combine free register list 742A with free register list 742B to derive the next dual table. Using an XOR operation (see also Figure 5 ) Combine free register list 742A with free register list 742B to derive the next XOR list.

[0068] At 908, the next dual table is written to dual table 760 for updating, and the next XOR list is written to single table 761 for updating. In addition, at 910, the next dual table is unmarked in split register list 750 to indicate that the newly derived pair is not split. Similarly, at 912, the next dual table is unmarked in free register list 742A and free register list 742B.

[0069] The set of bits in the single list 761 is derived from the free register list 742A or the free register list 742B (as a single register) via an XOR operation, where the resulting bit is marked if the corresponding bit is marked in the free register list 742A (e.g., even address) or the free register list 742B (e.g., odd address), but not in both. Therefore, the next XOR list (and the single list 761) is agnostic, or does not know whether it contains an even or odd PRN address value. The bits read from the single list 761 are used to determine all bits of the PRN address value except the LSB, but can be further queried or referenced against the free register list 742B to determine whether the single PRN is odd (indicated by the corresponding marking bit in the free register list 742B) or even.

[0070] In an example of making a double register, refer to Figure 4 , PRN 04 and PRN 05 are free (in register list 442A and register list 442B, respectively). If the number of free pairs (e.g., dual free list counter) does not meet the threshold number of free pairs (e.g., less than or equal to the threshold number of free pairs, such as 24), a new pair is created from the available free portion. PRN 04 is free, so that the derived dual register list 460 is updated accordingly (e.g., index 2 can be marked as free). PRN 04 is marked as not free in register list 442A (e.g., at index 2), and PRN 05 is marked as not free in register list 442B (e.g., at index 2). Split register list 450 is marked (e.g., at index 2) as dual or non-split.

[0071] In one example of making a single register available, PRN 04 is free and PRN 05 is not free. If the dual free list counter does not meet the threshold number of free pairs (e.g., less than or equal to the threshold number of free pairs, which may be 24, for example), a new pair is required. An XOR operation on PRN 04 and PRN 05 may determine whether index 2 corresponds to a single register. The derived single register list 461 is updated accordingly at index 2 to be marked as free. In some examples, if the dual free list counter meets the threshold number of free pairs (e.g., the number of free pairs is greater than the threshold number of free pairs), a new pair is not required.

[0072] FIG. 10A to FIG. 10B Reference Figure 7 Simplified flow chart of the various selection processes. Fig. 10AA process 1000 for picking a single PRN is illustrated. At 1002, a single list 761 is provided and / or updated. At 1004, the single list 761 is checked to determine if the single list 761 has 6 available PRNs (although in other examples, other numbers of PRNs may be requested) and if the P0 level (e.g., PRN 0) is invalid (e.g., requires a floating point register). If neither condition is met, then at 1006, the current iteration of the process 1000 ends. Otherwise, at 1008, the 6 PRNs are read and written to the P0 level flip-flops at 1010. Using an appropriate scheme or method, the P0 level is invalidated upon renaming the read while the P1 level (e.g., PRN 1) flip-flops are written.

[0073] Continuing to 1012, the free register list 742B is checked (e.g., odd address PRN) to determine if the P0 stage address is marked. If it is not marked in the free register list 742B, then at 1014, the LSB is determined to be 0. Otherwise, at 1016, the LSB is determined to be 1. In addition, at 1020, the address or PRN is written to the P1 stage flip-flop on a rename read (e.g., a new micro-op is in the pipeline, and the rename read is asserted to indicate that the operation requires a PRN) and is given to the rename block.

[0074] In an example of selecting a single PRN, further reference is made to Figure 4 , after picking a single PRN (e.g., using find top N logic), the corresponding entry in the derived single register list 461 is marked as non-free. The address of the picked PRN is checked against register list 442B to determine if the address is an odd number. If the picked PRN is found in register list 442B, it is marked as non-free in register list 442B and is confirmed as an odd number. If the picked PRN is not found in register list 442B, it is marked as non-free in register list 442A and is confirmed as an even number.

[0075] For example, for PRN 04 (having index 2 in register list 442A), index 2 of the derived single register list 461 may be marked as non-free. If index 2 of register list 442B is marked as free, then PRN = {2, 1'b1} = PRN 05. Otherwise, PRN = {2, 1'b0} = PRN 04. For PRN 05, index 2 of register list 442B is marked as non-free. For PRN 04, index 2 of register list 442A is marked as non-free.

[0076] Fig. 10BA process 1001 for selecting a dual register is illustrated. At 1030, the dual table 760 is provided and / or updated. At 1032, the dual table 760 is checked to determine if the dual table 760 has 6 available PRNs (although in other examples, other numbers of PRNs may be requested) and if the P0 stage is invalid (e.g., a floating point register is required). If these conditions are not met, then at 1034, the current iteration of the process 1001 ends. Otherwise, proceed to 1036, where the 6 PRNs are read from the dual table 760 for renaming. At 1038, the address is written to the P0 stage flip-flop. Using one scheme or method, the P0 stage is invalidated on the renaming read while the P1 stage flip-flop is written.

[0077] Process 1001 continues to 1048 where the address or PRN is written to the P1 level flip-flop on rename read. Process 1001 ends the current iteration of the process by giving the PRN to the rename block at 1050.

[0078] In one example of selecting a dual PRN, further reference is made to Figure 4 , after picking a dual PRN (using, for example, find top N logic), such as PRN 04 (having index 2 in register list 442A), that PRN is marked as non-free in derived dual register list 460. The rename stage may then use that dual PRN and / or assign it to a micro-op.

[0079] FIG. 11A to FIG. 11B 1100 is a simplified flow chart of an example renaming process 1100 in conjunction with the systems and methods described herein. At 1102, two conditions are evaluated: (1) whether the current micro-op size is less than 512 (e.g., whether the current instruction is less than the wide instruction size), and (2) whether there is no SSE merge (e.g., a merge-type operation for streaming single instruction multiple data (SIMD) extensions (SSE), which in some examples corresponds to an architectural signal for instructions that require wide instruction size registers). If any condition evaluates to false, then at 1104, a double PRN is assigned. If the micro-op is determined to be 512 or SSE merge is set, it will be assigned a double PRN.

[0080] If both conditions are true (indicating that a wide instruction sized register is not required), then the last stored odd single PRN may be evaluated as valid at 1104. If the last stored odd single PRN is valid (indicating that a single PRN is free), then at 1106 an odd single PRN is allocated, and at 1108 the stored odd single PRN is marked as invalid (e.g., not free or not free).

[0081] If at 1104 the last stored odd single PRN is invalid, then at 1110 it may be determined whether there is a valid second portion of the dual PRN. If there is a valid second portion of the dual PRN, at 1112 the second portion is allocated to the current micro-op.

[0082] If there is no valid second portion at 1110, then at 1114, the dual PRN is split to assign the first portion to the current micro-operation. At 1118, it can be determined whether the second portion of the dual PRN (split at 1114) will be used by another micro-operation in the current cycle. If the second portion is not used by another micro-operation in this cycle, then at 1120, the second portion is stored in the odd single PRN for use in the micro-operation of the next cycle (e.g., the iteration of the next cycle of 1104). If the second portion will be used by another micro-operation in this cycle, then at 1122, the second portion is assigned to another micro-operation of the cycle instead of storing the second portion, and avoiding the splitting of a new dual PRN in the current iteration of process 1100.

[0083] Additionally, after the dual PRN is split at 1114, an update to the split vector (e.g., split register list 150, split register list 450, split register list 750, etc.) is sent at 1116 to indicate that the dual PRN has been split. Process 1100 continues Fig. 11B The illustrated process 1101. At 1124, an architectural override is checked such that the micro-op may already have a PRN and a PRN from a free list may not be needed (e.g., a PRN allocated to the micro-op from a load / store (LS) / execute (EX) PRN first-in-first-out queue (FIFO) in an earlier pipeline stage). If there is no architectural override, then at 1126, the PRN allocated by the renaming process is used. Otherwise, at 1128, the PRN allocated by the renaming process is returned to the free list and the PRN allocated by the LS or EX FIFO is used.

[0084] In an example of allocating PRNs during renaming, further reference is made to Figure 4, PRN 04 can be a dual PRN. For the current micro-op read from the dispatch, if the micro-op size is less than 512 and there is no SSE merge, the availability of the stored split PRN is checked during the renaming. If there is an available stored split PRN and it has not been allocated, the stored split PRN is assigned to the current micro-op. If the stored split PRN is available, but is allocated to another micro-op, the availability of the corresponding second part (which may have been split in this cycle) is checked. If the second part is available, it is assigned to the current micro-op. Otherwise, PRN 04 is split and its first part is assigned to the current micro-op. After splitting PRN 04, PRN 05 can be assigned to another micro-op in this cycle, or stored for use in the next cycle. If there is an SSE merge, the current micro-op can be an SSE merge operation, or a 512-size instruction, so that a dual PRN can be assigned. Alternatively, if PRN 04 is a single PRN, and the current micro-op is not an SSE merge operation (or a 512-bit instruction), then PRN 04 may be assigned to the current micro-op.

[0085] The systems and methods described herein provide flexibility in allocating free registers in the renaming stage of the processor instruction pipeline. In one example, the processor architecture can support 512-bit instructions that require 512-bit registers. The processor can have 384 physical registers, each of which is 256 bits, organized into 192 pairs of physical registers so that each pair of physical registers meets the size of 512 bits. To simplify the management of registers, the processor can track 512-bit registers as 256-bit physical registers paired with 256-bit shadow (physical) registers for renaming, and track 384 single physical registers to maintain a complete list of returned physical register numbers.

[0086] The processor may further support smaller instructions, such as 256-bit instructions, 128-bit instructions, and the like. Although 512-bit registers may be used for smaller instructions, shadow registers may not be used for smaller instructions. Making shadow registers available can improve the performance of the processor's instructions per cycle. Shadow registers can be used by modifying the renaming scheme to map each physical register in a pair to a high or low logical register number. For example, a 512 micro-operation that requires a 512-bit physical register can be converted into two 256 micro-operations that require two 256-bit physical registers. However, this mapping may greatly increase the complexity and overhead of the renaming stage. This modification may require effectively doubling the queue size. For example, two micro-operations may need to track the high logical register number and the low logical register number mapped to two physical registers. Therefore, it may be necessary to save two or more instructions instead of one instruction in the retirement queue, scheduler queue, and other queues, which effectively reduces processor performance.

[0087] The systems and methods described herein can advantageously reduce the overhead of managing shadow registers. The systems and methods described herein can manage physical register pairs (e.g., using the derived dual register list 460 to manage register pairs, and using the derived single register list 461 to manage 192 single registers), rather than managing each physical register individually. For example, a processor can manage 192 register pairs. Because registers can be split as needed, normal renaming queues may not need to be doubled. Split registers can be tracked based on their original register pairs, where a bit vector is used to indicate whether the register is separated, and another bit vector is used to indicate whether the split portion is idle. In some examples, the control circuit 112 can also allocate idle single registers for micro-operations. Therefore, the systems and methods described herein can allow shadow registers and / or all registers to be used effectively. The scheme can be extended to allow only appropriate physical registers to be assigned to appropriate instruction widths without the need for dual queues, dual naming, and effectively use all registers and support wide instructions in the processor.

[0088] As described above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions (such as those contained in the modules described herein). In its most basic configuration, these computing devices can each include at least one storage device and at least one physical processor.

[0089] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device can store, load, and / or maintain one or more modules described herein. Examples of storage devices include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, variations or combinations of one or more of the above components, or any other suitable memory.

[0090] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor can access and / or modify one or more modules stored in the above-mentioned memory device. Examples of physical processors include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system on a chip (SOC), a portion of one or more of the above components, a variation or combination of one or more of the above components, or any other suitable physical processor.

[0091] Although illustrated as separate elements, the modules described and / or illustrated herein may represent parts of a single module or application. In addition, in some specific implementations, one or more of these modules may represent one or more software applications or programs that, when executed by a computing device, can cause the computing device to perform one or more tasks. For example, one or more of the modules described and / or illustrated herein may represent modules stored and configured to run on one or more computing devices or systems in the computing device described and / or illustrated herein. One or more of these modules may also represent all or part of one or more special-purpose computers configured to perform one or more tasks.

[0092] In addition, one or more of the modules described herein can convert data, physical devices, and / or representations of physical devices from one form to another. For example, one or more of the units described herein can receive instruction data to be converted, convert the instruction data, output the conversion result to determine whether to split the register, use the conversion result to split the register, and store the conversion result to manage the split register. Additionally or alternatively, one or more of the modules described herein can convert a processor, volatile memory, non-volatile memory, and / or any other part of a physical computing device from one form to another by executing on a computing device, storing data on a computing device, and / or otherwise interacting with a computing device.

[0093] In some implementations, the term "computer-readable medium" generally refers to any form of device, carrier, or medium that can store or carry computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media, such as carrier waves, and non-transitory media, such as magnetic storage media (e.g., hard drives, tape drives, and floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), and Blu-ray disks), electronic storage media (e.g., solid-state drives and flash memory media), and other distribution systems.

[0094] The process parameters and order of steps described and / or illustrated herein are given as examples only and may be changed as desired. For example, although the steps illustrated and / or described herein may be illustrated or discussed in a particular order, the steps do not necessarily need to be performed in the order shown or discussed. The various exemplary methods described and / or illustrated herein may also omit one or more of the steps described or illustrated herein, or include additional steps in addition to those disclosed.

[0095] The foregoing description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0096] Unless otherwise indicated, the terms "connected to" and "coupled to" (and their derivatives) used in the specification and claims should be interpreted as allowing both direct and indirect (i.e., via other elements or components) connections. In addition, the terms "a" or "an" used in the specification and claims should be understood to mean "at least one of..." Finally, for ease of use, the terms "including" and "having" (and their derivatives) used in the specification and claims are interchangeable with the word "comprising" and have the same meaning as the word "including".

Claims

1. A method, comprising: The data unit size of the detection instruction is smaller than the double register; allocating a first portion of the dual register to the instruction to make a second portion of the dual register available for allocation to an additional instruction; as well as The dual register is tracked as a split register.

2. The method according to claim 1, wherein: Detecting that the data unit size of the instruction is smaller than the double register further includes detecting the data unit size based on at least one of an instruction width of the instruction and an architectural signal.

3. The method according to claim 1, wherein: Tracking the double register includes marking the double register in a split register list.

4. The method according to claim 3, wherein: The split register list tracks split registers based on one of an even address value or an odd address value such that the corresponding second portion has the other of the even address value or the odd address value.

5. The method of claim 3, further comprising unmarking the double register in the split register list when the first portion and the second portion are idle.

6. The method of claim 1, further comprising selecting the first portion or the second portion of the double register from a free register list.

7. The method of claim 1, further comprising marking the first portion as free when the instruction is completed.

8. The method of claim 7, further comprising marking the second portion as free when the instruction is completed.

9. The method of claim 1, further comprising marking the first portion and the second portion as free when the instruction is completed.

10. The method according to claim 1, wherein: The data unit size corresponds to an instruction width of the instruction.

11. The method according to claim 1, wherein: The size of the double register corresponds to the wide instruction width.

12. The method according to claim 11, wherein: The size of the register portion corresponds to half the width of the wide instruction.

13. A method comprising: Detecting the data unit size from an architectural signal of the instruction; Detecting that the data unit size of the instruction is smaller than a register size; selecting a free register having the register size for the instruction from a free register list; allocating a first portion of the selected register to the instruction to make a second portion of the selected register available for allocation to an additional instruction; as well as Tracks the selected register as a split register in the split register list.

14. The method according to claim 13, wherein: The split register list tracks split registers based on one of an even address value or an odd address value such that the corresponding second portion has the other of the even address value or the odd address value.

15. The method of claim 13, further comprising unmarking selected registers in the split register list when the first portion and the second portion are idle.

16. The method according to claim 13, wherein: Free registers, each being part of a pair of registers, are tracked in the free register list.

17. The method of claim 13, further comprising marking the first portion as free when the instruction is completed.

18. A system, comprising: Physical storage; and At least one physical processor, the at least one physical processor comprising: Multiple registers; Control circuitry for managing register allocation of instructions, the control circuitry being configured to: For an instruction whose data unit size is smaller than a register, selecting a free register from the plurality of registers from a free register list; allocating a first portion of the selected registers to the instruction to make a second portion of the selected registers available for allocation to an additional instruction; and Tracks the selected register as a split register in the split register list.

19. The system of claim 18, wherein: Free registers, each being part of a pair of registers, are tracked in the free register list.

20. The system of claim 18, wherein: The first portion and the second portion of the selected register are tracked in a free register portion list.

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