Transmitter and receiver

Abstract

The subject matter of the present disclosure provides a transmitter for a master clock of an audio system. The transmitter comprises: an input configured to receive a message to be transmitted to a receiver of an audio device of an audio system and clock frequency information for synchronizing a clock signal of the audio device; a data stream generator configured to determine a data stream based on the message; a pulse shaper configured to generate an encoded clock signal in the form of a rectangular wave having a start edge timing based on a clock frequency and a stop edge timing earlier or later than half a cycle of the encoded clock signal according to a bit value of the data stream; and an output configured to transmit the encoded clock signal to a receiver.

Description

Technical Field

[0001] The subject matter of the present disclosure relates to a transmitter for a master clock of an audio system, and a receiver for an audio device of an audio system. More specifically, the transmitter and the receiver are capable of transmitting and receiving a clock signal for synchronizing audio devices within the audio system. Background Art

[0002] Audio devices within an audio system need to be synchronized. Synchronization can be achieved using a clock signal. For example, in one approach, a master clock can be used to synchronize more than two audio devices within an audio system.

[0003] An audio device receiving a clock signal can monitor its pulses to replicate the clock signal. However, for the audio device, more information is needed to understand the timing of the pulses. This is because cross-channel delays can mean that arbitrarily aligning a rising edge with the nearest clock pulse does not necessarily match the correct pulse of the clock signal between the devices being synchronized.

[0004] Prior art approaches have been attempted, but typically audio devices are tied to using a specific data transmission method, such as the Audio Engineering Society / European Broadcasting Union interfaces (AES / EBU) or the Sony / Philips Digital Interface Format (SPDIF).

[0005] The present disclosure aims to alleviate such problems and improve upon the prior art. Summary of the invention

[0006] According to one aspect of the present disclosure, a transmitter for a master clock of an audio system is provided. The transmitter includes: an input configured to receive a message to be sent to a receiver of an audio device of the audio system and clock frequency information for synchronizing a clock signal of the audio device; a data stream generator configured to determine a data stream based on the message; a pulse shaper configured to generate an encoded clock signal in the form of a rectangular wave having a start edge timing based on the clock frequency and an end edge timing that is earlier or later than half a cycle of the encoded clock signal according to the bit value of the data stream; and an output configured to transmit the encoded clock signal to the receiver. In this way, the message can be encoded into the encoded clock signal, so that both the clock timing and the message can be transmitted simultaneously without the need for a specific data transmission protocol.

[0007] In an embodiment, the transmitter may further include a pseudo-random number generator configured to generate a pseudo-random number key, wherein the data stream generator is configured to generate the data stream further based on the pseudo-random number key.

[0008] In one embodiment, the data stream may include a plurality of bits in the form of a frame, wherein the frame includes a synchronization portion, followed by a trigger portion, followed by a message portion, the message portion corresponding to the received message and being m bits long, wherein the synchronization portion is n plus s bits long, wherein n is the length of a pseudo-random number generator and s is the number of bits used to synchronize the receiver, and wherein the trigger portion is t bits long.

[0009] In one embodiment, s may be greater than m.

[0010] In one embodiment, the data stream generator can be configured to generate a data stream based on a payload of zero and a pseudo-random number key during a synchronization portion, generate a data stream based on a payload of one or more ones and a pseudo-random number key during a trigger portion, and generate a data stream based on a payload and a pseudo-random number key corresponding to a message during a message portion.

[0011] In one embodiment, the pseudo-random number generator may be a linear feedback shift register.

[0012] In one embodiment, the transmitter may further include a pulse narrower and a pulse stretcher, the pulse narrower being configured to generate a first rectangular wave having a pulse width less than half a period of the encoding clock signal, and the pulse stretcher being configured to generate a second rectangular wave having a pulse width greater than half a period of the encoding clock signal, wherein the pulse shaper may be configured to select the first rectangular wave or the second rectangular wave according to the bit value of the data stream.

[0013] In an embodiment, the pulse stretcher and the pulse narrower may be configured to generate the first rectangular wave and the second rectangular wave by combining pulses from waves having a frequency that is a multiple of the encoding clock signal.

[0014] In an embodiment, the message may include a sample count or a timestamp.

[0015] In one embodiment, the starting edge may be a rising edge, and the ending edge may be a falling edge.

[0016] According to one aspect of the present disclosure, a master clock device is provided, comprising the above transmitter.

[0017] According to one aspect of the present disclosure, a receiver for an audio device of an audio system is provided, the receiver comprising: an input configured to receive an encoded clock signal from a transmitter of a master clock for the audio system; a clock signal generator configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal; and a data stream recoverer configured to obtain a bit value of a data stream encoded in the encoded clock signal based on whether a termination edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal, and obtain a message based on the bit value of the data stream.

[0018] In an embodiment, the receiver may further include a pseudo-random number generator configured to generate a pseudo-random number key, wherein the data stream restorer may further be configured to obtain a message based on the bit value of the data stream and the pseudo-random number key.

[0019] In one embodiment, the data stream may include a plurality of bits in the form of frames, wherein the frame includes a synchronization portion, followed by a trigger portion, followed by a message portion, the message portion corresponding to the received message and being m bits long, wherein the synchronization portion is n plus s bits long, wherein n is the length of a pseudo-random number generator and s is the number of bits used to synchronize the receiver, and wherein the trigger portion is t bits long.

[0020] In one embodiment, s may be greater than m.

[0021] In an embodiment, the receiver may further include a match counter configured to reset the pseudo-random number generator in response to detecting the trigger portion, and may be configured to output the message in response to counting m bits after the trigger portion.

[0022] In one embodiment, the pseudo-random number generator may be a linear feedback shift register.

[0023] In one embodiment, the receiver may further include a pulse width detector configured to determine whether a termination edge of the encoding clock signal is earlier or later than half a cycle of the encoding clock signal by sampling the encoding clock signal at a frequency that is a multiple of the frequency of the wave used to generate the encoding clock signal pulses.

[0024] In an embodiment, the message may also include a sample count or a timestamp.

[0025] In an embodiment, the clock signal generator may be configured to generate a square wave clock signal by dividing the frequency of the encoded clock signal by two.

[0026] In one embodiment, the starting edge may be a rising edge, and the ending edge may be a falling edge.

[0027] According to an aspect of the present disclosure, there is provided an audio device including the above-mentioned receiver.

[0028] According to one aspect of the present disclosure, a system is provided, comprising the above transmitter and the above receiver.

[0029] According to one aspect of the present disclosure, there is provided an audio system, comprising the aforementioned master clock device and the aforementioned audio device. According to one aspect of the present disclosure, there is provided a method for encoding an encoded clock signal, the method comprising: receiving a message to be sent to a receiver of an audio device of the audio system and clock frequency information for synchronizing a clock signal of the audio device; determining a data stream based on the message; generating an encoded clock signal in the form of a rectangular wave, the rectangular wave having a start edge timing based on the clock frequency and an end edge timing that is earlier or later than half a cycle of the encoded clock signal according to a bit value of the data stream; and transmitting the encoded clock signal to a receiver.

[0030] In one embodiment, the starting edge may be a rising edge, and the ending edge may be a falling edge.

[0031] According to one aspect of the present disclosure, a method for obtaining a message and a clock signal from an encoded clock signal is provided, the method comprising: receiving an encoded clock signal from a transmitter of a master clock for an audio system; generating a square wave clock signal having a frequency based on the frequency of the encoded clock signal; obtaining a bit value of a data stream encoded in the encoded clock signal based on whether a termination edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal; and obtaining a message based on the bit value of the data stream.

[0032] In one embodiment, the terminating edge may be a falling edge.

[0033] According to another aspect of the present disclosure, a transient or non-transitory computer-readable medium is provided, on which instructions are stored. When the instructions are executed by a processor, the processor is caused to perform any of the above methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The presently disclosed subject matter may be best described with reference to the accompanying drawings, in which:

[0035] Figure 1 shows a block diagram of a system (audio system) according to one or more embodiments;

[0036] Figure 2 According to one or more embodiments, Figure 1 A block diagram of a transmitter of a clock source is shown;

[0037] Figure 3 According to one embodiment, Figure 2 A block diagram of a data stream generator for a transmitter;

[0038] Figure 4 Shown by Figure 2 The encoded clock signal generated by the transmitter and the receiver ( Figure 6 ) generated a recovered clock signal;

[0039] Figure 5 According to one or more embodiments, Figure 2 a block diagram of another transmitter other than the one shown;

[0040] Figure 6 Shown from Figure 1 A block diagram of a receiver of the audio device shown;

[0041] Figure 7 Shown from Figure 6 A block diagram of a data stream restorer for a receiver;

[0042] Figure 8 A flowchart illustrating a method of encoding an encoding clock signal according to one or more embodiments; and

[0043] Fig. 9 A flow chart of a method of deriving a message and a clock signal from an encoded clock signal is shown. DETAILED DESCRIPTION

[0044] It should be understood that although various features are described herein with reference to one or more embodiments, features from different embodiments may be included in other embodiments without constituting an addition of subject matter beyond that described herein.

[0045] refer to Figure 1 , an audio system 10 is provided. The audio system 10 includes a clock source device 12 (also referred to as a master clock or clock box) and one or more audio devices 14. The one or more audio devices can be devices suitable for producing audio. Examples of audio devices include a transmitter (e.g., a CD reader or MP3 player), a digital-to-analog converter (DAC), an upsampler, a headphone amplifier, and a user interface. Sound producing devices (including one or more speakers, headphones, etc.) can be connected to the one or more audio devices to produce the sound provided on the transmitter.

[0046] The clock box 12 can be connected to each audio device using a cable.

[0047] The clock box 12 includes Figure 2 The transmitter 18 is shown.

[0048] refer to Figure 2, the transmitter 18 includes an input 19 , a clock signal generator 20 , a frame counter 22 , a data stream generator 24 , a pulse widener 26 , a pulse narrower 28 , a pulse shaper 30 , and an output 32 .

[0049] Input 19 is configured to receive a clock signal. The clock signal is a square wave. The input square wave has a frequency f (wherein f is used interchangeably with F herein to indicate frequency)) which is intended to be used to synchronize the audio device 14 ( Figure 1 ). In this way, the input is configured to receive clock frequency information of a clock signal used to synchronize the audio device 14, since information related to the clock frequency is derived from the square wave itself.

[0050] The clock signal generator 20 obtains the input square wave from the input 19. The clock signal generator 20 is configured to generate a modified square wave based on the input square wave. The clock signal generator 20 can be provided in the form of a phase locked loop (PLL). The phase locked loop generates the modified square wave by doubling the frequency of the input square wave. In this way, the modified square wave has a frequency of 2f (or 2F).

[0051] The modified square wave is then used as input to a frame counter 22 (or counter), a data stream generator 24 , a pulse stretcher 26 , and a pulse narrower 28 .

[0052] The frame counter 22 knows the number of bits in a frame. The frame counter 22 can obtain the number of bits in a frame from a memory (not shown) of a clock source. The frame counter 22 is configured to count the number of pulses in the modified square wave within a frame and generate a restart condition when the data stream generator 24 needs to restart generating bit values ​​for another frame.

[0053] A frame is the number of bits required to send information to an audio device. A frame consists of a sync portion, followed by a trigger portion, followed by a message portion, which corresponds to the message being received. The message portion can be m bits long. The sync portion is n plus s bits long, where n is the length of the pseudo-random number generator (see below), and s is the number of bits used to synchronize the receiver. The trigger portion is t bits long.

[0054] refer to Figure 3 , a data stream generator 24 is connected to the input 19. The data stream generator 24 is configured to generate a data stream based at least in part on the message. In other words, the data stream generator 24 is configured to generate a data stream describing the message in binary form.

[0055] To achieve this, the data stream generator 24 includes a payload generator 31, a frame sync detector 33, a shift register 34, a switch 36, a pseudo-random number generator 38, and a data stream combiner 40. It should be noted that each of the payload generator 31, the frame sync detector 32, the shift register 34, the switch 36, and the pseudo-random number generator 38 has a modified square wave 2F as an input, and for the sake of brevity and to aid clarity of the drawings, this is not included. Figure 3 middle.

[0056] Input 19 also receives a message to be sent to the corresponding receiver of the audio device 14. The message may be in the form of a sample count or a timestamp, or even auxiliary data. Input 19 may be similar to Figure 2 The same input as shown, or different inputs. The sample count may indicate the sequential order of the samples of the data packet containing the audio samples. The timestamp may be the time according to the clock box 12. In practice, it is likely that one or the other of the timestamp and the sample count will be sent. The audio device will use the sample count and the timestamp so that the audio device knows which frame is being received. The auxiliary data may be any other data that can be transmitted as a message to the audio device. For example, the name of the clock box, its part number or serial number, or technical specifications may be transmitted. The auxiliary data may be transmitted alternately with the sample count or the timestamp.

[0057] The payload generator 31 is configured to receive a message and generate a payload in response. The payload may include a message in binary form. As described elsewhere in this disclosure, the payload may also be used to describe all binary values ​​within a frame. In this way, the payload generator 31 may be referred to as a payload message part generator.

[0058] The shift register 34 is configured to convert the effective load into serial data. In this way, the effective load can be a bit stream. The shift register 34 also receives a signal from the frame synchronization detector 33 about when to output the bit stream. This signal can be referred to as a load signal Load. Once the frame synchronization detector 33 counts the number of bits of the frame symbolizing the end of the message, the Load signal will be sent.

[0059] The frame synchronization detector 33 is configured to receive the frame synchronization information from the frame counter 22 ( Figure 2 ) receives a frame count signal Frame Count. The frame count signal indicates to the frame sync detector when the frame counter 22 has finished counting all the bits of a frame, so the frame count signal acts as a reset for the frame sync detector 33 to start counting again.

[0060] The frame synchronization detector 33 is also configured to output a synchronization signal Sync to a switch 36. The switch has two inputs. A first input 42 is the output of the shift register 34, i.e., a bit stream describing a message. A second input 44 is also a bit stream, which may also be referred to as a payload. The payload generator 31 may generate the additional bit stream or the additional bit stream may be generated by different sources. The additional payload may include two sub-payloads, i.e., a synchronization payload and a trigger payload.

[0061] To avoid confusion, the global input to the switch 36 can be considered as a payload. The payload can include multiple parts, each corresponding to a part of the frame. The payload can include a message part (output from the shift register 34) and is an input to the first input 42. There can be an m-bit binary value (0 or 1) in the message part. The number of bits m is selected to be sufficient to define the message using binary notation. The payload can also include a synchronization part input to the second input 44. The synchronization part can include a binary value of n plus s bits. Both n and s binary values ​​can be zero. The number of bits n can be the length of the pseudo-random key generated by the pseudo-random number generator 38 (see below). The number of bits s can be greater than the number of bits m. The reason for this can be most easily understood by referring to the receiver (see below). However, in general, in theory, the message payload may include a large number of areas consisting only of zeros, without one. If the message part is larger than the synchronization part, an erroneous reset of the pseudo-random number generator may occur in this case. The payload can also include a trigger part with t bits. The trigger part can be an input to the second input 44. The bit number t may be a single bit in length and may have a value of 1.

[0062] When the frame synchronization detector 33 receives the frame count signal Frame Count and resets, it is configured to send a synchronization signal Sync to the switch 36. The synchronization signal Sync is configured to switch the switch to the second input 44. In this way, when the synchronization signal Sync is valid, the synchronization part and the trigger part of the effective load are output to the data stream combiner 40. When the frame synchronization detector 33 has counted to n+s+t bits, the synchronization signal Sync ends. Without the synchronization signal Sync, the switch defaults to the first input 42. When the first input 42 is selected, the shift register 34 outputs the message part of the effective load to the data stream combiner 40.

[0063] In some embodiments, n may be 24 bits long, m may be 60 bits long, s may be 61 bits long, and t may be 1 bit long. Thus, a frame may be 146 bits long.

[0064] The pseudo-random number generator 38 is configured to generate a pseudo-random number key (or pseudo-random key). A suitable pseudo-random number generator 38 will continuously advance through all n-digit numbers. The numbers are unique because they will only appear again after all other possible numbers have been exhausted.

[0065] To achieve this, the pseudo-random number generator 38 may include a linear feedback shift-register (LFSR). The LFSR is capable of achieving a unique set of numbers other than zero.

[0066] If the series of n-bit numbers is viewed as a bit stream (without word boundaries), the LFSR will produce a unique number at any point in the bit stream. There may be other types of pseudo-random number generators 38 that have this property. Therefore, as long as the pseudo-random number generator 38 can operate in this manner, it is not necessary to provide for the use of a LFSR. For the purposes of the embodiments described herein, the pseudo-random number generator 38 may be a LFSR for illustrative purposes.

[0067] The LFSR may be 24 bits long. Thus, the pseudo-random key will consist of 24 bits of 1s and 0s presented in a random sequence, although their order is determined by the construction of the LFSR.

[0068] Although not included in this article for the sake of brevity Figure 3 , but the synchronization signal Sync can also be used for the LFSR. In this way, once the trigger portion is sent, the pseudo-random number generator will restart generating pseudo-random keys. Therefore, the pseudo-random number generator 38 is configured to generate a 24-bit pseudo-random key once during the first n bits, and then generate two 24-bit keys during the s period before resetting during the third key period. The end of the third key coincides with the trigger bit t. Then, when the load signal Load is valid and the synchronization signal Sync is invalid, the pseudo-random number generator 38 generates two-bit and multi-bit pseudo-random keys.

[0069] The data stream combiner 40 is configured to combine the payload with the pseudo-random key. For example, the data stream combiner 40 can be an exclusive OR gate XOR. The output of the data stream combiner 40 can be a data stream. In other words, the data stream generator is configured to generate a data stream based on a pseudo-random key. It can be understood that during the synchronization part, when the payload is zero, the data stream will be a pseudo-random key. During the trigger part, the data stream will be the opposite value of the pseudo-random key. During the message part, the message will appear to be encoded and is unlikely to match the pseudo-random key of all 60 bits. It should also be noted that the message part is shorter than the synchronization part, thereby avoiding false synchronization. If the message happens to be a large number of consecutive zeros, or ends with a large number of consecutive zeros, synchronization can still be detected at the trigger bit.

[0070] In this way, the data stream generator 24 is configured to generate a data stream based on a payload of zero and a pseudo-random number key during the synchronization part, generate a data stream based on a payload of one or more ones and a pseudo-random number key during the trigger part, and generate a data stream based on a payload and a pseudo-random number key corresponding to the message during the message part.

[0071] Reference again Figure 2 ,The switch uses the data stream as the switching signal.

[0072] The pulse stretcher 26 and pulse narrower 28 take a modified clock signal or a modified square wave as input. Although not shown in the figure for the sake of brevity, Figure 2 , but another input to the pulse stretcher 26 and the pulse narrower 28 is a fast clock. The frequency of the fast clock can be a multiple of the modified clock. For example, a square wave to a synchronous audio device can have a frequency of 48kHz. The square wave frequency can correspond to the sampling rate of the (one or more) audio signals. The modified clock signal can have a frequency of 96kHz. The high clock frequency can have a frequency that is a multiple (e.g., 32 times) of the frequency of the modified clock signal. The high clock frequency can be around 3.1MHz (to two significant figures).

[0073] refer to Figure 2 and Figure 4 , the pulse stretcher 26 can be configured to construct a modified clock signal using pulses from a high clock frequency. For example, if the modified clock signal is directly twice the clock signal frequency f, its frequency can be 2f or 2F. Therefore, a narrow pulse can be constructed using 15 / 32 pulses from a fast clock. A wide pulse can be constructed using 17 / 32 pulses from a fast clock. In this way, the pulse stretcher 26 and the pulse narrower 28 are configured to generate a first rectangular wave and a second rectangular wave by combining pulses from a wave with a frequency multiple of the encoded clock signal. Therefore, the falling edge of the narrow pulse is earlier than 1 / 2 cycle of the modified clock signal, while the falling edge of the wide pulse is later than 1 / 2 cycle of the modified clock signal.

[0074] The output from the pulse stretcher 26 may be a first rectangular wave having a pulse width less than half a period of the encoding clock signal. The output from the pulse narrower 28 may be a second rectangular wave having a pulse width greater than half a period of the encoding clock signal. The pulse shaper 30 is configured to generate an encoding clock signal in the form of a rectangular wave having a starting edge whose timing is based on the clock frequency information and a termination edge that is earlier or later than half a period of the encoding clock signal according to the bit value of the data stream. In some embodiments, the term "starting edge" and the term "termination edge" may be more specifically defined as "rising edge" and "falling edge", respectively. More specifically, the pulse shaper 30 may be configured to select the first rectangular wave or the second rectangular wave according to the bit value of the data stream. To achieve this, the pulse shaper 30 may be in the form of a switch. For example, when the bit value is one, the pulse shaper 30 may select the output of the pulse stretcher 26, i.e., the first rectangular wave. When the bit value is zero, the pulse shaper 30 may select the output of the pulse narrower, i.e., the second rectangular wave. Thus, when the bit value from the data stream is 1, the modified clock signal will have a 1 value or a high value at 1 / 2 cycle of the encoded clock signal. When the bit value from the data stream is zero, the modified clock signal will have a zero value or a low value at 1 / 2 cycle of the encoded clock signal.

[0075] The output of the pulse shaper 30 is the encoded clock signal. The output 32 is configured to transmit the encoded clock signal to a receiver.

[0076] refer to Figure 5 , a further embodiment of the transmitter 18' is provided. The reference numerals used in this embodiment are the same as those from Figure 2 The same reference numerals are used for the embodiments of the present invention, but with an apostrophe (') appended to the reference numerals. The following description explains Figure 5 Example and Figure 2 All other features are considered to be the same.

[0077] Input 19' is configured to receive a fast clock. The fast clock (nf or nF) can have a frequency that is a multiple of the clock signal used to synchronize the audio device. For example, a square wave to the synchronized audio device can have a frequency of 48kHz. The modified clock signal can have a frequency of 96kHz. The high clock frequency can have a frequency that is a multiple (e.g., 32 times) of the frequency of the modified clock signal. The high clock frequency can be around 3.1MHz (to two significant digits). In addition to the fast clock, the transmitter 18' can receive a clock frequency for the clock signal used to synchronize the audio device. The clock frequency can be provided in the form of clock frequency information.

[0078] Figure 5In the example, "n" can be a power of 2 (e.g., 2, 4, 8, 16, 32, etc.). Although "n" can be a variable, it can actually have a fixed value. In other words, the clock frequency information can be stored in a database and can be immutable, that is, it can be predetermined and can be fixed. Optionally, the clock frequency information can be embodied in the circuit of the hardware.

[0079] The clock signal generator 20' is configured to generate a modified square wave (2F) based on a fast clock (nF). The clock signal generator 20' may include one or more flip flops. Thus, the modified clock signal has a frequency of 2f (or 2F). The modified clock signal is input to a frame counter 22', a data stream generator 24', a pulse stretcher 26', and a pulse narrower 28', each of which is in the same frequency as the clock signal. Figure 2 The embodiments work the same way.

[0080] refer to Figure 6 , each audio device 14 ( Figure 1 ) includes a receiver 50.

[0081] The receiver 50 includes an input 52, a clock signal generator 54, a pulse width detector 56, a data stream restorer 58 and an output 64. The data stream restorer 58 includes a frame restorer 62 and a data stream restorer 60.

[0082] The input 52 may be configured to receive the encoding clock signal 18 from the transmitter.

[0083] The clock signal generator 54 can take the form of a counter. The counter can be a frequency division counter. The frequency division counter can divide the encoded clock signal having a frequency of 2f by two to generate a clock signal having a frequency of f. Therefore, the clock signal can be a square wave, rather than a rectangular wave of the encoded clock signal. The square wave can then be output from the output 64 to the processor of the audio device 14 to synchronize with other audio devices 14. In other words, the clock signal generator 54 can be configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal.

[0084] The pulse width detector 56 may be a wide and narrow detector. The pulse width detector 56 may be configured to determine whether the falling edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal by sampling the encoded clock signal at a frequency that is a multiple of the frequency of the wave used to generate the encoded clock signal pulse. For example, the transmitter has used a fast clock to generate the encoded clock signal pulse. The frequency of the timing for monitoring the falling edge may be a multiple of the fast clock. The frequency of the timing for monitoring the falling edge may be twice the frequency of the fast clock, for example, 6.1MHz (to two significant digits). Thus, if the value of the encoded clock signal is high or 1 at 32 / 64 pulses, a wide pulse is detected. If the value of the encoded clock signal is low or zero at 32 / 64 pulses, a narrow pulse is detected. The output from the pulse width detector 56 may be a bit stream of 1 and 0 corresponding to the wide pulse and the narrow pulse, respectively. Alternatively, in other embodiments, the same solution may be used to monitor the timing of the falling edge. For example, if the wide pulse and the narrow pulse are 15 and 17 fast clock cycles wide, respectively, then the test may be performed at 16 cycles.

[0085] The data stream restorer 58 is configured to receive the bit stream from the pulse width detector 56. Figure 7 The operation of the data stream restorer 58 can be best understood, but in summary, the data stream restorer 58 is configured to obtain the bit value of the data stream encoded in the encoding clock signal based on whether the falling edge of the encoding clock signal is earlier or later than half a period of the encoding clock signal. In addition, the data stream restorer 58 can be configured to obtain a message based on the bit value of the data stream.

[0086] refer to Figure 7 , the data stream restorer 58 includes a match counter 70, a pseudo-random number generator 72, a combiner 74, a shift register 76 and a payload latch 78. In broad terms, the match counter 70 and Figure 6 The frame recovery device 62 corresponds to the frame recovery device 62, and the pseudo-random number generator 72, the combiner 74, the shift register 76 and the effective load latch 78 are Figure 6 Corresponding to the data stream recovery device 70 in.

[0087] The match counter 70 (or counter) is configured to count the number of bits in the bit stream. The match counter 70 is configured to count the number of bits in the frame, i.e., 146 bits. The match counter 70 has two inputs, i.e., the bit stream from the pulse width detector and the output from the pseudo-random number generator 72. The match counter 70 has two outputs, one is the seed reset signal Reseed, and the other is the synchronization signal Sync. The match counter 70 is configured to compare the bit value from the bit stream with the bit value from the pseudo-random key. In response to a mismatch, the seed reset signal Reseed is sent to the pseudo-random number generator. It can be understood that the bit stream will match the pseudo-random key of 64 bits (i.e., message parts n and m) because zero is used for the payload of these parts of the frame. When comparing the trigger bit t, a mismatch will occur because the payload for t is 1. Therefore, the "exclusive or" combination of the trigger bit (1) and the pseudo-random key value will not have the same value as the pseudo-random key. Then, the seed reset signal Reseed is suspended for 60 bits. Another output, ie, the synchronization signal Sync, is output to the payload latch 78 at the last bit of the frame (the 60th bit after the reseed signal has been output).

[0088] Once an entire frame has been decoded, encoding will restart from the subsequent frame.

[0089] The pseudo-random number generator 72 receives the bit stream output by the pulse width detector. The first bit of the frame is regarded as the seed signal Seed. In response to the seed signal Seed, the pseudo-random number generator 72 generates a pseudo-random key. The pseudo-random number generator 72 may include a linear feedback shift register (LFSR). The LFSR may be 24 bits long. The LFSR may be the same as the LFSR in the transmitter. In this way, the pseudo-random number generator 72 will generate a pseudo-random key identical to the pseudo-random key in the transmitter. The pseudo-random number generator 72 repeatedly generates a 24-bit long pseudo-random key until a seed reset signal Reseed is received that guides it to reset and generate a pseudo-random key from the first bit again. In this way, the match counter is configured to reset the pseudo-random number generator in response to detecting a trigger portion. The pseudo-random key is output to the combiner 74 and the match counter 70.

[0090] Combiner 74 receives two inputs. The first input is a pseudo-random key. The second input is a bit stream output from a pulse width detector. The first input and the second input are combined by combiner 74. Combiner 74 can be provided in the form of an XOR gate. The combined bit stream is output from combiner 74 to shift register 76.

[0091] Thus, the data stream restorer is further configured to obtain a message based on the bit values ​​of the data stream and the pseudo-random number key.

[0092] In response to receiving the synchronization signal Sync, the effective load latch 78 is configured to latch the latest 60 bits in the shift register. The latest 60 bits correspond to bit m of the frame, which corresponds to the message. Thus, the match counter 70 is configured to output a message in response to counting m bits after the trigger portion.

[0093] The message may be a timestamp or a sample count. The output of the payload latch 78 may be a sample count or a timestamp. Thus, the payload latch may also be referred to as a message latch.

[0094] refer to Figure 6 , the output 64 is configured to output the decoded message (time stamp or sample count) to the audio device 14 ( Figure 1 ) processor that enables the audio device to synchronize the clock signal with other devices.

[0095] The various features of the transmitter and the receiver described in the foregoing embodiments may be embodied as instructions stored on a computer-readable medium. The instructions may be executed by a processor to enable the processor to perform the functions described herein.

[0096] refer to Figure 8 , the various features of the transmitter can be understood as method steps. The method can be a method for encoding a coded clock signal. In addition to the other details included above, the method also includes: in step S100, receiving a message to be sent to a receiver of an audio device of the audio system and clock frequency information for synchronizing a clock signal of the audio device; in step S102, determining a data stream based on the message; in step S104, generating a coded clock signal in the form of a rectangular wave, the rectangular wave having a rising edge timing based on the clock frequency and a falling edge timing that is earlier or later than half a cycle of the coded clock signal according to the bit value of the data stream; and in step S106, transmitting the coded clock signal to the receiver.

[0097] refer to Fig. 9 , various features of the receiver can be understood as method steps. The method can be a method of obtaining a message and a clock signal from a coded clock signal. The method includes: in step S200, receiving a coded clock signal from a transmitter of a master clock for an audio system; in step S202, generating a square wave clock signal having a frequency based on the frequency of the coded clock signal; in step S204, obtaining a bit value of a data stream encoded in the coded clock signal based on whether the falling edge of the coded clock signal is earlier or later than half a period of the coded clock signal; and in step S206, obtaining a message based on the bit value of the data stream.

Claims

1. A transmitter for a master clock of an audio system, the transmitter comprising: an input configured to receive a message to be sent to a receiver of an audio device of the audio system and clock frequency information for synchronizing a clock signal of the audio device; a data stream generator configured to determine a data stream based on the message; a pulse shaper configured to generate an encoding clock signal in the form of a rectangular wave having a start signal edge timing based on a clock frequency and an end signal edge timing that is earlier or later than a half period of the encoding clock signal according to a bit value of the data stream; as well as An output is configured to transmit the encoded clock signal to the receiver.

2. The transmitter according to claim 1, further comprising a pseudo-random number generator, the pseudo-random number generator being configured to generate a pseudo-random number key, wherein The data stream generator is configured to generate the data stream further based on the pseudo-random number key.

3. The transmitter according to claim 2, wherein: The data stream comprises a plurality of bits in the form of frames, wherein the frame comprises a synchronization portion, followed by a trigger portion, followed by a message portion, the message portion corresponding to the received message and being m bits long, wherein the synchronization portion is n plus s bits long, wherein n is the length of the pseudo-random number generator and s is the number of bits used to synchronize the receiver, and wherein the trigger portion is t bits long.

4. The transmitter according to claim 3, wherein: s is greater than m.

5. The transmitter according to claim 3 or 4, wherein: The data stream generator is configured to generate the data stream based on a payload of zeros and the pseudo-random number key during the synchronization part, generate the data stream based on a payload of one or more ones and the pseudo-random number key during the trigger part, and generate the data stream based on a payload corresponding to the message and the pseudo-random number key during the message part.

6. The transmitter according to any one of claims 2 to 5, wherein: The pseudo-random number generator is a linear feedback shift register.

7. The transmitter according to any one of the preceding claims, further comprising a pulse narrower and a pulse stretcher, wherein the pulse narrower is configured to generate a first rectangular wave having a pulse width less than half a period of the encoding clock signal, and the pulse stretcher is configured to generate a second rectangular wave having a pulse width greater than half a period of the encoding clock signal, wherein The pulse shaper is configured to select the first rectangular wave or the second rectangular wave according to a bit value of the data stream.

8. The transmitter according to claim 7, wherein: The pulse stretcher and the pulse narrower are configured to generate the first rectangular wave and the second rectangular wave by combining pulses from waves having a frequency that is a multiple of the encoding clock signal.

9. A transmitter according to any one of the preceding claims, wherein The message may include a sample count or a timestamp.

10. A master clock device comprising a transmitter according to any preceding claim.

11. A receiver for an audio device of an audio system, the receiver comprising: an input configured to receive an encoded clock signal from a transmitter of a master clock for the audio system; a clock signal generator configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal; as well as A data stream restorer is configured to obtain a bit value of a data stream encoded in the encoding clock signal based on whether a termination signal edge of the encoding clock signal is earlier or later than half a cycle of the encoding clock signal, and obtain a message based on the bit value of the data stream.

12. The receiver of claim 11, further comprising a pseudo-random number generator configured to generate a pseudo-random number key, wherein: The data stream restorer is further configured to obtain a message based on the bit values ​​of the data stream and the pseudo-random number key.

13. The receiver according to claim 12, wherein: The data stream comprises a plurality of bits in the form of frames, wherein the frame comprises a synchronization portion, followed by a trigger portion, followed by a message portion, the message portion corresponding to the received message and being m bits long, wherein the synchronization portion is n plus s bits long, wherein n is the length of the pseudo-random number generator and s is the number of bits used to synchronize the receiver, and wherein the trigger portion is t bits long.

14. The receiver according to claim 13, wherein: s is greater than m.

15. A receiver according to claim 13 or claim 14, further comprising a match counter configured to reset the pseudo-random number generator in response to detecting the trigger portion, and configured to output the message in response to counting m bits after the trigger portion.

16. A receiver according to any one of claims 12 to 15, wherein: The pseudo-random number generator is a linear feedback shift register.

17. The receiver according to any one of claims 11 to 16 further includes a pulse width detector, which is configured to determine whether the termination signal edge of the encoding clock signal is earlier or later than half a cycle of the encoding clock signal by sampling the encoding clock signal at a frequency that is a multiple of the frequency of the wave used to generate the encoding clock signal pulse.

18. A receiver according to any one of claims 11 to 17, wherein: The message may include a sample count or a timestamp.

19. A receiver according to any one of claims 11 to 18, wherein: The clock signal generator is configured to generate the square wave clock signal by dividing the frequency of the encoded clock signal by two.

20. An audio device comprising a receiver according to any one of claims 12 to 19.

21. A system comprising a transmitter according to any one of claims 1 to 9, and a receiver according to any one of claims 11 to 20.

22. A method for encoding an encoding clock signal, the method comprising: receiving a message to be sent to a receiver of an audio device of the audio system and clock frequency information for synchronizing a clock signal of the audio device; determining a data flow based on the message; generating an encoding clock signal in the form of a rectangular wave having a start signal edge timing based on a clock frequency and an end signal edge timing earlier or later than a half period of the encoding clock signal according to a bit value of the data stream; as well as The encoded clock signal is transmitted to the receiver.

23. A method of obtaining a message and a clock signal from an encoded clock signal, the method comprising: receiving an encoded clock signal from a transmitter of a master clock for an audio system; generating a square wave clock signal having a frequency based on the frequency of the encoded clock signal; Obtaining a bit value of a data stream encoded in the encoding clock signal based on whether a termination signal edge of the encoding clock signal is earlier or later than a half period of the encoding clock signal; as well as A message is obtained based on the bit values ​​of the data stream.

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