Method for manufacturing semiconductor device and semiconductor device

Abstract

According to an embodiment, a method comprises the step of providing a semiconductor body (1) having a top side (10). A mask (2) is applied on the top side of the semiconductor body, the mask comprising at least one first section (21) and at least one second section (22). The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. In a further step, a channel region (11) of the first conductivity type is formed in the semiconductor body (1) in the region of the at least one first section. Forming the channel region includes implanting a dopant of a first type into the semiconductor body through the top side. In a further step, an auxiliary layer (3) is deposited on a lateral side (22a) of the at least one second section, the lateral side facing the at least one first section. Thereby, the lateral extension of the at least one second section increases and the lateral extension of the at least one first section decreases. In a further step, a hole is created in the semiconductor body in the region of the first section having the reduced lateral extension, such that the hole extends from the top side through the channel region.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] US2012 / 0146090 A1 relates to a transistor device that can be manufactured with an integrated diode using self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in the top portion of the substrate near each gate trench. One or more source regions are formed in the top portion of the body region near each gate trench in a self-aligned manner. One or more thick insulator portions are formed above the gate electrode located on the top surface of the substrate, with spaces between adjacent thick insulator portions. Metal is formed on the top of the substrate, above the thick insulator portions. The metal forms a self-aligned contact to the substrate through the space between the thick insulator portions. An integrated diode is formed below the self-aligned contact.

[0003] US2012 / 0164810 A1 relates to a method for manufacturing a silicon carbide semiconductor device. A first impurity region is formed by ion implantation through a first opening formed in a mask layer. A mask portion having a mask layer and a spacer layer is formed by depositing a spacer layer on an etch stop layer (on which a mask layer has been provided). A second opening surrounded by a second sidewall is formed in the mask portion by anisotropic etching of the spacer layer. A second impurity region is formed by ion implantation through the second opening. Across a height as large as the second depth, the angle of the second sidewall relative to the surface is 90°±10°. Therefore, the accuracy of the extension of the impurity region can be improved. Summary of the invention

[0004] It is an object to provide an improved method for manufacturing a semiconductor device, for example a method with a reduced number of manufacturing steps and / or a method enabling smaller structures to be produced. It is a further object to provide an improved semiconductor device, for example with smaller structures.

[0005] Embodiments of the present disclosure relate to an improved method for manufacturing a semiconductor device and an improved semiconductor device.

[0006] First, a method for manufacturing a semiconductor device is described in detail.

[0007] According to an embodiment, a method for manufacturing a semiconductor device comprises the following steps: providing a semiconductor body having a top side. Applying a mask on the top side of the semiconductor body, wherein the mask comprises at least one first section and at least one second section. The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. In a further step, a channel region of a first conductivity type is formed in the semiconductor body in the region of the at least one first section. Forming the channel region comprises implanting a dopant of the first type into the semiconductor body through the top side. In a further step, an auxiliary layer is deposited on a lateral side of the at least one second section, the lateral side facing the at least one first section. Thereby, the lateral extension of the at least one second section is increased, and the lateral extension of the at least one first section is reduced. In a further step, a hole is generated in the semiconductor body in the region of the first section with a reduced lateral extension, so that the hole extends from the top side through the channel region.

[0008] The superior properties of wide bandgap semiconductors (WBG), such as high critical electric field and electron mobility or high-frequency switching, result in much larger Baliga figures of merit compared to commonly used silicon, making them ideal materials for power switches. This enables several applications targeting energy efficiency and power transportation.

[0009] Today, most commercially available power SiC-MOSFETs are based on cell designs with a planar channel aligned with the Si plane (i.e., at the wafer SiC (0001)). However, the increase in current density in such switches is hampered by the increase in junction FET (JFET) resistance as the injector size decreases and by the low inversion channel mobility. On the other hand, trench MOSFETs exhibiting a dry-etched U-shaped channel enable low on-resistance due to the lack of a JFET region and high cell density. Especially for SiC trench devices, the trench MOSFET architecture allows optimizing carrier mobility by designing the channel with respect to different crystal planes and increasing gate dielectric control.

[0010] Nevertheless, the trench cell design of the state-of-the-art process does not fully exploit the above advantages. Although different crystal planes are exploited for carrier transport, the trench pitch and width of the cell are still quite large, thus prohibiting the ultimate scaling of cell density and thus prohibiting high current density of the device.

[0011] The method disclosed herein enables self-aligned channel implantation and trench etching, and therefore replaces two independent photolithography steps. Therefore, fewer manufacturing steps are required, and smaller structures can be produced. The method is suitable for manufacturing different semiconductor devices, such as MOSFT or IGBT or JFET or MISFET.

[0012] The semiconductor body is based on Si, SiC, GaN, Ga2O3, for example. The semiconductor body may be based on a wide bandgap material. The semiconductor body may include a doped substrate and a doped drift layer on top of the substrate. The top side of the semiconductor body may be at least partially formed by the drift layer. For example, the substrate has a higher doping concentration than the drift layer. The substrate and the drift layer may have the same conductivity type. Both may be n-type doped or p-type doped.

[0013] In the step of providing the semiconductor body, the top side of the semiconductor body may be a flat surface without interruptions or recesses or holes.

[0014] The mask may be produced with the help of a photolithography process. For example, the mask comprises a photoresist. In the at least one second section, the mask is thicker than in the at least one first section. This may mean that the thickness of the mask in the at least one first section is zero, so that, for example, the top side of the semiconductor body is exposed in the region of the at least one first section. Alternatively, the thickness of the mask in the at least one first section may be greater than zero but still less than the thickness in the at least one second section. In both cases, a step is formed between the at least one first section and the at least one second section. The step forms a lateral side of the second section facing the at least one first section.

[0015] The thickness of the mask is measured in a direction perpendicular to the top side. "Thickness" herein means the average value of the maximum thickness. For example, the thickness of the mask in the at least one second section is at least 2 times, or at least 5 times, or at least 10 times, or at least 100 times the thickness of the mask in the at least one first section.

[0016] The mask comprises at least one first section (i.e., one or more first sections) and at least one second section (i.e., one or more second sections). All features disclosed herein for one first section are also disclosed for all first sections, and similarly, all features disclosed herein for one second section are also disclosed for all second sections. For simplicity, the expression "the at least one" is also referred to herein as "the".

[0017] For example, the mask comprises a second section forming a mesh, and a plurality of first sections, each of which is located within the mesh of the mesh. Alternatively, the mask comprises a first section forming a mesh, and a plurality of second sections, each of which is located within the mesh of the mesh. Another alternative is that the mask comprises a plurality of first sections and a plurality of second sections, wherein each first section is laterally located between two second sections.

[0018] The at least one first section is laterally adjacent to the at least one second section. In particular, the at least one second section adjoins the at least one first section in a lateral direction. For example, a step between the first section and the second section indicates a boundary between the first section and the second section. The second section may completely surround the at least one first section laterally. Alternatively, the first section may be located between two second sections in a first lateral direction. A lateral direction is understood herein as a direction parallel to the top side of the semiconductor body and / or parallel to a main extension plane of the semiconductor body.

[0019] The step of forming the channel region is performed after the step of applying the mask on the top side. The step of forming the channel region includes implanting a first type of dopant through the top side of the semiconductor body. The first type of dopant is a p-type dopant or an n-type dopant. The second type of dopant is different from the first type of dopant in this article, that is, it is an n-type dopant or a p-type dopant. For example, the first type of dopant is boron, and the second type of dopant is arsenic or phosphorus.

[0020] Forming the channel region may further include an annealing step, which is performed after implanting the first type of dopant. During the annealing step, the implanted first type of dopant diffuses further into the semiconductor body, such that the channel region extends into the semiconductor body.

[0021] The channel region has a first conductivity type. When the first type of dopant is a p-type dopant, the first conductivity type is hole conduction. That is, the channel region is p-type doped. When the first type of dopant is an n-type dopant, the first conductivity type is electron conduction, that is, the channel region is n-type doped. The second conductivity type is different from the first conductivity type in this article.

[0022] The channel region is formed in the region of the at least one first section, i.e., below the at least one first section. During the implantation, the dopant may impinge on the mask over the entire lateral extension of the mask, i.e., also in the region of the at least one second section. However, due to the greater thickness of the mask in the at least one second section, less dopant is implanted into the semiconductor body in the region of the second section. The amount of the first type of dopant implanted in the region of the second section is, for example, insufficient to form a region of the first conductivity type below the second section.

[0023] The channel region extends from the top side into the semiconductor body (depth of the channel region), for example, to at least 50 nm and / or at most 1 μm.

[0024] The step of depositing an auxiliary layer on the lateral side of the at least one second section is performed after forming the channel region. As mentioned above, the lateral side of the at least one second section may be formed by a step between the at least one second section and the at least one first section. Thus, the lateral side extends obliquely to (e.g., perpendicularly or almost perpendicularly to) the top side.

[0025] Due to the auxiliary layer, the width or lateral extension of the second section increases, while the width or lateral extension of the first section decreases. In other words, due to the deposition of the auxiliary layer on the lateral sides of the mask (also called the initial mask), the mask is supplemented by the deposited auxiliary layer and is thus transformed into a new mask, which includes the initial mask and the deposited auxiliary layer and has a narrower / smaller first section and a wider / larger second section.

[0026] The thickness of the auxiliary layer on the lateral side of the at least one second section is, for example, at least 50 nm and / or at most 1 μm. Thus, the lateral extension of the at least one second section at least increases this thickness (e.g., increases it by about twice the thickness), and the lateral extension of the at least one first section at least reduces this thickness (e.g., reduces it by about twice the thickness).

[0027] The material of the auxiliary layer is, for example, different from the material of the initial mask. For example, the auxiliary layer includes or consists of the following: SiO2, or SiN, or polysilicon.

[0028] The step of producing a hole in the semiconductor body is performed after applying the auxiliary layer. The hole is produced in the region of the first section with reduced lateral extension. During the production of the hole, the semiconductor body can be protected by the second section with increased lateral extension below the second section with increased lateral extension, so that the hole is indeed formed only in the region of the first section with reduced lateral extension.

[0029] Due to the reduced lateral extension of the first section, the resulting hole has a smaller lateral extension or width than the previously formed channel region. Thus, the hole is formed to pass through the channel region. For example, the hole laterally adjoins the channel region. For example, the hole is laterally completely surrounded by the channel region, or the channel region adjoins the hole on both sides relative to the first lateral direction.

[0030] For example, the produced holes protrude deeper into the semiconductor body relative to the channel region, such as at least 1.5 times deeper. By way of example, the depth of the holes is at least 500 nm and / or at most 2 μm.

[0031] According to a further embodiment, after forming the channel region and before depositing the auxiliary layer, a further auxiliary layer is deposited on the lateral side of the at least one second section, the further auxiliary layer increasing the lateral extension of the at least one second section and reducing the lateral extension of the at least one first section. Since the further auxiliary layer is deposited before the auxiliary layer, the further auxiliary layer is also referred to herein as the first auxiliary layer, and the auxiliary layer is therefore also referred to herein as the second auxiliary layer.

[0032] Thus, during the method, the lateral extension of the second section of the mask can be increased by a factor of two, and the lateral extension of the first section of the mask can be reduced by a factor of two. Or, in other words, the initial mask is transformed twice into a corresponding new mask, wherein each time the first section becomes narrower / smaller and the second section becomes wider / larger.

[0033] The thickness of the further auxiliary layer on the lateral side of the at least one second section may be in the same range as the thickness of the auxiliary layer on the lateral side. The further auxiliary layer may have a different material than the auxiliary layer and / or the mask. For example, the further auxiliary layer comprises or consists of: SiO2, or SiN, or polysilicon.

[0034] According to a further embodiment, after depositing the further auxiliary layer and before depositing the auxiliary layer, a contact region of the second conductivity type is formed in the semiconductor body in the region of the first section. The contact region is formed so that it is located between the channel region and the top side of the semiconductor body. The formation of the contact region comprises: implanting a dopant of the second type into the semiconductor body through the top side.

[0035] The formation of the contact region may include an annealing process after implanting the second type of dopant. During the annealing process, the second type of dopant further diffuses into the semiconductor body, so that the contact region further expands into the semiconductor body.

[0036] The contact region is at least partially formed from a previously formed channel region.Thus, the amount of implanted second type dopant is sufficient to convert a portion of the channel region having the first conductivity type to the second conductivity type.

[0037] Since the lateral extension of the first section during the implantation of the second type of dopant is reduced compared to the lateral extension of the first section during the implantation of the first type of dopant, the contact region has a smaller lateral extension than the channel region. Thus, in a lateral direction, the contact region is surrounded by the channel region, or the channel region adjoins the contact region on both sides relative to the first lateral direction.

[0038] The depth of the contact region is, for example, smaller than the depth of the channel region, so that the contact region is located between the channel region and the top side. In other words, along a vertical direction perpendicular to the top side, the contact region is arranged between the channel region and the top side.

[0039] According to a further embodiment, the hole is formed through the contact region. For example, the hole laterally adjoins the contact region. Since the lateral extension of the first section during the formation of the hole is smaller than the lateral extension of the first section during the implantation of the second type of dopant, the lateral extension of the hole is smaller than the lateral extension of the contact region. For example, the hole is laterally surrounded by the contact region, or the contact region adjoins the hole on both sides relative to the first lateral direction. For example, along the first lateral direction, the contact region is arranged between the hole and the channel region.

[0040] In the case of forming a hole, the channel region and / or the contact region formed in the region of the at least one first section can be divided into two channel regions and / or contact regions. All features disclosed herein and below with respect to one channel region or one contact region in the region of the at least one first section are also disclosed with respect to two contact regions or two channel regions in the region of the at least one first section.

[0041] According to a further embodiment, the auxiliary layer is deposited by a conformal (i.e. non-directional) deposition process. Due to this, the lateral sides of at least one second section, the top side of at least one second section, and the region of the first section are covered by the auxiliary layer. For example, in the region of the first section, the top side of the semiconductor body is covered by the auxiliary layer. For example, the auxiliary layer can be deposited by chemical vapor deposition (CVD for short).

[0042] According to a further embodiment, after depositing the auxiliary layer, a directional material removal process is applied, by which more auxiliary layer is removed in the region of the first section and at the top side of the second section than at the lateral sides of the at least one second section. The removal process may be an etching process, such as a dry etching process, for example a plasma etching process. A directional material removal process is also referred to as an anisotropic material removal process.

[0043] After the material removal process, the lateral sides of the at least one second section are still covered by at least the remaining part of the previously deposited auxiliary layer. However, after the directional material removal process, an area of ​​the at least one first section (now with a reduced lateral extension) and / or the top side of the at least one second section may be exposed. The hole is, for example, formed after performing the directional material removal process. For example, the thickness of the auxiliary layer on the lateral side detailed above relates to the thickness after the material removal process.

[0044] The same as disclosed for the auxiliary layer regarding the conformal deposition process and the subsequent directional material removal process can also be performed for the further auxiliary layer. The implantation of the second type of dopant is for example performed after applying the directional material removal process to the further auxiliary layer.

[0045] According to at least one embodiment, before depositing the auxiliary layer and / or before depositing the further auxiliary layer, a protective layer is deposited onto the semiconductor body, at least in the region of the at least one first section. The protective layer is configured to protect the semiconductor body when the (further) auxiliary layer is removed by means of a directional material removal process. For example, the protective layer is an etch stop layer which prevents an etchant from reaching the semiconductor body.

[0046] According to a further embodiment, before applying the mask, the semiconductor body has the second conductivity type at least at the top side. For example, the entire top side has the second conductivity type. In particular, the drift layer of the semiconductor body may have the second conductivity type. The substrate may also have the second conductivity type.

[0047] According to a further embodiment, during the implantation of the dopant of the first type, the at least one second section protects the underlying semiconductor body from the dopant of the first type, such that the semiconductor body in the region of the at least one second section still has the second conductivity type at the top side. In other words, the amount of the dopant of the first type that reaches into the semiconductor body in the region of the at least one second section is not sufficient to convert the conductivity type of the semiconductor body.

[0048] According to a further embodiment, the method further comprises the following steps: forming an electrical isolation layer at the surface of the hole. The isolation layer is, for example, SiO2. The formation of the isolation layer can be accomplished by filling the hole with an electrical isolation material or by oxidizing the surface of the hole. In particular, the surface of the hole is formed by the semiconductor body and defines the lateral surface and / or the bottom surface of the hole.

[0049] According to a further embodiment, the method further comprises: forming a gate electrode over and / or in the at least one hole, such that the gate electrode is electrically isolated from the semiconductor body by the electrical isolation layer. The gate electrode may comprise or consist of at least one of the following: a metal (e.g., Cu, Al, Au, Ag or alloys thereof) or highly doped polysilicon.

[0050] The formation of the electrical isolation layer and / or the gate electrode may be done with the mask still on the top side of the semiconductor body.

[0051] According to a further embodiment, the method comprises the step of removing the mask.During the removal of the mask, the auxiliary layer and / or the further auxiliary layer may be removed together with the initial mask.

[0052] According to a further embodiment, the method comprises the step of forming a main electrode on the top side such that the main electrode adjoins and is electrically connected to the semiconductor body in a region laterally adjacent to the at least one hole. In particular, this step is performed after removing the mask such that the main electrode adjoins the top side of the semiconductor body in a region in which the at least one second section of the mask previously covered the top side.

[0053] The main electrode is, for example, metallic, such as Cu, Al, Au, Ag or an alloy thereof. For example, the main electrode is electrically isolated from the gate electrode, for example by means of an electrical isolation layer. The main electrode may be adjacent to the contact region and the channel region and may be in electrical contact with them. For example, an ohmic contact is formed between the main electrode and the contact region and / or the channel region.

[0054] According to a further embodiment, the main electrode adjoins at least one diode region of the semiconductor body at the top side. The diode region has a second conductivity type. For example, the diode region is a region of the semiconductor body that has previously been covered by at least one second section of the mask and is therefore protected by it. The diode region can be formed by a drift layer. For example, the diode region and the main electrode together form a Schottky diode (also known as a JBS diode). Therefore, a Schottky contact is formed between the main electrode and the diode region.

[0055] In the first lateral direction, the contact region and the channel region may be arranged between the hole and the diode region.The diode region may adjoin the channel region in the first lateral direction.

[0056] According to a further embodiment, before applying the mask, a further mask is applied to the top side of the semiconductor body. The further mask may also include a photoresist and may be formed by photolithography.

[0057] According to a further embodiment, at least one plug region of the first conductivity type is formed in the semiconductor body with the help of a further mask. Forming the at least one plug region may also include implanting a dopant of the first type into the semiconductor body through the top side. After the implantation, an annealing process may be performed so that the plug region further expands into the semiconductor body.

[0058] According to a further embodiment, at least one plug region adjoins the top side and is at least partially formed in a region which is subsequently covered by the at least one second section of the mask.

[0059] The plug region can also be arranged in the region of the first section of the subsequently applied mask. For example, during the implantation of dopants of the second type, the plug region is converted to the second conductivity type in the region of the first section of the mask and thus becomes part of the contact region.

[0060] According to a further embodiment, the doping concentration in the at least one plug region is greater than the doping concentration in the channel region.When reference is made to the doping concentrations of different regions, this is meant in each case an average or maximum doping concentration of these regions.

[0061] For example, the doping concentration of at least one plug region is at least one order of magnitude greater than the doping concentration of the channel region. 18 cm -3 with 10 19 cm -3 The doping concentration in the channel region is, for example, between 10 16 cm -3 with 10 18 cm -3 between.

[0062] The doping concentration of the contact region is, for example, greater than the doping concentration of the drift layer and / or the diode region and / or the channel region, for example, greater by at least one order of magnitude. 18 cm -3 with 10 19 cm -3 The doping concentration of the drift layer and / or the diode region is, for example, between 10 15 cm -3 with 10 17 cm -3 Depending on the voltage level of the semiconductor device.

[0063] According to a further embodiment, the mask comprises a plurality of stripe-shaped first sections and a plurality of stripe-shaped second sections. For example, a first section is formed between every two second sections. Similarly, a second section may be formed between every two first sections. For example, the first section and the second section are arranged behind each other in an alternating manner along the first lateral direction.

[0064] The first section and the second section are stripe-shaped (ie, elongated). For example, the second section is formed as a rib. The main extension directions of the first section and the second section may extend parallel to each other. For example, the first section and the second section each extend along a second lateral direction perpendicular to the first lateral direction.

[0065] According to a further embodiment, channel regions and holes are formed in a plurality of or each region in the first section. Each channel region may be formed in a stripe shape, and each hole may be formed as a groove. The stripe-shaped channel region and the groove may all extend along the second lateral direction. When the groove is formed, the stripe-shaped channel region is each divided into two stripe-shaped channel regions spaced apart from each other along the first lateral direction.

[0066] Likewise, in the region of each first section, a stripe-shaped contact region may be formed. For example, the stripe-shaped contact region extends along the second lateral direction. When the grooves are formed, the stripe-shaped contact region is divided into two stripe-shaped contact regions spaced apart from each other along the first lateral direction.

[0067] All features disclosed so far and hereinafter for the formation of channel regions and / or contact regions and / or holes in the region of the at least one first section are also disclosed for the formation of all further channel regions and / or contact regions and / or holes in the region of further first sections of the mask.

[0068] According to a further embodiment, a plurality of plug regions are formed. Features disclosed in connection with at least one plug region are also disclosed for all other plug regions.

[0069] According to a further embodiment, each plug region is formed in a stripe shape (ie, elongated).

[0070] According to a further embodiment, the plug region extends obliquely to the channel region. For example, the plug region extends perpendicular to the channel region. The plug regions may extend along a first lateral direction and may be spaced apart from each other along a second lateral direction. For example, all the plug regions extend parallel to each other.

[0071] Next, a semiconductor device is described in detail. The semiconductor device can be manufactured using a method according to any one of the embodiments disclosed herein. Therefore, all features disclosed for the method are also disclosed for the semiconductor device, and vice versa.

[0072] According to an embodiment, a semiconductor device includes a semiconductor body having a top side. At least one hole extends from the top side into the semiconductor body. At least one hole defines an active area of ​​the semiconductor body along a first lateral direction parallel to the top side. The active area includes at least one channel region having a first conductivity type and at least one contact region having a second conductivity type. At least one channel region and at least one contact region are adjacent to at least one hole along a first lateral direction. At least one contact region is embedded in at least one channel region so that along a vertical direction perpendicular to the top side, at least one contact region is arranged between the top side and at least one channel region, and at least one contact region is adjacent to the top side in a vertical direction. The width of the active area measured along the first lateral direction is at most 3 times the depth of the at least one hole measured along the vertical direction.

[0073] Active areas with such aspect ratios (width / depth) can be produced using the methods described herein. For example, the width of the active area is at most 2 times the depth of the at least one hole, or at most as large as the depth of the at least one hole.

[0074] The active region of the semiconductor device is the region in which charge carriers are transported during operation. For example, the active region is formed between two holes and is bounded by the two holes in a first lateral direction. The active region is, for example, a continuous region of the semiconductor body.

[0075] The semiconductor device may comprise a plurality of active regions which are laterally spaced apart from one another by one or more holes.All features disclosed for one active region are also disclosed for all other active regions.

[0076] According to further embodiments, the width of the active area is at most 3 μm or at most 2.5 μm or at most 2 μm or at most 1.5 μm or at most 1 μm.

[0077] According to a further embodiment, the semiconductor device further includes a main electrode on the top side in the active area.

[0078] According to a further embodiment, the active region includes at least one diode zone, wherein the at least one diode zone has the second conductivity type.The at least one diode zone may adjoin a top side of the semiconductor body in a vertical direction.

[0079] According to a further embodiment, the main electrode adjoins at least one contact region and is in electrical contact therewith.Additionally, the main electrode may adjoin at least one diode region and / or at least one channel region and may be in electrical contact therewith.

[0080] According to a further embodiment, the surface of at least one hole is at least partially covered by the electrically isolating layer. These surfaces of the hole are formed by the semiconductor body. For example, the (multiple) lateral surfaces and the bottom surface of the hole are covered by the electrically isolating layer.

[0081] According to a further embodiment, the gate electrode is formed over and / or in the at least one hole and is electrically isolated from the semiconductor body by the isolation layer.

[0082] According to a further embodiment, the active area comprises at least one plug region, wherein the at least one plug region has the first conductivity type and adjoins the top side.For example, the at least one plug region has a higher doping concentration than the at least one channel region.

[0083] According to a further embodiment, the semiconductor device is a power semiconductor device. For example, the semiconductor device is a MOSFET or an IGBT or a JFET or a MISFET. A further main electrode may be applied on the bottom side of the semiconductor body, wherein the bottom side is opposite to the top side. The power semiconductor device may be configured for a voltage difference of at least 1 kV (e.g. at least 1.2 kV or at least 3.3 kV) between the main electrode and the further main electrode.

[0084] In the case of MISFET, JFET or MOSFET, the contact region is also called the source region. In the case of IGBT, the contact region is also called the emitter region.

[0085] According to a further embodiment, the semiconductor device comprises a plurality of holes, each hole being formed as a trench. The trenches are spaced apart from each other along a first lateral direction. Each trench extends along a second lateral direction. The first lateral direction and the second lateral direction are, for example, perpendicular to each other.

[0086] According to a further embodiment, the semiconductor device comprises a plurality of active regions, wherein each active region is arranged between a pair of trenches. Thus, along the first lateral direction, one active region is formed between each pair of trenches.

[0087] According to a further embodiment, each active area comprises at least two elongated channel regions, such as stripe-shaped channel regions. The channel regions extend along the second lateral direction. In addition, each active area comprises at least two elongated contact regions, such as stripe-shaped contact regions. Each contact region extends along the second lateral direction. The contact regions may be spaced apart from each other along the first lateral direction. Similarly, the channel regions may be spaced apart from each other along the first lateral direction.

[0088] The lengths of the trenches, the contact regions and / or the channel regions measured along the second lateral direction may all be the same.

[0089] According to a further embodiment, the channel region and the contact region of each active region each adjoin a trench delimiting the active region. Thus, in each active region, one contact region and one channel region adjoin the trench delimiting the active region on one side relative to the first lateral direction, and a further channel region and a further contact region adjoin the trench delimiting the active region on the other side relative to the first lateral direction.

[0090] According to a further embodiment, the width of the active area is the distance between two trenches delimiting the active area along the first lateral direction.

[0091] Hereinafter, a method for manufacturing a semiconductor device and a semiconductor device will be explained in more detail with reference to the accompanying drawings based on exemplary embodiments. The accompanying drawings are included to provide further understanding. In the accompanying drawings, elements of the same structure and / or function may be referenced by the same reference numerals. It will be understood that the embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale. As long as elements or components correspond to each other in terms of their functions in different drawings, their description will not be repeated for each of the following drawings. For clarity, elements may not appear in all drawings with corresponding reference symbols. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] Figure 1 and Figure 2A flow chart of an exemplary embodiment of a method for manufacturing a semiconductor device is shown.

[0093] Figures 3 to 18 shows different locations during an exemplary embodiment of a method for manufacturing a semiconductor device,

[0094] Fig.19 Exemplary embodiments of a semiconductor device are shown. DETAILED DESCRIPTION

[0095] Figure 1 A flow chart of a first exemplary embodiment of a method for manufacturing a semiconductor device is shown. In step S1, a semiconductor body having a top side is provided. Then, in a second step S2, a mask is applied on the top side, wherein the mask comprises at least one first section and at least one second section laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. In step S3, at least one channel region of a first conductivity type is formed in the semiconductor body in the region of the at least one first section, wherein the formation of the channel region comprises implanting a dopant of the first type into the semiconductor body through the top side. In step S4, an auxiliary layer is deposited on a lateral side of the at least one second section facing the at least one first section, the auxiliary layer increasing the lateral extension of the at least one second section and reducing the lateral extension of the at least one first section. In step S5, a hole is generated in the semiconductor body in the region of the first section having a reduced lateral extension, so that at least one hole extends from the top side through the channel region.

[0096] Figure 2A flow chart of a second exemplary embodiment of a method for manufacturing a semiconductor device is shown. Steps S1 to S5 are the same as in the first exemplary embodiment. After step S1, step S6 is performed, in which a further mask is applied to the top side of the semiconductor body. In step S7, at least one plug region with a first conductivity type is formed in the semiconductor body with the help of the further mask. Then, the further mask is removed and steps S2 and S3 are performed. After step S3 (in which a channel region is formed), step S8 is performed, in which a further auxiliary layer is deposited on the lateral side of at least one second section of the mask, the further auxiliary layer increasing the lateral extension of at least one second section and reducing the lateral extension of at least one first section. After that, in step S9, a contact region of a second conductivity type is formed in the semiconductor body in the region of the first section, so that the contact region is located between the channel region and the top side of the semiconductor body. Forming the contact region includes implanting a dopant of the second type through the top side. The contact region has a second conductivity type. After that, steps S4 and S5 are performed. After step S5 (in which the holes are formed), in step S10, an electrical isolation layer is formed on the surface of at least one hole. Then, in step S11, a gate electrode is formed above and / or in the at least one hole, wherein the gate electrode is electrically isolated from the semiconductor body by the electrical isolation layer. In step S12, the mask is removed, and in step S13, a main electrode is formed on the top side of the semiconductor body.

[0097] Figures 3 to 18 An exemplary embodiment of the method is now shown based on various positions during the method for manufacturing a semiconductor device. In this exemplary embodiment, the first type of dopant is a p-type dopant, and therefore the first conductivity type is hole conduction. The second type of dopant is an n-type dopant, and therefore the second conductivity type is electron conduction. However, the method can also be performed when the first type of dopant is an n-type dopant and the second type of dopant is a p-type dopant.

[0098] exist Figure 3 In the present invention, a semiconductor body 1 is provided. The semiconductor body 1 is based on a wide bandgap material, such as SiC, for example. The semiconductor body 1 comprises an n-type doped substrate 19 and an n-type doped drift layer 18 on top of the substrate 19. The doping concentration in the substrate 19 is greater than the doping concentration in the drift layer 18. For example, in the drift layer 18, the doping concentration is between 10 15 cm -3 with 10 17 cm -3 The drift layer 18 forms the top side 10 of the semiconductor body 1 .

[0099] Figure 3Different directions used in this document are also indicated. A lateral direction is defined in this document as a direction parallel to the top side 10 or the main extension plane of the semiconductor body 1. Figure 3 In the embodiment, the first lateral direction Q is perpendicular to the plane of the paper, and the second lateral direction L is parallel to the plane of the paper. The vertical direction V is a direction perpendicular to the top side 10 or the main extension plane, and is also parallel to Figure 3 The paper plane in the.

[0100] Figure 4 A position in the method is shown in which a first mask 8 (also referred to herein as further mask 8) is applied on the top side 10 of the semiconductor body 1. The mask 8 comprises a first section 81 in which the top side 10 is exposed and a second section 82 in which the top side 10 is covered by a mask material. The mask 8 is produced, for example, with the aid of photolithography. The mask material of the first mask 8 can be a photoresist.

[0101] Figure 5 The location is shown, i.e., the location in which a first type of dopant, i.e., a p-type dopant, such as boron, is implanted through the top side 10 into the semiconductor body 1. As a result, a plug region 14 is created in the region of the first section 81 of the first mask 8. The plug region 14 is therefore a p-doped region. The amount of implanted p-type dopant is therefore large enough to convert the previously n-doped semiconductor material below the first section 81 of the first mask 8 into a p-doped semiconductor material.

[0102] A certain amount of p-type dopant can reach the second section 82 through the first mask 8 and can be accommodated in the semiconductor body 1 below the second section 82. However, the shielding or protection performed by the second section 82 is so efficient that the amount of p-type dopant reaching into the semiconductor body 1 is insufficient to convert the n-doped semiconductor material into a p-doped material. Therefore, the plug region 14 is formed only in the region of the first section 81 of the first mask 8. In the region of the second section 82, the semiconductor body 1 is still n-doped.

[0103] The formation of the plug region 14 may include an annealing process after or during the implantation process, so that the implanted p-type dopant drifts further into the semiconductor body 1, due to which the plug region 14 further expands. The doping concentration in the plug region 14 after annealing is, for example, about 10 18 cm -3 with 10 19 cm -3 between.

[0104] and Figure 5In contrast to the situation shown in , the plug region 14 can also be formed in a trench. For this purpose, a trench can be formed in the semiconductor body 1 in the region of the first section 81, and then a p-type dopant can be implanted into the semiconductor body 1 in the region of the trench. In this way, it is achieved that the plug region 14 extends deeper into the semiconductor body 1.

[0105] exist Figure 6 , the semiconductor body 1 is shown in a plan view on the top side 10 after the first mask 8 has been removed. As can be seen here, the plug regions 14 are elongated stripe-like regions which each extend in a first lateral direction Q and are spaced apart from one another in a second lateral direction L.

[0106] Figure 7 A further position of the method is shown. Again, a plan view onto the top side 10 of the semiconductor body 1 is shown. Figure 7 In the embodiment of the present invention, a second mask 2 (also referred to herein as mask 2 for short) is applied to the top side 10 of the semiconductor body 1. The second mask 2 comprises a first section 21 and a second section 22. In the first section 21, the top side 10 of the semiconductor body 1 is exposed. However, in the second section 22, the top side 10 is covered by a mask material. The second mask 2 can again be produced by photolithography. The mask material can be a photoresist.

[0107] The first segments 21 and the second segments 22 are elongated stripe-like structures, each of which extends along the second lateral direction L. Along the first lateral direction Q, the first segments 21 and the second segments 22 are arranged in an alternating manner.

[0108] Figure 8 The semiconductor body 1 is shown again in cross section, but with Figures 3 to 5 Compared to the figure, this is now a rotated view, in which the second lateral direction L is perpendicular to the plane of the paper and the first lateral direction Q is parallel to the plane of the paper.

[0109] exist Figure 8 , a position is shown in which a first type of dopant, i.e. a p-type dopant, is implanted through the top side 10. In the first section 21, the semiconductor body 1 is not protected by the mask 2. Therefore, the amount of p-type dopant implanted into the semiconductor body 1 is greater in the region of the first section 21 than in the region of the second section 22. As a result of this, a channel region 11 is formed in the region of the first section 21. The channel region 11 has a first conductivity type, i.e. hole conduction or p-type doping. In other words, the amount of the p-type dopant implanted is sufficient to convert the previously n-doped semiconductor material in the region of the first section 21 into a p-doped semiconductor material. In the region of the second section 22, the amount of the p-type dopant implanted is insufficient to change the doping type. The formation of the channel region 11 may again include an additional annealing process.

[0110] Fig. 9 The method shows a position in which a first auxiliary layer 4 (also referred to herein as a further auxiliary layer) is deposited onto the initial mask 2. Thus, the first auxiliary layer 4 covers the top side of the semiconductor body 1 in the region of the first section 21, the top side of the initial mask 2 in the region of the second section 22, and also covers the lateral sides 22a of the second section 22. The lateral sides 22a extend perpendicularly to the top side 10 and are each formed by a step between the first section 21 and the second section 22 of the initial mask 2. For depositing the first auxiliary layer 4, a conformal or non-directional deposition process is used, such as CVD. The first auxiliary layer 4 comprises or consists of, for example, SiN or SiO2.

[0111] Fig.10 A further position in the method is shown, in which a directional material removal process (e.g., dry etching) is used to remove material of the first auxiliary layer 4 in the region of the first segment 21 and on the top side of the second segment 22. The directional material removal process does not remove or does not completely remove material of the first auxiliary layer 4 on the lateral side 22a of the second segment 22. As a result, at least a portion of the first auxiliary layer 4 remains on the lateral side 22a of the second segment 22. As a result, the second segments 22 become effectively wider (i.e., their lateral extension along the first lateral direction Q increases), wherein the first segments 21 become effectively narrower (i.e., their lateral extension along the first lateral direction Q decreases). The thickness of the remaining portion of the first auxiliary layer 4 on the lateral side 22a of the second segment 22 is, for example, at least 100 nm and at most 1 μm. As a result, the width of the second segments 22 is each increased by 2 times the thickness, while the thickness of the first segments is each reduced by 2 times the thickness.

[0112] Before applying the further auxiliary layer 4, a protective layer (not shown), for example an etch stop layer, may be applied to the top side 10 of the semiconductor body 1. The protective layer may protect the semiconductor body 1 in the region of the first section from being corroded during the directional material removal process.

[0113] Fig.11 The method shows a position in which a second type of dopant, i.e. an n-type dopant, is implanted through the top side 10 into the semiconductor body 1. Thereby, a contact region 12 is formed in the region of the first section 21 with a reduced lateral extension. Due to the reduced lateral extension of the first section 21 compared to an embodiment of a first type of dopant for forming the channel region 11, the contact region 12 is narrower than the channel region 11 (i.e. has a smaller lateral extension in the first lateral direction Q). Here too, the formation of the contact region 12 can additionally include an annealing step (not shown).

[0114] The contact region 12 is formed in a portion of the previously formed channel region 11 and has a second conductivity type (i.e., electronic conductivity or n-type doping). Therefore, the amount of the implanted n-type dopant is sufficient to convert the corresponding portion of the channel region 11 from p-type doping to n-type doping. For example, the doping concentration in the contact region 12 is 10 18 cm -3 with 10 19 cm -3 between.

[0115] like Fig.11 As can further be seen in FIG. 1 , the depth of the contact region 12 is smaller than the depth of the channel region 11 , wherein the depth is measured along the vertical direction V. Thus, the contact region 12 is formed along the vertical direction V between the top side 10 and the channel region 11 .

[0116] Fig.12 The method position is shown in which a second auxiliary layer 3 (also referred to herein as auxiliary layer 3 for short) is deposited onto the top side 10 of the semiconductor body 1 by means of a conformal deposition method. The auxiliary layer 3 covers the top side 10 in the region of the first section 21, the top side of the second section 22 and the lateral sides 22a of the second section 22. The second auxiliary layer 3 may have a different material than the first auxiliary layer 4. For example, the second auxiliary layer 3 is formed of SiN or SiO2.

[0117] exist Fig.13 In the position shown in , a directional material removal process (e.g. dry etching) is used to remove the second auxiliary layer 3 in the region of the first section 21 and on the top side of the second section 22. Due to the directional method, the remaining part of the second auxiliary layer 3 remains on the lateral side 22a of the second section 22, so that the width of the second section 22 is effectively increased again, wherein the width of the first section 21 is effectively reduced again. The thickness of the remaining part of the second auxiliary layer 3 on the lateral side 22a can be in the same range as the thickness of the first auxiliary layer 4.

[0118] exist Fig.14 In the region of the first section 21 with reduced width, a hole 5 in the form of a trench is etched into the semiconductor body 1. The etchant used for etching is preferably selected such that the etching rate of the semiconductor material of the semiconductor body 1 is greater than the etching rate of the mask material and / or the material of the first auxiliary layer 4 and / or the material of the second auxiliary layer 3.

[0119] The trenches 5 extend from the top side 10 through the contact region 12 and the channel region 11 and are deeper than the channel region 11. The trenches 5 each divide the previously connected contact region 12 and channel region 11 into two contact regions 12 and two channel regions 11, which adjoin the respective trenches 5 at both sides with respect to the first lateral direction Q. By way of example, the depth of the etched trenches 5 is 1 μm or less.

[0120] Fig.15 The method is shown at a position in which an electrically insulating layer 51 is formed at the surface of the trench 5. The electrically insulating layer 51 is formed, for example, by oxidation of the surface of the trench 5. Additionally, a gate electrode 7 is formed in the trench 5.

[0121] exist Fig.16 , the second mask 2 and the remaining parts of the auxiliary layers 3, 4 on the lateral sides 22a of the second section 22 are removed. As a result, the top side 10 of the semiconductor body 1 is exposed in the region between the trenches 5. Between each pair of trenches 5, the top side 10 is partially formed by two contact regions 12, two channel regions 11 and one diode region 13. As a result, the contact regions 12 are embedded in the channel regions 11, so that the contact regions 12 and the channel regions 11 adjoin the trenches 5, but are electrically isolated from the gate electrodes 7 in the trenches 5 by means of the electrical isolation layer 51. The diode region 13 is formed by the drift layer 18 and is therefore doped n-type.

[0122] Thanks to the method described herein, only one lithography step is needed to produce the channel region 11, the contact region 12 and the trench 5. Such a self-aligned process allows very small structures to be produced. The distance between two adjacent trenches 5 measured along the first lateral direction Q is, for example, at most 3 times the depth of the trench 5. For example, the distance is at most 3 μm. The width of each of the contact regions 12 measured along the first lateral direction Q is, for example, at most 1 μm or at most 500 nm.

[0123] Fig.17 Shown in perspective Fig.16 The semiconductor body 1 is shown in FIG. 1 , so that the positions of the trench 5, the contact region 12, the channel region 11, the diode region 13 and the plug region 14 relative to each other are visible. The plug region 14 extends obliquely to the trench 5 and adjoins the top side 10 in the region previously covered by the second section 22 of the mask 2.

[0124] exist Fig.18 , a first main electrode 6 is applied to the top side 10 of the semiconductor body 1 in a position. The main electrode 6 adjoins the semiconductor body 1 in the region between the trenches 5 and is in direct contact with the contact region 12, the channel region 11 and the diode region 13. The first main electrode 6 is formed, for example, of metal. The first main electrode is electrically isolated from the gate electrode 7 by means of an electrical isolation layer 51.

[0125] Fig.19 The finally finished semiconductor device 100 is shown. The semiconductor device 100 is for example a power semiconductor device, such as a power MOSFET. On the bottom side of the semiconductor body 1 opposite to the top side 10, a second main electrode 9 is applied. The first main electrode 6 is a source electrode and the second main electrode 9 is a drain electrode.

[0126] The plug region 14 is used, for example, to electrically contact the channel region 11. Since the plug region 14 has a high doping concentration, an ohmic contact can be formed between the plug region 14 and the first main electrode 6. On the other hand, the plug region 14 is electrically connected to the channel region 11, so that the channel region 11 is finally electrically connected to the first main electrode 6 well.

[0127] During operation, a voltage difference is applied between the first main electrode 6 and the second main electrode 9, which voltage difference is, for example, greater than 1 kV. In forward operation of the MOSFET, the current flowing between the main electrodes 6, 9 is controlled by the gate electrode 7. In the on-mode, electrons are injected from the first main electrode 6 into the contact region 12. From the contact region, the electrons pass through the channel region 11 along the trench 5 down into the drift layer 18, from which the electrons flow to the second main electrode 9. The diode region 13 forms a Schottky diode together with the first main electrode 6, which is blocked in the on-mode.

[0128] The charge carrier flow therefore takes place mainly in the region between the trenches 5 , which is why this region is referred to herein as active region A. With the method described herein, very small structures of the active region A can be produced.

[0129] As stated Figures 1 to 19 The embodiments shown in the present invention represent exemplary embodiments of an improved method for manufacturing a semiconductor device and an improved semiconductor device; therefore, they do not constitute a complete list of all embodiments according to the improved method and the improved semiconductor device. The actual method and device may differ from the embodiments shown in terms of elements, the order of method steps, etc.

[0130] Reference numerals

[0131] 1Semiconductor body

[0132] 2 (Second) Mask

[0133] 3 (Second) Auxiliary Layer

[0134] 4 First / Additional Auxiliary Layer

[0135] 5 holes

[0136] 6 (First) Main Electrode

[0137] 7 Gate electrode

[0138] 8 First / Additional Masks

[0139] 9 Second main electrode

[0140] 10 Top side

[0141] 11 Channel region

[0142] 12 Contact area

[0143] 13 Diode region

[0144] 14 Plug Area

[0145] 18 Drift layer

[0146] 19 Substrate

[0147] 21 First Segment

[0148] 22 Second Section

[0149] 22a The lateral side of the second section 22

[0150] 51 electrical isolation layer

[0151] 81 The first section of mask 8

[0152] 82 The second section of mask 8

[0153] 100 Semiconductor Devices

[0154] Si method steps

[0155] Q First lateral direction

[0156] L Second lateral direction

[0157] V vertical direction

Claims

1. A semiconductor device (100), comprising: - a semiconductor body (1) having a top side (10), wherein - at least one hole (5) extends from the top side (10) into the semiconductor body (1), - the at least one hole (5) delimits an active area (A) of the semiconductor body (1) along a first lateral direction (Q), - the active area (A) comprises at least one channel region (11) of a first conductivity type, and at least one contact region (12) of a second conductivity type, - the at least one channel region (11) and the at least one contact region (12) adjoin the at least one hole (5) along the first lateral direction (Q), - the at least one contact region (12) is embedded in the at least one channel region (11) such that, in a vertical direction perpendicular to the top side (10), the at least one contact region (12) is arranged between the top side (10) and the at least one channel region (11) and such that the at least one contact region (12) adjoins the top side (10), - the width of the active area (17) measured along the first lateral direction (Q) is at most 3 times the depth of the at least one hole (5) measured along the vertical direction (V), - the active area (A) comprises at least one plug region (14) having the first conductivity type and adjoining the top side (10), - the at least one plug region (14) has a higher doping concentration than the at least one channel region (11).

2. The semiconductor device (100) according to claim 1, comprising: - a plurality of channel regions (11) formed in stripe shapes, - a plurality of holes (5) formed as grooves, and - a plurality of plug areas (14) formed in stripe shape, wherein: The plug region (14) extends obliquely to the channel region (11).

3. The semiconductor device (100) according to claim 1 or 2, wherein: - The width of the active area (A) is at most 3 μm.

4. The semiconductor device (100) according to any one of the preceding claims, further comprising: - a main electrode (6) on the top side (10) in the active area (A), wherein - the active area (A) comprises at least one diode zone (13), the at least one diode zone having the second conductivity type, - the at least one diode region (13) adjoins the top side (10), The main electrode (6) adjoins the at least one contact region (12) and the at least one diode region (13) and is in electrical contact with the at least one contact region (12) and the at least one diode region (13).

5. The semiconductor device (100) according to any one of the preceding claims, wherein: - the surface of the at least one hole (5) is at least partially covered by an electrically isolating layer (51), A gate electrode (7) is formed on and / or in the at least one hole (5) and is electrically isolated from the semiconductor body (1) by the isolation layer (51).

6. The semiconductor device (100) according to any one of the preceding claims, wherein: - the semiconductor device (100) is a power semiconductor device, - the semiconductor device (100) comprises a plurality of holes (5), each hole being formed as a trench, wherein the trenches (5) are spaced apart from one another along the first lateral direction (Q) and each trench (5) extends along a second lateral direction (L), - the semiconductor device (100) comprises a plurality of active areas (A), each active area being arranged between a pair of trenches (5), - each active area (A) comprises at least two elongated channel regions (11) extending along said second lateral direction (L), and at least two elongated contact regions (12) extending along said second lateral direction (L), - the channel region (11) and the contact region (12) of each active area (A) each adjoin a trench (5) delimiting said active area (A), The width of the active area (A) is the distance between two trenches (5) delimiting said active area (A) along said first lateral direction (Q).

7. A method for manufacturing a semiconductor device, the method comprising: - providing a semiconductor body (1) having a top side (10), - a mask (2) is applied on the top side (10), wherein - the mask (2) comprises at least one first section (21) and at least one second section (22) laterally adjacent to the at least one first section (21), - the mask (2) is thicker in the at least one second section (22) than in the at least one first section (21), - a channel region (11) of a first conductivity type is formed in the region of the at least one first section (21) and in the semiconductor body (1), wherein: - forming the channel region (11) comprises implanting a first type of dopant into the semiconductor body (1) through the top side (10), - depositing an auxiliary layer (3) on a lateral side (22a) of the at least one second section (22) facing the at least one first section (21), said auxiliary layer increasing the lateral extension of the at least one second section (22) and reducing the lateral extension of the at least one first section (21), - producing a hole (5) in the region of the at least one first section (21) with reduced lateral extension and in the semiconductor body (1), such that the hole (5) extends from the top side (10) through the channel region (11), - before applying the mask (2), applying a further mask (8) to the top side (10) of the semiconductor body (1), - forming at least one plug region (14) of the first conductivity type in the semiconductor body (1) with the aid of the further mask (8), wherein the at least one plug region (14) - adjoining said top side (10), - is formed at least partially in a region of the top side (10) which is subsequently covered by the at least one second section (22) of the mask (2), - the doping concentration in the at least one plug region (14) is greater than the doping concentration in the channel region (11).

8. The method according to claim 7, wherein: - after forming the channel region (11) and before depositing the auxiliary layer (3), depositing a further auxiliary layer (4) on the lateral side (22a) of the at least one second section (22), the further auxiliary layer increasing the lateral extension of the at least one second section (22) and reducing the lateral extension of the at least one first section (21), - after depositing the further auxiliary layer (4) and before depositing the auxiliary layer (3), forming a contact region (12) of a second conductivity type in the semiconductor body (1) in the region of the first section (21), such that the contact region (12) is located between the channel region (11) and the top side (10), wherein the forming of the contact region (12) comprises: implanting a dopant of the second type through the top side (10) into the semiconductor body (1), - The hole (5) is formed through the contact area (12).

9. The method according to claim 7 or 8, wherein: - the auxiliary layer (3) is deposited by a conformal deposition process so that the lateral sides (22a) of the at least one second section (22), the top side of the at least one second section (22) and the area of ​​the first section (21) are covered by the auxiliary layer (3), - Then, a directed material removal process is applied, by which more of the auxiliary layer (3) is removed in the region of the first section (21) and at the top side of the second section (22) than at the lateral sides (22a) of the second section (22).

10. The method according to any one of claims 7 to 9, wherein: - before applying the mask (2), the semiconductor body (1) has the second conductivity type at least at the top side (10), - During the implantation of the first type of dopant, the at least one second section (22) protects the underlying semiconductor body (1) from the influence of the first type of dopant, so that the semiconductor body (1) still has the second conductivity type at the top side (10) in the region of the at least one second section (22).

11. The method according to any one of claims 7 to 10, further comprising: - forming an electrical isolation layer (51) on the surface of the hole (5), - forming a gate electrode (7) on and / or in the at least one hole (5), such that the gate electrode (7) is electrically isolated from the semiconductor body (1) by the electrical isolation layer (51), - removing the mask (2), - forming a main electrode (6) on the top side (10) such that in a region laterally adjacent to the at least one hole (5) the main electrode (6) adjoins and is electrically connected to the semiconductor body (1).

12. A method according to claim 11 insofar as claim 11 is dependent upon claim 10, wherein: The main electrode (6) adjoins at the top side (10) at least one diode region (13) of the semiconductor body (1), the at least one diode region having the second conductivity type.

13. The method according to any one of claims 7 to 12, wherein: - the mask (2) comprises a plurality of stripe-shaped first sections (21) and a plurality of stripe-shaped second sections (22), - forming channel regions (11) and holes (5) in the region of several of the first sections (21), wherein each channel region (11) is formed in a stripe shape and each hole (5) is formed in a groove.

14. The method according to claim 13, wherein: - forming a plurality of plug regions (14), - Each plug area (14) is formed in a stripe shape, The plug region (14) extends obliquely to the channel region (11).

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