Programming power controller via logic device

Abstract

The invention relates to programming a power controller via a logic device. A computing device includes a main printed circuit board (PCB), one or more computing components mounted on the main PCB, a baseboard management controller (BMC) mounted on the main PCB, a power subsystem, and a logic device coupled to the main PCB. The power subsystem includes a power controller having a first logic pin, and the logic device is communicatively connected to the first logic pin. The logic device is configured to program the power controller by placing the power controller in a programming mode and inputting programming information into the power controller via the first logic pin.

Description

[0001] introduction

[0002] Computing devices (such as servers) typically include power subsystems that are configured to convert input power (such as mains AC power or high-voltage DC input power) into one or more different forms suitable for components of electronic devices. Such electrical subsystems typically include a power supply unit (PSU) and one or more voltage regulators (VRs) and other power delivery components. The PSU is typically configured to perform the initial stage of power conversion to provide bulk power to the entire electronic device, and is often provided as a removable unit that is different from the main printed circuit board (PCB) (e.g., motherboard) of the computing system. In contrast, VRs are typically configured to provide regulated power only to a specific component (such as a CPU), and are generally arranged to be physically adjacent to the components they power (such as mounted on the main PCB). For example, in some computer systems, the PSU can convert higher voltage AC or DC input power into one or more lower voltage DC power signals (e.g., 12V DC, 5V DC, and 3.3V DC), and then a group of VRs arranged adjacent to the CPU on the main PCB can convert one of these power signals from the PSU into a regulated low-voltage high-current power signal (e.g., 1.2V) suitable for powering the CPU.

[0003] The power subsystem typically includes multiple power controllers (e.g., microcontrollers, state machines, etc.) that control the operation of the powered components. For example, a PSU often includes at least a primary microcontroller that is part of the primary side of the PSU and controls the functions of the primary side, and a secondary microcontroller that is part of the secondary side of the PSU and controls the functions of the secondary side. In addition, a VR typically also includes a controller that controls its functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Alone or with Figure 1 The present disclosure can be understood from the following detailed description. The accompanying drawings are included to provide a further understanding of the present disclosure, and these drawings are incorporated into and constitute a part of this specification. The accompanying drawings illustrate one or more examples of the present teachings and together with the description explain certain principles and operations. In the drawings:

[0005] Figure 1 is a block diagram illustrating an example computing device.

[0006] Figure 2 is a schematic timing and signal diagram illustrating a first example sequence of events and signals associated with programming a voltage regulator controller.

[0007] Figure 3is a block diagram illustrating a portion of an example computing device in a first state.

[0008] Figure 4 It's a picture. Figure 3 A block diagram of an example computing device of the portion being in a second state.

[0009] Figure 5 It's a picture. Figure 3 The block diagram of the portion of an example computing device is in a third state.

[0010] Figure 6 It's a picture. Figure 3 The block diagram of the portion of an example computing device is in a fourth state.

[0011] Figure 7 is a process flow diagram illustrating an example method.

[0012] Figure 8 is a schematic timing and signal diagram illustrating a second example sequence of events and signals associated with programming a voltage regulator controller. DETAILED DESCRIPTION

[0013] As described above, the power subsystem of a computing device typically includes multiple microcontrollers that control various functions, such as the microcontroller of a PSU and a VR controller. These power controllers are often commodity parts purchased by computing device manufacturers from various suppliers. Typically, the power controller can be initially programmed by the supplier. If it is desired to reprogram or configure the power controller later, such programming is typically performed by the baseboard management controller (BMC) of the main PCB of the computing device via an I2C communication bus (or a similar communication bus). However, there are multiple problems associated with this method of programming the power controller. Therefore, in order to alleviate or solve these problems, a new and improved method for programming a power controller is disclosed herein, which method, in particular, utilizes logic devices and direct logic pin connections rather than BMCs and I2C buses to program the power controller. The following will further describe the problems of programming the power controller using BMCs and I2C buses, as well as various aspects of the new and improved method disclosed herein.

[0014] A first problem associated with using a BMC and an I2C bus to program a power controller is that it is expected that in the future (at least in some cases) manufacturers of computing devices may have less control (or perhaps no control) over the configuration of the BMC used in the computing device. Therefore, if the BMC continues to be used to program the power controller, it can be expected that the manufacturer of the computing device will have less control (or perhaps no control) over the manner in which the power controller is programmed. In some cases, however, the manufacturer of the computing device may desire to retain control over how the power controller is programmed, for example because this may allow the manufacturer to optimize power usage for different system configurations, improve security, or otherwise improve the power controller. Therefore, there is a need for a method of programming a power controller that allows the manufacturer of the computing device to retain control over programming even if they cannot control the configuration of the BMC.

[0015] For example, due to the expected industry shift to the use of modular BMCs, it may occur that the computing device manufacturer has reduced control over the BMC (and therefore reduced control over programming the power controller). Traditionally, the BMC is tightly integrated into the main PCB of the computing device and may be proprietary to the manufacturer of the computing device, so the BMC is generally a known quantity and is directly or indirectly under the control of the manufacturer of the computing device. In contrast, modular BMCs may be less tightly integrated into the main PCB (e.g., they may be removable), more standardized, and potentially interchangeable. Therefore, in the case of a modular BMC system design, there may be BMCs from multiple different sources for the device, and therefore the manufacturer of the computing device may not be able to ensure that the BMC they expect will be the one that is ultimately used. For example, even if the manufacturer initially uses a proprietary BMC in the device, the modular nature of the BMC may allow the original BMC to be later replaced with a different BMC from a different source. Therefore, the manufacturer of the computing device may no longer be able to predict or control which BMC will be used in their computing device, and therefore they may lack control over how the BMC will program / configure the power controller.

[0016] The second problem with relying on the BMC and I2C bus to configure the power controller is that it may make it more difficult and expensive to use power controllers from multiple suppliers, and this is true regardless of whether a traditional BMC design or a modular BMC design is used. Typically, in order to ensure an adequate supply of commodity parts (such as power controllers), manufacturers of computing devices may expect to utilize multiple different suppliers for those parts. However, as discussed in more detail below, if power controllers from different suppliers are to be used, and if the BMC is to configure these power controllers, then in some cases, for each power controller from a different supplier, a circuit board with a different configuration may be required, even if the overall computing device including these power controllers is otherwise the same. This means that the manufacturer of the computing device may need to design and produce multiple circuit boards with different configurations for each model of computing device, which may be expensive. In addition, the design of having multiple different circuit boards for each model of computing device may cause a surge in SKUs, complicate logistics, and generally increase the cost and difficulty of manufacturing. Therefore, a method for programming a power controller is needed to allow the use of power controllers from different suppliers without requiring circuit boards with different configurations to accommodate these power controllers.

[0017] Some reasons why different configurations of circuit boards may be needed when using power controllers from different suppliers and programming the controllers using BMC are as follows. Typically, the BMC communicates with the power controller via an I2C communication bus (or other similar buses), and this bus-based communication typically requires that each device communicating via the bus has (and identifies) an assigned bus address. However, as described above, the power controller is often a commodity part, and in order to ensure the compatibility of these power controllers with a plurality of different systems (these systems may potentially assign different I2C addresses to their power controllers), the manufacturer of the power controller typically will not program it with a single predetermined I2C bus address. Instead, the power controller is configured to learn their assigned I2C bus addresses from the systems in which they are installed. However, because the BMC relies on the I2C bus to communicate with the power controller, and because the I2C communication with the power controller depends on the controller knowing their assigned I2C addresses, the BMC cannot notify the controller of its I2C address. Instead, the circuit board is typically hardwired to indicate a particular bus address to a given power controller by providing a predetermined electrical signal (e.g., a predetermined voltage) having predetermined properties to the power controller, and the power controller is configured to infer its I2C address from the signal (e.g., one voltage indicates a first address, a second voltage indicates a second address, and so on). For example, a main PCB of a computing device may be provided with one or more resistors for each VR controller, and the resistance of these resistors may be carefully selected so that when the electrical signal flows through the resistors to the VR controllers, each VR controller receives a particular voltage indicating its corresponding I2C address. In this way, by appropriately selecting the resistors, the correct I2C address of the VR controller is hard-coded into the system board. However, each power controller vendor may configure their power controller to interpret the electrical signals received from the circuit board in a different manner, for example, a first voltage may be understood by a first vendor's power controller as indicating one address, but may instead be understood by a second vendor's power controller as indicating a different address. Thus, the circuit board may need to provide different electrical signals (e.g., different voltages) to indicate the address depending on which vendor's power controller is used, and because these electrical signals are hardwired into the circuit board, different circuit board configurations may be required for different vendors' power controllers (e.g., different resistor combinations may be required for each vendor).

[0018] A third problem with using a BMC and I2C bus to program the power controller is that configuration changes made in this manner tend to be slow. Typically, when changes to the programming are made through the BMC and I2C bus, and the power controller needs to interrupt its ongoing process to communicate through the I2C bus, interpret and analyze the communications from the I2C bus, and then take action based on the programming, this can take a non-negligible amount of time. Furthermore, in many cases, programmed configuration changes require the power controller to be power cycled after the configuration change in order for the changes to take effect. The latency to make configuration changes and the potential need to power cycle for some changes to take effect can make it impractical to use the BMC and I2C bus to dynamically make configuration changes in real time (such as changes to adjust the operating set points of a device in response to changing conditions)

[0019] The present disclosure provides technical solutions to the above-mentioned problems, which include using a logic device (e.g., a complex programmable logic device (CPLD)) of a main PCB to program the power controller via a direct connection to one or more logic pins of the power controller, rather than using a BMC and an I2C bus (or in addition to) to program the power controller. A logic device (e.g., a CPLD) can be provided to manage logic signals that control the operation of the power controller during use, such as a power sequencing function during startup of the device. By also programming the power controller using a logic device, even if the manufacturer of the computing system does not have control over the BMC used in the computing system, they can retain some control over how to configure the power controller. In addition, because the logic device does not use the I2C bus to communicate with the power controller (unlike the BMC), the logic device can configure the power controllers even if the power controllers from different vendors initially have unknown or incorrect I2C addresses.

[0020] In some examples, the programming performed by the logic device can include configuring the I2C address of the power controller during initial startup. Once the I2C address has been programmed by the logic device, the BMC can thereafter be able to communicate with the power controller via the I2C bus in the usual manner. Therefore, in some examples, the address of the power controller may no longer need to be hardwired into the circuit board, because the logic device can instead directly instruct the controller which address to use. Or, alternatively, the address can still be hardwired into the circuit board, and the logic device can instruct the power controller how to correctly interpret the hardwired electrical signals so that all vendors' controllers will interpret the electrical signals in the same manner (even if the initial programming of the vendor's controller will cause the controllers to interpret the signals differently). In either case, using a logic device to program the power controller can make the same circuit board configuration compatible with power controllers from multiple different vendors, and can avoid the need to provide system boards with different configurations for controllers from different vendors.

[0021] In addition, in some examples, programming of the power controller by the logic device includes a direct signal connection between the logic device and the microcontroller (capable of device register access), and this connection can be very fast compared to the relatively slow communication process via the BMC and the I2C bus. In addition, changes made via this direct communication with device register access generally do not require power cycling before the change can be applied. Therefore, the examples disclosed herein may be more suitable for dynamic changes to the configuration of the power controller. This can facilitate optimization of overall energy performance by reprogramming the power controller to better cope with current conditions. For example, the power controller can be reconfigured to operate with optimized parameters specific to the installed processor. For example, a low-power processor can disable the phase of the VR, reduce the switching frequency of the VR, and optimize the phase threshold to maximize the efficiency of that particular processor SKU.

[0022] The following will refer to Figures 1 to 7 Examples of computing devices and associated methods that implement these methods are described in further detail.

[0023] Figure 1 An example computing device 100 is illustrated. The computing device 100 includes a main printed circuit board (PCB) 110 (sometimes also referred to as a motherboard) and a power supply unit (PSU) 160. The computing device 100 may also include additional components, such as data storage media, expansion cards, cooling devices, or other components familiar to those of ordinary skill in the art and not illustrated herein.

[0024] The main PCB 110 includes one or more CPUs 120 , one or more memory devices 125 , and one or more voltage regulators (VRs) 130 for supplying power to the CPUs 120 . Figure 1 Only one of each of the above components is illustrated to simplify the illustration, but it should be understood that in various examples, any number of each of these components may be mounted on the main PCB 110. In addition, the main PCB 110 includes a BMC 140, an I2C bus 145, and a logic device 150. As will be described in more detail below, the logic device 150 is configured to program one or more power controllers of the computing device 100 according to the example techniques described herein. Each of these components will be described in more detail below.

[0025] As is familiar to those of ordinary skill in the art, CPU 120 includes one or more processors and associated support components. Memory 125 may include volatile or non-volatile memory devices, such as random access memory (RAM), that store instructions that can be executed by CPU 120. In some examples, CPU 120 and memory 125 may be separate modules that are removably mounted to main PCB 110, while in other examples, CPU 120 and memory 125 may be part of the same integrated circuit (e.g., a socket on chip or SoC) that is removably mounted to circuit board 110 or integrated in circuit board 110.

[0026] The voltage regulator 130 is configured to supply regulated power to the CPU 120 (or, in an example including such an SoC, to the SoC including the CPU 120). More specifically, the voltage regulator 130 may include a VR converter 131 and a VR controller 135. The VR converter 131 receives a DC power signal (e.g., pwr_2) from the PSU 160 and, under the control of the VR controller 135, converts the DC power signal into an output DC power signal (e.g., p_cpu) suitable for the CPU 120. For example, pwr_2 may be a large-capacity DC power signal of 12V, 5V, or 3.3V, while p_cpu may have a relatively low voltage (e.g., 1.2V) but relatively tighter regulation (lower voltage fluctuation) and relatively higher current. In some examples, a plurality of VRs 130 are provided for each CPU 120, and the plurality of VRs may be arranged in phase to further improve the power supply to the CPU 120, as is familiar to those of ordinary skill in the art.

[0027] In some examples, the VR converter 131 includes an actively controlled DC-DC converter having a switching regulator (or switch mode power supply) topology. In such examples, the VR converter 131 includes (among other things) one or more switches that are turned on and off at a specific frequency and duty cycle, where the duty cycle determines how much current flows through the VR converter 131. By appropriately controlling the duty cycle, the voltage output by the VR converter 131 can be controlled. Examples of switching regulator topologies that can be used in the VR converter 131 include, but are not limited to, a buck converter, a boost converter, a buck-boost converter, or any other switching regulator topology. Examples of buck converter topologies are as follows: Figure 3 shown and will be described below.

[0028] The signal controlling the VR converter 131 may be generated by a VR controller 135. The VR controller 135 may include a microcontroller configured to determine appropriate parameters for the control signal (e.g., an appropriate duty cycle for the switch), and configured to generate and output the control signal to the VR converter 131. The VR controller 135 may also dynamically adjust the control signal in the face of changing conditions (e.g., a changing load presented by the CPU 120) to ensure that the p_cpu is maintained near a target voltage. For example, the VR controller 135 may sense the voltage of the p_cpu and compare the voltage to the target voltage, and if the p_cpu is different from the target voltage, the VR controller 135 may adjust the control signal (e.g., change the duty cycle) to bring the p_cpu closer to the target voltage. In some examples, the VR controller 135 is an example of a power controller that the logic device 150 may program according to the techniques disclosed herein.

[0029] In some examples, VR converter 131 and VR controller 135 are provided as separate components that together form voltage regulator 130. For example, VR controller 135 may be provided as one integrated circuit, while VR converter 131 is provided as a separate integrated circuit or as a collection of discrete components (e.g., transistors, inductors, capacitors, diodes, etc.). In other examples, VR converter 131 and VR controller 135 may be provided as part of the same integrated circuit.

[0030] For ease of understanding, VR 130 is illustrated as supplying power to CPU 120, but it should be understood that computing device 100 may also include other VRs (not illustrated) for supplying power to other components of computing device 100, such as VRs for supplying power to a graphics processing unit (GPU), VRs for supplying power to a memory (e.g., memory 125), VRs for supplying power to a hardware accelerator, etc. These other VRs may be similar to VR 130, and may include a VR controller similar to VR controller 135. In examples including such other VRs, the VR controllers therein may be additional examples of power controllers that may be programmed by logic device 150 according to the techniques disclosed herein.

[0031] BMC 140 may include a dedicated microcontroller integrated into main PCB 110 that provides and manages an interface between system management software and the hardware of computing device 100. BMC 140 may also sense operating conditions of components of computing device 100, provide alerts to system administrators, manage certain aspects of system security, and provide out-of-band management options for administrators. BMCs are familiar to those of ordinary skill in the art, and therefore BMC 140 is not described in further detail herein.

[0032] The BMC 140 may communicate with other components of the computing device 100, particularly the VR controller 126 and / or the PSU controller 165, via an I2C communication bus 145. Although the acronym "I2C" technically refers to an inter-integrated circuit communication bus / protocol, the term is used more broadly herein to also include any related communication bus / protocol that is based on, compatible with, or a modified version of an inter-integrated circuit, such as: System Management Bus (SMBus), Power Management Bus (PMBus), Intelligent Platform Management Bus (IPMB), Two-Wire Interface (TWI), Two-Wire Serial Interface (TWSI), and Improved Inter-Integrated Circuit (I3C).

[0033] The PSU 160 includes power conversion circuitry to convert input power into one or more output power signals for powering other components of the computing device 100. For example, the PSU 160 can convert AC power or high voltage DC power into low voltage DC signals that can be supplied to the main PCB 110. One or more of these power signals can also be supplied to other components (not shown), such as data storage media. The power signals provided by the PSU 160 can also be referred to as power "rails". Figure 11 and 2. In the example, the power signals provided by PSU 160 include pwr_1 and pwr_2, but in other examples, any number of power signals can be generated by PSU 160, including one, two, three, or more. In some examples, PSU 160 generates a 12V power signal, a 5V power signal, and / or a 3.3V power signal. PSU 160 includes one or more PSU controllers 165, which include a microcontroller that controls the operation of PSU 160. In some examples, these PSU controllers 165 constitute examples of power controllers described herein that logic device 150 can program according to example methods described herein.

[0034] The logic device 150 is a device including one or more logic circuits that are coupled to the main PCB 110 and are configured to send logic signals to the power controller, in particular, to control the overall operation of the power delivery subsystem of the controller. Specifically, the logic device 150 can control the power-on sequence of the computing device 100. In some examples, the logic device 150 includes a complex programmable logic device (CPLD). In other examples, the logic device 150 may include some other form of logic device, such as a collection of discrete logic gates formed in a logic circuit, a programmable logic device (PLD), a field programmable gate array (FPGA), etc. In some examples, the logic device 150 is integrated in the main PCB 110, which means that the logic device 150 is formed in the main PCB 110 and / or is soldered to the main PCB 110, so that the logic device cannot generally be removed from the main PCB 110 without potentially destructive operations such as cutting or desoldering. This is in contrast to being removably mounted to the main PCB 110 (for some examples, this may be the case with the CPU 120, which can be removed by unlocking the retention mechanism).

[0035] The power-on sequence may begin when the device 100 is powered on. After power-on, power is not immediately supplied to all components of the computing device 100. Instead, power is first supplied to the logic device 150 (and other components), and then the logic device 150 may determine whether to supply power to other components (such as the CPU 120), and if so, when to supply power to that component. Specifically, in systems with multiple voltage rails (which includes most computing devices), it may be necessary to turn on these rails in a predetermined order to prevent leakage or damage to the device, and the power sequencing controlled by the logic device 150 ensures that this order is followed. In addition, during the power sequencing, the logic device 150 may check various aspects of the system (e.g., check whether the voltage supplied by the PSU 160 is within specified limits), and if everything is acceptable, the logic device 150 may provide enable signals to the various power controllers that control different parts of the power delivery subsystem (e.g., different voltage rails) in the appropriate sequence described above to enable those devices to begin supplying power to their components. For example, VR controller 135 may be configured to prevent VR converter 131 from converting pwr_2 to output power p_cpu before receiving an enable signal from logic device 150, thereby keeping CPU 120 powered off until logic device 150 determines that it is time to power it on. The different parts of the power delivery subsystem may be provided with their respective enable signals in a specific sequence determined by logic device 150, which is why this is referred to as a power-on sequence or power sequencing. The enable signal provided by logic device 150 may be provided via a logic input pin of the power controller (e.g., Figure 1 The logic input pin 138 in the power controller 130 is provided to a power controller (such as VR controller 135), and the logic input pin is electrically connected to the logic output pin of the logic device 150. In addition to sending an enable signal to the power controller, the logic device 150 may also have various other input or output logic pins connected to the input or output logic pins of the power controller to monitor the status of the power controller and / or control its operation.

[0036] In addition, the logic device 150 further includes power controller programming logic 151. The power controller programming logic 151 includes logic for programming one or more of the power controllers, including logic for performing operations 152 and 153. Operation 152 includes causing the power controller of the computing device 100 to enter a programming mode, and operation 153 includes inputting programming information to the power controller via a logic pin of the power controller. In some examples, the power controller programmed in this manner is the VR controller 135. In some examples, the power controller programmed in this manner is the PSU controller 165. In some examples, the power controller programmed in this manner is another power controller (not shown), such as a VR controller of another VR converter (not shown). In some examples, the logic device 150 can program multiple power controllers (including any combination of the foregoing). To aid understanding, the following description will focus primarily on the example of programming the VR controller 135 by the logic device 150, but it should be understood that the same principles described with respect to programming the VR controller 135 apply mutatis mutandis to programming other power controllers in the device 100 in those examples where the other power controllers are programmed by the logic device 150. Furthermore, the use of the VR controller 135 as an example below should not be misinterpreted as implying that the logic device 150 must program the VR controller 135. Rather, as described above, in various different examples, different power controllers (or different combinations of power controllers) (which may include any combination of one or more of the VR controller 135, the PSU controller 165, or other power controllers) may be programmed by the logic device 150.

[0037] In some examples, placing the power controller in programming mode in operation 152 may include sending a predetermined signal or code to the power controller, which is configured to interpret the predetermined signal or code as a command to enter programming mode, such as: applying a specific voltage to a specific logic pin of the power controller, applying a voltage to a specific logic pin for a predetermined amount of time, pulsing a signal on a specific logic pin continuously for a predetermined number of times, or any other form of signal. In some examples, the power controller may be automatically placed in programming mode in certain circumstances without requiring the logic device 150 to directly send a signal. For example, in some embodiments, whenever the VR controller 135 is powered on but the logic device 150 does not send an enable signal to the VR controller 135, the VR controller 135 may automatically enter programming mode, and thus in such an example, the logic device 150 may place the VR controller 135 in programming mode by not supplying an enable signal after power has been initially supplied. Once programming has been completed, the logic device 150 may then supply an enable signal to resume normal operation.

[0038] As described above, operation 153 includes inputting programming information via a logic pin of the power controller. This logic pin may also be referred to herein as a "first logic pin" (in this context, "first" is merely a label and does not imply any order). For example, Figure 1 VR controller 135 is shown having a first logic pin 136 connected to logic pin 156 of logic device 150, and in some examples, programming information can be sent from pin 156 to pin 136 for input into VR controller 135. Figure 1 , logic pins of VR controller 135 are shown, but logic pins of other power controllers (such as PSU controller 165) are not shown to simplify the drawing, but it should be understood that in some examples, other power controllers (such as PSU controller 165) may also have a "first logic pin" for logic device 150 to input programming information to the power controller. Examples of logic pins that may be part of a power controller (such as VR controller 135) may include an enable pin, a power good pin, a voltage regulator thermal pin, a catastrophic failure pin, an alarm pin, a power alarm pin, an input OK pin, an I2C alarm pin, a presence pin, and an installation pin, and in some examples, one of these pins may be repurposed to be used as the first logic pin 136 in programming mode.

[0039] In some examples, during operation 153, logic device 150 and power controller can operate as a scan chain, and programming information can be shifted to the power controller by using a plurality of logic pins including at least the first logic pin described above. For example, in power mode, logic device 150 can generate a clock signal and apply the clock signal to a second logic pin of the power controller, such as second logic pin 137 of VR controller 135. The clock signal applied to second logic pin 137 can include a series of cyclically repeated values ​​applied to second logic pin 137, such as a cycle of a logic high voltage followed by a logic low voltage followed by a logic high voltage, etc. Then, for each clock cycle (or half cycle) of the clock signal, logic device 150 can supply one bit of programming data to first logic pin 136, where the bit is indicated by a predetermined voltage applied to first logic pin 136 (e.g., a high voltage indicates a logic 1 and a low voltage indicates a logic 0, and vice versa). The power controller (e.g., VR controller 135) can further be configured to monitor the clock signal of the second logic pin 137 when in programming mode, sample the voltage value present on the first logic pin 136 at each clock cycle (or half cycle), and shift the sampled value to an internal storage medium (such as a shift register, flash memory, etc.) for subsequent processing. The power controller can sample (read) the value of the first logic pin 136 at the rising edge, the falling edge, or both the rising edge and the falling edge of the clock signal. In this way, a set of programming information can be serially shifted into the power controller one bit at a time.

[0040] In some examples, multiple logic pins of the power controller can be used in the manner described above to simultaneously shift programming information into the power controller, which can enable multiple bits to be shifted in at once in parallel. For example, if N logic pins (not counting pins for clock signals) are used for programming, then for each clock cycle (or half-cycle), N bits of programming information can be simultaneously (in parallel) shifted into the power controller.

[0041] In some examples, programming the power controller in operation 153 may include setting / assigning an I2C bus address for the power controller. In some examples, programming the power controller in operation 153 may include otherwise changing the configuration of the power controller, such as changing an operating set point (e.g., a target voltage), changing which phases of the multi-phase VR 130 are operational, changing the switching frequency of the VR 130, changing phase thresholds (e.g., to maximize efficiency for a particular processor SKU), or other changes to the configuration of the power controller. In some examples, some changes to the configuration of the power controller may be made dynamically (e.g., substantially in real time) based on changes in conditions.

[0042] Now go to Figures 2 to 7 , an example process of programming a power controller using an example of computing device 100 will be described. In this example, CPLD 250 is used to reprogram VR controller 235 that controls VR converter 231. CPLD 250, VR controller 235, and VR converter 231 are example configurations of logic device 150, VR controller 135, and VR converter 131 described above. In addition, in Figures 2 to 7 In the example, it is assumed that programming occurs at the initial power-up of the device.

[0043] like Figure 2 As shown, at event 201 , the computing system may be powered on, which causes the PSU to begin supplying power (eg, pwr_1 and pwr_2 ) to the CPLD 250 , the VR controller 235 , and the VR converter 231 . Figure 3 The electrical device is illustrated in a first state prior to event 201 (ie, prior to the device being powered on). Thus, in this first state, the CPLD 250 and VR controller 235 are powered off, and the VR converter 231 does not supply power to the CPU. Figure 4 The second state is shown following event 201 (i.e., following device power-up). In this second state, power is supplied from the PSU to the CPLD 250, the VR controller 235, and the VR converter 231 (e.g., Figure 4 ), but no power is output from VR converter 231 to CPU because CPLD 250 has not yet sent an enable signal to VR controller 235 via enb pin, and thus VR controller 235 has not yet supplied control signal CTRL to VR converter 231. For example, in some embodiments, VR converter 231 may include Figure 3 The switch 216 (eg, transistor), inductor 217, capacitor 218, and diode 219 are arranged as shown in detail 235' in FIG. Figure 4 In the state shown, since the control signal CTRL is not asserted, the switch 216 remains in the off (non-conductive) state, and thus no power flows through the power converter 231 in this state even though the input power (pwr_2) is supplied to the VR converter 231.

[0044] Return to Figure 2 In response to the initial power-on, in event 202a, CPLD 250 begins a power sequencing process. As described above, this process may include performing various checks and then, if everything is OK, issuing an enable signal to enable power to be supplied to other components.

[0045] Concurrently with event 202a, in event 202b, the VR controller may automatically enter programming mode. This may occur in this example because the VR controller 235 has been powered on, but has not yet received an enable signal from the CPLD 250.

[0046] As part of the power sequencing process, at event 203, CPLD 250 may determine whether VR controller 235 requires programming. In some examples, CPLD 250 may determine that VR controller 235 requires programming if VR controller 235 does not already have an I2C address programmed therein. If CPLD 250 determines that VR controller 235 does require programming, CPLD 250 may maintain an enable signal (ENB) to keep the VR controller in a programming mode.

[0047] The CPLD 250 may then send the programming information to the VR controller via one or more logic pins of the VR controller. Figure 5 The diagram shows a bit of programming information being transmitted by the CPLD 250 via a first logic pin (at Figures 3 to 6 The third state of the VR controller 235 is supplied to the second logic pin (labeled as "prog" in Figures 3 to 7 The clock signal is asserted (labeled “clk” in FIG. Figure 5 The state shown may be repeated multiple times (e.g., once for each bit of programming information), with the voltage value asserted on the prog pin changing depending on which bit is being transferred. The clock signal asserted on the clk pin may change value between each data transfer (once or twice, depending on whether the data is sampled on the rising edge, the falling edge, or both the rising and falling edges of the clock). Although only one prog pin is shown, in some examples, multiple pins may be used to transfer data simultaneously in parallel. Although the prog pin is shown in Figure 1 to aid understanding, the prog pin is shown in Figure 2 to facilitate understanding. Figures 3 to 6 Although the prog pin is labeled “prog” in the MCU, this does not necessarily mean that the prog pin is dedicated only to programming—in some examples, the prog pin can be dedicated to programming, while in other examples, the prog pin can be used for other functions during normal operation and can be used for programming only in programming mode.

[0048] return Figure 2, at event 204, CPLD 250 determines that programming of VR controller 235 is complete (e.g., all data has been transferred), and therefore CPLD 250 can return to normal power sequencing operations (including transmitting enable signal ENB to VR controller if CPLD 250 deems it appropriate to do so). In response to receiving enable signal ENB, VR controller exits programming mode at event 205 and generates control signal CTRL to cause VR to begin supplying power to CPU. Control signal CTRL can be, for example, applied to VR converter 231 (see Figure 3 ) of the switch 216, which causes the switch 216 to cycle between an on (conductive) state and an off (non-conductive) state. This causes power to flow through the converter 231, thereby supplying power P_cpu having a voltage that depends on the duty cycle of the CTRL signal. Figure 6 A fourth state corresponding to event 206 is illustrated, wherein the enable signal ENB is asserted and thus the control signal CTRL is generated, and the output power p_cpu is supplied.

[0049] Figure 7 An example process is illustrated. This process is one example of how computing device 100 may program a power controller.

[0050] In block 401 , the CPLD receives initial power when the computing device is powered on.

[0051] In block 402 , in response to receiving initial power, the CPLD begins a power-up sequence.

[0052] In block 404, the CPLD determines whether the power controller of the electronic device needs to be programmed. The power controller may need to be programmed because, for example, this is the first time the power controller has been detected and a new I2C address needs to be programmed into it. If the controller needs to be programmed, the process continues down the "yes" branch to block 406. If the controller does not need to be programmed, the process continues down the "no" branch to block 408.

[0053] In block 406, the CPLD may suspend the remainder of the power-up sequence, retain the enable signal from the power controller to be programmed, and begin sending programming information to the power controller via one or more of its logic pins.

[0054] In block 408, once programming is complete, the CPLD may resume or continue with the remainder of the power-on sequence.

[0055] In block 410 , as part of continuing the power-on sequence, the CPLD may send an enable signal to the power controller.

[0056] Now turn to Figure 8 , this article describes another example of programming a power controller. This example is similar to Figure 2 The example of is different in that in this example, programming is performed while the device is in operation, rather than at initial power-up. Figure 8 In FIG. 1 , before programming occurs, the control signal CTRL_1 is supplied to the VR converter, and the VR converter supplies the output power p_cpu to the CPU.

[0057] At event 301, the CPLD determines that the VR controller needs to be programmed (e.g., a configuration parameter needs to be changed). This determination may occur in response to sensor feedback, a sensed event, a change in state, or any other identified condition deemed by the CPLD as necessary to change the configuration of the VR controller. The CPLD then sends a command PROG_start to the VR controller to cause it to enter programming mode.

[0058] In event 302, the VR controller receives the command PROG_start and enters programming mode.

[0059] At event 303, the CPLD begins sending programming information to the VR controller via logic pins therein.

[0060] In event 304, the CPLD determines that programming is complete and sends a command PROG_end to the VR controller to exit programming mode.

[0061] At event 305, the VR controller receives PROG_end and exits programming mode. Upon exiting programming mode, the VR controller applies the configuration changes made during programming. In some cases, applying the configuration changes may cause the control signals output by the VR controller to change (e.g., change their frequency) according to the new configuration settings, such as Figure 8 The control signal changes from CTRL_1 to CTRL_2 as shown in Figure 1. Application configuration changes may also result in changes to the power signal output by the VR converter, as shown in Figure 1. Figure 8 The change from p_cpu to p_cpu* is shown in .

[0062] exist Figure 8 In the sequence shown, the configuration of the power controller is dynamically changed in real time while the computing device is operating. This type of programming can be useful, for example, to dynamically change the configuration of the power controller in response to changing conditions in order to optimize the power efficiency of the power subsystem.

[0063] In the above description, various types of electronic circuits are described. As used herein, "electronic" is intended to be broadly understood to include all types of circuits that utilize electricity, including digital and analog circuits, direct current (DC) and alternating current (AC) circuits, and circuits for converting electricity into another form of energy and circuits for using electricity to perform other functions. In other words, as used herein, there is no distinction between "electronic" circuits and "electrical" circuits.

[0064] It should be understood that both the general description and the detailed description provide examples that are illustrative in nature and are intended to provide an understanding of the present disclosure without limiting the scope of the present disclosure. Various mechanical, compositional, structural, electronic and operational changes may be made without departing from the scope of the present specification and claims. In some instances, well-known circuits, structures and techniques are not shown or described in detail to avoid obscuring the examples. In two or more drawings, the same number represents the same or similar element.

[0065] In addition, unless the context indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. In addition, the terms "comprise", "including", "comprising", etc. indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. Unless explicitly stated otherwise, the components described as coupled may be directly electrically or mechanically coupled, or may be indirectly coupled via one or more intermediate components. Unless the context of the specification indicates otherwise, mathematical and geometric terms do not necessarily have to be used in accordance with their strict definitions, as one of ordinary skill in the art will understand that, for example, substantially similar elements that function in a substantially similar manner can easily fall within the scope of a descriptive term, even if the term also has a strict definition.

[0066] And / or: Occasionally, the phrase "and / or" is used herein in conjunction with a list of items. This phrase is meant to include any combination of the items in the list - from a single item to all items, and any permutations in between. Thus, for example, "A, B, and / or C" means "one of {A}, {B}, {C}, {A, B}, {A, C}, {C, B}, and {A, C, B}."

[0067] Elements and related aspects described in detail with reference to one example may be included in other examples where they are not specifically shown or described when feasible. For example, if an element is described in detail with reference to one example and is not described with reference to a second example, the element may still be claimed to be included in the second example.

[0068] In addition, unless otherwise stated herein or the context implies otherwise, when approximate terms such as "substantially," "approximately," "about," "around," "roughly," and the like are used, this should be understood to mean that mathematical precision is not required, but rather refers to a range of variation that includes but is not strictly limited to the stated value, characteristic, or relationship. In particular, in addition to any ranges (if any) explicitly recited herein, the range of variation implied by the use of such approximate terms includes at least any insignificant variations and those variations that are typical for items of the type in question due to manufacturing tolerances or other tolerances in the relevant art. In any case, unless otherwise indicated, the range of variation may at least include values ​​within ±1% of the recited value, characteristic, or relationship.

[0069] In view of the disclosure herein, further modifications and alternative examples will be apparent to those of ordinary skill in the art. For example, the apparatus and method may include additional components or steps omitted from the diagram and description for operational clarity. Accordingly, this specification is only interpreted as illustrative and is to teach those skilled in the art to perform the general manner of this teaching. It should be understood that the various examples shown and described herein will be considered exemplary. Elements and materials, and the arrangement of these elements and materials may be used to replace those shown and described herein, parts and processes may be reversed, and certain features of this teaching may be utilized independently, all of which will be apparent to those skilled in the art who benefit from the description herein. Without departing from the scope of this teaching and the appended claims, the elements described herein may be changed.

[0070] It is to be understood that the specific examples set forth herein are non-limiting and that modifications in structure, dimensions, materials, and methods may be made without departing from the scope of the present teachings.

[0071] Other examples from this disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the appended claims to be given their broadest breadth, including equivalents under applicable law.

Claims

1. A computing device, comprising: Main printed circuit board (PCB); One or more computing components mounted on the main PCB; a baseboard management controller (BMC) mounted on the main PCB; A power subsystem, the power subsystem comprising a power controller, the power controller comprising a first logic pin; as well as a logic device coupled to the main PCB and communicatively connected to the first logic pin, Wherein, the logic device is configured to program the power controller by placing the power controller in a programming mode and inputting programming information into the power controller via the first logic pin.

2. The computing device of claim 1, in, The power subsystem includes a voltage regulator (VR) mounted to the main PCB, the VR including a VR converter configured to supply power to one of the computing components and a VR controller configured to control the VR converter, and Wherein, the power controller includes the VR controller.

3. The computing device of claim 2, in, The one or more computing components include a central processing unit (CPU), and the VR converter is configured to supply power to the CPU.

4. The computing device of claim 1, in, The logic device is configured to place the power controller into the programming mode by withholding an enable signal from the power controller.

5. The computing device of claim 1, in, The logic device is configured to place the power controller into the programming mode by sending a command to the power controller via a logic pin of the power controller, including the first logic pin or another logic pin of the power controller.

6. The computing device of claim 1, in, The logic device is configured to input the programming information into the power controller by supplying a clock signal to a second logic pin of the power controller and shifting bits of the programming information into the power controller by applying a signal to the first logic pin in synchronization with the clock signal.

7. The computing device of claim 1, in, The logic device is a complex programmable logic device configured to control a power-on sequence of the computing device.

8. The computing device of claim 7, in, The logic device is integrated in the main PCB.

9. The computing device of claim 7, in, The logic device is configured to program the power controller as part of the power-on sequence in response to the computing device being powered on.

10. The computing device of claim 9, in, The computing device further includes a communication bus capable of communicatively coupling the BMC with the power subsystem, and Wherein, programming the power controller through the logic device includes programming a bus address of the power controller.

11. The computing device of claim 1, in, The power subsystem includes a power supply unit (PSU) removably coupled to the main PCB, and Wherein, the power controller is a part of the PSU.

12. The computing device of claim 1, in, The logic device is separate and distinct from the BMC, and the logic device is configured to program the power converter independently of the BMC.

13. The computing device of claim 1, in, The computing device further includes a communication bus capable of communicatively coupling the BMC with the power subsystem, and Wherein programming of the power controller via the logic device is independent of any communications sent via the communication bus.

14. The computing device of claim 1, in, The logic device includes an output logic pin electrically coupled directly to the first logic pin, and the programming information is transferred from the output logic pin to the first logic pin.

15. A method comprising: Providing a main printed circuit board (PCB) and one or more computing components mounted to the main PCB, and a baseboard management controller (BMC) mounted to the main PCB; Providing a power subsystem, the power subsystem comprising a power controller, the power controller comprising a first logic pin; as well as providing a logic device coupled to the main PCB and communicatively connected to the first logic pin; The logic device is configured to program the power controller by placing the power controller in a programming mode and inputting programming information into the power controller via the first logic pin.

16. A method of programming a power controller of a power subsystem of a computing device, the computing device comprising a main printed circuit board (PCB), one or more computing components coupled to the PCB, and a baseboard management controller (BMC) mounted to the PCB, the method comprising: placing the power controller in a programming mode via a logic device coupled to the main PCB; as well as Programming information is input into the power controller by the logic device via a first logic pin of the power controller.

17. The method of claim 16, in, Inputting the programming information into the power controller includes supplying a clock signal from the logic device to a second logic pin of the power controller and shifting bits of the programming information into the power controller by applying a signal from the logic device to the first logic pin in synchronization with the clock signal.

18. The method of claim 16, in, The logic device is a complex programmable logic device configured to control a power-on sequence of the computing device, and Wherein programming of the power controller is performed as part of the power-on sequence in response to the computing device being powered on.

19. The method of claim 16, in, The computing device further includes a communication bus capable of communicatively coupling the BMC with the power subsystem, and Wherein, programming the power controller through the logic device includes programming a bus address of the power controller.

20. The method of claim 16, in, The computing device further includes a communication bus capable of communicatively coupling the BMC with the power subsystem, and Wherein programming of the power controller via the logic device is independent of any communications sent via the communication bus.

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