Data management method, storage device and storage medium

Abstract

The invention discloses a data management method, storage equipment and a storage medium. The data management method comprises the following steps: performing offset processing on a set reading voltage to obtain a plurality of offset voltages; reading data of a plurality of storage units corresponding to a target word line in the target storage block by adopting the offset voltage to obtain read data; performing comparative analysis on the read data and the original data, and determining a target voltage width based on a set read voltage according to an analysis result; and when the target voltage width is smaller than a set voltage width threshold value, moving data of the target storage block. By means of the mode, the reliability of the storage data of the storage block can be judged so as to move the storage data, so that the frequency of pre-replacement is reduced, and the reading performance of a product is improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a data management method, a storage device, and a storage medium. Background Art

[0002] Flash (flash memory) is a non-volatile memory, that is, data will not be lost even if power is off, and it can be erased or written multiple times during operation. NAND Flash memory is a type of Flash memory, which uses a nonlinear macro unit mode internally, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. NAND Flash memory has the advantages of large capacity and fast rewrite speed, and is suitable for storing large amounts of data, so it has been increasingly widely used in the industry. However, due to the large capacity and multiple stacking layers of NAND Flash, the reliability of NAND Flash deteriorates, and the reliability of the current data block cannot be accurately estimated, resulting in frequent pre-replacement in advance when using some NAND Flash, which causes the product to quickly experience frequent speed drops and greatly reduces its service life. How to help the FW firmware correctly identify the reliability of data and thereby reduce the frequency of entering pre-replacement has become an urgent problem to be solved. Summary of the invention

[0003] To solve the above problems, the present application provides a data management method, a storage device and a storage medium, which can determine the reliability of storage block storage data to move the storage data, thereby reducing the frequency of pre-replacement and improving product reading performance.

[0004] A technical solution adopted in the present application is: to provide a data management method, which includes: offsetting a set read voltage to obtain multiple offset voltages; using the offset voltage to read data of multiple storage cells corresponding to a target word line in a target storage block to obtain read data; comparing and analyzing the read data and the original data, and determining a target voltage width based on the set read voltage according to the analysis results; when the target voltage width is less than a set voltage width threshold, moving the data of the target storage block.

[0005] Among them, the read data and the original data are compared and analyzed, and the target voltage width based on the set read voltage is determined according to the analysis result, including: comparing and analyzing the read data and the original data to determine an offset voltage set whose comparative analysis results meet preset conditions; determining the target voltage width according to the offset voltage set.

[0006] Among them, the read data and the original data are compared and analyzed to determine the offset voltage set whose comparison analysis results meet the preset conditions, including: in the process of performing a first direction offset based on the set read voltage, the read data and the original data are compared and analyzed to determine the first offset amount at which the comparison analysis result does not meet the preset conditions for the first time; and in the process of performing a second direction offset based on the set read voltage, the read data and the original data are compared and analyzed to determine the second offset amount at which the comparison analysis result does not meet the preset conditions for the first time; determining the target voltage width according to the offset voltage set, including: determining the target voltage width according to the first offset and the second offset.

[0007] Among them, the read data and the original data are compared and analyzed to determine the offset voltage set whose comparison and analysis results meet the preset conditions, including: comparing the read data corresponding to the target offset voltage with the original data to obtain global error bit data; determining the regional error bit data corresponding to a threshold voltage distribution area according to the global error bit data; when the regional error bit value is less than the set error bit number threshold, determining that the target offset voltage meets the preset conditions, thereby determining the offset voltage set.

[0008] The step of comparing the read data corresponding to the target offset voltage with the original data to obtain global error bit data includes: performing a logical exclusive OR operation on the read data corresponding to the target offset voltage and the original data to obtain global error bit data.

[0009] Among them, determining regional error bit data corresponding to a threshold voltage distribution area based on global error bit data includes: obtaining reference data of each threshold voltage distribution area; comparing original data with reference data to determine regional status data corresponding to each threshold voltage distribution area; determining regional error bit data corresponding to a threshold voltage distribution area based on global error bit data and regional status data.

[0010] Among them, the original data is compared with the reference data to determine the regional status data corresponding to each threshold voltage distribution area, including: when the target bit of the original data is the same as the reference data of the target threshold voltage distribution area, the target bit of the regional status data corresponding to the target threshold voltage distribution area is determined to be bit 1 and the remaining bits are bit 0.

[0011] Among them, determining the regional error bit data corresponding to a threshold voltage distribution area according to the global error bit data and the regional status data includes: performing a logical AND operation on the global error bit data and the regional status data corresponding to a threshold voltage distribution area to determine the regional error bit data corresponding to the corresponding threshold voltage distribution area.

[0012] Another technical solution adopted in the present application is: a storage device, which includes: a memory, the memory includes multiple storage blocks, the storage block includes multiple word lines, and each word line corresponds to multiple storage cells; a processor, connected to the memory, the processor is used to execute the above-mentioned data management method to manage the data stored in the memory.

[0013] Another technical solution adopted by the present application is: a computer-readable storage medium, in which program data is stored, and the program data implements the above-mentioned data management method when executed by a processor.

[0014] The present application provides a data management method, a storage device and a storage medium, the data management method comprising: offsetting a set read voltage to obtain a plurality of offset voltages; using the offset voltage to read the data of a plurality of storage cells corresponding to a target word line in a target storage block to obtain read data; comparing and analyzing the read data and the original data, and determining a target voltage width based on the set read voltage according to the analysis result; when the target voltage width is less than the set voltage width threshold, the data of the target storage block is moved. In the above manner, the target voltage width is determined by using logical operations and the adjustment of the offset step lengths in the first direction and the second direction based on the set read voltage, and then by judging the size of the target voltage width and the set voltage width threshold, the reliability of the storage block data can be accurately evaluated, when the target voltage width is greater than the set voltage width threshold, the data of the target storage block is not moved; when the target voltage width is less than the set voltage width threshold, the data of the target storage block is moved, thereby reducing the frequency of pre-replacement and improving the product reading performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0016] Figure 1 It is a flowchart of an embodiment of a data management method provided by the present application;

[0017] Figure 2 is a threshold voltage distribution diagram of a two-layer unit flash memory provided by the present application;

[0018] Figure 3 It is a flowchart of an embodiment of determining a first offset and a second offset in a data management method provided by the present application;

[0019] Figure 4is a threshold voltage distribution diagram of a three-layer cell flash memory provided by the present application;

[0020] Figure 5 is a structural schematic diagram of an embodiment of a storage device provided by the present application;

[0021] Figure 6 It is a structural schematic diagram of an embodiment of a computer-readable storage medium provided by the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0023] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0024] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0025] See also Figure 1 , Figure 1 : is a flow chart of an embodiment of a data management method provided by the present application, the data management method comprising:

[0026] Step 11: Perform an offset process on the set read voltage to obtain a plurality of offset voltages.

[0027] Among them, for NAND flash memory, according to the amount of data stored in a storage unit, NAND flash memory can be divided into four types: single-level cell flash memory (SLC), two-level cell flash memory (MLC), three-level cell flash memory (TLC) and four-level cell flash memory (QLC), which are 1 bit / cell, 2 bit / cell, 3 bit / cell and 4 bit / cell respectively. Among them, the threshold voltage distribution VT distribution is usually used to characterize the characteristics of NAND flash memory, with the horizontal axis being the voltage value and the vertical axis being the number of cells with a certain voltage value of Vt. The threshold voltage distribution generally refers to the distribution of all storage cell voltages on a word line combined, which is similar to the normal distribution.

[0028] Optionally, in one embodiment, the two-layer cell flash memory divides the electron capture states in the floating gate into four types, which are converted into binary 11, 01, 00, and 10. Figure 2 As shown, Figure 2 This is the threshold voltage distribution diagram of the two-layer unit flash memory provided by the present application. The two-layer unit flash memory needs to be read twice to determine the Vt value of all cells. First, read Vrd2 to determine the "0" and "1" of the Lower Page; then read Vrd1 and Vrd3 to determine the "0" and "1" of the Upper Page, where Vrd is the set read voltage, and there are 3 set read voltages in the two-layer unit flash memory.

[0029] In one embodiment, the offset processing performed on the set read voltage may be performed by using a set offset step size to perform a corresponding first direction offset or a second direction offset on the set read voltage.

[0030] Optionally, the value of the offset step can be preset, and each time the read voltage is set to offset the first direction or the second direction by one unit, that is, each time the read voltage is set to offset the first direction or the second direction by one unit. Δ X n Optionally, the read voltage Vrd is set to shift the read voltage in the first direction or the second direction by one unit, and the shift step is Δ X1, get the first offset voltage Vt1, the second first direction offset or second direction offset step length is two units, then the offset step length is Δ X2, the second offset voltage Vt2 is obtained, the nth first direction offset or second direction offset step length is n units, then the offset step length is Δ X n , get the nth offset voltage Vt n Among them, the nth offset voltage Vt n The corresponding maximum offset step length in the first direction or the maximum offset step length in the second direction is smaller than the error bit number threshold.

[0031] The error bit number threshold is used to limit the maximum offset step length in the first direction and the maximum offset step length in the second direction in the threshold voltage distribution. Therefore, different NAND flash memories correspond to different error bit number thresholds.

[0032] Optionally, each first direction offset or second direction offset step is Δ X1, Δ X2, ΔX n It can be a geometric sequence or an arithmetic sequence, etc., and there is no limitation here.

[0033] Optionally, the first offset voltage Vt1, the second offset voltage Vt2, and the nth offset voltage Vt n A set of offset voltages can be formed.

[0034] Step 12: Using an offset voltage to read data of a plurality of storage cells corresponding to a target word line in a target storage block to obtain read data.

[0035] Optionally, selective reading only requires calculating a plurality of storage cell data corresponding to a few specific word lines in the storage block to obtain read data.

[0036] Step 13: Compare and analyze the read data and the original data, and determine the target voltage width based on the set read voltage according to the analysis result.

[0037] The target voltage width is the sum of the maximum offset step in the first direction and the maximum offset step in the second direction, which is equivalent to the target voltage width being the sum of the first offset and the second offset. The first offset corresponds to the offset voltage based on the maximum offset step in the first direction of the set read voltage, and the second offset corresponds to the offset voltage based on the maximum offset step in the second direction of the set read voltage.

[0038] Specifically, by continuously adjusting the offset step length in the first direction and the offset step length in the second direction, the corresponding offset voltage reads the data of multiple storage cells corresponding to the target word line in the target storage block to obtain the read data, and compares and analyzes the original data until the first offset and the second offset are determined. Figure 3 As shown, Figure 3 This is a flow chart of an embodiment of determining the first offset and the second offset in the data management method provided by the present application, which specifically includes the following steps:

[0039] Step 31: Compare the read data corresponding to the target offset voltage with the original data to obtain global error bit count (Fail Bit Count, FBC).

[0040] The read data and the original data are subjected to a logical exclusive OR (XOR) operation to obtain global error bit data. Specifically, the logical exclusive OR operation is for two binary numbers involved in the operation. If the two corresponding values ​​are different, the result of the bit is 1, otherwise it is 0, that is, 0^0=0, 0^1=1, 1^0=1, 1^1=0.

[0041] Optionally, the read data and the original data may be octal numbers, decimal numbers, or hexadecimal numbers, which are not limited here.

[0042] It can be understood that when performing a logical XOR operation, may be first converted into a binary number and then the logical operation is performed.

[0043] Step 32: Determine regional error bit data (Level Fail Bit Count, Level FBC) corresponding to a threshold voltage distribution region according to the global error bit data.

[0044] Among them, first determine the voltage state value in each threshold voltage distribution area (such as a two-layer unit flash memory, the voltage state value is 11, 01, 00, 10), and then determine the regional state data (LevelMask) corresponding to each threshold voltage distribution area. Specifically, determine the voltage state value in each area in the threshold voltage distribution area, and number each threshold voltage distribution area. Optionally, each threshold voltage distribution area is numbered from left to right and named as regional state data Ln, where the total number between L1 and Ln is equal to the total number of threshold voltage distribution areas.

[0045] Furthermore, the voltage state value in the threshold voltage distribution area corresponding to the target area state data is compared with the target bit of the original data. When the voltage state value of the target threshold voltage distribution area is the same as the target bit of the original data, the target bit of the target area state data is determined to be bit 1, and the remaining bits are bit 0, wherein the specific numerical length of the area state data is the same as the length of the original data.

[0046] Further, the obtained global error bit data and the regional status data are logically ANDed to obtain regional error bit data, and then the regional error bit data is converted into a regional error bit value. Specifically, the binary regional error bit data obtained by the logical operation is counted to determine the number of binary digital "1"s to determine the regional error bit value.

[0047] Among them, the logical AND operation is that the binary values ​​of the two numbers are 1 at the same time, the result is 1, otherwise it is 0, that is, 0&0=0, 0&1=0, 1&1=1.

[0048] In one embodiment, a three-layer cell flash memory is the most common flash memory particle currently, and is widely used. Three information bits can be stored in each storage cell, and the voltage has eight variations from 111 to 101, that is, there are eight threshold voltage distribution regions, such as Figure 4 As shown, Figure 4 This is a threshold voltage region distribution diagram of the three-layer unit flash memory provided by the present application. It can be understood that the order of reading data in the three-layer unit flash memory is to read Vrd1 and Vrd5 first, and determine the "0" and "1" of the Lower Page; then read Vrd2, Vrd4 and Vrd6, and determine the "0" and "1" of the Middle Page; then read Vrd3 and Vrd7, and determine the "0" and "1" of the Upper Page. The voltage state values ​​in each region of the threshold voltage distribution are 111, 110, 100, 000, 010, 011, 001, 101 from left to right, and the corresponding regional state data are numbered from left to right as L0, L1, L2, L3, L4, L5, L6, L7.

[0049] Optionally, in one embodiment, the original data is respectively Upper Page data 0x8D converted into binary 10001101, Middle Page data 0x9E converted into binary 10011110, and Lower Page data 0xB9 converted into binary 10111001. By combining the original data and the voltage state value in each threshold voltage distribution region, the regional state data can be determined, as shown in the following table:

[0050] Upper Page Date 1 0 0 0 1 1 0 1 Middle Page Date 1 0 0 1 1 1 1 0 Lower Page Date 1 0 1 1 1 0 0 1 Area status data L0 1 0 0 0 1 0 0 0 Regional status data L1 0 0 0 0 0 1 0 0 Regional status data L2 0 0 0 0 0 0 0 0 Regional status data L3 0 1 0 0 0 0 0 0 Regional status data L4 0 0 0 0 0 0 1 0 Regional status data L5 0 0 0 1 0 0 0 0 Regional status data L6 0 0 1 0 0 0 0 0 Regional status data L7 0 0 0 0 0 0 0 1

[0051] Step 33: When the regional error bit value is less than the set error bit number threshold, it is determined that the target offset voltage meets the preset condition, thereby determining an offset voltage set, and determining the target voltage width according to the offset voltage set.

[0052] When the target offset voltage satisfies the regional error bit value less than the set error bit number threshold, the first direction offset step or the second direction offset step corresponding to the target offset voltage is determined, and then the set read voltage is increased by an offset step by the first direction offset step or the second direction offset step to obtain the target offset voltage, so that a plurality of target offset voltages that meet the preset conditions can be formed into an offset voltage set. Each target offset voltage corresponds to a different first direction offset step or a second direction offset step, that is, corresponds to a different first offset value or a second offset value.

[0053] Optionally, in one embodiment, the maximum offset step length in the first direction is determined as the first offset in the offset voltage set that meets the preset condition, and the maximum offset step length in the second direction is determined as the second offset. Then, the target voltage width is determined according to the first offset and the second offset.

[0054] Optionally, in one embodiment, the maximum offset step in the first direction and the maximum offset step in the second direction are determined in the offset voltage set that meets the preset conditions. First, the maximum offset step in the first direction is offset again to obtain the target offset voltage. For the specific implementation process, please refer to the description of the above-mentioned embodiment, which will not be repeated here. The target offset voltage is made to fail to satisfy the regional error bit value less than the set error bit number threshold for the first time, and the first offset is obtained. The maximum offset step in the second direction is offset again to obtain the target offset voltage. The same method is used to make the target offset voltage fail to satisfy the regional error bit value less than the set error bit number threshold for the first time, and the second offset is obtained. Then, the target voltage width is determined based on the first offset and the second offset.

[0055] Step 14: When the target voltage width is less than the set voltage width threshold, the data of the target storage block is moved.

[0056] The voltage width threshold is set based on the NAND flash memory big data model analysis. Therefore, a NAND flash memory usually corresponds to a set voltage width threshold.

[0057] When the target voltage width is less than the set voltage width threshold, the data of the target storage block is moved, that is, the data of the target storage block is pre-replaced. When the target voltage width is greater than the set voltage width threshold, the data of the target storage block is not moved.

[0058] In one embodiment, when the error probability of the threshold voltage distribution in the NAND flash memory increases and multiple errors occur, one of the errors can be selected to determine the regional status data corresponding to the current error, thereby determining the target voltage width, and further determining whether the target block data in the NAND flash memory is moved.

[0059] Different from the prior art, a data management method provided by the embodiment of the present disclosure includes: offset processing the set read voltage to obtain multiple offset voltages; using the offset voltage to read the data of multiple storage cells corresponding to the target word line in the target storage block to obtain the read data; comparing and analyzing the read data and the original data, and determining the target voltage width based on the set read voltage according to the analysis result; when the target voltage width is less than the set voltage width threshold, the data of the target storage block is moved. In the above manner, the target voltage width is determined by using logical operations and the adjustment of the offset step length in the first direction and the second direction based on the set read voltage, and then by judging the size of the target voltage width and the set voltage width threshold, the reliability of the storage block data can be accurately evaluated. When the target voltage width is greater than the set voltage width threshold, the data of the target storage block is not moved; when the target voltage width is less than the set voltage width threshold, the data of the target storage block is moved, thereby reducing the frequency of pre-replacement and improving the product reading performance.

[0060] See also Figure 5 , Figure 5 It is a structural schematic diagram of an embodiment of a storage device provided by the present application, wherein the storage device 51 includes a memory 511 and a processor 512 connected to each other, wherein the memory 511 includes multiple storage blocks, each storage block includes multiple word lines, each word line corresponds to multiple storage cells, and the processor 512 is used to execute program data to implement the following method: offset processing is performed on a set read voltage to obtain multiple offset voltages; the offset voltage is used to read the data of multiple storage cells corresponding to the target word line in the target storage block to obtain read data; the read data and the original data are compared and analyzed, and a target voltage width based on the set read voltage is determined according to the analysis result; when the target voltage width is less than the set voltage width threshold, the data of the target storage block is moved.

[0061] Optionally, the storage device 51 in the embodiment of the present application can be a personal computer, a tablet computer, a mobile phone, a server, etc., which is not limited here.

[0062] See also Figure 6 , Figure 6 It is a structural diagram of an embodiment of a computer-readable storage medium provided by the present application, wherein program data 62 is stored in the computer-readable storage medium 61, and the program data 62, when executed by the processor, is used to implement the following method: offset processing is performed on the set read voltage to obtain multiple offset voltages; the offset voltage is used to read the data of multiple storage cells corresponding to the target word line in the target storage block to obtain read data; the read data and the original data are compared and analyzed, and the target voltage width based on the set read voltage is determined according to the analysis result; when the target voltage width is less than the set voltage width threshold, the data of the target storage block is moved.

[0063] Among them, the processor in the above embodiment can also be called CPU (Central Processing Unit). The processor may be an integrated circuit chip with signal processing capabilities. The processor can also be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, 15ASIC), a field-programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. In addition, the processor can be implemented by multiple integrated circuit chips.

[0064] Among them, the memory or computer-readable storage medium in the above embodiments can be a medium that can store program data, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or it can also be a server that stores the program data. The server can send the stored program data to other devices for execution, or it can also execute the stored program data by itself.

[0065] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0066] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0067] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0068] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A data management method, applied to a storage device, characterized in that: The data management method comprises: performing an offset process on the set read voltage to obtain a plurality of offset voltages; Using the offset voltage to read data of a plurality of storage cells corresponding to a target word line in a target storage block to obtain read data; Comparing and analyzing the read data and the original data, and determining a target voltage width based on the set read voltage according to the analysis result; When the target voltage width is smaller than a set voltage width threshold, data of the target storage block is moved.

2. The data management method according to claim 1, characterized in that: The comparing and analyzing the read data and the original data, and determining the target voltage width based on the set read voltage according to the analysis result, includes: Comparing and analyzing the read data with the original data to determine a set of offset voltages whose comparative analysis results meet preset conditions; A target voltage width is determined according to the offset voltage set.

3. The data management method according to claim 2, characterized in that: The comparing and analyzing the read data with the original data to determine a set of offset voltages whose comparison and analysis results meet preset conditions includes: In the process of performing the first direction shift based on the set read voltage, the read data and the original data are compared and analyzed to determine a first shift amount by which the comparison and analysis result does not satisfy the preset condition for the first time; and In the process of performing the second direction shift based on the set read voltage, the read data and the original data are compared and analyzed to determine a second shift amount by which the comparison and analysis result does not satisfy the preset condition for the first time; The determining the target voltage width according to the offset voltage set comprises: A target voltage width is determined according to the first offset and the second offset.

4. The data management method according to claim 2, characterized in that: The comparing and analyzing the read data with the original data to determine a set of offset voltages whose comparison and analysis results meet preset conditions includes: Comparing the read data corresponding to the target offset voltage with the original data to obtain global error bit data; Determine regional error bit data corresponding to a threshold voltage distribution region according to the global error bit data; When the regional error bit value is less than the set error bit number threshold, it is determined that the target offset voltage meets a preset condition, thereby determining an offset voltage set.

5. The data management method according to claim 4, characterized in that: The comparing the read data corresponding to the target offset voltage with the original data to obtain global error bit data includes: A logical exclusive OR operation is performed on the read data corresponding to the target offset voltage and the original data to obtain global error bit data.

6. The data management method according to claim 4, characterized in that: The determining of regional error bit data corresponding to a threshold voltage distribution region according to the global error bit data includes: Acquire reference data of each threshold voltage distribution region; Comparing the original data with the reference data to determine the region state data corresponding to each threshold voltage distribution region; Regional error bit data corresponding to a threshold voltage distribution region is determined according to the global error bit data and the regional status data.

7. The data management method according to claim 6, characterized in that: The comparing the original data with the reference data to determine the region state data corresponding to each threshold voltage distribution region includes: When the target bit of the original data is the same as the reference data of the target threshold voltage distribution region, it is determined that the target bit of the region status data corresponding to the target threshold voltage distribution region is bit 1 and the remaining bits are bit 0.

8. The data management method according to claim 6, characterized in that: The step of determining regional error bit data corresponding to a threshold voltage distribution region according to the global error bit data and the regional status data includes: A logic AND operation is performed on the global error bit data and the regional state data corresponding to a threshold voltage distribution region to determine the regional error bit data corresponding to the corresponding threshold voltage distribution region.

9. A storage device, characterized in that: The storage device comprises: A memory, wherein the memory includes a plurality of memory blocks, the memory blocks include a plurality of word lines, and each of the word lines corresponds to a plurality of memory cells; A processor is connected to the memory, and the processor is used to execute the method according to any one of claims 1 to 8 to manage the data stored in the memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program data, and when the program data is executed by a processor, it is used to implement the method according to any one of claims 1 to 8.

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