Memory management methods and storage devices

Abstract

This invention provides a memory management method and a memory device. The method includes: detecting a usage imbalance event for a first operating mode; based on the usage imbalance event, and if the counting information meets preset conditions, performing a first type of cross-regional fetch operation to extract a third entity unit from a third type of idle entity unit, and using the third entity unit based on the first operating mode; updating the counting information based on the first type of cross-regional fetch operation; and if the counting information does not meet the preset conditions, prohibiting the execution of the first type of cross-regional fetch operation. This improves the performance and stability of the memory device.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] In recent years, with the rapid advancement of electronic product technology, consumers have increasingly higher demands for the experience of electronic storage products, and the market demand for faster and more convenient storage solutions is also growing. NAND flash memory (FLASH) has demonstrated outstanding advantages in mobile applications such as mobile phones and smart sensing devices due to its characteristics of data non-volatility, low power consumption, compact design, no moving parts, and fast read and write speeds.

[0003] With the rapid evolution of flash memory technology, NAND flash memory has transitioned from two-dimensional (2D) to three-dimensional (3D), and in terms of storage cells, it has gradually evolved from single-layer cell (SLC) to three-layer (TLC) and even four-layer (QLC) storage cells. This series of technological innovations has greatly improved the storage density of NAND flash memory while reducing the cost per unit capacity. However, as the thickness of the oxide layer inside flash memory continues to decrease, the impact of erase and write operations on the storage medium becomes more significant, thus affecting the durability and reliability of flash memory.

[0004] Therefore, effectively managing NAND flash memory has become one of the core issues of concern for engineers in the industry. Optimizing management strategies not only helps extend the lifespan of flash memory but also further improves the overall performance and stability of the system, ensuring users receive a smoother and more reliable user experience. Summary of the Invention

[0005] This invention provides a memory management method and a storage device that can improve the performance and stability of the storage device.

[0006] Embodiments of the present invention provide a memory management method for a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: extracting a first physical unit from a first type of idle physical unit from the plurality of physical units, and using the first physical unit based on a first operating mode; extracting a second physical unit from a second type of idle physical unit from the plurality of physical units, and using the second physical unit based on a second operating mode; detecting a usage imbalance event for the first operating mode; and, based on the usage imbalance event, performing a first type of cross-region extraction operation to extract a third physical unit from a third type of idle physical unit from the plurality of physical units, and using the third physical unit based on the first operating mode, if the count information does not meet the preset conditions; updating the count information based on the first type of cross-region extraction operation; and prohibiting the execution of the first type of cross-region extraction operation if the count information does not meet the preset conditions.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is used to: extract a first physical unit from a first type of idle physical unit among the plurality of physical units, and use the first physical unit based on a first operating mode; extract a second physical unit from a second type of idle physical unit among the plurality of physical units, and use the second physical unit based on a second operating mode; detect a usage imbalance event for the first operating mode; and, based on the usage imbalance event, if the counting information meets a preset condition, perform a first type of cross-region extraction operation to extract a third physical unit from a third type of idle physical unit among the plurality of physical units, and use the third physical unit based on the first operating mode; update the counting information based on the first type of cross-region extraction operation; and if the counting information does not meet the preset condition, prohibit the execution of the first type of cross-region extraction operation.

[0008] Based on the above, the first entity unit can be extracted from the first type of idle entity units and used based on the first operating mode. The second entity unit can be extracted from the second type of idle entity units and used based on the second operating mode. Upon detecting a usage imbalance event for the first operating mode, a first type of cross-region extraction operation can be executed to extract from the third type of idle entity units and use based on the first operating mode, provided that the counting information meets preset conditions. The counting information can be updated according to the first type of cross-region extraction operation. Furthermore, if the counting information does not meet the preset conditions, the first type of cross-region unit extraction operation can be prohibited. This effectively improves the performance and stability of the storage device. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of the first type of cross-regional extraction operation and the first type of cross-regional return operation according to an embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram illustrating the second type of cross-regional extraction operation and the second type of cross-regional return operation according to an embodiment of the present invention;

[0014] Figure 6 This is a flowchart illustrating a memory management method according to an embodiment of the present invention;

[0015] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0017] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0018] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 via connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0019] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0020] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0021] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0022] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0026] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B) and 302(1) to 302(E). Each physical unit includes multiple storage cells for non-volatile storage of data.

[0027] In one embodiment, an entity unit may include one or more entity erasure units. Furthermore, an entity unit may include multiple sub-entity units. For example, a sub-entity unit may include one or more entity programming units.

[0028] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be considered as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0030] In one embodiment, a physical erase unit may include multiple physical programmable units. The multiple physical programmable units in a physical erase unit can be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to the multiple physical programmable units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programmable units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit can be considered as a physical block.

[0031] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1) to 301(A), 302(1) to 302(C), 301(A+1) to 301(B), 302(C+1) to 302(D), and 302(D+1) to 302(E) with data area (also referred to as first data area) 31, data area (also referred to as second data area) 32, idle area (also referred to as first idle area) 33, idle area (also referred to as second idle area) 34, and idle area (also referred to as third idle area) 35, respectively. Entity units 301(1) to 301(A) and 302(1) to 302(C) in data areas 31 and 32 all store data (also referred to as user data) from host system 11. For example, any entity unit in data areas 31 and 32 can store valid data and / or invalid data. In addition, the entity units 301(A+1) to 301(B), 302(C+1) to 302(D) and 302(D+1) to 302(E) in the idle areas 33 to 35 do not store any data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, this physical unit can be associated with one of the free zones 33-35. Furthermore, physical units in free zones 33-35 can be erased to clear the data in those physical units. In one embodiment, physical units in free zones 33-35 are also referred to as idle physical units. In one embodiment, free zones 33-35 are also referred to as a free pool.

[0033] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle areas 33-35 and instruct the memory module 122 to store the data into the selected physical unit. After the data is stored into this physical unit, this physical unit can be associated with the data area 31 or 32.

[0034] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 310(1) to 310(F) to map physical units (i.e., physical units 301(1) to 301(A) and 302(1) to 302(C)) in data areas 31 and 32. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table).

[0037] In one embodiment, entity units 301(1) to 301(B) belong to the first type of entity units, while entity units 302(1) to 302(E) belong to the second type of entity units. In one embodiment, entity units 301(1) to 301(A) in data area 31 are also referred to as the first type of data entity units, and entity units 301(A+1) to 301(B) in idle area 33 are also referred to as the first type of idle entity units. In one embodiment, entity units 302(1) to 302(C) in data area 32 are also referred to as the second type of data entity units, and entity units 302(C+1) to 301(D) in idle area 34 are also referred to as the second type of idle entity units. In one embodiment, entity units 302(D+1) to 301(E) in idle area 35 are also referred to as the third type of idle entity units.

[0038] In one embodiment, the total number of entity units 301(1) to 301(B) may account for 5% to 10% of the total number of entity units in memory module 122. In one embodiment, the total number of entity units 302(1) to 302(D) may account for 80% to 90% of the total number of entity units in memory module 122. In one embodiment, the total number of entity units 302(D+1) to 302(E) may account for 5% to 10% of the total number of entity units in memory module 122. In one embodiment, the total number of entity units of each type in memory module 122 may be adjusted according to practical needs, and the present invention does not impose any limitations.

[0039] In one embodiment, the memory control circuit 23 may perform a fetch operation (also referred to as a first type of non-cross-area fetch operation) to fetch at least one entity unit (also referred to as a first entity unit) from the first type of idle entity units (i.e., entity units 301(A+1) to 301(B) in the idle area 33). The memory control circuit 23 may then use (e.g., operate) the first entity unit based on an operating mode (also referred to as a first operating mode). For example, the memory control circuit 23 may instruct the memory module 122 to program the first entity unit based on the first operating mode to store data (also referred to as first data) in the first entity unit. Simultaneously, the first entity unit used to store the first data may be associated with the data area 31. In response to the first entity unit being associated with the data area 31, the total number of entity units belonging to the data area 31 (i.e., first type of data entity units) increases, and the total number of entity units belonging to the idle area 33 (i.e., first type of idle entity units) decreases accordingly.

[0040] In one embodiment, the memory control circuit 23 can also perform a return operation (also known as a first type of non-cross-area return operation) to return the first entity unit from the data area 31 to the idle area 33. For example, when the data stored in the first entity unit (i.e., the first data) does not contain valid data, the memory control circuit 23 can reassociate the first entity unit to the idle area 33 through the first type of non-cross-area return operation. In response to returning (i.e., reassociating) the first entity unit to the idle area 33, the total number of entity units belonging to the data area 31 (i.e., the first type of data entity units) will decrease, while the total number of entity units belonging to the idle area 33 (i.e., the first type of idle entity units) will increase accordingly.

[0041] In one embodiment, the memory control circuit 23 may perform another fetch operation (also referred to as a second type of non-cross-area fetch operation) to fetch at least one entity unit (also referred to as a second entity unit) from the second type of idle entity units (i.e., entity units 302(C+1) to 302(D) in the idle area 34). The memory control circuit 23 may then use (e.g., operate) the second entity unit based on another operating mode (also referred to as a second operating mode). For example, the memory control circuit 23 may instruct the memory module 122 to program the second entity unit based on the second operating mode to store data (also referred to as second data) in the second entity unit. Simultaneously, the second entity unit used to store the second data may be associated with the data area 32. In response to the second entity unit being associated with the data area 32, the total number of entity units belonging to the data area 32 (i.e., second type of data entity units) increases, while the total number of entity units belonging to the idle area 34 (i.e., second type of idle entity units) decreases accordingly.

[0042] In one embodiment, the memory control circuit 23 may also perform another return operation (also known as a second type of non-cross-area return operation) to return the second entity unit from the data area 32 to the idle area 34. For example, when the data stored in the second entity unit (i.e., the second data) does not contain valid data, the memory control circuit 23 can reassociate the second entity unit to the idle area 34 through the second type of non-cross-area return operation. In response to returning (i.e., reassociating) the second entity unit to the idle area 34, the total number of entity units belonging to the data area 32 (i.e., the second type of data entity units) will decrease, while the total number of entity units belonging to the idle area 34 (i.e., the second type of idle entity units) will increase accordingly.

[0043] In one embodiment, after operating (e.g., programming) an entity unit based on a first operating mode, a storage unit within that entity unit may store a certain number (also referred to as the first quantity) of bit data. Furthermore, after operating (e.g., programming) an entity unit based on a second operating mode, a storage unit within that entity unit may store another number (also referred to as the second quantity) of bit data. The first quantity may be less than the second quantity. For example, the first quantity may be "1", while the second quantity may be "2", "3", "4", or other values ​​greater than "1".

[0044] In one embodiment, the first operating mode may include SLC mode or virtual SLC mode. Furthermore, the second operating mode may be one of MLC mode, TLC mode, or QLC mode. It should be noted that the first and second operating modes can also be adjusted according to practical needs, and this invention is not limited thereto.

[0045] In one embodiment, a third type of idle physical unit (i.e., physical units 302(D+1) to 301(E) in the idle area 35) can be used to replace damaged physical units (also called bad blocks) in physical units 301(1) to 301(B) and 302(1) to 302(D). For example, the memory control circuit 23 can detect whether there are damaged physical units in physical units 301(1) to 301(B) and 302(1) to 302(D). If there are damaged physical units in physical units 301(1) to 301(B) and 302(1) to 302(D), the memory control circuit 23 can select at least one physical unit from the idle area 35 to replace the damaged physical unit. Thus, the normal operation of the storage device 12 can be maintained.

[0046] In one embodiment, the memory control circuit 23 can detect a usage imbalance event for a first operating mode. The usage imbalance event refers to the overuse of a first type of entity unit (e.g., entity units 301(1) to 301(B)) in the memory module 122.

[0047] In one embodiment, the durability of the first type of physical units (e.g., physical units 301(1) to 301(B)) in memory module 122 is higher than that of the second type of physical units (e.g., physical units 302(1) to 302(D)) in memory module 122. However, if the usage of the first type of physical units (e.g., physical units 301(1) to 301(B)) in memory module 122 far exceeds the usage of the second type of physical units (e.g., physical units 302(1) to 302(D)) in memory module 122, the memory control circuit 23 may determine that the usage imbalance event has occurred.

[0048] In one embodiment, the memory control circuit 23 can obtain usage information (also referred to as first usage information) of multiple entity units (also referred to as first target entity units) used in the memory module 122 based on a first operating mode. For example, the first target entity unit includes some or all of the first type of entity units. The first usage information reflects the usage level of the first target entity unit. Furthermore, the memory control circuit 23 can obtain usage information (also referred to as second usage information) of multiple entity units (also referred to as second target entity units) used in the memory module 122 based on a second operating mode. For example, the second target entity unit includes some or all of the second type of entity units. The second usage information reflects the usage level of the second target entity unit. Then, the memory control circuit 23 can determine whether the usage imbalance event has occurred based on the first usage information and the second usage information.

[0049] In one embodiment, the first usage information includes a usage assessment value (also referred to as the first usage assessment value). The first usage assessment value may reflect the average usage of the first target entity unit. For example, the first usage assessment value may be positively correlated with the average usage of the first target entity unit. That is, the higher the average usage of the first target entity unit, the larger the first usage assessment value may be.

[0050] In one embodiment, the first usage assessment value may be determined based on the read count, programmed count, erase count, and / or bit error rate of at least one entity unit in the first target entity unit. For example, the higher the average read count, average programmed count, average erase count, and / or average bit error rate of at least one entity unit in the first target entity unit, the larger the first usage assessment value may be.

[0051] In one embodiment, the second usage information includes another usage assessment value (also referred to as the second usage assessment value). The second usage assessment value may reflect the average usage of the second target entity unit. For example, the second usage assessment value may be positively correlated with the average usage of the second target entity unit. That is, the higher the average usage of the second target entity unit, the larger the second usage assessment value may be.

[0052] In one embodiment, the second usage assessment value may be determined based on the read count, program count, erase count, and / or bit error rate of at least one entity unit in the second target entity unit. For example, the higher the average read count, average program count, average erase count, and / or average bit error rate of at least one entity unit in the second target entity unit, the larger the second usage assessment value may be.

[0053] In one embodiment, the memory control circuit 23 can obtain the difference between a first usage assessment value and a second usage assessment value. For example, assuming the first usage assessment value and the second usage assessment value are values ​​V1 and V2 respectively, the memory control circuit 23 can subtract V2 from V1 or subtract V1 from V2 to obtain the difference. Then, the memory control circuit 23 can determine whether the usage imbalance event has occurred based on this difference.

[0054] In one embodiment, the memory control circuit 23 can compare the difference with a preset value. If the difference is greater than the preset value, the memory control circuit 23 can determine that the usage imbalance event has occurred. However, if the difference is not greater than (e.g., less than or equal to) the preset value, the memory control circuit 23 can determine that the usage imbalance event has not occurred.

[0055] In one embodiment, based on the usage imbalance event, the memory control circuit 23 can determine whether a count information meets a preset condition. Based on whether the count information meets the preset condition, the memory control circuit 23 can perform corresponding processing actions to improve or resolve the usage imbalance event.

[0056] In one embodiment, when the counting information meets preset conditions, the memory control circuit 23 may execute a cross-region retrieval operation (also referred to as a first type of cross-region retrieval operation) to retrieve at least one entity unit (also referred to as a third entity unit) from the third type of idle entity units (i.e., entity units 302(D+1) to 302(E) in the idle area 35). Then, the memory control circuit 23 may use (e.g., operate) the third entity unit based on a first operating mode. For example, the memory control circuit 23 may instruct the memory module 122 to program the third entity unit based on the first operating mode to store data (also referred to as third data) in the third entity unit. Simultaneously, the third entity unit used to store the third data may be associated with the data area 31. In response to the third entity unit being associated with the data area 31, the total number of entity units belonging to the data area 31 (i.e., first type of data entity units) increases, while the total number of entity units belonging to the idle area 35 (i.e., third type of idle entity units) decreases accordingly.

[0057] In one embodiment, the counting information may include a count value. The count value may reflect the total number of third entity units that have not yet been restored to the third type of idle entity unit. That is, the count value may reflect the total number of entity units in data area 31 that have not yet been returned to idle area 35.

[0058] In one embodiment, the memory control circuit 23 can compare the count value with a threshold value to obtain a comparison result. Then, the memory control circuit 23 can determine whether the count information meets a preset condition based on this comparison result. For example, if the comparison result shows that the count value is not greater than (e.g., less than or equal to) this threshold value, the memory control circuit 23 can determine that the count information meets the preset condition. However, if the comparison result shows that the count value is greater than this threshold value, the memory control circuit 23 can determine that the count information does not meet the preset condition.

[0059] In one embodiment, the memory control circuit 23 can determine the threshold value based on the total number of the third type of idle entity units. For example, the memory control circuit 23 can set the threshold value to be no greater than (i.e., less than or equal to) the total number of the third type of idle entity units. For example, assuming that the total number of entity units 302(D+1) to 302(E) in the current or preset idle area 35 is N, the memory control circuit 23 can set the threshold value to M, and M is no greater than N.

[0060] In one embodiment, after performing a first type of cross-region retrieval operation, the memory control circuit 23 can update the counting information based on this first type of cross-region retrieval operation. For example, the memory control circuit 23 can increment the count value by "1" to reflect the total number of entity units in the current data area 31 that have not yet been returned to the idle area 35.

[0061] In one embodiment, if the count information does not meet the preset conditions, the memory control circuit 23 may prohibit the execution of the first type of cross-regional cell retrieval operation. That is, after detecting the usage imbalance event, if the count information does not meet the preset conditions, the memory control circuit 23 may not execute the first type of cross-regional cell retrieval operation. Thus, the number of physical units in the current data area 31 that have not yet been returned to the idle area 35 can be controlled to a preset number (i.e., not exceeding the threshold value), thereby preventing the physical units (i.e., the third type of idle physical units) in the idle area 35 from being overused.

[0062] In one embodiment, by using a first type of cross-region retrieval operation to treat the physical units in the idle area 35 (i.e., the third type of idle physical units) as first type physical units, the third type of idle physical units can help alleviate the heavy usage of the first type of physical units by the storage device 12 in the event of the aforementioned usage imbalance. This reduces the usage levels of the first type of physical units and the second type of physical units, thereby improving or resolving the usage imbalance. By improving or resolving the usage imbalance, the performance and stability of the storage device 12 can be effectively improved, and its lifespan can also be effectively extended.

[0063] In one embodiment, after performing the first type of cross-region retrieval operation, the memory control circuit 23 may perform a data merging operation on the data area 31 to return at least a portion of the physical units in the data area 31 that have not yet been returned to the idle area 35 to the idle area 35. For example, the data merging operation may include a garbage collection (GC) operation.

[0064] In one embodiment, the data merging operation may include a cross-region return operation (also referred to as a first type of cross-region return operation). This first type of cross-region return operation is used to restore the third entity unit previously used based on the first operating mode to a third type of idle entity unit. For example, by performing the data merging operation, valid data originally stored in the third entity unit can be moved or copied to other entity units for storage, causing the valid data in the third entity unit to become invalid data. When all the data stored in the third entity unit is invalid data, the memory control circuit 23 can return (i.e., re-associate) the third entity unit to the idle area 35 through the first type of cross-region return operation. Thus, the total number of entity units (i.e., third type of idle entity units) in the idle area 35 can be gradually restored (i.e. increased).

[0065] Figure 4 This is a schematic diagram illustrating the first type of cross-region retrieval operation and the first type of cross-region return operation according to an embodiment of the present invention. Please refer to... Figure 4In the first type of cross-region retrieval operation, entity unit 302(i) can be retrieved from idle region 35 and used based on a first operation mode (e.g., programmatic). Then, entity unit 302(i) can be associated with data region 31 to alleviate the heavy use of the first type of entity unit by storage device 12.

[0066] After performing the first type of cross-area retrieval operation, in the first type of cross-area return operation, the data merging operation can be used to move or clear the valid data currently stored in entity unit 302(i). Then, entity unit 302(i) can be reassociated from data area 31 to idle area 35 to ensure that there are still enough entity units (i.e., third type of idle entity units) in idle area 35 for subsequent use.

[0067] In one embodiment, based on the usage imbalance event, if the counting information does not meet the preset conditions (e.g., the third type of idle entity units have been exhausted or nearly exhausted), the memory control circuit 23 may perform another cross-region retrieval operation (also referred to as a second type of cross-region retrieval operation) to retrieve at least one entity unit (also referred to as a fourth entity unit) from the second type of idle entity units (i.e., entity units 302(C+1) to 302(D) in the idle area 34). Then, the memory control circuit 23 may use (e.g., operate) the fourth entity unit based on a first operating mode. For example, the memory control circuit 23 may instruct the memory module 122 to program the fourth entity unit based on the first operating mode to store data (also referred to as fourth data) in the fourth entity unit. Simultaneously, the fourth entity unit used to store the fourth data may be associated with the data area 31. In response to the fourth entity unit being associated with the data area 31, the total number of entity units belonging to the data area 31 (i.e., the first type of data entity units) increases, while the total number of entity units belonging to the idle area 34 (i.e., the second type of idle entity units) decreases accordingly. Therefore, even if the third type of idle physical units are exhausted or nearly exhausted, the second type of idle physical units can still be used to help alleviate the heavy use of the first type of physical units by the storage device 12, thereby improving or resolving the usage imbalance event. By improving or resolving the usage imbalance event, the performance and stability of the storage device 12 can be effectively improved, and the service life of the storage device 12 can also be effectively extended.

[0068] In one embodiment, after performing the second type of cross-region retrieval operation, the memory control circuit 23 may also perform the data merging operation on the data area 31 to return at least a portion of the physical units in the data area 31 that have not yet been returned to the idle area 34 to the idle area 34.

[0069] In one embodiment, the data merging operation may include another cross-area return operation (also referred to as a second type of cross-area return operation). This second type of cross-area return operation is used to restore the fourth entity unit previously used based on the first operating mode to a second type of idle entity unit. For example, by performing the data merging operation, valid data originally stored in the fourth entity unit can be moved or copied to other entity units for storage, causing the valid data in the fourth entity unit to become invalid data. When all the data stored in the fourth entity unit is invalid data, the memory control circuit 23 can return (i.e., re-associate) the fourth entity unit to the idle area 34 through the second type of cross-area return operation. Thus, the total number of entity units (i.e., second type of idle entity units) in the idle area 34 can be gradually restored (i.e. increased).

[0070] Figure 5 This is a schematic diagram illustrating the second type of cross-regional extraction operation and the second type of cross-regional return operation according to an embodiment of the present invention. Please refer to... Figure 5 In the second type of cross-region retrieval operation, entity unit 302(j) can be retrieved from idle region 34 and used based on the first operation mode (e.g., programmatic). Then, entity unit 302(j) can be associated with data region 31 to alleviate the heavy use of the first type of entity unit by storage device 12.

[0071] After performing the second type of cross-area retrieval operation, in the second type of cross-area return operation, the data merging operation can be used to move or clear the valid data currently stored in entity unit 302(j). Then, entity unit 302(j) can be reassociated from data area 31 to idle area 34 to ensure that there are still enough entity units (i.e., second type of idle entity units) in idle area 34 for subsequent use.

[0072] In one embodiment, the memory control circuit 23 can dynamically adjust the trigger threshold of the data merging operation based on the second type of cross-region fetch operation performed. The trigger threshold can be used to trigger the data merging operation.

[0073] In one embodiment, the trigger threshold includes a numerical value (also referred to as a first trigger threshold). The first trigger threshold is used to trigger a data merging operation (also referred to as a first data merging operation) for data area 31. For example, the first data merging operation can be triggered when the total number of entity units (i.e., first type of idle entity units) in idle area 33 is less than the first trigger threshold. In response to the first data merging operation being triggered, memory control circuitry 23 can perform the first data merging operation on at least one entity unit in data area 31. For example, the first data merging operation may include at least one of the first type of cross-area return operation and the second type of cross-area return operation. In addition, the first data merging operation may also include returning at least one entity unit in idle area 31 to idle area 33 to increase the total number of entity units (i.e., first type of idle entity units) belonging to idle area 33.

[0074] In one embodiment, the trigger threshold includes another value (also referred to as a second trigger threshold). The second trigger threshold is used to trigger a data merging operation (also referred to as a second data merging operation) for data area 32. For example, the second data merging operation can be triggered when the total number of entity units (i.e., second type of idle entity units) in idle area 34 is less than the second trigger threshold. In response to the second data merging operation being triggered, memory control circuitry 23 can perform the second data merging operation on at least one entity unit in data area 32. For example, the second data merging operation may include returning at least one entity unit in idle area 32 to idle area 34 to increase the total number of entity units (i.e., second type of idle entity units) belonging to idle area 34.

[0075] In one embodiment, the memory control circuit 23 can detect whether the total number of physical units (i.e., second-type idle physical units) in the idle area 34 is less than a preset number. In one embodiment, the memory control circuit 23 can determine to adjust at least one of the first trigger threshold and the second trigger threshold based on whether the total number of second-type idle physical units is less than the preset number.

[0076] In one embodiment, when the total number of second-type idle entity units is less than the preset number, the memory control circuit 23 can synchronously adjust the first trigger threshold and the second trigger threshold according to the executed second-type cross-region retrieval operation. For example, the memory control circuit 23 can adjust the first trigger threshold from one value (also called the first value) to another value (also called the second value) to trigger the first data merging operation in advance. The second value can be less than the first value. Furthermore, the memory control circuit 23 can adjust the second trigger threshold from one value (also called the third value) to another value (also called the fourth value) to trigger the second data merging operation in advance. The fourth value can be less than the third value.

[0077] In one embodiment, when the total number of second-type idle entity units is not less than (e.g., greater than or equal to) the preset number, the memory control circuit 23 may (only) adjust the second trigger threshold value according to the second-type cross-region retrieval operation performed. For example, the memory control circuit 23 may adjust the second trigger threshold value from a third value to a fourth value to trigger the second data consolidation operation in advance.

[0078] In one embodiment, if a second type of cross-region retrieval operation is performed and the total number of second type of idle entity units is less than the preset number, it indicates that all types of idle entity units may already be in large quantities. In this case, by simultaneously adjusting the first trigger threshold and the second trigger threshold, the data merging operation for storage areas 31 and 32 can be forcibly triggered in advance, thereby accelerating the release (i.e., return) of various types of idle entity units. Thus, although the access performance of the storage device 12 may be significantly reduced, the stability of the subsequent operation of the storage device 12 can be effectively ensured.

[0079] On the other hand, if a second type of cross-region retrieval operation is performed and the total number of second type idle entity units is not less than the preset number, it indicates that although a large number of third type idle entity units have been used, the number of second type idle entity units is still sufficient. In this case, by adjusting the second trigger threshold separately, the data consolidation operation for storage area 32 can be forcibly triggered in advance. Thus, the stability of subsequent operation of storage device 12 can be effectively ensured without significantly affecting the access performance of storage device 12.

[0080] Figure 6 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 6 In step S601, a first entity unit is extracted from the first type of idle entity units in the memory module and used based on a first operating mode. In step S602, a second entity unit is extracted from the second type of idle entity units in the memory module and used based on a second operating mode. In step S603, a usage imbalance event for the first operating mode is detected. In step S604, it is determined whether the counting information meets preset conditions.

[0081] If the counting information meets the preset conditions, in step S605, based on the usage imbalance event, and if the counting information meets the preset conditions, a first type of cross-region extraction operation is performed to extract a third entity unit from the third type of idle entity unit in the memory module, and the third entity unit is used based on the first operation mode. In step S606, the counting information is updated according to the first type of cross-region extraction operation. On the other hand, if the determination result of step S604 is that the counting information does not meet the preset conditions, then in step S607, the first type of cross-region unit extraction operation is prohibited.

[0082] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 7 In step S701, a second type of cross-region extraction operation is performed to extract a fourth entity unit from the second type of idle entity units in the memory module, and the fourth entity unit is used based on the first operation mode. In step S702, the trigger threshold of the data merging operation is adjusted according to the second type of cross-region extraction operation.

[0083] However, Figure 6 and Figure 7 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 6 and Figure 7 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 6 and Figure 7 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0084] In summary, the memory management method and storage device proposed in this invention can perform cross-region retrieval operations at appropriate times to help alleviate the heavy usage of the first type of entity units by utilizing one or more types of idle entity units. This narrows the usage gap between the first and second types of entity units, thereby improving or resolving the aforementioned usage imbalance. By improving or resolving this usage imbalance, the performance and stability of the storage device can be effectively enhanced, and its lifespan can be effectively extended.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For use in a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: The plurality of entity units are respectively associated with the first data area, the second data area, the first idle area, the second idle area, and the third idle area; Through a first type of non-cross-area extraction operation, a first entity unit is extracted from the first type of idle entity units associated with the first idle area from the plurality of entity units, and the first entity unit is used based on a first operation mode, wherein the first type of idle entity units are used alternately between the first data area and the first idle area, and an entity unit used based on the first operation mode is used to store a first number of bits of data. Through a second type of non-cross-area extraction operation, a second entity unit is extracted from the second type of idle entity units associated with the second idle area from the plurality of entity units, and the second entity unit is used based on a second operation mode, wherein the second type of idle entity units are used alternately between the second data area and the second idle area, and an entity unit used based on the second operation mode is used to store a second number of bit data, and the first number is less than the second number; Obtain a first usage assessment value for multiple first target entity units used based on the first operating mode; Obtain a second usage assessment value for multiple second target entity units used based on the second operating mode; The difference between the first usage assessment value and the second usage assessment value determines whether a usage imbalance event has occurred for the first operating mode. According to the aforementioned imbalance event, if the counting information meets the preset conditions, a first type of cross-region extraction operation is performed to extract a third entity unit from the third type of idle entity units associated with the third idle area from the plurality of entity units, and the third entity unit is used based on the first operation mode, wherein the third type of idle entity unit is also used to replace the damaged entity units in the first data area, the second data area, the first idle area, and the second idle area; According to the first type of cross-regional extraction operation, the counting information is updated, wherein the counting information includes a count value, and the count value reflects the total number of the third entity units that have not yet been restored to the third type of idle entity units; and If the counting information does not meet the preset conditions, the first type of cross-regional extraction operation is prohibited.

2. The memory management method according to claim 1 further includes: The count value is compared with the threshold value to obtain the comparison result; as well as Based on the comparison results, it is determined whether the counting information meets the preset conditions.

3. The memory management method according to claim 2 further includes: The threshold value is set based on the total number of the third type of idle entity units.

4. The memory management method according to claim 1, further comprising: According to the imbalance event, if the counting information does not meet the preset conditions, a second type of cross-region extraction operation is performed to extract a fourth entity unit from the second type of idle entity unit, and the fourth entity unit is used based on the first operation mode; as well as Based on the second type of cross-region extraction operation, adjust the trigger threshold for the data merging operation.

5. The memory management method according to claim 4, wherein the step of adjusting the trigger threshold of the data merging operation includes: Detect whether the total number of the second type of idle entity units is less than a preset number; If the total number of the second type of idle entity units is not less than the preset number, adjust the second trigger threshold value of the second data merging operation for the second type of idle entity units; as well as If the total number of the second type of idle entity units is less than the preset number, adjust the second trigger threshold and the first trigger threshold for the first data merging operation for the first type of idle entity units.

6. The memory management method according to claim 5, wherein the first data merging operation includes at least one of a first type of inter-region return operation and a second type of inter-region return operation. The first type of cross-region return operation is used to restore the third entity unit used based on the first operation mode to the third type of idle entity unit, and The second type of cross-region return operation is used to restore the fourth entity unit used based on the first operation mode to the second type of idle entity unit.

7. The memory management method according to claim 5, wherein the step of adjusting the first trigger threshold includes: The first trigger threshold is adjusted from a first value to a second value to trigger the first data merging operation earlier, wherein the second value is less than the first value, and The steps for adjusting the second trigger threshold include: The second trigger threshold is adjusted from the third value to the fourth value to trigger the second data merging operation in advance, wherein the fourth value is less than the third value.

8. The memory management method according to claim 1, The first usage assessment value reflects the average usage of the plurality of first target entity units, and the second usage assessment value reflects the average usage of the plurality of second target entity units.

9. The memory management method according to claim 1, wherein the step of determining whether the usage imbalance event has occurred based on the difference between the first usage assessment value and the second usage assessment value includes: Compare the difference with a preset value; as well as If the difference is greater than the preset value, it is determined that the usage imbalance event has occurred.

10. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory module comprises multiple physical units, and the memory controller is used to: The plurality of entity units are respectively associated with the first data area, the second data area, the first idle area, the second idle area, and the third idle area; Through a first type of non-cross-area extraction operation, a first entity unit is extracted from the first type of idle entity units associated with the first idle area from the plurality of entity units, and the first entity unit is used based on a first operation mode, wherein the first type of idle entity units are used alternately between the first data area and the first idle area, and an entity unit used based on the first operation mode is used to store a first number of bits of data. Through a second type of non-cross-area extraction operation, a second entity unit is extracted from the second type of idle entity units associated with the second idle area from the plurality of entity units, and the second entity unit is used based on a second operation mode, wherein the second type of idle entity units are used alternately between the second data area and the second idle area, and an entity unit used based on the second operation mode is used to store a second number of bit data, and the first number is less than the second number; Obtain a first usage assessment value for multiple first target entity units used based on the first operating mode; Obtain a second usage assessment value for multiple second target entity units used based on the second operating mode; The difference between the first usage assessment value and the second usage assessment value determines whether a usage imbalance event has occurred for the first operating mode. According to the aforementioned imbalance event, if the counting information meets the preset conditions, a first type of cross-region extraction operation is performed to extract a third entity unit from the third type of idle entity units associated with the third idle area from the plurality of entity units, and the third entity unit is used based on the first operation mode, wherein the third type of idle entity unit is also used to replace the damaged entity units in the first data area, the second data area, the first idle area, and the second idle area; According to the first type of cross-regional extraction operation, the counting information is updated, wherein the counting information includes a count value, and the count value reflects the total number of the third entity units that have not yet been restored to the third type of idle entity units; as well as If the counting information does not meet the preset conditions, the first type of cross-regional extraction operation is prohibited.

11. The storage device of claim 10, wherein the memory controller is further configured to: The count value is compared with a threshold value to obtain a comparison result; and Based on the comparison results, it is determined whether the counting information meets the preset conditions.

12. The storage device of claim 11, wherein the memory controller is further configured to: The threshold value is set based on the total number of the third type of idle entity units.

13. The storage device of claim 10, wherein the memory controller is further configured to: Based on the aforementioned imbalance event, if the counting information does not meet the preset conditions, a second type of cross-regional extraction operation is performed to extract a fourth entity unit from the second type of idle entity units, and the fourth entity unit is used based on the first operation mode; and Based on the second type of cross-region extraction operation, adjust the trigger threshold for the data merging operation.

14. The storage device of claim 13, wherein the operation of the memory controller adjusting the trigger threshold of the data merging operation includes: Detect whether the total number of the second type of idle entity units is less than a preset number; If the total number of the second type of idle entity units is not less than the preset number, adjust the second trigger threshold value of the second data merging operation for the second type of idle entity units; as well as If the total number of the second type of idle entity units is less than the preset number, adjust the second trigger threshold and the first trigger threshold for the first data merging operation for the first type of idle entity units.

15. The storage device of claim 14, wherein the first data merging operation includes at least one of a first type of cross-region return operation and a second type of cross-region return operation. The first type of cross-region return operation is used to restore the third entity unit used based on the first operation mode to the third type of idle entity unit, and The second type of cross-region return operation is used to restore the fourth entity unit used based on the first operation mode to the second type of idle entity unit.

16. The storage device of claim 14, wherein the operation of the memory controller adjusting the first trigger threshold includes: The first trigger threshold is adjusted from a first value to a second value to trigger the first data merging operation earlier, wherein the second value is less than the first value, and The operation of adjusting the second trigger threshold includes: The second trigger threshold is adjusted from the third value to the fourth value to trigger the second data merging operation in advance, wherein the fourth value is less than the third value.

17. The storage device according to claim 10, The first usage assessment value reflects the average usage of the plurality of first target entity units, and the second usage assessment value reflects the average usage of the plurality of second target entity units.

18. The storage device of claim 10, wherein the operation of the memory controller determining whether the usage imbalance event has occurred based on the difference between the first usage assessment value and the second usage assessment value includes: Compare the difference with a preset value; as well as If the difference is greater than the preset value, it is determined that the usage imbalance event has occurred.

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