Storage device and control method thereof

Abstract

The present invention provides a storage device and a control method thereof, including: a flash memory chip, electrically connected to a host computer, a storage block of the flash memory chip is marked as a data block or a code block, a storage page of the storage block includes a plurality of core word areas, the core word area includes a main data storage area and a user data storage area, and the address of the main data storage area is a first address; a memory, electrically connected to the host computer and the flash memory chip, the memory includes a plurality of mapping storage areas, when the main data is read out from the flash memory chip, the main data is stored in the mapping storage area, in the mapping storage area, the storage address of the main data is a second address, and the free bytes of the mapping storage area are a third address; and a control firmware, stored in a code block, when the host computer reads and writes user data, the control firmware runs in the flash memory chip, and allows the user data to be written to the third address or read out from the third address. The present invention can improve storage space utilization and storage performance.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a storage device and a control method thereof. Background Art

[0002] Random Access Memory (RAM), also called main memory, is an internal memory that directly exchanges data with the CPU. Random Access Memory can be read and written at any time, and the speed is very fast, so Random Access Memory is usually used as a temporary data storage medium for operating systems or other running programs. For storage devices with flash memory as the storage medium, if the host computer wants to read and write data in the storage device, the storage efficiency and reliability can be effectively improved through the random access memory.

[0003] During the data storage process of the random access memory, the stored data is aligned according to a predetermined byte, such as four-byte alignment, and when it is less than four bytes, it is rounded to four bytes. Therefore, a lot of space in the random access memory is idle, and the performance of the storage device is not fully developed. Summary of the invention

[0004] The object of the present invention is to provide a storage device and a control method thereof, which can improve the space utilization and storage performance of the storage device.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a storage device, comprising:

[0007] A flash memory chip is electrically connected to a host computer, a storage block of the flash memory chip is marked as a data block or a code block, a storage page of the storage block includes a plurality of core word areas, the core word areas include a main data storage area and a user data storage area, and an address of the main data storage area is a first address;

[0008] a memory electrically connected to the host computer and the flash memory chip, the memory comprising a plurality of mapping storage areas, when the main data is read out from the flash memory chip, the main data is stored in the mapping storage area, in the mapping storage area, the storage address of the main data is a second address, and the free bytes of the mapping storage area are a third address; and

[0009] The control firmware is stored in the code block. When the host computer reads and writes user data, the control firmware runs in the flash memory chip and allows the user data to be written into the third address or read out from the third address.

[0010] In one embodiment of the present invention, the user data storage area stores user data, and the main data storage area stores hardware error correction data of the flash memory chip and bad block management data of the flash memory chip.

[0011] In one embodiment of the present invention, the control firmware includes a macro definition storage module, in which a plurality of macro definition instructions are stored, the macro definition instructions including an instruction name, a flash plane address of the flash memory chip, a storage area type in the flash memory chip, an address of the core word area, a pointer parameter and the third address, wherein the third address is a free byte address in the mapped storage area associated with the core word area.

[0012] In one embodiment of the present invention, the control firmware includes an assignment unit, and when the host computer calls the third address, the assignment unit assigns values ​​to the pointer parameters of multiple mapped storage areas, wherein the pointer parameters of multiple mapped storage areas are different.

[0013] In one embodiment of the present invention, the control firmware includes an access unit, which is electrically connected to the host computer and the assignment unit. The access unit stores access program statements, which run in the flash memory chip, output the value of the pointer parameter, and output the third address related to the pointer parameter to the host computer according to the macro definition instruction.

[0014] In one embodiment of the present invention, the storage device includes a processor, and the processor includes an error correction module. When the host computer edits the data at the third address, before compiling the macro definition instruction, the error correction module reads the macro definition instruction and corrects the error of the macro definition instruction.

[0015] In one embodiment of the present invention, the addresses of the multiple mapped storage areas are continuous, and in the mapped storage areas, the second addresses are continuous, and in the memory, the first addresses of the multiple mapped storage areas are the initial addresses of the second addresses, wherein the initial address of the second addresses is a preset address.

[0016] In one embodiment of the present invention, the third address has an address offset compared to the initial address, and the address offset is the sum of the total number of bytes of the interval flash memory planes, the total number of bytes of the interval mapping storage area and the number of bytes of the main data storage unit, wherein the interval flash memory planes are all flash memory planes before the flash memory plane where the third address is located, and the interval mapping storage area is all mapping storage areas before the mapping storage area where the third address is located.

[0017] In one embodiment of the present invention, the control firmware includes a write data control module, in which a preset alignment byte number is stored, and the total number of bytes of the mapped storage area is a multiple of the alignment byte number.

[0018] The present invention provides a control method for a storage device, based on the storage device as described above, comprising the following steps:

[0019] When reading data from the main data storage area, the main data is written into the mapping storage area according to the byte alignment writing mode, the address of the main data storage area is set to the first address, and the address of the mapping storage area is set to the second address;

[0020] Obtaining free bytes of the mapped storage area, and setting the address of the free bytes to a third address; and

[0021] When the host computer reads and writes user data, the control firmware runs in the flash memory chip and allows the user data to be written to the third address or read from the third address.

[0022] As described above, the present invention provides a storage device and a control method thereof, which can process idle space in a memory, thereby improving the space utilization of the memory. Moreover, the storage device and the control method thereof provided by the present invention can directly address the fragmented space of the memory without occupying extra space, which not only improves the utilization of the memory, but also ensures the storage performance of the memory.

[0023] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0025] Figure 1 FIG. 4 is a schematic diagram of the structure of a storage device in an embodiment of the present invention.

[0026] Figure 2 FIG. 4 is a schematic diagram of the structure of the core word area in one embodiment of the present invention.

[0027] Figure 3 Schematic diagram of data transfer relationship between a mapping storage area and a main data storage area in one embodiment of the present invention.

[0028] Figure 4FIG. 1 is a schematic diagram of the structure of the control firmware in one embodiment of the present invention.

[0029] Figure 5 Schematic diagram of a macro definition instruction in an embodiment of the present invention.

[0030] Figure 6 The flowchart of the control method of the storage device in one embodiment of the present invention.

[0031] In the figure: 100, storage device; 200, main controller; 210, processor; 211, error correction module; 220, memory; 221, mapping storage area; 300, flash memory chip; 310, data block; 320, code block; 321, control firmware; 3211, macro definition storage module; 3212, compilation module; 3213, assignment unit; 3214, access unit; 3215, write data control module; 330, core word area; 331, user data storage area; 332, main data storage area; 333, error correction data storage area; 400, host computer. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] See also Figure 1As shown, the storage medium used by the storage device 100 provided by the present invention is a flash memory. In this embodiment, the storage device 100 includes a main controller 200 and a flash memory chip 300. The main controller 300 is electrically connected to the host computer 400 and the flash memory chip 300. In this embodiment, the host computer 400 is a computer system, and specifically can be any digital device that can call a storage medium, such as a computer, a mobile phone, etc. The flash memory chip 300 is not limited to NAND flash memory and NOR flash memory. The main controller 200 includes a processor 210 and a memory 220. In this embodiment, the processor 210 is, for example, a reduced instruction system computer (RISC), and specifically an ARM processor. In this embodiment, the memory 220 can be a static random access memory (SRAM) or a dynamic random access memory (DRAM). In this embodiment, the flash memory chip 300 includes at least one flash plane. The flash plane includes a plurality of storage blocks, storage blocks. The storage block includes a plurality of storage pages. The plurality of storage blocks are divided into a data block 310 and a code block 320. The data block 310 stores user data, and the code block 320 stores design firmware.

[0034] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, a storage page includes a plurality of core word areas 330. In this embodiment, a storage page includes, for example, 4 core word areas 330. The core word area 330 includes a user data storage area 331, a main data storage area 332, and an error correction data storage area 333. The user data storage area 331 is used to store user data sent by the host computer 400. In this embodiment, the user data storage area 331 stores, for example, 4KB of data. A storage page stores, for example, 16KB of user data. The main data storage area 332 is used to store preset data set during design, for example, for storing hardware error correction data and bad block management data of the flash memory chip 300. In this embodiment, the main data storage area 332 stores, for example, 10KB of data. The error correction data storage area 333 is used to store error correction codes. The error correction code is, for example, a low-density parity-check code (LDPC code).

[0035] See also Figures 1 to 3As shown, in one embodiment of the present invention, when the host computer 400 wants to call the storage data of the main data storage area 332, an address mapping relationship is established between the main data storage area 332 and the memory 220. It should be noted that in the design stage, the address mapping relationship between the main data storage area 332 and the memory 220 is determined and recorded in the form of a mapping table or firmware. When calling the storage data of the main data storage area 332, each byte in the main data storage area 332 is mapped to a preset byte in the memory 220. Figure 3 As shown, for example, 10 bytes in the main data storage area 332 are read to a preset position in the memory 220. In this embodiment, the memory 220 includes a mapping storage area 221. The address of the mapping storage area 221 is determined during the design phase, and the addresses of multiple mapping storage areas 221 are continuous, and in the mapping storage area 221, the second address is continuous. In the case of four-byte alignment, the actual occupied space in the memory 220 is 12 bytes. Therefore, for each data of a main data storage area 332 read out, for example, 2 bytes are wasted in the mapping storage area 221. The larger the number of flash memory planes, the larger the idle storage space of the memory 220 will be. In this embodiment, when the flash memory chip 300 includes one flash memory plane, a storage page is read, and the occupied space in the memory 220 is, for example, 48 bytes. When the flash memory chip 300 includes two flash memory planes, a storage page is read, and the occupied space in the memory 220 is, for example, 96 bytes. And so on. It should be noted that the present invention does not limit the data volume of the main data storage area 332 to 10 bytes, so the present invention does not limit the free storage space in the memory 220 either.

[0036] See also Figures 1 to 4As shown, in one embodiment of the present invention, the code block 320 stores the control firmware 321. The control firmware 321 includes a macro definition storage module 3211, a compilation module 3212 and a write data control module 3215. The compilation module 3212 includes an assignment unit 3213 and an access unit 3214. The macro definition storage module 3211 stores macro definition instructions. In this embodiment, the control firmware 321 runs in the flash memory chip 300. Specifically, the operating system of the storage device 100 is based on the local execution system (executed in place, XIP), thereby supporting the control firmware 321 to run directly in the flash memory chip 300. In the firmware design stage, the macro definition instructions are set, and the macro definition instructions are, for example, in the macro definition storage module 3211. In this embodiment, the address of the main data storage area 332 is set to the first address, and the address in the memory 220 that forms a mapping relationship with the first address is set to the second address. In this embodiment, the second address is a continuous address. The starting address of the second address is obtained, and according to the starting address of the second address, a macro definition instruction is set to serve as an interface for the free bytes in the second address. In this embodiment, the address of the free bytes in the second address is set to the third address. The free bytes refer to the bytes in the memory 220 that are free due to the byte alignment rule after the data in the core word area 330 is in the memory 220. It should be noted that the starting address of the second address refers to the physical address of the memory 220 that is first written to the main data storage area 332 in the second address, and may also refer to the physical address of the memory 220 that is first read by the host computer 400. In this embodiment, the third address in the memory 220 is defined by a macro definition instruction. The preset alignment byte number is stored in the write data control module 3215. In this embodiment, the total number of bytes of the mapped storage area 221 is an integer multiple of the alignment byte number. For example, the preset alignment byte number is 4 bytes. When the number of bytes in the main data storage area 332 is 10, the total number of bytes in the mapped storage area 221 is set to 12. In a single mapped storage area 221, the number of bytes of the third address is 2 bytes. If the number of bytes of the main data storage area 332 is 9, the total number of bytes of the mapped storage area 221 is set to 12, and the number of bytes of the third address in a single mapped storage area 221 is 3 bytes. For another example, the preset alignment byte number is 2 bytes, and if the number of bytes of the main data storage area 332 is 9, the total number of bytes of the mapped storage area 221 is set to 10, and the number of bytes of the third address in a single mapped storage area 221 is 1 byte.

[0037] See also Figures 1 to 4As shown, in one embodiment of the present invention, the starting address in the second address is represented by BE_METADATA_BUF_ADDR, for example. Plane represents the physical address of the flash memory plane in the flash memory chip 300, wherein plane0 can represent the physical address of the first flash memory plane in the flash memory chip 300, plane1 can represent the physical address of the second flash memory plane in the flash memory chip 300, and so on, planeN can represent the physical address of the N+1th flash memory plane in the flash memory chip 300. The starting sequence number of the flash memory plane can also be plane1, then planeN represents the physical address of the Nth flash memory plane in the flash memory chip 300, and the present invention does not limit this. Specifically, META refers to the main data storage area 332, and CORE_WORD refers to the core word area 330. Among them, the core word area 330 is sorted in the form of numbers to correspond to the order in which the core word area 330 is written into the memory 220. For example, CORE_WORD_0 represents the first core word area 330 for transferring data to the memory 220, CORE_WORD_1 represents the second core word area 330 for transferring data to the memory 220, and so on, CORE_WORD_N represents the N+1th core word area 330 for transferring data to the memory 220. The starting sequence number of the core word area 330 may also be CORE_WORD_1, and CORE_WORD_N represents the physical address of the Nth core word area 330 in the storage page, which is not limited in the present invention.

[0038] See also Figures 1 to 5As shown, in one embodiment of the present invention, in the macro definition instruction, the address of the flash plane, the type of storage area, the address of the core word area 330, the pointer parameter, and the third address are defined in sequence. The address of the flash plane is PLANEN, and N is a natural number. The type of storage area is the type of storage area in the core word area 330, and can specifically be a user data storage area 331, a main data storage area 332, or an error correction data storage area 333. In this embodiment, the type of storage area is the main data storage area 332. The address of the core word area 330 is the address of the core word area 330 in the storage page, such as CORE_WORD_0, CORE_WORD_1, CORE_WORD_2, and CORE_WORD3. The pointer parameter is a parameter value defined in the present invention. The third address is the address of the free byte in the memory 220, and is obtained according to the initial address of the second address. For example, the macro definition instruction can be expressed as #define PLANE0_META_CORE_WORD_0 (*((u16_t*)(BE_METADATA_BUF_ADDR + 0*0x30 + 0*0xC + 0x0A))). Wherein, define is the name of the macro definition instruction, and (*((u16_t*) refers to a pointer parameter. Wherein, the number of addresses included in a flash memory plane is, for example, 0x30, that is, 48 ​​bytes. Wherein, 0xC represents the total number of bytes mapped to a core word area 330, that is, 12 bytes. Wherein, 0x0A is, for example, the address offset of the initial address of the third address in the first mapped storage area 221 relative to the initial address of the second address. Wherein the initial address of the second address is the first physical address of multiple mapped storage areas 221. In this embodiment, in the first mapped storage area 22 1, the address offset is the storage capacity of the main data storage area 332, specifically, the number of bytes of the main data storage area 332. In the memory 220, the address offset of the third address relative to the initial address of the second address is the sum of the number of bytes away from the flash memory page, the number of bytes away from the mapped storage area 221, and the number of bytes of the main data storage area 332. In this embodiment, BE_METADATA_BUF_ADDR+0x0A means that 10 bytes are added to the initial address of the second byte, that is, the initial address of the third address in the first mapped storage area 221.Therefore, #define PLANE0_META_CORE_WORD_0 (*((u16_t*) (BE_METADATA_BUF_ADDR + 0*0x30 +0*0xC + 0x0A))) means that the main data storage area 332 of the first core word area 330 of the flash page plane0 is mapped to the memory 220, and the initial address of the third address occupied in the memory 220 is the initial address of the third address in the first mapped storage area 221. By analogy, the macro definition instruction provided by the present invention can be expressed as. Figure 5 shown.

[0039] See also Figure 1 , Figure 3 and Figure 5 As shown, in one embodiment of the present invention, Figure 5 The macro definition instruction #definePLANE0_META_CORE_WORD_1 (*((u16_t*)(BE_METADATA_BUF_ADDR + 0*0x30 + 1*0xC +0x0A))) shown in the figure indicates that the main data storage area 332 of the second core word area 330 of the flash page plane0 is mapped to the memory 220, and the initial address of the third address occupied in the memory 220 can also indicate the initial address of the third address in the second mapped storage area 221. The same applies to the subsequent operations. Figure 5 The macro definition instruction #define PLANE0_META_CORE_WORD_2 (*((u16_t*)(BE_METADATA_BUF_ADDR + 0*0x30 + 2*0xC + 0x0A))) shown indicates that the main data storage area 332 of the third core word area 330 of the flash page plane0 is mapped to the memory 220, and the initial address of the third address occupied in the memory 220 is. Figure 5 The macro definition instruction #define PLANE0_META_CORE_WORD_3 (*((u16_t*)(BE_METADATA_BUF_ADDR + 0*0x30 + 3*0xC + 0x0A))) shown indicates that the main data storage area 332 of the fourth core word area 330 of the flash page plane0 is mapped to the memory 220, and the initial address occupied by the third address in the memory 220. Figure 5The macro definition instruction #define PLANE1_META_CORE_WORD_0 (*((u16_t*)(BE_METADATA_BUF_ADDR + 1*0x30 + 0*0xC + 0x0A))) shown in the figure indicates that the main data storage area 332 of the first core word area 330 of the flash page plane1 is mapped to the memory 220, and occupies the initial address of the third address in the memory 220. Similarly, #define PLANE1_META_CORE_WORD_1 (*((u16_t*)(BE_METADATA_BUF_ADDR + 1*0x30 + 1*0xC + 0x0A))) indicates that the main data storage area 332 of the first core word area 330 of the flash page plane1 is mapped to the memory 220, and occupies the initial address of the third address in the memory 220. #define PLANE1_META_CORE_WORD_2 (*((u16_t*)(BE_METADATA_BUF_ADDR + 1*0x30 + 2*0xC + 0x0A))), indicates that the main data storage area 332 of the second core word area 330 of the flash page plane1 is mapped to the memory 220, and the initial address of the third address occupied in the memory 220. #define PLANE1_META_CORE_WORD_2 (*((u16_t*)(BE_METADATA_BUF_ADDR + 1*0x30 + 2*0xC + 0x0A))), indicates that the main data storage area 332 of the third core word area 330 of the flash page plane1 is mapped to the memory 220, and the initial address of the third address occupied in the memory 220. #definePLANE1_META_CORE_WORD_3 (*((u16_t*)(BE_METADATA_BUF_ADDR + 1*0x30 + 3*0xC +0x0A))), indicates that the main data storage area 332 of the fourth core word area 330 of the flash page plane1 is mapped to the memory 220, and the initial address of the third address occupied in the memory 220. In this embodiment, the macro definition instruction is stored in the macro definition storage module 3211.

[0040] See also Figures 1 to 5As shown, in one embodiment of the present invention, when the host computer 400 retrieves data, the data in the user data storage area 321 and the data in the error correction data storage area 333 can be written into the memory 220, and can be written into the free bytes of the third address. In this embodiment, when the free bytes of the third address are called, the host computer 400 starts the compilation module 3212. The compilation module 3212 reads the macro definition instruction from the macro definition storage module 3211 and runs the macro definition instruction. Among them, the assignment unit 3213 assigns a pointer parameter. Specifically, the assignment unit 3213 assigns different values ​​to the pointer parameters in each macro definition instruction. Among them, the assignment unit 3213 stores an assignment statement, and the pointer parameter in the macro definition instruction is assigned by the assignment statement. For example, the assignment statement may be void SetMetaGapData() {PLANE0_META_CORE_WORD_0 = 0x12; PLANE0_META_CORE_WORD_1 = 1x34; PLANE0_META_CORE_WORD_2 = 0x56; PLANE0_META_CORE_WORD_3 = 0x78; PLANE1_META_CORE_WORD_0 = 0x12; PLANE1_META_CORE_WORD_1 = 0x34; PLANE1_META_CORE_WORD_2 = 0x56; PLANE1_META_CORE_WORD_3 = 0x78;}. In this embodiment, the assignment unit 3213 assigns a value to the first core word area 330 of the flash plane plane0, and the assigned value is, for example, 0x12. The value assignment unit 3213 assigns a value to the second core word area 330 of the flash plane plane0, and the value assigned is, for example, 1x34. Similarly, the value assignment unit 3213 assigns a value to the fourth core word area 330 of the flash plane plane1, and the value assigned is, for example, 0x78.

[0041] See also Figure 1 , Figure 4 and Figure 5As shown, in one embodiment of the present invention, after the assignment unit 3213 completes the assignment, each idle byte corresponds to a different pointer parameter, and the pointer parameter of each idle byte is assigned a different value. When the host computer 400 retrieves data, the access unit 3214 outputs the value of the pointer parameter. In this embodiment, the access unit 3214 can output the value of the pointer parameter through a print instruction. The access unit 3214 stores access program statements, and the access program statements are, for example, void GetMetaGapData() {printf("Meta GAP: %04X%04X%04X%04X %04X%04X%04X%04X", PLANE0_META_CORE_WORD_0, PLANE0_META_CORE_WORD_1, PLANE0_META_CORE_WORD_2, PLANE0_META_CORE_WORD_3, PLANE1_META_CORE_WORD_0, PLANE1_META_CORE_WORD_1, PLANE1_META_CORE_WORD_2, PLANE1_META_CORE_WORD_3);}. In the compilation stage, the assignment and output of the macro definition instruction are completed, and the third address can be obtained according to the value of the pointer parameter. After obtaining the third address, the host computer 400 directly reads the corresponding data from the third address. In this embodiment, the third address does not need to be recorded, and the third address is obtained by only using the parameter value while bypassing the memory 220. This not only improves the storage idle utilization rate of the memory 220, but also allows data to be retrieved from the memory 220 without increasing the burden on the memory 220.

[0042] See also Figures 2 to 4 As shown, before the control firmware 321 runs, the host computer 400 reads the program statements in the control firmware 321, and uses error checking and correction (ECC) to check the program statements in the control firmware 321. When the program statements are correct, the control firmware 321 is directly run in the flash memory chip 300, specifically, the program statements in the control firmware 321 are executed. The error correction code obtained by the error checking and correction can be stored in the error correction data storage area 333. It should be noted that the error checking and correction process is executed by the processor 210 in the main controller 200, and can be specifically executed by the error correction module 211 in the processor 210. The error correction module 211 can obtain the error correction code by the verification method of the low-density parity check code. The present invention does not limit the specific working algorithm of the error correction module 211.

[0043] See also Figure 1 and Figure 6As shown, the present invention provides a control method for a storage device 100. The control method for the storage device 100 includes steps S10 to S30.

[0044] Step S10, when reading data from the main data storage area, write the main data into the mapped storage area in a byte-aligned writing manner, set the address of the main data storage area to a first address, and set the address of the mapped storage area to a second address.

[0045] Step S20: Obtain the free bytes of the mapped storage area, and set the address of the free bytes as the third address.

[0046] Step S30: When the host computer reads and writes user data, the control firmware is run in the flash memory chip, and the user data is allowed to be written to or read from the third address.

[0047] See also Figure 1 and Figure 6 As shown, in one embodiment of the present invention, in step S10, the byte alignment writing mode refers to aligning the main data storage area 332 and the mapping storage area 221 according to the preset alignment byte number. The total number of bytes of the mapping storage area 221 is an integer multiple of the preset alignment byte number. When editing the main data of the main data storage area 332, the main data is written into the mapping storage area 221, and an idle byte is formed. In step S20, the address of the idle byte is obtained as the third address. In this embodiment, in the design stage, according to the address of the flash plane, the type of storage area, the address of the core word area 330, the pointer parameter, and the third address, a macro definition instruction is formed and stored in the macro definition instruction storage module 3211. In the initialization state, the pointer parameter in the macro definition instruction is assigned to null. In step S30, the macro definition instruction is called and compiled, the pointer parameter is assigned, and the pointer parameter value of each mapping storage area 221 is output. According to the pointer parameter value of the mapping storage area 221, the corresponding third address is accessed. When the host computer 400 reads and writes user data, the third address can be accessed by compiling a macro definition instruction.

[0048] The present invention provides a storage device, which includes a flash memory chip, a memory and a control firmware. The flash memory chip is electrically connected to a host computer, a storage block of the flash memory chip is marked as a data block or a code block, and a storage page of the storage block includes multiple core word areas, the core word area includes a main data storage area and a user data storage area, and the address of the main data storage area is a first address. The memory is electrically connected to the host computer and the flash memory chip, and the memory includes multiple mapping storage areas. When the main data is read out from the flash memory chip, the main data is stored in the mapping storage area. In the mapping storage area, the storage address of the main data is a second address, and the free bytes of the mapping storage area are a third address. The control firmware is stored in the code block. When the host computer reads and writes user data, the control firmware runs in the flash memory chip and allows user data to be written to a third address or read from a third address. The present invention can process idle space in the memory, thereby improving the space utilization of the memory. And according to the storage device and the control method thereof provided by the present invention, it is possible to directly address the dynamic fragmented space of the memory without occupying excess space, which not only improves the utilization of the memory, but also ensures the storage performance of the memory.

[0049] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A storage device, characterized in that: include: A flash memory chip is electrically connected to a host computer, a storage block of the flash memory chip is marked as a data block or a code block, a storage page of the storage block includes a plurality of core word areas, the core word areas include a main data storage area and a user data storage area, and an address of the main data storage area is a first address; A memory, electrically connected to the host computer and the flash memory chip, the memory comprising a plurality of mapping storage areas, when the main data is read out from the flash memory chip, the main data is stored in the mapping storage area, in the mapping storage area, the storage address of the main data is the second address, and the free bytes of the mapping storage area are the third address, wherein the free bytes are bytes that are free in the memory due to the byte alignment rule after the main data is stored in the memory, wherein the total number of bytes of the mapping storage area is an integer multiple of a preset number of alignment bytes, the initial address of the third address has an address offset compared to the initial address of the second address, and the address offset is the sum of the total number of bytes of the interval flash plane, the total number of bytes of the interval mapping storage area and the number of bytes of the main data storage unit, wherein the interval flash plane is all flash planes before the flash plane where the third address is located, and the interval mapping storage area is all mapping storage areas before the mapping storage area where the third address is located; as well as The control firmware is stored in the code block. When the host computer reads and writes user data, the control firmware runs in the flash memory chip and allows the user data to be written into the third address or read out from the third address.

2. A storage device according to claim 1, characterized in that: The user data storage area stores user data, and the main data storage area stores hardware error correction data of the flash memory chip and bad block management data of the flash memory chip.

3. A storage device according to claim 1, characterized in that: The control firmware includes a macro definition storage module, in which multiple macro definition instructions are stored. The macro definition instructions include an instruction name, a flash plane address of the flash memory chip, a storage area type in the flash memory chip, an address of the core word area, a pointer parameter and the third address, wherein the third address is a free byte address in the mapped storage area associated with the core word area.

4. A storage device according to claim 3, characterized in that: The control firmware includes an assignment unit. When the host computer calls the third address, the assignment unit assigns values ​​to the pointer parameters of the plurality of mapped storage areas, wherein the pointer parameters of the plurality of mapped storage areas are different.

5. A storage device according to claim 4, characterized in that: The control firmware includes an access unit, which is electrically connected to the host computer and the assignment unit. The access unit stores access program statements, which run in the flash memory chip, output the value of the pointer parameter, and output the third address related to the pointer parameter to the host computer according to the macro definition instruction.

6. A storage device according to claim 3, characterized in that: The storage device includes a processor, and the processor includes an error correction module. When the host computer edits the data at the third address, before compiling the macro definition instruction, the error correction module reads the macro definition instruction and corrects the error of the macro definition instruction.

7. A storage device according to claim 1, characterized in that: The addresses of the multiple mapped storage areas are continuous, and in the mapped storage areas, the second addresses are continuous, and in the memory, the first addresses of the multiple mapped storage areas are the initial addresses of the second addresses, wherein the initial addresses of the second addresses are preset addresses.

8. A storage device according to claim 1, characterized in that: The control firmware comprises a data writing control module, in which a preset number of alignment bytes is stored, and the total number of bytes in the mapping storage area is a multiple of the number of alignment bytes.

9. A method for controlling a storage device, based on the storage device according to claim 1, characterized in that: The following steps are involved: When reading data from the main data storage area, the main data is written into the mapping storage area according to the byte alignment writing mode, the address of the main data storage area is set to the first address, and the address of the mapping storage area is set to the second address; Obtaining free bytes of the mapped storage area, and setting the address of the free bytes to a third address; and When the host computer reads and writes user data, the control firmware runs in the flash memory chip and allows the user data to be written to the third address or read from the third address.

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