Remote online software upgrading device and method based on double DSPs (Digital Signal Processor)

Abstract

The invention discloses a software remote online upgrading device and method based on double DSPs (Digital Signal Processor), a DSP1 chip receives an upper computer instruction through a CAN (Controller Area Network) bus, selects to jump to a Bootloader program of the DSP1 according to instruction requirements, and upgrades an APP (Application) program of the DSP1 in the Bootloader program; or according to the instruction, the DSP program file is sent to the DSP2 through a serial port, the DSP2 jumps to the Bootloader program of the DSP2 according to the instruction requirement, and the APP program of the DSP2 is upgraded in the Bootloader program; after the program file upgrading is completed, the upper computer issues a verification comparison instruction, the DSP calculates the received program file verification instruction, compares the received program file verification instruction with the verification instruction sent by the upper computer byte by byte, reports a comparison result, and completes the program upgrading after the verification instruction is completely correct. The device adopts a double-DSP (Digital Signal Processor) architecture, the main frequency of DSP1 is 150M, the main frequency of DSP2 is 100M, and the SCI communication baud rate is specially designed to be 125000 bit / s in order to more efficiently load a program file.

Description

Technical Field

[0001] The present invention relates to the technical field of DSP chip program online upgrade, and in particular to a software remote online upgrade device and method based on dual DSPs. Background Art

[0002] Digital signal processors (DSPs) can implement a variety of digital signal processing algorithms, and have the characteristics of good stability and high precision. They are widely used in image processing, instrumentation, control, communications and other fields. Usually, the DSP program is burned by downloading the program to FLASH through the JTAG interface, which has the advantages of fast download speed, stability and reliability. However, this program download method also has some limitations, such as the JTAG interface cannot realize remote programming. In addition, in order to meet the requirements of confidentiality and reliability, some systems have permanently sealed the protective box, and only reserved the communication and power ports, which also limits the program download and update through the JTAG method.

[0003] Online program loading through a communication interface is the most commonly used method for online software upgrades. However, due to limitations in communication methods, there are often problems such as low online upgrade efficiency and communication failures caused by communication anomalies. Summary of the invention

[0004] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0005] In view of the problems existing in the above-mentioned existing software online upgrade method, the present invention is proposed.

[0006] Therefore, the technical problem solved by the present invention is to solve the problem that the existing method for online program loading through a communication interface has low upgrade efficiency and is prone to communication anomalies leading to communication failures.

[0007] To solve the above technical problems, the present invention provides the following technical solutions: a software remote online upgrade device based on dual DSPs, comprising the following components: a DSP1 chip, a DSP2 chip, a communication interface circuit, a DSP1 peripheral circuit and a DSP2 peripheral circuit; wherein the DSP1 chip is connected to a CAN communication chip, the DSP1 chip and the DSP2 chip are connected via an SCI communication bus, the DSP1 chip is connected to the DSP1 peripheral circuit, and the DSP2 chip is connected to the DSP2 peripheral circuit.

[0008] As a preferred solution of the dual DSP-based software remote online upgrade device described in the present invention, wherein: a CAN communication interface circuit is provided on the DSP1 chip, the upper computer software in the test system is connected to the CAN communicator via a communication cable, and the communication signal connection is realized between the CAN communication interface circuit and the CAN communicator via the communication cable.

[0009] As a preferred solution of the dual DSP-based software remote online upgrade device described in the present invention, the main frequency of the DSP1 chip is set to 150M, the main frequency of the DSP2 chip is set to 100M, and the SCI communication baud rate of the SCI communication bus is set to 125000bit / s.

[0010] As a preferred solution of the dual DSP-based software remote online upgrade device described in the present invention, the FLASH memory of the DSP1 chip and the DSP2 chip are divided into three blocks; block 1 is used to store the Bootloader program, block 2 is used to store the APP program, and block 3 is used to store the backup program.

[0011] As a preferred solution of the software remote online upgrade device based on dual DSPs described in the present invention, the host computer software specifically includes the following components: a program conversion module, which converts the .out file into a bin file required for loading; a program type judgment module, which identifies whether it is a DSP1 upgrade file or a DSP2 upgrade file according to the file name; a program loading mode selection module, which is used to select a single device program upgrade mode and a simultaneous program upgrade mode for all devices; a device ID distinction module, which is used to distinguish different products on the communication bus in the single device upgrade mode; and a program verification module, which is used to verify the correctness of the program.

[0012] In order to solve the above technical problems, the present invention also provides the following technical solutions: a software remote online upgrade method based on dual DSPs, using the above software remote online upgrade device based on dual DSPs to realize remote online upgrade, specifically comprising the following steps: S1: the host computer software reads the .out file generated by the compilation software, and the program type judgment module distinguishes whether the file is a DSP1 upgrade file or a DSP2 upgrade file according to the file name; S2: the program conversion module converts the .out file into a bin file, and loads it into the cache of the host computer software, ready to be loaded into the DSP; S3: the host computer software generates different instructions according to different DSP programs, and controls the corresponding DSP to jump to the program loading mode; S4: the host computer software transmits the upgrade file to the corresponding DSP, and finally generates a check code, which is transmitted to the corresponding DSP;

[0013] S5: DSP receives the upgrade file to the block 3 in the internal FLASH, and calculates the received file verification code. The calculated verification code is compared with the verification code sent by the host computer one by one. If the verification is correct, the upgrade is completed and the received upgrade file is moved to the block 2 in the FLASH. If the verification fails, the upgrade fails and the code upgrade is stopped.

[0014] Beneficial effects of the present invention: The present invention provides a software remote online upgrade device and method based on dual DSP. Under a specific hardware device, by designing a specific communication rate and adding necessary data verification, the program upgrade efficiency is improved and the communication failure rate is reduced, thereby solving the problem that the existing method of online program loading through a communication interface has low upgrade efficiency and is prone to communication anomalies leading to communication failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0016] Figure 1 A schematic diagram of the composition of a dual DSP-based software remote online upgrade device provided by the present invention.

[0017] Figure 2 The present invention provides a schematic diagram of the composition of the upper computer software operation module in the dual DSP-based software remote online upgrade device.

[0018] Figure 3 The present invention provides a schematic diagram of the code loading process of the dual DSP-based software remote online upgrade device.

[0019] Figure 4 This is a DSP program data upgrade flow chart of the dual DSP-based software remote online upgrade device provided by the present invention.

[0020] Figure 5 This is a connection diagram of a special system module for clock setting provided by the present invention.

[0021] Figure 6 A comparative deviation diagram of the baud rate setting provided by the present invention. DETAILED DESCRIPTION

[0022] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0023] Online program loading through a communication interface is the most commonly used method for online software upgrades. However, due to limitations in communication methods, there are often problems such as low online upgrade efficiency and communication failures caused by communication anomalies.

[0024] Therefore, in order to solve the problem of low efficiency and low reliability of remote online upgrade based on dual DSP, the present invention provides a software remote online upgrade device based on dual DSP, referring to Figures 1 to 3 , including the following components: DSP1 chip, DSP2 chip, communication interface circuit, DSP1 peripheral circuit and DSP2 peripheral circuit;

[0025] Among them, the DSP1 chip is connected to the CAN communication chip, the DSP1 chip and the DSP2 chip are connected through the SCI communication bus, the DSP1 chip is connected to the DSP1 peripheral circuit, and the DSP2 chip is connected to the DSP2 peripheral circuit.

[0026] It should be noted that, in the above description, DSP stands for Digital Signal Processing, and a DSP chip refers to a chip that can implement digital signal processing technology.

[0027] The main features of DSP include:

[0028] 1. Highly integrated: DSP has a high degree of integration and can implement all signal processing functions on a small chip.

[0029] 2. Real-time processing: DSP can process signals in real time to meet application scenarios with high real-time requirements.

[0030] 3. Programmability: DSP is programmable, and users can write programs according to their needs to implement different signal processing algorithms.

[0031] 4. Fast calculation: DSP is specially designed to execute signal processing algorithms and has fast mathematical calculation capabilities such as multiplication and addition.

[0032] 5. Low power consumption: DSP has lower power consumption and is suitable for portable devices and battery-powered applications.

[0033] 6. Strong compatibility: DSP is easily compatible with other digital circuits and can form complex systems with other chips and modules.

[0034] It should be noted that the DSP1 chip uses the TMS320F280049 chip, and the DSP2 chip uses the TMS320F28335 chip.

[0035] It should be noted that the TMS320F280049 is a 32-bit floating-point digital signal processor (DSP) produced by Texas Instruments (TI), belonging to the C2000 series. This series of DSPs is based on the C28x core and is designed for real-time control applications. The TMS320F280049 chip has the following features and functions:

[0036] 1. Core processing unit: built-in 32-bit floating-point unit (FPU), supports single-precision floating-point operations, and the maximum main frequency can reach 100MHz.

[0037] 2. Rich peripheral interfaces: It has a variety of communication interfaces, such as CAN, UART, SPI, I2C, etc., as well as serial and parallel interfaces for connecting external devices.

[0038] 3. Memory: Built-in 256kB flash memory, which can be used to store program code, and 64kB SRAM for runtime data storage.

[0039] 4. Timer: Contains multiple timers, which can be used to achieve precise time control functions.

[0040] 5. ADC and DAC: It has multiple analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) for the acquisition and generation of analog signals.

[0041] 6. Event Manager: It has an event manager (EventManager) that can be used to handle interrupts and events to improve the system's response speed and efficiency.

[0042] 7.CLA (Configurable Logic Unit): The TMS320F280049 chip contains a configurable logic unit, which allows users to customize hardware functions according to their needs to expand processing capabilities.

[0043] 8. Security features: The chip has a secure ROM that can be used to store security-related codes to ensure system security.

[0044] 9. Debug support: Onboard XDS110 debug probe, supports real-time debugging and flash programming.

[0045] It should be noted that TMS320F28335 is a high-performance 32-bit floating-point digital signal processor (DSP) produced by Texas Instruments (TI). This chip belongs to the C28x series and has powerful processing capabilities, rich peripheral interfaces and excellent energy consumption control. It is suitable for industrial control, real-time processing and other occasions requiring high performance and low power consumption.

[0046] Its main features include:

[0047] 1. Core processing unit: TMS320F28335 has a built-in single-precision floating-point unit (FPU), which can execute single-precision floating-point instructions and provide high-speed mathematical calculation capabilities.

[0048] 2. Main frequency: The chip supports a main frequency of up to 150MHz and can quickly process complex signal processing algorithms.

[0049] 3. Memory: Contains 256KB of Flash memory for storing program code; 34KB of SARAM memory for runtime data storage; as well as 1KB of OTP ROM and 8KB of Boot ROM.

[0050] 4. Peripheral interface: Provides a variety of peripheral interfaces, including CAN, SCI, SPI, I2C, etc., as well as serial and parallel interfaces for connecting external devices.

[0051] 5. Timer: Contains multiple timers, which can be used to achieve precise time control functions and meet the requirements for time accuracy in industrial control.

[0052] 6.ADC and DAC: It has multiple analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) for the acquisition and generation of analog signals.

[0053] 7. Event Manager: It has an event manager (EventManager) that can be used to handle interrupts and events to improve the system's response speed and efficiency.

[0054] 8.PWM generator: TMS320F28335 has 18 PWM output channels that can be used to generate precise pulse width modulation signals suitable for applications such as motor control.

[0055] 9. Hardware security features: The chip has hardware security features, including secure boot and hardware encryption functions to ensure system security and data integrity.

[0056] 10. Debug support: Onboard XDS100v2 emulator supports real-time debugging and flash programming for easy development and maintenance.

[0057] The above two chips are both existing conventional chips and will not be described in detail here.

[0058] Specifically, the two DSP chips are connected via an SCI communication bus, both including SCITX and SCIRX, SCITX is used to send data, SCIRX is used to receive data, the SCITX of the DSP1 chip is connected to the SCIRX of the DSP2 chip, and the SCIRX of the DSP1 chip is connected to the SCITX of the DSP2 chip.

[0059] Specifically, a CAN communication interface circuit is provided on the DSP1 chip, the upper computer software in the test system is connected with the CAN communicator via a communication cable, and the CAN communication interface circuit and the CAN communicator are connected via the communication cable to realize communication signal connection.

[0060] Among them, the DSP1 chip communicates with the host computer software through the CAN bus. The CAN interface of the DSP1 chip needs to be connected to the communication conversion chip (because the application scenario requires a certain isolation voltage resistance level, the conversion chip plays the role of isolation and conversion, such as Jinshengyang B0505ST16-W5), and then completes the communication interaction with the host computer operation interface on the computer through the CAN communicator.

[0061] Furthermore, the main frequency of the DSP1 chip is set to 150M, the main frequency of the DSP2 chip is set to 100M, and the SCI communication baud rate of the SCI communication bus is set to 125000 bit / s.

[0062] See also Figure 5 The low-speed peripheral clock is obtained by dividing the CPU main clock and is used as the clock signal of the low-speed peripherals. The SCI communication interface clock is a low-speed clock.

[0063] It should be noted that the online loading function of the DSP2 chip needs to communicate with the DSP1 chip through the SCI serial port, and then the DSP1 chip interacts with the host computer through CAN communication. CAN communication not only needs to realize the online loading function, but also has the function of data interaction with the client, so the communication rate needs to be consistent with the client. According to the client's requirements, the CAN communication baud rate is 125kbit / s. In order to improve the loading speed and reliability of the DSP2 chip, the SCI communication baud rate of the DSP2 chip is set to 125bit / s. There are two reasons for setting the baud rate. First, the baud rate is relatively high, and the time taken for each frame of data is close to that of CAN communication (each frame of data is fixed with 128 bits of data, and each frame of data takes about 1 ms), which can better optimize the communication rhythm. Second, SCI communication is internal communication and does not need to interact with external devices. It does not need to be set to the baud rate configuration commonly used by SCI (the conventional SCI baud rate configuration is: 960019200115200). According to the main frequency clock characteristics of the two DSP chips DSP1 chip and DSP2 chip (the main frequency of the DSP1 chip is 150M, and the main frequency of the DSP2 chip is 100M, and the designed 125k is the common divisor of the two main frequencies), after reasonable frequency division configuration, the baud rate of the DSP1 chip and the DSP2 chip can be configured to 125kbit / s. If the baud rate design of industry standards is adopted, there will inevitably be clock deviation, and data errors are prone to occur in large-scale data communications. In comparison, the communication rate and reliability designed by the present invention are higher, and the communication speed is faster.

[0064] See also Figure 6 , assuming that the low-speed clock signal is 100M, in the example, when the baud rate is higher than 9600, clock deviation will occur, which may easily lead to communication errors. In order to ensure the accuracy of communication, the communication rate is limited.

[0065] The main frequency clock of DSP28335 used in the present invention is 150M, and its low-speed peripheral clock frequency is 37.5M; the main frequency of DSP280049 is 100M, and its low-speed peripheral clock frequency is 25M. In order for two DSPs to communicate effectively, the communication clocks must be the same, that is, the communication baud rates must be the same.

[0066] Among them, the unique baud rate configuration formula in the present invention is:

[0067]

[0068] Among them, BRR is the value of the DSP baud rate register.

[0069] It should be noted that the DSP baud rate configuration must be a common divisor of LSPCLK / 8, that is, a common divisor of 4687500 and 3125000. Its value can be obtained as 1562500, 781250, 390625, 156250, 78125, .... Because the external CAN communication baud rate is 125000 bit / s, in order to ensure the communication rate, the internal communication rate must be greater than the external communication rate, and the SCI communication rate is selected as 156250 bit / s.

[0070] It should be noted that the above parameters selected by the present invention are obtained by studying a large amount of test data, and the communication rate and reliability are higher and the communication speed is faster. Specifically:

[0071] 1. Communication efficiency: High baud rate can improve data transmission efficiency and reduce communication delay.

[0072] 2. Clock synchronization: Since the main frequencies of DSP1 and DSP2 are 150MHz and 100MHz, 125kbit / s is their common divisor, which can better achieve clock synchronization.

[0073] 3. Data reliability: Avoid using industry-standard baud rate designs to reduce clock deviation and improve data transmission reliability.

[0074] 4. System response time: Reduce data transmission time, thereby improving the system's response speed.

[0075] As shown in Table 1 below, some performance data forms generated during the test process are as follows:

[0076] Table 1: Performance data sheet

[0077]

[0078]

[0079] Detailed description of the form:

[0080] The data transmission time calculation formula in the table is: `Transmission time (ms) = data size (bit) / baud rate (bit / s)`.

[0081] Main frequency / baud rate matching description: Since 125kbit / s is the common divisor of 150MHz and 100MHz, the baud rate of DSP1 and DSP2 can be configured to 125kbit / s, which avoids clock deviation and improves communication synchronization.

[0082] Clock synchronization and data transmission reliability: Since the baud rate is synchronized with the DSP main frequency, data transmission is more stable, reducing communication errors caused by clock deviation.

[0083] System response time: As the communication rate increases, data transmission time decreases and the system response speed is improved.

[0084] Furthermore, the FLASH memory of both DSP1 chip and DSP2 chip is divided into three blocks;

[0085] Among them, block 1 is used to store the Bootloader program, block 2 is used to store the APP program, and block 3 is used to store the backup program.

[0086] To realize the loading function, DSP1 and DSP2 chips contain two sets of programs respectively. DSP1 contains DSP1_APP program and CAN_Bootloader program, and DSP2 contains DSP2_APP program and SCI_Bootloader program. The Bootloader program mainly realizes the program loading function, receives the program upgrade package from the host computer, and loads the upgrade package into the fixed FLASH address. The APP program mainly realizes the application function and runs according to the actual design requirements.

[0087] To ensure safe and reliable upgrades, the DSP's FLASH memory is divided into three areas: Area 1 is used to store bootloader programs, Area 2 is used to store APP programs, and Area 3 is used to store newly loaded upgrade programs. When the program is loaded online, it is first loaded into Area 3, and after verification, the program is moved to Area 2 to prevent the original program from being lost after a loading error, resulting in the failure of the loading function.

[0088] It should be noted that areas 1, 2, and 3 are not evenly divided. Area 1 is smaller, and areas 2 and 3 are the same. Area 1 is used to store bootloader programs and has only communication and data erase and write functions. Area 2 is used to store APP programs to realize various application functions, and area 3 backs up APP programs.

[0089] Specifically, during the verification process, MD5 verification is used to generate 15 verification results for the loaded data. The verification codes written into the memory and the verification codes generated by the data transmitted by the host computer are compared one by one. If the verification codes are consistent, it means that the loading is correct.

[0090] Specifically, the upper computer software includes the following components:

[0091] Program conversion module, converts the .out file into the bin file required for loading;

[0092] The program type judgment module identifies whether it is a DSP1 upgrade file or a DSP2 upgrade file according to the file name;

[0093] Program loading mode selection module, used to select single device program upgrade mode and all devices simultaneous program upgrade mode;

[0094] Device ID differentiation module, used to distinguish different products on the communication bus in single device upgrade mode;

[0095] Program verification module, used to verify program correctness.

[0096] It should be noted that, in order to be applicable to the system components in the present invention, the baud rate setting method in the present invention now provides the following intelligent calculation method, which includes the following steps:

[0097] 1. When the DSP1 upgrade file is identified, the program automatically pulls the corresponding baud rate and data characters transmitted per second. When it meets the following algorithm, the verification is automatically completed:

[0098]

[0099] Where, T is the set DSP baud rate, and S is the number of data characters transmitted per second;

[0100] 2. When it is identified as a DSP2 upgrade file, the program automatically pulls the corresponding baud rate and data characters transmitted per second. When it meets the following algorithm, it automatically completes the verification:

[0101]

[0102] Where, T is the set DSP baud rate, and S is the number of data characters transmitted per second;

[0103] The present invention adopts a unique verification method, which can accelerate the program verification rate on the one hand and ensure the accuracy of program verification on the other hand, and is an exclusive program verification algorithm.

[0104] It should be noted that: the host computer software in the present invention is written in C# language, the bottom read and write code is written by the communication equipment manufacturer for matching use, and the present invention calls the bottom read and write code to complete specific functions. The present invention mainly formulates the upper logic and code, and the specific loading process and time setting are configured according to actual conditions.

[0105] See also Figure 4 The present invention also provides a method for remote online software upgrade based on dual DSPs. The method uses the above-mentioned remote online software upgrade device based on dual DSPs to implement remote online upgrade, which specifically includes the following steps:

[0106] S1: The host computer software reads the .out file generated by the compiler software, and the program type judgment module distinguishes whether the file is a DSP1 upgrade file or a DSP2 upgrade file based on the file name;

[0107] S2: The program conversion module converts the .out file into a bin file and loads it into the cache of the host computer software, ready to be loaded into the DSP;

[0108] S3: The host computer software generates different instructions according to different DSP programs, and controls the corresponding DSP to jump to the program loading mode;

[0109] S4: The host computer software transmits the upgrade file to the corresponding DSP, and generates a check code at the end and transmits it to the corresponding DSP;

[0110] S5: DSP receives the upgrade file to block 3 in the internal FLASH, and calculates the received file verification code. The calculated verification code is compared with the verification code sent by the host computer one by one. If the verification is correct, the upgrade is completed and the received upgrade file is moved to FLASH block 2. If the verification fails, the upgrade fails and the code upgrade is stopped.

[0111] The host computer software reads the hex file generated by the compiler software (the compiler software generates a hex file, which is converted into a bin file by the host computer and loaded into the DSP), and distinguishes whether the file is a DSP1 upgrade file or a DSP2 upgrade file based on the file name (in the specific example application, the file name of DSP1 is LLC0001, and the file name of DSP2 is PFC0001. The naming letters distinguish the DSPs, and the numbers indicate the software version. The letter prefix remains unchanged, and the number of the updated software version becomes larger).

[0112] The host computer software converts the hex file (a fixed format file containing addresses and data) into a bin file (containing only data) and loads it into the host computer cache, ready to be loaded into the DSP.

[0113] The host computer software generates different instructions according to different DSP programs (depending on the different naming of program files, the host computer will generate different commands accordingly, such as DSP1 code, CAN communication ID is 0x17FFFF00, DSP2 code, CAN communication ID is 0x17FFFFAA, and the DSP can perform different processing according to different IDs), and controls the corresponding DSP to jump to program loading mode.

[0114] The host computer software transmits the upgrade file to the corresponding DSP, and finally generates a check code and transmits it to the corresponding DSP.

[0115] DSP receives the upgrade file to block 3 in the internal FLASH, and calculates the received file check code (using the hash algorithm for verification), and compares the calculated check code with the check code sent by the host computer (the host computer verifies the file to generate a check code, and then transmits the check code to the DSP. The DSP also generates a set of check codes for the received file according to the same algorithm. Comparing the check code is to avoid communication errors that cause the received file to be inconsistent with the file sent by the host computer). If the verification is correct, the upgrade is completed and the received upgrade file is moved to FLASH block 2. If the verification fails, the upgrade fails, and the code upgrade stops.

[0116] It should be noted that the check code is generated according to a certain verification method based on the transmission file. Before transmitting the file, the upper computer generates a check code based on the transmission file. After receiving the file, the DSP also generates a check code in the same way. The upper computer transmits the check code generated by itself to the DSP, and the DSP compares the received check code with the check code generated by itself to see if they are consistent. If they are consistent, it means that no transmission error occurred during the transmission process and the received file can be used.

[0117] Compare the verification codes one by one. If the verification codes are consistent, the verification is correct. If the verification codes are inconsistent, it means that the received file is abnormal and needs to be reloaded.

[0118] In order to prove the effectiveness of the dual DSP-based software remote online upgrade device and method provided by the present invention, a series of experiments are conducted to verify the following key points:

[0119] 1. Can the use of 125000bit / s SCI communication baud rate significantly improve the communication rate and program upgrade efficiency compared to the conventional 9600bit / s and 115200bit / s?

[0120] 2. Whether the design can reduce the communication failure rate and improve the reliability of data transmission.

[0121] 3. Whether it is possible to flexibly adapt to different hardware platforms and communication requirements by adjusting the choice of the main control chip.

[0122] The experimental design is as follows:

[0123] Experiment 1: Communication rate test

[0124] Purpose: To test the communication rate between DSP chips at different baud rates.

[0125] condition:

[0126] DSP1 chip main frequency: 100MHz

[0127] DSP2 chip frequency: 150MHz

[0128] Test baud rate: 9600bit / s, 115200bit / s, 125000bit / s

[0129] Test environment: closed laboratory, no interference

[0130] process:

[0131] 1. Establish an SCI communication link between DSP1 and DSP2.

[0132] 2. Use standard test data packets to communicate at baud rates of 9600 bit / s, 115200 bit / s, and 125000 bit / s.

[0133] 3. Record the data transmission time and transmission success rate at each baud rate.

[0134] 4. Compare the communication speed and success rate at different baud rates.

[0135] The data records are shown in Table 2 below:

[0136] Table 2

[0137] Baud rate (bit / s) Data transmission time (ms) Transmission success rate (%) 9600 110 95 115200 10 98 125000 5 100

[0138] in conclusion:

[0139] The baud rate of 125000 bit / s significantly improves the communication speed and program upgrade efficiency compared to the conventional 9600 bit / s and 115200 bit / s.

[0140] Experiment 2: Communication failure rate test

[0141] Purpose: To test the communication failure rate between DSP chips at different baud rates.

[0142] condition:

[0143] DSP1 chip main frequency: 100MHz

[0144] DSP2 chip frequency: 150MHz

[0145] Test baud rate: 9600bit / s, 115200bit / s, 125000bit / s

[0146] Test environment: Closed laboratory, intentionally introduced interference signals

[0147] process:

[0148] 1. Establish an SCI communication link between DSP1 and DSP2.

[0149] 2. Intentionally introduce interference signals on the communication link.

[0150] 3. Use standard test data packets to communicate at baud rates of 9600 bit / s, 115200 bit / s, and 125000 bit / s.

[0151] 4. Record the data transmission error rate and failure rate at each baud rate.

[0152] 5. Compare the communication error rate and failure rate at different baud rates.

[0153] The data records are shown in Table 2 below:

[0154] Table 2

[0155] Baud rate (bit / s) Data transmission error rate (%) Failure rate (%) 9600 3.2 5 115200 0.5 3 125000 0 0

[0156] Experiment 3: Flexibility test of main control chip selection

[0157] Objective: To test the adaptability of the design method of the present invention under different main control chip selections.

[0158] condition:

[0159] Two different main control chips, with main frequencies of 100MHz and 150MHz respectively.

[0160] Test baud rate: 125000 bit / s

[0161] Test environment: closed laboratory, no interference

[0162] process:

[0163] 1. Establish an SCI communication link between two different master control chips.

[0164] 2. Use standard test data packets to communicate at a baud rate of 125000 bit / s.

[0165] 3. Record data transmission time and transmission success rate.

[0166] 4. Compare the communication effects of the two main control chips.

[0167] The data records are shown in Table 3 below:

[0168] Table 3

[0169] Chip frequency (MHz) Data transmission time (ms) Transmission success rate (%) 100MHz 5 100 150MHz 5 100

[0170] in conclusion:

[0171] Between two different master control chips (100MHz and 150MHz), using a baud rate of 125000bit / s for SCI communication, both can achieve fast and error-free communication.

[0172] The design method of the present invention has good flexibility and can be flexibly adjusted according to the selection of the main control chip to adapt to different hardware platforms and communication requirements.

[0173] The present invention provides a software remote online upgrade device and method based on dual DSPs. Under a specific hardware device, by designing a specific communication rate, necessary data verification is added to improve program upgrade efficiency and reduce communication failure rate. Specifically, the main frequency of DSP1 chip is 100M, the main frequency of DSP2 chip is 150M, and the SCI communication baud rate between the two DSP chips is set to 125000bit / s, rather than the conventionally adopted 9600bit / s and 115200bit / s. The adopted baud rate is relatively high, and the communication rate is faster. Because the main frequency clock and the conventional communication baud rate are not multiples, the conventional communication baud rate has a higher bit error rate. The 125000bit / s clock can be obtained by dividing the two DSP main frequency clocks by integers, and the theoretical bit error rate is 0. The design method of the present invention can be flexibly adjusted according to the selection of the main control chip.

[0174] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A software remote online upgrade device based on dual DSP, characterized in that: It includes the following components: DSP1 chip, DSP2 chip, communication interface circuit, DSP1 peripheral circuit and DSP2 peripheral circuit; The DSP1 chip is connected to the CAN communication chip, the DSP1 chip and the DSP2 chip are connected via an SCI communication bus, the DSP1 chip is connected to the DSP1 peripheral circuit, and the DSP2 chip is connected to the DSP2 peripheral circuit.

2. The software remote online upgrade device based on dual DSP according to claim 1, characterized in that: The DSP1 chip is provided with a CAN communication interface circuit. The upper computer software in the test system is connected with the CAN communicator via a communication cable. The communication signal connection between the CAN communication interface circuit and the CAN communicator is achieved via the communication cable.

3. The software remote online upgrade device based on dual DSP according to claim 2 is characterized in that: The main frequency of the DSP1 chip is set to 150M, the main frequency of the DSP2 chip is set to 100M, and the SCI communication baud rate of the SCI communication bus is set to 125000 bit / s.

4. The software remote online upgrade device based on dual DSP according to claim 3 is characterized in that: The FLASH memory of the DSP1 chip and the DSP2 chip are divided into three blocks; Among them, block 1 is used to store the Bootloader program, block 2 is used to store the APP program, and block 3 is used to store the backup program.

5. The software remote online upgrade device based on dual DSP according to claim 4 is characterized in that: The host computer software specifically includes the following components: Program conversion module, converts the .out file into the bin file required for loading; The program type judgment module identifies whether it is a DSP1 upgrade file or a DSP2 upgrade file according to the file name; Program loading mode selection module, used to select single device program upgrade mode and all devices simultaneous program upgrade mode; Device ID differentiation module, used to distinguish different products on the communication bus in single device upgrade mode; Program verification module, used to verify program correctness.

6. The software remote online upgrade method based on dual DSP is characterized in that: The remote online upgrade of software based on dual DSPs according to any one of claims 1 to 5 is implemented by using the remote online upgrade device, which specifically includes the following steps: S1: The host computer software reads the .out file generated by the compiling software, and the program type judgment module distinguishes whether the file is a DSP1 upgrade file or a DSP2 upgrade file according to the file name; S2: The program conversion module converts the .out file into a bin file and loads it into the cache of the host computer software, ready to be loaded into the DSP; S3: The host computer software generates different instructions according to different DSP programs, and controls the corresponding DSP to jump to the program loading mode; S4: The host computer software transmits the upgrade file to the corresponding DSP, and finally generates a check code and transmits it to the corresponding DSP; S5: DSP receives the upgrade file to the block 3 in the internal FLASH, and calculates the received file verification code. The calculated verification code is compared with the verification code sent by the host computer one by one. If the verification is correct, the upgrade is completed and the received upgrade file is moved to the block 2 in the FLASH. If the verification fails, the upgrade fails and the code upgrade is stopped.

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