A register resource management method and related device

Abstract

The present application discloses a register resource management method and related devices, and relates to the field of computer technology. The register resource management method includes: obtaining a computing program; based on the computing program, obtaining multiple first computing instructions; based on each first computing instruction, obtaining multiple second computing instructions in each computing step; based on each second computing instruction, obtaining the maximum number of active register units in each computing step; based on the maximum number of active register units in each computing step, allocating registers to the computing program. The present application allocates registers to the computing program by determining the maximum number of units of registers that may be occupied during the execution of the computing program. Compared with the single branch pre-allocation method, which is prone to insufficient register allocation in the application scenario of ultra-long instruction words, the present application will not have the phenomenon of insufficient register allocation.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and specifically to a register resource management method and related devices. Background Art

[0002] Very Long Instruction Word (VLIW) is a very long instruction combination that connects many instructions together to increase the speed of operation. VLIW is instruction-level parallelism, hyperthreading is thread-level parallelism, and multi-core is chip-level parallelism. All three methods are effective ways to improve the parallel computing performance of computing devices. To maximize the potential of VLIW, the reasonable allocation of register resources becomes one of the decisive factors. The management of register resources is directly related to the smooth execution of instruction flow and the efficient allocation of computing resources.

[0003] It should be noted that, although the existing single branch pre-allocation method has shown initial success in alleviating register resource shortages, its limitations are becoming increasingly prominent when faced with the branch structure and variable execution paths of extremely complex computing programs in very long instruction words. Figure 4 As shown, Figure 4 It is a schematic diagram of the execution of computing instructions of a computing program, which has X1 to X5, a total of 5 computing instructions. The normal execution order of the computing program is to execute in sequence according to the order of computing instructions X1 to X5, and the single branch pre-allocation method allocates registers to the entire computing program based on the execution order of computing instructions X1 to X5, so that the number of allocated register units can meet the use of all computing instructions (the specific allocation method of the single branch pre-allocation method is shown in the specific implementation method). In the application scenario of very long instruction words, if the execution order of each computing instruction is not X1 to X5 due to software or hardware problems, it is very likely that the registers allocated to the computing program based on the single branch pre-allocation method are insufficient. If there are insufficient registers available during the execution of the computing program, it will cause a series of chain reactions such as unbalanced register allocation, increased risk of instruction overflow, and memory access bottlenecks, which seriously restricts the performance of the very long instruction word architecture in high-performance and high-load computing tasks. Summary of the invention

[0004] The purpose of the present application is to provide a register resource management method and related devices to solve the technical problem of unreasonable register allocation in the application scenario of very long instruction words.

[0005] To achieve the above objectives, this application provides the following technical solutions:

[0006] In a first aspect, the present application proposes a technical solution for a register resource management method, the register resource management method comprising:

[0007] Obtaining a computing program; the computing program is obtained based on a very long instruction word, the computing program includes a plurality of computing instructions, each computing instruction is executed respectively through a plurality of computing steps; the number of computing steps is the same as the number of computing instructions;

[0008] Based on the computing program, obtaining a plurality of first computing instructions; the first computing instruction is any computing instruction in the computing program;

[0009] Based on each first computing instruction, a plurality of second computing instructions in each computing step are obtained; the second computing instruction is any first computing instruction executable in the corresponding computing step;

[0010] Based on each second computing instruction, obtaining a maximum number of active register units in each computing step;

[0011] Registers are allocated to the computational procedure based on a maximum number of active register units within each computational step.

[0012] In a second aspect, the present application proposes a technical solution for a register resource management device, the register resource management device comprising:

[0013] A reading module, used for acquiring a computing program; the computing program is obtained based on a very long instruction word, the computing program includes a plurality of computing instructions, each computing instruction is executed respectively through a plurality of computing steps; the number of computing steps is the same as the number of computing instructions;

[0014] And, based on the computing program, obtaining a plurality of first computing instructions; the first computing instruction is any computing instruction in the computing program;

[0015] A processing module, configured to obtain a plurality of second computing instructions in each computing step based on each first computing instruction; the second computing instruction is any first computing instruction executable in the corresponding computing step;

[0016] and, based on each second computing instruction, obtaining a maximum number of active register units within each computing step;

[0017] And, allocating registers to the computing program based on a maximum number of active register units within each computing step.

[0018] In a third aspect, the present application proposes a technical solution for a register resource management system, the register resource management system comprising:

[0019] The reader obtains a computing program; the computing program is obtained based on a very long instruction word, the computing program includes a plurality of computing instructions, each computing instruction is executed respectively through a plurality of computing steps; the number of computing steps is the same as the number of computing instructions;

[0020] And, based on the computing program, obtaining a plurality of first computing instructions; the first computing instruction is any computing instruction in the computing program;

[0021] The processor obtains a plurality of second computing instructions in each computing step based on each first computing instruction; the second computing instruction is any first computing instruction executable in the corresponding computing step;

[0022] and, based on each second computing instruction, obtaining a maximum number of active register units within each computing step;

[0023] And, allocating registers to the computing program based on a maximum number of active register units within each computing step.

[0024] In a fourth aspect, the present application proposes a technical solution of a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the register resource management method as described in any one of the first aspects is implemented.

[0025] Compared with the prior art, the beneficial effects of this application are:

[0026] This application allocates registers for a computing program by determining the maximum number of units of registers that may be occupied during the execution of the computing program. Compared with the single branch pre-allocation method, which is prone to insufficient register allocation in the application scenario of very long instruction words, this application will not have insufficient register allocation. In other words, this application will not lead to a series of chain reactions such as register allocation imbalance, increased instruction overflow risk, and memory access bottlenecks caused by insufficient register allocation. It can alleviate the bottleneck of register resource allocation to the greatest extent and improve the execution efficiency of computing programs in the application scenario of very long instruction words. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A flowchart of a register resource management method proposed in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of the structure of a register resource management device proposed in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a register resource management system proposed in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of the execution flow of a computing program proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects (for example, the first calculation instruction and the second calculation instruction are respectively represented as different calculation instructions, and the others are similar), and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described here can be implemented in an order other than the content illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules does not have to be limited to those steps or modules that are clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The division of modules that appear in the embodiments of the present application is only a logical division. There may be other division methods when implemented in actual applications, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling between modules, and the communication connection can be electrical or other similar forms, which are not limited in the embodiments of the present application. Furthermore, the modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in multiple circuit modules, and the purpose of the embodiment of the present application can be achieved based on some or all of the modules according to actual needs.

[0032] Before understanding the embodiments of the present application, in the subsequent embodiments of the present application, the following Figure 4 The calculation program shown in the figure illustrates various embodiments in the present application. For ease of understanding, it is assumed that any one of the calculation instructions X1 to X5 only needs to occupy a unit number of registers when performing calculations. The corresponding register names are R1 to R5, respectively. Please refer to Table 1 and Table 3 for details. It should be noted that the present application is only based on Figure 4 The calculation program shown in the figure is used to illustrate various embodiments of the present application below, which does not mean that the register resource management method proposed in the present application is only applicable to the following embodiments. Figure 4 It should be understood that the register resource management method proposed in this application is applicable to Figure 4 Of course, in other computing programs, each computing instruction may also occupy more than one unit of registers, for example, two units or three units of registers, etc., which will not be listed in detail later.

[0033] In an embodiment of the present application, a unit number of registers may refer to one register (for example, an 8-byte, 16-byte, 32-byte or 64-byte register), or may refer to a group of registers consisting of multiple registers (for example, 2, 3 or 4 registers, etc.).

[0034] It should be clear that if Figure 4 As shown, Figure 4 The corresponding calculation program has 5 calculation instructions, that is, the calculation program needs 5 calculation steps to complete the calculation, and these five calculation steps are defined as calculation step 1 to calculation step 5. Under normal circumstances, calculation step 1 executes calculation instruction X1; calculation step 2 executes calculation instruction X2; calculation step 3 executes calculation instruction X3; calculation step 4 executes calculation instruction X4; calculation step 5 executes calculation instruction X5. According to the normal calculation process, the registers that each calculation step needs to occupy are shown in Table 1.

[0035] Table 1 Register occupancy table of normal program execution order

[0036]

[0037] It should be clear that, as can be seen from Table 1, in calculation step 1, register R1 needs to be occupied, while registers R2 to R5 do not need to be occupied. In calculation step 2, registers R1 and R2 need to be occupied, while registers R3 to R5 do not need to be occupied. Since calculation instruction X3 is the parent calculation instruction of calculation instruction X1 and calculation instruction X2, when calculation instruction X3 is executed, the occupation of registers R1 and R2 is released, that is, in calculation step 3, register R3 needs to be occupied, while registers R1, R2, R4 and R5 do not need to be occupied. In calculation step 4, registers R3 and R4 need to be occupied, while registers R1, R2 and R5 do not need to be occupied. Since calculation instruction X5 is the parent calculation instruction of calculation instruction X3 and calculation instruction X4, when calculation instruction X5 is executed, the occupation of registers R3 and R4 is released, that is, in calculation step 5, only register R5 needs to be occupied, while registers R1 to R4 do not need to be occupied.

[0038] It is easy to understand that based on Table 1, the number of register units required to be used in each calculation step can be obtained, specifically, as shown in Table 2.

[0039] Table 2. Table of the number of units occupied by registers in normal program execution order

[0040]

[0041] From Table 2, we can see that Figure 4The calculation program shown in the figure, under the normal program execution order, only needs to allocate 2 units of registers to the calculation program to meet the calculation requirements of the calculation program. The single branch pre-allocation method in the prior art is based on this principle. Figure 4 The calculation procedure shown allocates registers.

[0042] It should be clear that there is a one-to-one correspondence between the calculation steps and the calculation instructions. That is, each calculation step can only execute one calculation instruction. In other words, the number of calculation steps is equal to the number of calculation instructions. For example, in Figure 4 In the calculation program shown, there are 5 calculation instructions, so when the calculation program is executed, there are 5 calculation steps, which are not described here. It is easy to understand that each calculation step can be performed in parallel or in series, that is, in the embodiment of the present application, there is no restriction on the calculation steps of each calculation instruction.

[0043] Table 3 Register occupancy table in the application scenario of very long instruction words

[0044]

[0045] It should be noted that in the application scenarios of very long instruction words, such as Figure 4 The calculation program shown in Table 1 may not have the same calculation instructions as those shown in Table 1 in each calculation step. It is easy to understand that since calculation instructions X1 and X2 are sub-calculation instructions of calculation instruction X3, it is impossible to execute calculation instruction X3 before calculation instructions X1 and X2 are executed. Similarly, calculation instructions X3 and X4 are sub-calculation instructions of calculation instruction X5, that is, it is impossible to execute calculation instruction X5 before calculation instructions X3 and X4 are executed. In other words, in the application scenario of very long instruction words, such as Figure 4 In the calculation program shown, the calculation instruction that may be executed in calculation step 1 is any one of calculation instruction X1, calculation instruction X2 and calculation instruction X4; the calculation instruction that may be executed in calculation step 2 is any one of calculation instruction X1, calculation instruction X2 and calculation instruction X4; ..., and so on. Specifically, the registers occupied in each calculation step in the application scenario of the very long instruction word are shown in Table 3 above.

[0046] It should be clear that in the application scenario of very long instruction words, assuming that a single branch pre-allocation method is adopted as follows Figure 4The calculation program shown allocates 2 units of registers, and calculation step 1 executes calculation instruction X4, that is, register R4 is occupied, that is, one of the 2 allocated units of registers is occupied; then calculation step 2 will occupy the other of the two units of registers regardless of whether it executes calculation instruction X1 or calculation instruction X2. In other words, in calculation step 3, whether it executes calculation instruction X1 or calculation instruction X2, no register is available in the calculation step. If no register is available in the calculation step, it will trigger a series of chain reactions such as unbalanced register allocation, increased risk of instruction overflow, and memory access bottlenecks, which seriously restricts the performance of the very long instruction word architecture in high-performance and high-load computing tasks.

[0047] In order to solve the above technical problems, the present application proposes a register resource management method, which is applied to very long instruction word calculation. Figure 1 As shown, the register resource management method includes steps S100 to S500.

[0048] Step S100: Obtain a calculation program.

[0049] In this embodiment, the computing program is obtained based on the very long instruction word. It is easy to understand that obtaining the computing program contained therein based on the very long instruction word is a mature technology and will not be described in detail here. Generally, the computing program includes multiple computing instructions, and each computing instruction is executed separately through multiple computing steps, that is, the number of computing steps and computing instructions described below is the same.

[0050] Step S200: Based on the calculation program, a plurality of first calculation instructions are obtained.

[0051] In this embodiment, the first calculation instruction is any calculation instruction in the calculation program. Figure 4 The calculation program shown includes calculation instructions X1 to X5, a total of 5 calculation instructions. Figure 4 For example, the first calculation instruction may be any one of the calculation instructions X1 to X5. Figure 4 The calculation program shown includes a total of five first calculation instructions (ie, calculation instruction X1 to calculation instruction X5).

[0052] Step S300: Based on each first computing instruction, a plurality of second computing instructions in each computing step are obtained.

[0053] In this embodiment, the second calculation instruction is any first calculation instruction executable in the corresponding calculation step. Figure 4In the calculation program shown, any one of the calculation instructions X1, calculation instruction X2 and calculation instruction X4 can be executed in calculation step 1, that is, calculation instruction X1, calculation instruction X2 and calculation instruction X4 are the second calculation instructions corresponding to calculation step 1. In calculation step 2, if calculation step 1 executes calculation instruction X1, then the calculation instructions that can be executed in calculation step 2 are calculation instruction X2 and calculation instruction X4; if calculation step 1 executes calculation instruction X2, then the calculation instructions that can be executed in calculation step 2 are calculation instruction X1 and calculation instruction X4; if calculation step 1 executes calculation instruction X4, then the calculation instructions that can be executed in calculation step 2 are calculation instruction X1 and calculation instruction X2. In other words, the calculation instruction that can be executed in calculation step 2 is any one of the calculation instruction X1, calculation instruction X2 and calculation instruction X4. In other words, calculation instruction X1, calculation instruction X2 and calculation instruction X4 are the second calculation instructions corresponding to calculation step 2. In calculation step 3, if the calculation instructions executed by calculation step 1 and calculation step 2 are calculation instruction X1 and calculation instruction X2, then calculation step 3 can execute calculation instruction X3 and calculation instruction X4; if the calculation instructions executed by calculation step 1 and calculation step 2 are calculation instruction X1 and calculation instruction X4, then calculation step 3 can execute calculation instruction X2; if the calculation instructions executed by calculation step 1 and calculation step 2 are calculation instruction X2 and calculation instruction X4, then calculation step 3 can execute calculation instruction X1. In other words, the calculation instruction that can be executed by calculation step 3 is any one of calculation instruction X1 to calculation instruction X4. In other words, calculation instruction X1 to calculation instruction X4 are the second calculation instructions corresponding to calculation step 2. Multiple second calculation instructions of other calculation steps, and so on.

[0054] Step S400: Based on each second computing instruction, obtain the maximum number of active register units in each computing step.

[0055] It should be clear that in this embodiment, if Figure 4 The registers that may be active in each calculation step in the calculation program shown are shown in Table 3. That is to say, in the embodiment of the present application, the maximum number of active register units in each calculation step can be obtained based on the registers that may be active in each calculation step shown in Table 3. Specifically, in this embodiment, the maximum number of active register units in a calculation step is equal to the sum of the number of register units that need to be occupied when calculating each second calculation instruction in the calculation step. Based on this, the following Table 4 can be obtained from Table 3.

[0056] Table 4 Table of the number of units occupied by registers in the application scenarios of very long instruction words

[0057]

[0058] It is easy to understand that in this embodiment, if the number of registers allocated to the computing program can meet the storage requirements of all possible computing instructions, it will not cause insufficient registers when the computing program is executed. Figure 4 The calculation program shown allocates 4 units of registers. Therefore, no matter what calculation instructions are executed in each calculation step, there will be no phenomenon that no registers are available within the calculation step.

[0059] It should be noted that if a calculation step may execute a parent calculation instruction, it means that the child calculation instructions corresponding to the parent calculation instruction must be executed, that is, the calculation step must not execute any child calculation instruction corresponding to the parent calculation instruction. Similarly, if a calculation step may execute any child calculation instruction of a parent calculation instruction, it means that the child calculation instructions corresponding to the parent calculation instruction must not be executed, that is, the calculation step must not execute the parent calculation instruction.

[0060] like Figure 4 As shown, since calculation instruction X3 is the parent calculation instruction of calculation instruction X1 and calculation instruction X2, that is to say, if any one of calculation instruction X1 and calculation instruction X2 is not executed, calculation instruction X3 cannot be executed. As shown in Table 3, in calculation step 3, if calculation step 1 and calculation step 2 do not execute any one of calculation instruction X1 and calculation instruction X2, calculation step 3 cannot execute calculation instruction X3. If calculation instruction X3 is not executed in calculation step 3, only registers R1, R2 and R4 can be occupied (that is, 3 units of registers are occupied). In calculation step 3, if calculation step 1 and calculation step 2 have executed calculation instruction X1 and calculation instruction X2, calculation step 3 can execute calculation instruction X3 or execute calculation instruction X4. If calculation step 3 executes calculation instruction X3, registers R1 and R2 must be released, that is, calculation step 3 only occupies register R3 (that is, occupies 1 unit of register); if calculation step 3 executes calculation instruction X4, it may only occupy registers R1, R2, and R4 (that is, occupy 3 units of register). In other words, in this embodiment, calculation step 3 only needs to use 3 units of registers at most. If 4 units of registers are allocated to calculation step 3, register resources will be wasted.

[0061] In order to improve the utilization efficiency of registers and avoid wasting register resources due to too many registers allocated to the computing program, in one embodiment of the present application, step S400, based on each second computing instruction, obtains the maximum number of active register units in each computing step, including step S410.

[0062] Step S410: Acquire each calculation step as each first calculation step.

[0063] In this embodiment, the first calculation step is any one of the calculation steps. For each first calculation step, steps S420 to S480 are executed to obtain the maximum number of active register units in each first calculation step (ie, each calculation step).

[0064] In this embodiment, the first calculation step is any one of the calculation steps. Figure 4 For example, the calculation program includes 5 calculation instructions, that is, the calculation program requires 5 calculation steps to complete. In other words, Figure 4 In the example embodiment, the first calculation step may be any one of calculation steps 1 to 5.

[0065] Step S420: based on each second calculation instruction in a first calculation step, obtain the first register unit quantity.

[0066] In this embodiment, the number of first register units in a calculation step (ie, the first calculation step) is equal to the sum of the number of register units required for calculation of each second calculation instruction in the calculation step. The specific calculation method of the first register unit number is as described above and will not be repeated here.

[0067] Step S430: Based on each second calculation instruction in the first calculation step, obtain a third calculation instruction.

[0068] In this embodiment, the third computing instruction is any parent computing instruction of each second computing instruction in the first computing step, and each second computing instruction in the first computing step includes all child computing instructions of the third computing instruction.

[0069] As shown in Table 3, Figure 4In the calculation program shown, since each second calculation instruction corresponding to calculation step 1 and calculation step 2 has no parent calculation instruction, the third calculation instruction cannot be obtained based on each second calculation instruction corresponding to calculation step 1 and calculation step 2. Although each second calculation instruction corresponding to calculation step 4 and calculation step 5 has a parent calculation instruction (that is, calculation instruction X3 and calculation instruction X5), each second calculation instruction corresponding to calculation step 4 and calculation step 5 does not have all the child calculation instructions of calculation instruction X3 and calculation instruction X5. In other words, the third calculation instruction cannot be obtained based on each second calculation instruction corresponding to calculation step 4 and calculation step 5. The second calculation instructions corresponding to calculation step 3 are respectively calculation instructions X1 to calculation instruction X4, among which calculation instruction X3 is the parent calculation instruction, and each second calculation instruction corresponding to calculation step 3 includes all the child calculation instructions of calculation instruction X3 (that is, calculation instruction X1 and calculation instruction X2).

[0070] That is to say, in the embodiment shown in Table 3, the third calculation instruction (ie, calculation instruction X3) can be obtained only based on each second calculation instruction corresponding to calculation step 3.

[0071] Step S440: Based on the third computing instruction, obtain multiple fourth computing instructions.

[0072] In this embodiment, the fourth calculation instruction is any sub-calculation instruction of the third calculation instruction. That is, in the embodiment of the present application, if the third calculation instruction has several sub-calculation instructions, then based on the third calculation instruction, it is possible to obtain a plurality of fourth calculation instructions with the same number of sub-calculation instruction units as the third calculation instruction. In the embodiment shown in Table 3, the plurality of fourth calculation instructions of calculation step 3 are respectively calculation instruction X1 and calculation instruction X2 (i.e., sub-calculation instruction of calculation instruction X3).

[0073] Step S450: Based on the third calculation instruction, obtain the second register unit quantity.

[0074] In this embodiment, the second register unit quantity is equal to the register unit quantity required to be occupied by the third calculation instruction when calculating. In the embodiment shown in Table 3, the third calculation instruction (i.e., calculation instruction X3) in calculation step 3 occupies register R3 (i.e., 1 unit of register).

[0075] Step S460: Based on each fourth calculation instruction, obtain the third register unit quantity.

[0076] In this embodiment, the third register unit quantity is equal to the sum of the register unit quantities required to be occupied by each fourth calculation instruction when calculating. In the embodiment shown in Table 3, each fourth calculation instruction (i.e., calculation instruction X1 and calculation instruction X2) in calculation step 3 occupies register R1 and register R2 (i.e., 2 units of registers).

[0077] Step S470: Based on the second register unit quantity and the third register unit quantity, obtain a fourth register unit quantity.

[0078] In this embodiment, the fourth register unit quantity is the smallest register unit quantity between the second register unit quantity and the third register unit quantity. In the embodiment shown in Table 3, the second register unit quantity corresponding to step 3 is 1, and the third register unit quantity corresponding to step 3 is 2. Since the fourth register unit quantity is the smallest register unit quantity between the second register unit quantity and the third register unit quantity, the fourth register unit quantity corresponding to step 3 is 1.

[0079] Step S480: Obtain the maximum number of active register units in the first calculation step based on the first number of register units minus the fourth number of register units.

[0080] As can be seen from the foregoing, if any of the child computing instructions in a parent computing instruction is not executed, the current computing step will definitely not be able to execute the parent computing instruction. In the case where the current computing step executes a parent computing instruction, the registers occupied by all the child computing instructions of the parent computing instruction must be released. In other words, in this computing step, whether it is executing the parent computing instruction or executing any of the child computing instructions in the parent computing instruction, even if the first register unit number is subtracted from the fourth register unit number, which is a smaller number of register units occupied by the parent computing instruction and each child computing instruction of the parent computing instruction, it can meet the subsequent storage needs, thereby reducing the waste of register resources.

[0081] It should be noted that subtracting one value from another is a mature technology and will not be described in detail here. In the embodiment shown in Table 3, the number of first register units corresponding to step 3 is 4, and the number of fourth register units corresponding to step 3 is 1, so the maximum number of active register units corresponding to step 3 is equal to 4-1=3. Based on this, Table 5 can be obtained.

[0082] Table 5 Table of the number of units occupied by registers in the application scenarios of very long instruction words

[0083]

[0084] As can be seen from Table 5, in the embodiments of the present application, if the following Figure 4 The calculation program shown allocates 3 units of registers. No matter what calculation instruction is executed in each calculation step, there will be no phenomenon that no registers are available in the calculation step. That is to say, in this embodiment, when the number of register units is sufficient for the calculation program, the number of allocated register units can be minimized. That is, the utilization efficiency of registers can be improved, and the phenomenon of register resource waste caused by too many registers allocated to the calculation program can be avoided.

[0085] Step S500: Allocate registers for the computing program based on the maximum number of active register units in each computing step.

[0086] It should be clear that in the embodiments of the present application, registers may be allocated to the calculation program according to the maximum number of active register units with the largest value in each calculation step.

[0087] From Table 5, we can see that Figure 4 In the calculation program shown, the maximum number of active register units in each calculation step is 3. That is, 3 units of registers can be allocated to the calculation program so that the calculation program can be executed smoothly. It is easy to understand that the number of register units occupied in the calculation steps after calculation step 3 (that is, calculation steps 4 and 5) is obviously less than 3. In other words, the registers that will definitely not be used later during the execution of the program can be allocated to other programs for use to improve the utilization efficiency of the registers.

[0088] In order to improve the utilization efficiency of registers, in one embodiment of the present application, step S500: allocating registers to the computing program based on the maximum number of active register units in each computing step, includes steps S510 to S530.

[0089] Step S510: Obtain a sorting sequence based on the maximum number of active register units in each calculation step.

[0090] In this embodiment, a sequence unit in the sorting sequence includes at least a calculation step and a maximum number of active register units within the calculation step; the sorting rule is that if the maximum number of active register units is larger, the corresponding sequence unit is sorted higher; if the maximum number of active register units is the same and the calculation step is later, the corresponding sequence unit is sorted higher.

[0091] Specifically, in this embodiment, the sorting sequence obtained based on Table 5 is shown in Table 6.

[0092] Table 6 Sorting sequence table

[0093]

[0094] Step S520: Based on the sorting sequence, obtain the second calculation step and the third calculation step.

[0095] In this embodiment, the second calculation step and the third calculation step are adjacent in sequence, and the second calculation step is arranged after the third calculation step. The maximum number of active register units corresponding to the second calculation step and the third calculation step are not equal.

[0096] In this embodiment, taking Table 6 as an example, although calculation step 3 (ranked as 1) and calculation step 2 (ranked as 2) are adjacent in sequence, since the maximum number of active register units corresponding to calculation step 3 and calculation step 2 is equal, calculation step 3 and calculation step 2 cannot form the second calculation step and the third calculation step described above. Calculation step 1 (ranked as 3) and calculation step 4 (ranked as 4) are adjacent in sequence, and the maximum number of active register units corresponding to calculation step 1 and calculation step 4 is not equal, so calculation step 1 and calculation step 4 can form the second calculation step and the third calculation step described above. That is to say, in the following Figure 4 In the example embodiment, the second calculation step may be calculation step 1, and the third calculation step may be calculation step 4. Similarly, calculation step 4 and calculation step 5 may also constitute the second calculation step and the third calculation step described above.

[0097] Step S530: After the third calculation step is executed, registers are reallocated to the calculation program based on the maximum number of active register units corresponding to the third calculation step.

[0098] In this embodiment, taking Table 6 as an example, after calculation step 4 is executed, the register that cannot be used by calculation step 4 can be allocated to other programs. Specifically, the number of register units that can be allocated is equal to the number of register units occupied by the second calculation step minus the number of register units to be occupied by the third calculation step, which is not described here. It can be seen from Table 6 that after calculation step 4 is executed, a register can be allocated for use by other programs; after calculation step 5 is executed, a register can also be allocated for use by other programs.

[0099] It should be clear that, during the execution of a computing program, this embodiment timely allocates registers that are not used by a computing program for use by other computing programs, which can greatly improve the utilization efficiency of the registers.

[0100] The embodiment of the register resource management method proposed in the present application allocates registers for the computing program by determining the maximum number of units of registers that may be occupied during the execution of the computing program. Compared with the single branch pre-allocation method, which is prone to insufficient register allocation in the application scenario of very long instruction words, the present application will not have the phenomenon of insufficient register allocation. In other words, the present application will not cause a series of chain reactions such as register allocation imbalance, increased instruction overflow risk, and memory access bottlenecks caused by insufficient register allocation. It can alleviate the bottleneck of register resource allocation to the greatest extent and improve the execution efficiency of computing programs in the application scenario of very long instruction words.

[0101] After introducing the register resource management method proposed in the embodiment of the present application, the following introduces a register resource management device proposed in the embodiment of the present application. Figure 2 As shown, the register resource management device 10 includes:

[0102] A reading module 11 is used to obtain a calculation program; the calculation program is obtained based on the very long instruction word, the calculation program includes a plurality of calculation instructions, each of which is executed respectively through a plurality of calculation steps; the number of the calculation steps is the same as the number of the calculation instructions;

[0103] And, based on the computing program, obtaining a plurality of first computing instructions; the first computing instruction is any computing instruction in the computing program;

[0104] The processing module 12 is used to obtain multiple second computing instructions in each computing step based on each first computing instruction; the second computing instruction is any first computing instruction executable in the corresponding computing step;

[0105] and, based on each second computing instruction, obtaining a maximum number of active register units within each computing step;

[0106] And, allocating registers to the computing program based on a maximum number of active register units within each computing step.

[0107] As a specific embodiment of the technical solution of the present application, the maximum number of active register units in a calculation step is equal to the sum of the number of register units required to be occupied when calculating each second calculation instruction in the calculation step.

[0108] As a specific embodiment of the technical solution of the present application, the processing module 12 is further used to obtain each calculation step as each first calculation step; the first calculation step is any calculation step in each calculation step;

[0109] And, for each first calculation step, the following operations are performed to obtain the maximum number of active register units in each first calculation step:

[0110] Based on each second calculation instruction in a first calculation step, obtaining a first register unit quantity; the first register unit quantity is equal to the sum of the register unit quantities required to be occupied when each second calculation instruction in the first calculation step is calculated;

[0111] And, based on each second computing instruction in the first computing step, a third computing instruction is obtained; the third computing instruction is any parent computing instruction of each second computing instruction, and each second computing instruction includes all child computing instructions of the third computing instruction;

[0112] And, based on the third computing instruction, a plurality of fourth computing instructions are obtained; the fourth computing instruction is any sub-computing instruction of the third computing instruction;

[0113] And, based on the third calculation instruction, obtaining a second number of register units; the second number of register units is equal to the number of register units required to be occupied when the third calculation instruction is calculated;

[0114] And, based on each fourth calculation instruction, obtaining a third register unit quantity; the third register unit quantity is equal to the sum of the register unit quantities required to be occupied when each fourth calculation instruction is calculated;

[0115] and, based on the second register unit quantity and the third register unit quantity, obtaining a fourth register unit quantity; the fourth register unit quantity being the smallest register unit quantity between the second register unit quantity and the third register unit quantity;

[0116] And, based on subtracting the fourth register unit quantity from the first register unit quantity, obtaining a maximum active register unit quantity in the first calculation step.

[0117] As a specific embodiment of the technical solution of the present application, the processing module 12 is further used to allocate registers to the calculation program based on the largest value of each maximum number of active register units in each calculation step.

[0118] As a specific embodiment of the technical solution of the present application, the processing module 12 is further used to obtain a sorting sequence based on the maximum number of active register units in each calculation step; a sequence unit in the sorting sequence includes at least a calculation step and the maximum number of active register units in the calculation step; the sorting rule is that if the maximum number of active register units is larger, the corresponding sequence unit is ranked higher; if the maximum number of active register units is the same and the calculation step is later, the corresponding sequence unit is ranked higher;

[0119] and, based on the sorting sequence, obtaining a second calculation step and a third calculation step; the second calculation step and the third calculation step are adjacent in sequence, and the third calculation step is located after the sorting of the second calculation step; the maximum number of active register units corresponding to the second calculation step and the third calculation step are not equal;

[0120] And, after the third calculation step is executed, registers are reallocated to the calculation program based on the maximum number of active register units corresponding to the third calculation step.

[0121] The embodiment of the register resource management device proposed in the present application allocates registers for the computing program by determining the maximum number of units of registers that may be occupied during the execution of the computing program. Compared with the single branch pre-allocation method, which is prone to cause insufficient register allocation in the application scenario of very long instruction words, the present application will not have the phenomenon of insufficient register allocation. In other words, the present application will not cause a series of chain reactions such as register allocation imbalance, increased instruction overflow risk, and memory access bottleneck caused by insufficient register allocation. It can alleviate the bottleneck of register resource allocation to the greatest extent and improve the execution efficiency of computing programs in the application scenario of very long instruction words.

[0122] After introducing the register resource management device proposed in the embodiment of the present application, the following introduces a register resource management system proposed in the embodiment of the present application. Figure 3 As shown, the register resource management system 20 includes:

[0123] The reader 21 obtains a computing program; the computing program is obtained based on the very long instruction word, the computing program includes a plurality of computing instructions, each computing instruction is executed respectively through a plurality of computing steps; the number of computing steps is the same as the number of computing instructions;

[0124] And, based on the computing program, obtaining a plurality of first computing instructions; the first computing instruction is any computing instruction in the computing program;

[0125] The processor 22 obtains a plurality of second computing instructions in each computing step based on each first computing instruction; the second computing instruction is any first computing instruction executable in the corresponding computing step;

[0126] and, based on each second computing instruction, obtaining a maximum number of active register units within each computing step;

[0127] And, allocating registers to the computing program based on a maximum number of active register units within each computing step.

[0128] As a specific embodiment of the technical solution of the present application, the maximum number of active register units in a calculation step is equal to the sum of the number of register units required to be occupied when calculating each second calculation instruction in the calculation step.

[0129] As a specific embodiment of the technical solution of the present application, the processor 22 is further used to obtain each calculation step as each first calculation step; the first calculation step is any calculation step in each calculation step;

[0130] And, for each first calculation step, the following operations are performed to obtain the maximum number of active register units in each first calculation step:

[0131] Based on each second calculation instruction in a first calculation step, obtaining a first register unit quantity; the first register unit quantity is equal to the sum of the register unit quantities required to be occupied when each second calculation instruction in the first calculation step is calculated;

[0132] And, based on each second computing instruction in the first computing step, a third computing instruction is obtained; the third computing instruction is any parent computing instruction of each second computing instruction, and each second computing instruction includes all child computing instructions of the third computing instruction;

[0133] And, based on the third computing instruction, a plurality of fourth computing instructions are obtained; the fourth computing instruction is any sub-computing instruction of the third computing instruction;

[0134] And, based on the third calculation instruction, obtaining a second number of register units; the second number of register units is equal to the number of register units required to be occupied when the third calculation instruction is calculated;

[0135] And, based on each fourth calculation instruction, obtaining a third register unit quantity; the third register unit quantity is equal to the sum of the register unit quantities required to be occupied when each fourth calculation instruction is calculated;

[0136] and, based on the second register unit quantity and the third register unit quantity, obtaining a fourth register unit quantity; the fourth register unit quantity being the smallest register unit quantity between the second register unit quantity and the third register unit quantity;

[0137] And, based on subtracting the fourth register unit quantity from the first register unit quantity, obtaining a maximum active register unit quantity in the first calculation step.

[0138] As a specific embodiment of the technical solution of the present application, the processor 22 is further used to allocate registers to the calculation program based on the largest number of maximum active register units in each calculation step.

[0139] As a specific embodiment of the technical solution of the present application, the processor 22 is further used to obtain a sorting sequence based on the maximum number of active register units in each calculation step; a sequence unit in the sorting sequence includes at least a calculation step and the maximum number of active register units in the calculation step; the sorting rule is that if the maximum number of active register units is larger, the corresponding sequence unit is ranked higher; if the maximum number of active register units is the same and the calculation step is later, the corresponding sequence unit is ranked higher;

[0140] and, based on the sorting sequence, obtaining a second calculation step and a third calculation step; the second calculation step and the third calculation step are adjacent in sequence, and the third calculation step is located after the sorting of the second calculation step; the maximum number of active register units corresponding to the second calculation step and the third calculation step are not equal;

[0141] And, after the third calculation step is executed, registers are reallocated to the calculation program based on the maximum number of active register units corresponding to the third calculation step.

[0142] The embodiment of the register resource management system proposed in the present application allocates registers for the computing program by determining the maximum number of units of registers that may be occupied during the execution of the computing program. Compared with the single branch pre-allocation method, which is prone to cause insufficient register allocation in the application scenario of very long instruction words, the present application will not have the phenomenon of insufficient register allocation. In other words, the present application will not cause a series of chain reactions such as register allocation imbalance, increased instruction overflow risk, and memory access bottlenecks caused by insufficient register allocation. It can alleviate the bottleneck of register resource allocation to the greatest extent and improve the execution efficiency of computing programs in the application scenario of very long instruction words.

[0143] After introducing the register resource management system proposed in the embodiment of the present application, a computer-readable storage medium proposed in the embodiment of the present application is introduced below. A computer program is stored on the computer-readable storage medium. When the computer program is executed by the processor, the register resource management method described in any of the above embodiments is implemented.

[0144] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0145] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0146] In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0147] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. The purpose of the solution of this embodiment can be achieved based on some or all of the modules according to actual needs.

[0148] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0149] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0150] The computer program product includes one or more computer instructions. When the computer program is loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0151] The technical solutions provided in the embodiments of the present application are introduced in detail above. The principles and implementation methods of the embodiments of the present application are explained by using specific examples in the embodiments of the present application. The description of the above embodiments is only used to help understand the methods and core ideas of the embodiments of the present application. At the same time, for those skilled in the art, according to the ideas of the embodiments of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the embodiments of the present application.

Claims

1. A register resource management method, characterized in that: include: Obtaining a calculation program; the calculation program is obtained based on a very long instruction word, the calculation program includes a plurality of calculation instructions, and each calculation instruction is executed respectively through a plurality of calculation steps; The number of computational steps and computational instructions is the same; Based on the computing program, obtaining a plurality of first computing instructions; The first computing instruction is any computing instruction in the computing program; Based on each first computing instruction, a plurality of second computing instructions in each computing step are obtained; the second computing instruction is any first computing instruction executable in the corresponding computing step; Based on each second computing instruction, obtaining a maximum number of active register units in each computing step; allocating registers to the computational program based on a maximum number of active register units within each computational step; The obtaining, based on each second computing instruction, a maximum number of active register units in each computing step includes: Acquire each calculation step as each first calculation step; the first calculation step is any one of the calculation steps; For each first calculation step, the following operations are performed to obtain the maximum number of active register units within each first calculation step: Based on each second calculation instruction in a first calculation step, obtaining a first register unit quantity; the first register unit quantity is equal to the sum of the register unit quantities required to be occupied when each second calculation instruction in the first calculation step is calculated; Based on each second computing instruction in the first computing step, a third computing instruction is obtained; the third computing instruction is any parent computing instruction of each second computing instruction, and each second computing instruction includes all child computing instructions of the third computing instruction; Based on the third computing instruction, a plurality of fourth computing instructions are acquired; the fourth computing instruction is any sub-computing instruction of the third computing instruction; Based on the third calculation instruction, obtaining a second number of register units; the second number of register units is equal to the number of register units required to be occupied when calculating the third calculation instruction; Based on each fourth calculation instruction, obtain a third register unit quantity; the third register unit quantity is equal to the sum of the register unit quantities required to be occupied when each fourth calculation instruction is calculated; Based on the second register unit quantity and the third register unit quantity, obtaining a fourth register unit quantity; the fourth register unit quantity is the smallest register unit quantity between the second register unit quantity and the third register unit quantity; The maximum active register unit quantity in the first calculation step is obtained based on the first register unit quantity minus the fourth register unit quantity.

2. The register resource management method according to claim 1, characterized in that: The maximum number of active register units in a calculation step is equal to the sum of the numbers of register units required to be occupied when calculating each second calculation instruction in the calculation step.

3. The register resource management method according to claim 1 or 2, characterized in that: The allocating registers to the computing program based on the maximum number of active register units in each computing step includes: The registers are allocated to the calculation program based on the largest value among the respective maximum active register unit quantities of the respective calculation steps.

4. The register resource management method according to claim 3, characterized in that: The allocating registers to the computing program based on the maximum number of active register units in each computing step includes: Based on the maximum number of active register units in each calculation step, a sorting sequence is obtained; a sequence unit in the sorting sequence includes at least a calculation step and the maximum number of active register units in the calculation step; the sorting rule is that if the maximum number of active register units is larger, the corresponding sequence unit is ranked higher; if the maximum number of active register units is the same and the calculation step is later, the corresponding sequence unit is ranked higher; Based on the sorting sequence, a second calculation step and a third calculation step are obtained; the second calculation step and the third calculation step are adjacent in sequence, and the third calculation step is located after the sorting of the second calculation step; the maximum number of active register units corresponding to the second calculation step and the third calculation step are not equal; After the third calculation step is executed, registers are reallocated to the calculation program based on the maximum number of active register units corresponding to the third calculation step.

5. A register resource management device, characterized in that: include: A reading module, used for obtaining a calculation program; The computing program is obtained based on a very long instruction word, and the computing program includes a plurality of computing instructions, each of which is executed respectively through a plurality of computing steps; The number of computational steps and computational instructions is the same; and, based on the computing program, obtaining a plurality of first computing instructions; The first computing instruction is any computing instruction in the computing program; A processing module, configured to obtain a plurality of second computing instructions in each computing step based on each first computing instruction; the second computing instruction is any first computing instruction executable in the corresponding computing step; and, based on each second computing instruction, obtaining a maximum number of active register units in each computing step; and, allocating registers to the computational program based on a maximum number of active register units within each computational step; The processing module is further used to obtain each calculation step as each first calculation step; the first calculation step is any calculation step in each calculation step; And, for each first calculation step, the following operations are performed to obtain the maximum number of active register units in each first calculation step: Based on each second calculation instruction in a first calculation step, obtaining the first register unit quantity; The first number of register units is equal to the sum of the number of register units required to be occupied by each second calculation instruction in the first calculation step; And, based on each second computing instruction in the first computing step, a third computing instruction is obtained; the third computing instruction is any parent computing instruction of each second computing instruction, and each second computing instruction includes all child computing instructions of the third computing instruction; And, based on the third computing instruction, a plurality of fourth computing instructions are obtained; the fourth computing instruction is any sub-computing instruction of the third computing instruction; and, based on the third calculation instruction, obtaining a second register unit quantity; The second register unit quantity is equal to the register unit quantity required to be occupied when the third calculation instruction is calculated; and, based on each fourth calculation instruction, obtaining a third register unit quantity; The third number of register units is equal to the sum of the number of register units required to be occupied when each fourth calculation instruction is calculated; and, based on the second register unit quantity and the third register unit quantity, obtaining a fourth register unit quantity; The fourth register unit quantity is the smallest register unit quantity between the second register unit quantity and the third register unit quantity; And, based on subtracting the fourth register unit quantity from the first register unit quantity, obtaining a maximum active register unit quantity in the first calculation step.

6. The register resource management device according to claim 5, characterized in that: The maximum number of active register units in a calculation step is equal to the sum of the numbers of register units required to be occupied when calculating each second calculation instruction in the calculation step.

7. The register resource management device according to claim 5 or 6, characterized in that: The processing module is further configured to allocate registers to the computing program based on the largest number of maximum active register unit quantities of each computing step.

8. The register resource management device according to claim 7, characterized in that: The processing module is further configured to obtain a sorting sequence based on the maximum number of active register units in each calculation step; a sequence unit in the sorting sequence includes at least a calculation step and a maximum number of active register units in the calculation step; The sorting rule is that if the maximum number of active register units is larger, the corresponding sequence unit is ranked higher; if the maximum number of active register units is the same and the calculation step is later, the corresponding sequence unit is ranked higher; and, based on the sorting sequence, obtaining a second calculation step and a third calculation step; the second calculation step and the third calculation step are adjacent in sequence, and the third calculation step is located after the sorting of the second calculation step; the maximum number of active register units corresponding to the second calculation step and the third calculation step are not equal; And, after the third calculation step is executed, registers are reallocated to the calculation program based on the maximum number of active register units corresponding to the third calculation step.

9. A register resource management system, characterized in that: include: The reader obtains a computing program; the computing program is obtained based on the very long instruction word, the computing program includes a plurality of computing instructions, and each computing instruction is executed respectively through a plurality of computing steps; The number of computational steps and computational instructions is the same; and, based on the computing program, obtaining a plurality of first computing instructions; The first computing instruction is any computing instruction in the computing program; The processor obtains a plurality of second computing instructions in each computing step based on each first computing instruction; the second computing instruction is any first computing instruction executable in the corresponding computing step; and, based on each second computing instruction, obtaining a maximum number of active register units in each computing step; and, allocating registers to the computational program based on a maximum number of active register units within each computational step; The processor is further used to obtain each calculation step as each first calculation step; the first calculation step is any calculation step in each calculation step; And, for each first calculation step, the following operations are performed to obtain the maximum number of active register units in each first calculation step: Based on each second calculation instruction in a first calculation step, obtaining the first register unit quantity; The first number of register units is equal to the sum of the number of register units required to be occupied by each second calculation instruction in the first calculation step; And, based on each second computing instruction in the first computing step, a third computing instruction is obtained; the third computing instruction is any parent computing instruction of each second computing instruction, and each second computing instruction includes all child computing instructions of the third computing instruction; And, based on the third computing instruction, a plurality of fourth computing instructions are obtained; the fourth computing instruction is any sub-computing instruction of the third computing instruction; and, based on the third calculation instruction, obtaining a second register unit quantity; The second register unit quantity is equal to the register unit quantity required to be occupied when the third calculation instruction is calculated; and, based on each fourth calculation instruction, obtaining a third register unit quantity; The third number of register units is equal to the sum of the number of register units required to be occupied when each fourth calculation instruction is calculated; and, based on the second register unit quantity and the third register unit quantity, obtaining a fourth register unit quantity; The fourth register unit quantity is the smallest register unit quantity between the second register unit quantity and the third register unit quantity; And, based on subtracting the fourth register unit quantity from the first register unit quantity, obtaining a maximum active register unit quantity in the first calculation step.

10. The register resource management system according to claim 9, characterized in that: The maximum number of active register units in a calculation step is equal to the sum of the numbers of register units required to be occupied when calculating each second calculation instruction in the calculation step.

11. The register resource management system according to claim 9 or 10, characterized in that: The processor is further configured to allocate registers to the computing program based on the largest number of maximum active register unit quantities of each computing step.

12. The register resource management system according to claim 11, characterized in that: The processor is further configured to obtain a sorting sequence based on the maximum number of active register units in each calculation step; a sequence unit in the sorting sequence includes at least a calculation step and a maximum number of active register units in the calculation step; The sorting rule is that if the maximum number of active register units is larger, the corresponding sequence unit is ranked higher; if the maximum number of active register units is the same and the calculation step is later, the corresponding sequence unit is ranked higher; and, based on the sorting sequence, obtaining a second calculation step and a third calculation step; the second calculation step and the third calculation step are adjacent in sequence, and the third calculation step is located after the sorting of the second calculation step; the maximum number of active register units corresponding to the second calculation step and the third calculation step are not equal; And, after the third calculation step is executed, registers are reallocated to the calculation program based on the maximum number of active register units corresponding to the third calculation step.

13. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the register resource management method according to any one of claims 1 to 4 is implemented.

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