Parallel processing module, method and asynchronous circuit for compressed and uncompressed instruction sets

Abstract

The present invention discloses a parallel processing module, method and asynchronous circuit of a compressed and non-compressed instruction set. First, a mixed instruction is stored in a buffer Buffer1 module, and then the compressed instruction and the non-compressed instruction are separated by a mixedInstrDivsion module, and the separated non-compressed instruction is directly stored in a buffer Buffer2 module. The separated compressed instruction is expanded by a mixInstrProcess module, and the expansion of four compressed instructions is completed in parallel in one round. Finally, the expanded non-compressed instruction is stored in the buffer Buffer2 module for use by a decoding module. By adopting a parallel processing method, more instructions can be divided and expanded in the same time period, and the instruction processing speed of the compression processing stage in a superscalar processor is improved. The overall stage realizes the parallel execution of multiple instructions, and improves the performance of the processor. The parallel processing module of the present invention is implemented by a BBD type asynchronous circuit, which not only avoids the clock problem, but also can greatly reduce power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of processors, and in particular relates to a parallel processing module, method and asynchronous circuit for compressed and uncompressed instruction sets. Background Art

[0002] In the RISC-V instruction set, 16-bit compressed instructions are used to replace 32-bit ordinary instructions to shorten the code length, so that a series of programs can obtain good code compression effects. The instruction type of 16-bit compressed instructions is called C-type compressed instructions (RVC for short) in RISC-V. RVC instructions can replace 50%-60% of RISC-V instructions and reduce the code size by 25%-30%. In the processor of superscalar architecture, the overall performance is improved by executing instructions in parallel. However, due to the addition of RVC instructions, the instruction types in the processor memory include both compressed instructions and non-compressed instructions. Therefore, parallel processing of mixed instructions is a key issue. The processing of mixed instructions is completed before the decoding stage. The core operation mainly includes two aspects: one is the division of compressed instructions and non-compressed instructions, and the other is the expansion of compressed instructions. Due to the difference in bit width between the compressed instruction set and the non-compressed instruction set, the starting address of the next instruction in the mixed instruction processing is uncertain, and the starting address of the next instruction depends on the current instruction. There is a dependency relationship between instructions. Therefore, the above two aspects of the core operation are necessary and serial.

[0003] In the processing of mixed instructions in superscalar processors, the existing technology usually uses a state machine to process compressed instructions. This method is a serial processing method. Only one instruction can be obtained at a time, and multiple instructions cannot be processed in parallel. The method of directly decoding compressed instructions in the decoding stage increases the complexity of the decoding circuit and the decoding time, thereby affecting the overall performance. In addition, the existing circuits are all implemented in a synchronous circuit. During the development process, a series of problems caused by clock reasons such as clock jitter and clock skew will occur. Summary of the invention

[0004] In view of the problems existing in the above background technology, the purpose of the present invention is to provide a parallel processing module, method and asynchronous circuit for compressed and uncompressed instruction sets.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] Parallel processing modules for compressed and uncompressed instruction sets, including:

[0007] Buffer1 module: used to cache the mixed instructions taken out by the parallel processing module. The Buffer1 module is built with 64 16-bit registers, each register is defined as a block, and the Buffer1 module has a built-in counter, which is used to record the number of compressed blocks;

[0008] mixedInstrDivsion module: used to identify compressed instructions and non-compressed instructions in the 16 blocks input by the Buffer1 module, and return the offset of each instruction in the 16 blocks and the number of blocks processed in this round; the mixedInstrDivsion module divides compressed instructions into non-compressed instructions according to whether the last two digits of the instruction are 11;

[0009] mixInstrProcess module: used to expand the 16-bit compressed instruction recognized by the mixedInstrDivsion module into a 32-bit non-compressed instruction of the corresponding function; the mixInstrProcess module includes 4 extenCompress modules, each of which can expand a 16-bit compressed instruction into a 32-bit non-compressed instruction, and complete the expansion of 4 compressed instructions in parallel;

[0010] Buffer2 module: used to store the uncompressed instructions recognized by the mixedInstrDivsion module and the uncompressed instructions processed by the mixInstrProcess module for use by the decoding module. The Buffer2 module is built with 16 32-bit registers.

[0011] Furthermore, the mixedInstrDivsion module includes a preCompress module and a postCompress0 module, wherein:

[0012] preCompress module: used for pre-identifying compressed instructions. The preCompress module includes 16 last2Judge modules. The 16 last2Judge modules take the lower 2 bits of each register from the 16 intermediate registers and send them to the last2Judge module to identify compressed instructions and non-compressed instructions.

[0013] postCompress0 module: contains 16 case modules, which exhaustively enumerate the instruction distribution; the postCompress0 module is used to match the instruction result output by the last2Judge module with the instruction distribution of the case module.

[0014] The method for parallel processing of compressed and uncompressed instruction sets comprises the following steps:

[0015] S1, the mixed instructions taken out by the parallel processing module are cached in the Buffer1 module, and the 64 blocks in the Buffer1 module are numbered in sequence. The Buffer1 module sends 16 blocks to the subsequent intermediate registers in each round;

[0016] S2, the mixedInstrDivsion module distinguishes the mixed instructions in each register of the 16 blocks sent by the Buffer1 module, and distinguishes the compressed instructions and the non-compressed instructions according to whether the last two digits of the instruction are 11. If the last two digits of the instruction are 11, it is a non-compressed instruction and is directly stored in the Buffer2 module; if the last two digits of the instruction are not 11, it is a compressed instruction and is input into the mixedInstrProcess module; after a round of mixed instruction identification processing is completed, the mixedInstrDivsion module returns the number of blocks processed in this round and updates the counter;

[0017] S3, the mixInstrProcess module expands four 16-bit compressed instructions into four 32-bit uncompressed instructions in parallel at a time through the internal extenCompress module;

[0018] S4, caches the 32-bit uncompressed instructions processed by the mixInstrProcess module in the Buffer2 module for use by the decoding module.

[0019] Furthermore, in S2, the mixedInstrDivsion module uses the following method to distinguish instructions: if the last two digits of the instruction are 11, 1 is output; if not 11, 0 is output, and the results of 16 last2Judge modules are concatenated to output a 16-bit data packet result; then the 16-bit data packet result is judged twice, 8 bits each time, and 4 instructions are divided out from it, and the instruction distribution of the 4 instructions is matched. After the match is successful, the offsets of the 4 instructions are output, and the status of the 4 instructions is recorded in Arry[7:0], and the number of bits of the result processed this time is returned.

[0020] Furthermore, in S3, the method for the extenCompress module to perform instruction expansion is:

[0021] First, divide the opcode and function code fields in the instruction format, refer to the instruction set architecture manual, and find the non-compressed instructions corresponding to the compressed instructions;

[0022] Secondly, the register number domain in the compressed instruction is divided and mapped to the corresponding 32 registers in the uncompressed instruction;

[0023] Finally, the divided immediate values ​​are mapped to the immediate value field of the non-compressed instruction.

[0024] The present invention further provides an asynchronous circuit for implementing a parallel processing module of compressed and uncompressed instruction sets, wherein the asynchronous circuit adopts an asynchronous clockless circuit driven by a two-phase single-rail self-timing Click controller family event based on a bounded bundle data (BBD) handshake protocol, referred to as a BBD type asynchronous circuit.

[0025] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects:

[0026] (1) The present invention uses a parallel processing method to divide and expand more instructions in the same time period, so that the superscalar processor can improve the instruction processing speed in the compression processing stage and realize parallel execution of multiple instructions in the overall stage, thereby improving the performance of the processor;

[0027] (2) The circuit of the parallel processing module for implementing the compressed and uncompressed instruction sets of the present invention adopts an asynchronous clockless event driving method, thereby avoiding clock problems and significantly reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the internal mechanism of the parallel processing module of the compressed and non-compressed instruction sets provided by an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of the structure of a Click circuit provided by an embodiment of the present invention;

[0030] Figure 3 It is a schematic diagram of the principle of the BBD handshake protocol provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] In the RISC-V instruction set, the last two bits of the instruction are usually used to distinguish compressed instructions from non-compressed instructions. The last two bits of the non-compressed instruction are usually 11, while the compressed instruction ends with 00, 01 and 10. This provides a basis for distinguishing the two mixed instructions. Therefore, the present invention divides the compressed and non-compressed instructions in the superscalar processor based on this, separates the compressed instructions from the non-compressed instructions, and if it is a compressed instruction, it is expanded and the expanded instruction is stored in the buffer for use by the decoding module. If it is not a compressed instruction, it is directly stored in the buffer. In order to satisfy the parallel decoding of the instructions of the decoding module as much as possible, an algorithm similar to exhaustive comparison is used in the compressed instruction processing process to generate 8 instructions in parallel for full utilization of the decoding module.

[0033] 1. Cache of compressed and uncompressed instructions

[0034] The mixed instructions are cached in the Buffer1 module. The Buffer1 module is built with 64 16-bit registers. Each register is defined as a block. The 64 blocks in the Buffer1 module are numbered in sequence. The Buffer1 module has a built-in 6-bit counter to record the number of blocks processed by compression. The Buffer1 module sends 16 blocks (the block pointed to by the current counter and the 15 blocks after it) to the subsequent intermediate registers in each round. When the Buffer1 module is in the initial state, its internal register is empty, and it is necessary to fetch mixed instructions from the instruction cache twice in a row to fill the Buffer1 module. After a round of mixed instruction processing is completed, the number of blocks processed in this round is returned and the counter is updated. Therefore, the value of the counter will increase by 8 to 16 each round. When the value of the counter crosses 31 (that is, the highest bit of the 6-bit counter changes from 0 to 1), a signal is sent to the instruction cache and a mixed instruction is fetched. The fetched 16*32-bit mixed instruction will cover the first 32 blocks; when the value of the counter crosses 63 (that is, the highest bit changes from 1 to 0), the remaining 32 blocks are updated.

[0035] 2. Division of compressed and non-compressed instructions

[0036] The mixedInstrDivsion module is used to identify the compressed instructions and non-compressed instructions in each register of the 16 blocks input by the Buffer1 module, and the offset of each instruction in the 16 blocks and the number of blocks processed in this round are returned. The compressed instructions and non-compressed instructions are divided, and the compressed instructions are input into the subsequent mixInstrProcess module for expansion processing, and the non-compressed instructions are directly stored in the Buffer2 module. Among them, the mixedInstrDivsion module includes the preCompress module and the postCompress0 module. The preCompress module is used to pre-identify compressed instructions and contains 16 last2Judge modules. The 16 last2Judge modules take the lower 2 bits of each register from the 16 intermediate registers and send them to the last2Judge module to identify compressed instructions and non-compressed instructions. If the lower 2 bits of the register are 11, it outputs 1, and if not 11, it outputs 0. The results of the 16 last2Judge modules are spliced ​​to output a 16-bit data packet, namely result[15:0]; the postCompress0 module identifies 8 bits in the result at a time and divides 4 instructions from it. The postCompress0 module will be used twice in one round of identification, and 8 instructions will be identified from 16 blocks. The postCompress0 module contains 16 case modules, which exhaustively enumerate the distribution of 4 instructions, as shown in Table 1:

[0037] Table 1 Distribution of 4 instructions in 16 case modules

[0038] 1111XXXX 10X11XXX 0X111XXX 0X0X11XX 1110XXXX 10X10XXX 0X110XXX 0X0X10XX 110X1XXX 10X0X1XX 0X10X1XX 0X0X0X1X 110X0XXX 10X0X0XX 0X10X0XX 0X0X0X0X

[0039] Each of the four divided instructions is matched with the instruction distribution in Table 1. After a successful match, the offsets of the four instructions are output, recorded as offset1~4. At the same time, the status of the four instructions is recorded in Arry[7:0], and the number of bits of the result of this processing is returned.

[0040] 3. Processing of compression instructions

[0041] The mixInstrProcess module is used to expand the 16-bit compressed instructions identified by the mixedInstrDivsion module into 32-bit non-compressed instructions of corresponding functions. The mixInstrProcess module contains 4 extenCompress modules. Each extenCompress module can expand a 16-bit compressed instruction into a 32-bit non-compressed instruction, and complete the expansion of 4 compressed instructions in parallel. The expansion method is: first, divide the opcode and function code fields in the instruction format, refer to the instruction set architecture manual, and find the non-compressed instructions corresponding to the compressed instructions; second, divide the register number field in the compressed instruction and map it to the corresponding 32 registers in the non-compressed instruction; finally, map the divided immediate number to the immediate number field of the non-compressed instruction; the above process can complete the expansion of compressed instructions to non-compressed instructions. After a round of discrimination, 8 data packets offset and 8-bit data packet arry are obtained. Combining the two, 8 instructions are taken out from the intermediate register, and the compressed instructions are input into the extenCompress module for processing, and the non-compressed instructions are input into the Buffer2 module.

[0042] 4. Cache of non-compressed instructions

[0043] The non-compressed instructions identified by the mixedInstrDivsion module and the non-compressed instructions processed by the mixInstrProcess module are cached in the Buffer2 module, that is, all 32-bit non-compressed instructions for the decoding module to use. The Buffer2 module is built with 16 32-bit registers. The decoding module takes 8 instructions each time. If the Buffer2 module is full and not used, it will notify the entire processing module to stop running. If the Buffer2 module is used and there is idle time, the entire processing module will run. The Buffer2 module will store the processed instructions according to its corresponding Arry in blocks 0 to 7 or 8 to 15 according to its own idle situation. Finally, multiple instructions are sent in parallel to the subsequent stages, thereby improving the overall parallel speed.

[0044] 5. Asynchronous mechanism

[0045] The parallel processing module of the compressed and uncompressed instruction sets of the present invention is implemented by an asynchronous circuit design. The asynchronous circuit adopts an asynchronous clockless circuit driven by a two-phase single-rail self-timing Click controller family event based on a bounded bundle data (BBD) handshake protocol, referred to as a BBD type asynchronous circuit. The structural diagram of the Click circuit is shown in FIG. Figure 2 As shown, the input request signal in_R and the output response signal in_A are used to communicate with the upper-level click module, and the input response signal out_A and the output request signal out_R are connected to the lower-level click module. In the initial state, all input and output level signals are kept at a low level. When the in_R signal flips, the controller starts, and the fire also changes from a low level to a high level. At the same time, the trigger copies the data from the D end (data input end) to the Q end (data output end). After a delay unit, the level signals of in_A and out_R are pulled high to generate the next-level Click request signal and the previous-level Click response signal; then, the fire signal is pulled low from a high level to generate a complete pulse signal, and the data is transmitted smoothly under this control. The BBD type asynchronous circuit is a method to partially solve the timing problem. The asynchronous micro-pipeline control circuit is one of the many implementation methods of the BBD type asynchronous circuit. The implementation process is further explained through the asynchronous micro-pipeline control circuit. The principle of the BBD handshake protocol is as follows Figure 3 As shown. The BBD asynchronous circuit contains two paths: the control path and the data path. The control path is composed of an asynchronous controller and a delay unit; the data path is composed of data, registers, and combinational logic circuits. Assuming that in the initialization state, when the input data (Data) arrives, the req request signal of the control module flips from 0 to 1, and then generates a local control signal fire to the register CP end, and the data path begins to transmit the data to the combinational logic (combination logic, CL) module. After the CL module completes the calculation, it continues to pass the data result through the fire signal of the next level control circuit, and after the next level control circuit completes the reception, it will send an ack response signal to the previous level control circuit, indicating that the input data register can continue to access data at this time, and the cycle is carried out in sequence until the data transmission and calculation are completed.

[0046] The BBD asynchronous circuit effectively distinguishes the actual sorting and logical sorting functions implied in the circuit timing, that is, the design implementation is divided into two parts: the data module and the control module. Among them, the matching delay between the two adjacent asynchronous controllers in the control path must be greater than the time required for the CL module calculation, otherwise it will lead to the output of incorrect data results. The logical sorting of the entire circuit design is guaranteed by the "request-response" mechanism, and the adjacent controllers are synchronized through handshakes.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A parallel processing module for compressed and uncompressed instruction sets, characterized in that: include: Buffer1 module: used to cache the mixed instructions taken out by the parallel processing module. The Buffer1 module is built with 64 16-bit registers, each register is defined as a block, and the Buffer1 module has a built-in counter, which is used to record the number of compressed blocks; mixedInstrDivsion module: used to identify compressed instructions and non-compressed instructions in the 16 blocks input by the Buffer1 module, and return the offset of each instruction in the 16 blocks and the number of blocks processed in this round; the mixedInstrDivsion module divides compressed instructions into non-compressed instructions according to whether the last two digits of the instruction are 11; mixInstrProcess module: used to expand the 16-bit compressed instruction recognized by the mixedInstrDivsion module into a 32-bit non-compressed instruction of the corresponding function; the mixInstrProcess module includes 4 extenCompress modules, each of which can expand a 16-bit compressed instruction into a 32-bit non-compressed instruction, and complete the expansion of 4 compressed instructions in parallel; The mixedInstrDivsion module includes a preCompress module and a postCompress0 module, wherein: preCompress module: used for pre-identifying compressed instructions. The preCompress module includes 16 last2Judge modules. The 16 last2Judge modules take the lower 2 bits of each register from the 16 intermediate registers and send them to the last2Judge module to identify compressed instructions and non-compressed instructions. postCompress0 module: contains 16 case modules, which exhaustively enumerate the instruction distribution. The postCompress0 module is used to match the instruction result output by the last2Judge module with the instruction distribution of the case module. Buffer2 module: used to store the uncompressed instructions recognized by the mixedInstrDivsion module and the uncompressed instructions processed by the mixInstrProcess module for use by the decoding module. The Buffer2 module is built with 16 32-bit registers.

2. A method for implementing parallel processing of compressed and uncompressed instruction sets using the parallel processing module of claim 1, characterized in that: The steps include: S1, the mixed instructions taken out by the parallel processing module are cached in the Buffer1 module, and the 64 blocks in the Buffer1 module are numbered in sequence. The Buffer1 module sends 16 blocks to the subsequent intermediate registers in each round; S2, the mixedInstrDivsion module distinguishes the mixed instructions in each register of the 16 blocks sent by the Buffer1 module, and distinguishes the compressed instructions and the non-compressed instructions according to whether the last two digits of the instruction are 11. If the last two digits of the instruction are 11, it is a non-compressed instruction and is directly stored in the Buffer2 module; if the last two digits of the instruction are not 11, it is a compressed instruction and is input into the mixedInstrProcess module; after a round of mixed instruction identification processing is completed, the mixedInstrDivsion module returns the number of blocks processed in this round and updates the counter; S3, the mixInstrProcess module expands four 16-bit compressed instructions into four 32-bit uncompressed instructions in parallel at a time through the internal extenCompress module; S4, caches the 32-bit uncompressed instructions processed by the mixInstrProcess module in the Buffer2 module for use by the decoding module.

3. The method for parallel processing of compressed and uncompressed instruction sets as claimed in claim 2, characterized in that: In S2, the mixedInstrDivsion module uses the following method to distinguish instructions: if the last two digits of the instruction are 11, 1 is output; if not 11, 0 is output, and the results of 16 last2Judge modules are concatenated to output a 16-bit data packet result; then the 16-bit data packet result is judged twice, 8 bits each time, and 4 instructions are divided out from it, and the instruction distribution of the 4 instructions is matched. After the match is successful, the offsets of the 4 instructions are output, and the status of the 4 instructions is recorded in Arry[7:0], and the number of bits of the result processed this time is returned.

4. The method for parallel processing of compressed and uncompressed instruction sets as claimed in claim 2, characterized in that: In S3, the method for the extenCompress module to perform instruction expansion is: First, divide the opcode and function code fields in the instruction format, refer to the instruction set architecture manual, and find the non-compressed instructions corresponding to the compressed instructions; Secondly, the register number domain in the compressed instruction is divided and mapped to the corresponding 32 registers in the uncompressed instruction; Finally, the divided immediate values ​​are mapped to the immediate value field of the non-compressed instruction.

5. An asynchronous circuit for implementing the parallel processing module of the compressed and uncompressed instruction sets according to claim 1, characterized in that: The asynchronous circuit adopts an asynchronous clockless circuit driven by a two-phase single-rail self-timing Click controller family event based on a bounded data binding handshake protocol, that is, a BBD type asynchronous circuit.

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