Buffer cache memory for write or store drive of RAID protected memory

Abstract

The invention relates to a buffered cache memory for write or storage drive of RAID protected memory. A system and method are provided for a write or store driven buffer cache memory for a reliable RAID protected memory. For example, a system is provided that may include a RAID subsystem configured to maintain integrity of segments of memory. The system may further include a buffer memory communicatively coupled to the RAID subsystem. And the RAID subsystem may be configured to limit a frequency of RAID access memory command amplification by accessing the buffer memory, the subsystem being performing an operation configured to maintain the integrity of the segment of the memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 63 / 517,290 filed on August 2, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The following generally relates to one or more systems for memory. In particular, the present disclosure designs reliability, availability, and serviceability (RAS) features of memory. Background Art

[0004] Memory integrity is a hallmark of modern computing. Memory systems are often equipped with hardware and / or software / firmware protocols configured to check the integrity of one or more memory segments. These protocols can also determine whether the data located therein is accessible to higher-level subsystems or whether the data is error-free.

[0005] Typical RAS infrastructures for memory systems can be configured to detect and repair errors in the system. For example, RAS features can include error correction systems and subsystems that implement error correction codes. Such protocols are hardware features that can automatically correct memory errors after they are flagged by the RAS infrastructure. These errors can be due to noise, cosmic rays, hardware transients due to sudden changes in power lines, or physical errors in the media storing the data.

[0006] In addition, as computer memory subsystems expand in capacity, data errors become more common. Error detection and correction methods may be used alone or in combination to ensure that data read from memory is identical to data previously stored or written. RAID (Reliable Array of Independent Disks) is one such error correction method. RAID was developed for, and has historically been used for, asynchronously accessed storage devices (e.g., disks).

[0007] In contrast, computer system main memory fault protection typically uses methods of operating multiple memory components in lockstep. Compared to such methods, RAID achieves relatively efficient and higher performance memory read access, and provides both memory device and more comprehensive channel fault tolerance and data protection compared to other data integrity methods. Fast and efficient read access is desirable because reads typically speed up computing system performance, and therefore speed up power consumption. Write access typically has less impact on system performance.

[0008] RAID data and channel protection inherently incurs significant memory access amplification when data is to be written. Typically, for each write (or store) to memory requested by the host computing system, RAID requires two separate memory read (or load) accesses followed by two write (or store) accesses. This write access memory operation or command amplification complicates the use of RAID to protect low-latency, typically synchronously accessed memory that services a mix of read and write requests.

[0009] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), flash memory, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power source. SRAM memory cells can maintain their programmed state for the duration that the system is powered on. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time even in the absence of external power.

[0010] Many memory devices include multiple memory components. For example, a single read or write operation from a memory controller transfers data from or to multiple memory components in parallel. Thus, a single access may include data stored across multiple memory devices. Compute Express Link (CXL) DRAM memory devices typically require high RAS. Summary of the invention

[0011] One aspect of the present disclosure relates to a system comprising: a reliable independent array of disks (RAID) subsystem configured to maintain the integrity of a segment of memory; and a buffer memory communicatively coupled to the RAID subsystem, wherein the RAID subsystem is configured to limit the frequency of RAID access memory command amplification by accessing the buffer memory when performing an operation to maintain the integrity of the segment of memory.

[0012] In some embodiments, the RAID subsystem is further configured to perform three back-end writes.

[0013] Another aspect of the present disclosure relates to a method for reducing reliable independent disk array (RAID) command amplification when accessing a computer memory system. The method includes performing, by a RAID subsystem configured to maintain the integrity of a segment of memory, operations including: caching data in a buffer memory of the memory system; and limiting the frequency of RAID access memory command amplification by accessing the buffer memory to retrieve data while performing the operation to maintain the integrity of the segment of memory.

[0014] In some embodiments, the buffer memory is a cache memory.

[0015] In some embodiments, the memory is computer system memory.

[0016] In some embodiments, the memory is a storage memory.

[0017] In some embodiments, the frequency at which the RAID access memory commands are amplified is the frequency at which the write access memory commands are amplified.

[0018] In some embodiments, the data includes user write data and RAID XOR parity data.

[0019] In some embodiments, the parity data need not be read more than once for any later write requests.

[0020] In some embodiments, the operations further include reducing RAID parity reads when more than one data write request is collected into the buffer memory.

[0021] In some embodiments, the operations further include performing two or three back-end reads when two user data writes are collected for a given RAID stripe.

[0022] Another aspect of the present disclosure relates to a non-transitory computer-readable medium having computer-executable instructions stored thereon, which, if executed by a computing device, causes the computing device to perform a method for reducing reliable independent disk array (RAID) command amplification when accessing a computer memory system. The method includes performing, by a RAID subsystem configured to maintain the integrity of a segment of memory, operations including: caching data in a buffer memory of the memory system; and limiting the frequency of RAID access memory command amplification by accessing the buffer memory to retrieve data when performing the operation to maintain the integrity of the segment of memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The illustrative embodiments may take the form of various components and arrangements of components. The illustrative embodiments are shown in the accompanying drawings, and the same reference numerals throughout the drawings may indicate corresponding or similar parts in the various figures. The drawings are only used for the purpose of illustrating the embodiments and should not be construed as limiting the present disclosure. In view of the following illustrative description of the drawings, the novel aspects of the present disclosure should become apparent to those of ordinary skill in the relevant art.

[0024] Figure 1 A block diagram illustrating a system including a host and a memory module according to aspects of the present disclosure.

[0025] Figure 2 A table showing command amplification execution for several cases according to several aspects of the present disclosure is illustrated.

[0026] Figure 3 Graphs illustrating several aspects according to the present disclosure.

[0027] Figure 4 Graphs illustrating several aspects according to the present disclosure.

[0028] Figure 5 Graphs illustrating several aspects according to the present disclosure.

[0029] Figure 6 Graphs illustrating several aspects according to the present disclosure.

[0030] Figure 7 Graphs illustrating several aspects according to the present disclosure.

[0031] Figure 8 Graphs illustrating several aspects according to the present disclosure.

[0032] Fig. 9 Methods according to several aspects of the present disclosure are described. DETAILED DESCRIPTION

[0033] Although illustrative embodiments are described herein for particular applications, the present disclosure is not limited thereto. Those skilled in the art having knowledge of the teachings provided herein will recognize additional applications, modifications, and embodiments within the scope thereof as well as additional areas in which the present disclosure may be of obvious utility.

[0034] By way of example only and not limitation, embodiments of the present disclosure include a platform of RAID protected memory devices. Embodiments are characterized by the use and / or mechanization of buffer memory or cache memory, not to improve read performance, but to reduce the frequency of RAID write access memory command amplification in memory, and thus reduce its negative performance and power consumption impact.

[0035] Embodiments provide several advantages over conventional systems. For example, a write cache as provided by embodiments for caching either or both of data read from a memory or storage device back end and / or write data written by a host front end can reduce the number of back end reads and writes, and filter requests to the back end for accesses that are close to each other in both address space and cycle or access sequence order.

[0036] Additionally, write caching as provided by embodiments may also be combined with RAS schemes and prefetching to also reduce average read latency. For example, the following may be prefetched and cached to reduce latency and / or operations involved in completing subsequent host system requests.

[0037] Figure 1 A functional block diagram of a system 100 according to an embodiment is illustrated. The system 100 includes a host system 102 coupled to a memory module 101 via a communication link 105. The host system 102 may be a system or subsystem configured to access the memory module 101 to write data therein or read data therefrom. By way of example and not limitation, the host system may be a central processing unit (CPU), a graphics processing unit (GPU), or generally a computer system or subsystem that is equipped in hardware and software with components and protocols for performing write and read operations from the memory module 101.

[0038] Additionally, one of ordinary skill in the art will readily appreciate that the arrangement of data in the memory module 101 may be arbitrary, and the methods and systems disclosed herein are not limited to a particular data arrangement when considering the memory module 101. Furthermore, the host system 102 may be communicatively coupled to the memory module 101 via a bus, a CXL bus, or may be co-located on the same chip or on the same board.

[0039] Memory module 101 may include a front end module 106 having circuitry for input and output functions. Such circuitry may include, for example, but not limited to, hardware for packaging commands received from host system 102 in a predetermined format, and similarly circuitry for packaging data obtained from memory in a predetermined format before routing such data to host system 102 upon request.

[0040] The memory module 101 may include a buffer cache (or buffer memory) 108 configured to cache write data in order to limit the frequency of RAID access memory command amplification. This feature may be achieved by accessing the buffer cache 108 to retrieve data when performing operations to maintain the integrity of the segments of the memory component 114. In general, the buffer cache 108 may be configured for write caching and pre-fetching write data stored therein.

[0041] The memory module 101 may further include a security and reliability, availability, and serviceability (SRAS) module 110 that may be configured to perform one or more tasks associated with maintaining the integrity of data located in the memory component 114. By way of example and not limitation, one such task may be a RAID protocol configured to ensure the integrity of the data in the memory component 114. When executing such a RAID protocol, the SRAS module 110 may be configured to cache write data in the buffer cache 108 and / or it may be configured to pre-fetch write data from the buffer cache 108 to reduce RAID access command amplification.

[0042] The memory module 101 may further include a back-end module 112 that interfaces the SRAS module 110 with the memory component 114. The back-end module 112 may generally include interface circuitry that allows read / write operations to be performed on one or more sectors of the memory component 114.

[0043] The memory module 101 may include a memory component 114. The memory component 114 may include memory cells of any architecture without departing from the teachings of the present disclosure. For example, the memory component 114 may include a DRAM array, an SRAM array, etc. In general, the memory component 114 may be any storage technology that uses an array of memory segments to store data.

[0044] Figure 2 Several execution examples 200 according to an embodiment are described. Figure 2 middle, Figure 1 The host system 102 of the embodiment exchanges commands and / or data with the memory module 101 at a bandwidth corresponding to, for example but not limited to, an 8-lane CXL3 host interface. Therefore, the execution results of the embodiments depend on these constraints. Without loss of generality, one of ordinary skill in the art will recognize that the execution results may vary depending on bandwidth and other factors while providing the reduction in command amplification provided by the embodiments.

[0045] Specifically, table 202 shows typical read / write hybrid commands sent from host system 102 to memory module 101. These commands may occur in several non-limiting sample cases in column 202a of table 202. For example, sample case 1 Figure 2(1F2) represents 100% write commands; sample case-2F2 represents 30% read commands and 70% write commands; sample case-3F2 represents an even split: 50% read and 50% write commands; and sample case-4F2 represents 100% read commands. The read commands 202b and write commands 202c of table 202 illustrate general bandwidth consumption. Here, bandwidth consumption is a function of the architecture of the communication link 105 coupling the host system 102 and the memory module 101.

[0046] Table 204 depicts a scenario where the RAID protocol is initially executed, i.e., as RAID protocols in current advanced technology systems typically do. In this sampling approach, in an embodiment, write command 204c is amplified by 2 times compared to right command 202c. Table 204 also illustrates read command overhead 204b. This results in additional bandwidth usage and memory access. As can be seen in column 204d of table 204, when considering sample cases 1 to 3, write commands are amplified by at least 2.5 times (e.g., 2.5×, 3.11×, 4×, etc.). The only sample case without command amplification is sample case-4, in which all requests of host system 102 are read requests.

[0047] Table 206 illustrates the execution of an embodiment employing write caching and prefetching commands with buffer cache 108. For Case-1F2, command amplification is 1.25× (reduced from 4× in Table 204), for Case-2F2 is 2× (reduced from 3.11×), and for Case-3F2 is 1.12× (reduced from 2.5×). As shown here, system 100 can reduce memory access command amplification and save bandwidth and power using an exemplary write caching and prefetching method.

[0048] Figure 3 Graph 300 illustrates memory access patterns for an initial RAID case when read cache hits and misses occur in the absence of RAS errors. In particular, graph 300 shows three sample cases: Sample Case 100: Sample Case 201: Sample Case 302: Sample Case 303: Sample Case 304: Sample Case 305: Sample Case 306: Sample Case 307: Sample Case 308: Sample Case 309: Sample Case 101: Sample Case 309: Figure 3 (1F3); when there is a cache read miss 304 without cache allocation, sample case-2F3; and when there is a cache read miss 306 with allocation, sample case-3F3. In sample case-3F3, cache allocations require additional cache transactions over time, such as cache requests 308 and eviction victims 310, which require and consume additional cache bandwidth. By way of example, if the cache is kept clean, i.e., all writes are written through to the memory component 114, no eviction victim 310 is required.

[0049] Figure 4 Description for sample cases (e.g., Sample Case-1 Figure 4 400 of memory access patterns for sample cases (1F4) and (2F4), characterized by read / write collection cache hits and misses in the absence of RAS errors. In these cases, cache misses (e.g., 402 and 404) occur in the case of allocation, and cache misses with collected RAS stripe evictions occur before allocation. Cache allocations then require additional cache transactions, increasing required cache bandwidth. If the cache is kept clean, i.e., all writes are written through to the memory component 114, then there is no need to evict the victim segment 406.

[0050] Figure 5 Description used in case (for example, sample case-1 Figure 5 5F5) and a sample case-2F5) of memory access patterns, characterized by write cache hits without and with collection and cache allocation. In these cases, parity is not allocated in the cache, and striped parity reads are updated by the RAS manager (e.g., within the SRAS module 110) in the buffer cache 108. In this embodiment, writes cache both new data 502 and parity, thereby enabling striped collection. Parity is updated using updates to the miss table array. In addition, write requests initiate both data and parity cache requests, and the tags must know the RAS mapping from the SRAS module 110.

[0051] Figure 6 Description used in case (for example, sample case-1 Figure 6 An exemplary graph 600 of memory access patterns for sample cases (1F6) and (2F6) characterized by write cache misses with gather and parity cache allocation. In these cases, writes are not allocated in cache and stripe parity reads and updates are affected by the RAS manager in the SRAS module 110. In addition, writes allocated in cache are dirty (i.e., there is no write-through) and the victim stripe parity is updated by the RAS manager of the SRAS module 110.

[0052] Figure 7 Description used in case (for example, sample case-1 Figure 7An exemplary graph 700 of memory access patterns for sample cases (1F7) and (2F7) characterized by write cache misses with gather and parity cache allocation. In these cases, writes are not allocated in the cache and striped parity reads are updated by the RAS manager of the SRAS module 110. Additionally, writes allocate new data and the miss table updates the parity in the cache to enable gather.

[0053] Figure 8 Description used in case (for example, sample case-1 Figure 8 8) and sample case - 2F8), characterized by a write cache miss with a collect on a RAS stripe of the cache. In sample cases - 1F8 and 2F8, write requests (e.g., 802 and 804) cache both new data 806 and stripe parity 808, which enables collect, and miss table 810 updates stripe parity 808. In these cases, if parity is always the last stripe sector to be evicted, a write data cache hit with a RAS stripe parity cache miss is not possible. If the cache is maintained clean, the victim cache line does not need to be evicted and written back to memory. However, the write request initiates both data and parity cache requests, and the cache tags are aware of the RAS mapping.

[0054] As one of ordinary skill in the art will readily recognize, the write cache features contemplated in the present disclosure can be implemented in several ways. By way of example only, four non-limiting examples of write cache implementations for use with a RAID5 (4+1) subsystem to implement channel fault tolerance within an overall RAS scheme of a 64B host system user data cache line length are noted below. Write cache lines can be managed as 64B sectors to match the host system cache line size and facilitate write cache management.

[0055] In a first embodiment, the row or block size of the write cache memory is 320B (i.e., 256B user data + 64B RAID XOR or 5×64B sectors per write cache line, sized to fit exactly in a RAID stripe). In a second embodiment, a write cache memory may have a row or block size greater than 320B (e.g., 512B), with an entire RAID stripe containing both 4 user data 64B sectors and an associated RAID stripe exclusive-OR (XOR) 64B sector constituting a 320B portion of a cache line.

[0056] In a third embodiment, separate cache memories may be used, one cache having a 256B cache line / block size containing 4 adjacent 64B user data sectors, and a second cache having a 64B cache line / block size for RAS XOR. In a fourth embodiment, the row or block size of the write cache memory is 64B, where each row can store a 64B host system user data cache line or a 64B RAID XOR without cache index conflicts between all user data cache lines and the RAID stripe XOR in the RAID stripe.

[0057] Fig. 9 A flow chart illustrating an exemplary method 900 of practicing an embodiment of the present invention, beginning at block 902. The method 900 includes allocating host write request data into a write buffer cache (e.g., buffer cache 108) at block 904. At decision block 906, the method 900 detects whether enough time and / or unrelated requests have passed, or infers that the backend memory (e.g., memory component 114) is opportunistically available based on one or more measurements of past requests. Such requests may include, for example, a moving average request rate over a variable time window.

[0058] If the backend memory is available, the method 900 includes reading the old data and calculating partial parity for storage in the buffer cache at block 908. The method 900 further includes repeating blocks 904 to 908 for write requests to the same RAID stripe. Additionally, at block 910, the method 900 further includes waiting until the data or parity cache entry is to be victimized, or if the entire RAID stripe has been written and the backend memory is available, whether the method includes initiating a victimization.

[0059] If the case write for the entire RAID data stripe has been cached, method 900 includes calculating parity (ie, discarding the cached portion of parity) and writing both the data and the calculated parity to the back end.

[0060] Otherwise, the method 900 continues to block 912 to read the original parity from the back-end memory and calculate the new stripe parity. Block 912 also includes writing both the parity and the new data sectors to the back-end memory. Alternatively, the method 900 will continue to block 914 to read the unwritten data sectors from the back-end, calculate the new stripe parity, and write both the new parity and the new data sectors to the back-end. The exemplary method 900 ends at block 916.

[0061] Having described several specific embodiments, a general embodiment consistent with the teachings of the present disclosure is now described. By way of example and not limitation, such embodiments may be systems or methods. An example system may include a RAID subsystem configured to maintain the integrity of a segment of memory. The system may further include a buffer memory coupled to the RAID subsystem in a communicative manner. And the RAID subsystem may be configured to limit the frequency of RAID access memory command amplification by accessing the buffer memory, and the subsystem is performing an operation configured to maintain the integrity of a segment of memory.

[0062] Without loss of generality, the buffer memory may be a cache memory, or it may be a memory module of a computer system, or it may be a memory module of a storage device. The RAID subsystem is further configured to limit the frequency of amplification of RAID write access memory commands. In addition, the system may be configured to cache data in the buffer memory, and the cached data may be user data and / or RAID XOR parity data. In such cases, the parity does not need to be read more than once for any later write request.

[0063] In addition, the RAID subsystem may be further configured to reduce RAID parity reads when more than one data write request is collected into the buffer memory. And the RAID subsystem may be further configured to perform two or three back-end reads and / or three back-end writes when two user data writes are collected for a given RAID stripe.

[0064] An example method may be configured for reducing RAID command amplification when accessing memory. The method may include performing certain operations by a RAID subsystem configured to maintain the integrity of a segment of memory. The operations may include caching data in a buffer memory and limiting the frequency of RAID access memory command amplification. The latter may be achieved by accessing the buffer memory to retrieve data when performing operations to maintain the integrity of the segment of memory.

[0065] In the above method, the buffer memory may be one of the cache memories. In addition, the memory (i.e., not the buffer memory) may be a computer system memory or a storage memory. In the above method, the frequency of RAID access memory command amplification may be the frequency of write access memory command amplification, and the cached data may include write user data and / or RAID XOR parity data. And for any later write request, the parity data does not need to be read more than once.

[0066] The operations may further include reducing RAID parity reads when more than one data write request is collected into the buffer memory. And the operations may further include performing two or three back-end reads when two user data writes are collected for a given RAID stripe. In addition, the operations may include performing three back-end writes.

[0067] In general, embodiments impart several advantages, some of which are discussed below. For example, a write cache for caching either or both of data read from a memory or storage device back end and / or write data written by a host front end as provided by embodiments can reduce the number of back end reads and writes, and filter requests to the back end for accesses that are close to each other in both address space and cycle or access sequence order.

[0068] Additionally, write caching as provided by embodiments may also be combined with RAS schemes and prefetching to similarly reduce average read latency. For example, the following may be prefetched and cached to reduce latency and / or operations involved in completing subsequent host system requests: When a RAID detects a failed read, channel fault tolerance requires reading all other user data and parity in the associated RAID stripe, which may then be cached to satisfy future host read requests.

[0069] Those skilled in the relevant art will appreciate that various adaptations and modifications of the above embodiments may be configured without departing from the scope and spirit of the present disclosure. It is therefore to be understood that within the scope of the appended claims, the present disclosure may be practiced in a manner other than as specifically described herein.

Claims

1. A system comprising: A reliable independent disk array RAID subsystem configured to maintain the integrity of the memory segment; and a buffer memory communicatively coupled to the RAID subsystem, Wherein the RAID subsystem is configured to limit the frequency of RAID access memory command amplification by accessing the buffer memory when performing operations to maintain the integrity of the segment of the memory.

2. The system of claim 1, wherein the buffer memory is a cache memory.

3. The system of claim 1, wherein the memory is a computer system memory. The system according to claim 1 , wherein the memory is a storage memory.

5. The system of claim 1, wherein the frequency at which RAID access memory commands are amplified is a frequency at which write access memory commands are amplified.

6. The system of claim 1, wherein the system is configured to cache write user data and RAID XOR parity data in the buffer memory.

7. The system of claim 6, wherein the parity data need not be read more than once for any later write request.

8. The system of claim 1, wherein the RAID subsystem is further configured to reduce RAID parity reads when more than one data write request is collected into the buffer memory.

9. The system of claim 1, wherein the RAID subsystem is further configured to perform two or three back-end reads when two user data writes are collected for a given RAID stripe.

10. A method for reducing reliable independent disk array (RAID) command amplification when accessing a computer memory system, the method comprising: Operations performed by a RAID subsystem configured to maintain the integrity of a segment of memory include: caching data in a buffer memory of the memory system; and The frequency of RAID access memory command amplification is limited by accessing the buffer memory to retrieve the data while performing operations to maintain the integrity of the sectors of the memory.

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