One-time programmable control of memory subsystems
By introducing controller-managed OTP write operations in the memory subsystem, the problems of high cost and low portability of traditional OTP memory are solved, and the secure storage of OTP data and the flexibility of the system are improved.
Patent Information
- Application Number
- CN202411056076.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-22
- Filing Date
- 2024-08-02
- Publication Date
- 2025-02-14
AI Technical Summary
Traditional microcontrollers use one-time programmable (OTP) memory to increase costs and reduce portability when storing sensitive data, while having limitations in encryption and preventing playback attacks.
A memory subsystem is designed, including one-time programmable (OTP) areas and shared areas, which manages OTP write operations through the controller, prevents the processor from providing shared memory operations, ensures the confidentiality and immutability of OTP data, and in the Recover shared memory after writing is completed.
It reduces the overall cost of OTP operation, avoids CPU locking, realizes confidentiality and immutability of the OTP area, and improves the flexibility and portability of the system.
Smart Images
Figure CN119441124A_ABST
Abstract
Description
[0001] CROSS REFERENCE TO RELATED APPLICATIONS
[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 517,372, entitled "SECURE ONE-TIME PROGRAMMABLE MEMORY CONTROLLER ARCHITECTURE", attorney file number T102931US01, filed on August 3, 2023. The entire contents of the above patent application are hereby cited. Background Art
[0003] Microcontrollers, including but not limited to those intended for security applications, may employ one-time programmable (OTP) memory to store sensitive data. In traditional designs, OTP memory is a dedicated hardware block with its own logic to implement field programming and security functions. These OTP features increase cost and reduce portability. Another traditional example is the use of encryption to store sensitive data in a security module without OTP memory. However, such systems are susceptible to replay attacks (firmware image rollback) and have limitations in encryption data verification and support for different types of applications. Summary of the invention
[0004] In one example, a device includes: a hardware security module; a processor; a memory subsystem; and a controller. The memory subsystem includes a write interface and a memory. The write interface includes a storage / storage device. The memory includes a first area and a second area. The first area is a one-time programmable (OTP) area. The second area is a shared area. The controller is located between the hardware security module, the processor, and the memory subsystem. The controller is configured to: receive an OTP write request instruction from the hardware security module; in response to the OTP write request instruction and the confirmation of the processor, prevent the processor from providing a shared memory operation; cause OTP data associated with the OTP write request instruction to be written to the first area of the memory; clear the storage of the write interface after completing the writing of the OTP data; and stop preventing the provision of the shared memory operation after clearing the storage of the write interface.
[0005] In another example, a circuit includes a controller adapted to be coupled to a memory subsystem. The controller is configured to: receive an OTP write request; in response to the OTP write request, block a shared memory request from being provided to the memory subsystem; cause OTP data associated with the OTP write request to be provided to the memory subsystem; receive a notification that the OTP data has been written to the memory subsystem; and in response to the notification, stop blocking the shared memory request from being provided to the memory subsystem.
[0006] In another example, a method includes: receiving an OTP write request instruction through a first interface; in response to the OTP write request instruction and an acknowledgement by the processor, preventing the processor from providing a shared memory operation; writing OTP data associated with the OTP write request instruction to a first area of a memory through a second interface separate from the first interface; clearing the storage of the write interface after completing the writing of the OTP data; and stopping preventing the providing of the shared memory operation after clearing the storage of the write interface. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 is a schematic diagram illustrating an example system.
[0008] Figure 2 is a schematic diagram illustrating another example system.
[0009] Figure 3 is a schematic diagram showing example signaling for a first interface and a second interface.
[0010] Figure 4 is a flow chart illustrating an example OTP control method. DETAILED DESCRIPTION
[0011] In the drawings, the same reference numbers or other reference identifiers are used to indicate features having the same or similar features. These features may have the same or similar features in function and / or structure.
[0012] This article describes a memory subsystem having a one-time programmable (OTP) area and a shared area. The memory subsystem can be read and written through a firewall. In some examples, the OTP write operation is managed by a controller. Example operations of the controller include: receiving an OTP write request instruction from a hardware security module; in response to the OTP write request instruction, blocking the processor from providing a shared memory operation; writing OTP data related to the OTP write request instruction to the OTP area of the memory subsystem; clearing the storage of the write interface after completing the writing of the OTP data; and stopping blocking the provision of the shared memory operation after clearing the storage of the write interface. In some examples, the OTP read operation is performed through a parallel interface.
[0013] In some examples, the controller emulates OTP memory using shared flash memory by reusing existing flash controller hardware. In some examples, timing flexibility for a system processor is supported, where the start of an OTP write operation is adjustable to allow the system processor to complete operations with a threshold priority. In some examples, system processor operations below a threshold priority are deferred until the OTP write operation is completed. In some examples, the controller ensures that the OTP region of the memory subsystem adheres to security properties of confidentiality and immutability while avoiding CPU lockup during ongoing OTP operations.
[0014] By using a controller and a shared memory subsystem, the overall cost of providing OTP operations is reduced compared to using separate OTP memory and / or duplication of logic. In some cases, the controller is integrated with standard interfaces and can reuse hardware with existing hardware security module options.
[0015] Figure 1 is a schematic diagram showing an example system 100. As shown, the system 100 includes a hardware security module (HSM) 102, a processor (CPU) 106, a controller 110, a memory subsystem 150, a first interface 170, a second interface 172, and a system bus 174. The memory subsystem 150 includes a write interface (I / F) 156 and a memory 162. The memory 162 includes a first area 166 and a second area 168. In one example, the system 100 is a system on a chip (SoC). In another example, the system 100 includes multiple integrated circuits (ICs). For example, the HSM 102, the processor 106, and the controller 110 may be components of a first IC, while the memory subsystem 150 is a component of a second IC.
[0016] exist Figure 1 In the example of FIG. 1 , HSM 102 has terminal 104. Processor 106 has first terminal 108 and second terminal 109. Controller 110 has first terminal 112, second terminal 114, third terminal 116, fourth terminal 118, and fifth terminal 120. Memory subsystem 150 has first terminal 152 and second terminal 154. Write I / F 156 has first terminal 158 and second terminal 160. Memory 162 has first terminal 164 and second terminal 165.
[0017] A terminal of the HSM 102 is coupled to a first terminal 112 of the controller 110. A first terminal 108 of the processor 106 is coupled to a second terminal 114 of the controller 110. A second terminal 109 of the processor 106 is coupled to a third terminal 116 of the controller 110. A fourth terminal 118 of the controller 110 is coupled to the system bus 174. A fifth terminal 120 of the controller 110 is coupled to both a first terminal 152 of the memory subsystem 150 and a first terminal 158 of the write I / F 156. A second terminal 160 of the write I / F 156 is coupled to a first terminal 164 of the memory 162. A second terminal 165 of the memory 162 is coupled to a second terminal 154 of the memory subsystem 150.
[0018] exist Figure 1 In an example of the controller 110, the controller 110 includes an OTP control logic 122, a multiplexer (MUX) 140, a write interface (I / F) firewall 134, and the multiplexer 140. The OTP control logic 122 has a first terminal 124, a second terminal 126, a third terminal 128, a fourth terminal 130, a fifth terminal 132, and a sixth terminal 133. In some cases, the OTP control logic 122 includes a finite state machine (FSM) with dedicated hardware for performing OTP operations. In some examples, the OTP control logic 122 includes a processor and a memory having OTP instructions executed by the processor. When the OTP instruction is executed, the OTP instruction causes the processor of the OTP control logic 122 to perform an OTP operation such as the example OTP operation described herein. The write I / F firewall 134 has a first terminal 135, a second terminal 136, and a third terminal 138. The multiplexer 140 has a first terminal 142 , a second terminal 144 , a third terminal 146 , and a fourth terminal 148 .
[0019] In some examples, the operation of the HSM 102 includes: identifying an OTP write trigger; in response to identifying the OTP write trigger, providing an OTP write request instruction, the OTP write request instruction being provided to the controller 110; in response to providing the OTP write request instruction, receiving a first confirmation from the controller 110, the first confirmation indicating that the OTP write request instruction has been received; in response to providing the OTP write request instruction, receiving a second confirmation from the controller 110, the second confirmation indicating that the controller 110 is ready for the OTP write operation; and providing OTP data associated with the OTP write request instruction to the controller 110. The operation of the HSM 102 involves sending and receiving instructions containing data and / or signals between the HSM 102 and the controller 110 through the first interface 170. In some examples, the instructions provided from the HSM 102 to the controller 110 are sent from the terminal 104 of the HSM 102 to the terminal 112 of the controller 110. Moreover, the instructions provided from the controller 110 to the HSM 102 are sent from the terminal 112 of the controller 110 to the terminal 104 of the HSM 102. In other examples, the HSM 102 and the controller 100 may include other terminals associated with the first interface 170 .
[0020] The processor 106 operates as follows: performs processing operations based on instructions and / or data stored in the memory subsystem 150; receives a first interrupt instruction from the controller 110; provides a first confirmation to the controller 110 in response to the first interrupt instruction, the first confirmation indicating that the first interrupt instruction is received; provides a second confirmation to the controller 110 in response to the first interrupt instruction, the second confirmation indicating that the processor 106 is in a standby state. During the standby state, the processor 106 does not read or write to the memory subsystem 150. During the OTP write (e.g., when the processor is in the standby state), the content and location of the OTP write are not visible to the processor 106.
[0021] The controller 110 operates as follows: receiving an OTP write request instruction from the HSM 102; providing a confirmation to the HSM 102 in response to the OTP write request instruction; providing a first interrupt instruction to the processor 106 in response to the OTP write request instruction; receiving a first confirmation from the processor 106 in response to the first interrupt instruction, the first confirmation indicating that the processor 106 has received the first interrupt instruction; receiving a second confirmation from the processor 106 in response to the first interrupt instruction, the second confirmation indicating that the processor 106 is in a standby state; sending a notification to the HSM 102, the notification indicating that the controller 110 is ready for an OTP write operation; receiving OTP data from the HSM 102 through the first interface 170 in response to the notification, and transmitting the OTP data to the memory subsystem 150 through the second interface 172; clearing the storage of the write I / F 156 after completing the OTP write operation; and providing a second interrupt instruction to the processor 106, the second interrupt instruction indicating that the shared memory operation is available.
[0022] More specifically, the OTP control logic 122 of the controller 112 operates as follows: receiving an OTP write request instruction from the HSM 102 at the first terminal 124; providing an acknowledgment to the HSM 102 at the first terminal 124 in response to the OTP write request instruction; and providing a control signal (OTP_CS) at the sixth terminal 133 in response to the OTP write request instruction. In some examples, the OTP_CS provides an identifier and mode information to the write I / F firewall 134, wherein the identifier controls the OTP write access of the write I / F firewall 134. In some examples, the write I / F firewall 134 monitors write access attempts to the memory subsystem 150 from the system bus 174 and blocks any attempt to trigger programming of the first region 166 of the memory 162 of the memory subsystem 150.
[0023] The OTP control logic 122 of the controller 112 also operates as follows: in response to an OTP write request instruction, providing a first interrupt instruction to the processor 106 at the fourth terminal 130; in response to the first interrupt instruction, receiving a first confirmation from the processor 106 at the second terminal 126, the first confirmation indicating that the processor 106 has received the first interrupt instruction; in response to the first interrupt instruction, receiving a second confirmation from the processor 106 at the second terminal 126, the second confirmation indicating that the processor 106 is in a standby state; providing a notification to the HSM 102 at the first terminal 124, the notification indicating that the controller 112 is ready for an OTP write operation; in response to the notification, receiving OTP data from the HSM 102 at the first terminal 124 through the first interface 170; in response to receiving the OTP data, providing a multiplexer control signal (MUX SEL) at the third terminal 128; and providing the OTP data to the fifth terminal 132 after providing MUX SEL to the third terminal 128.
[0024] Write I / F firewall 134 operates as follows: receives OTP_CS at first terminal 135; receives write requests and / or write data at second terminal 136; and provides each write request and / or write data at third terminal 138 in response to an identifier provided along with the respective write request and / or write data and the current mode of controller 110. Mode options include OTP mode and shared memory mode.
[0025] Multiplexer 140 operates as follows: receives OTP data at first terminal 142; receives other data at second terminal 144; receives MUX_SEL at third terminal 146; and provides OTP data or other data at fourth terminal 148 in response to MUX_SEL.
[0026] The memory subsystem 150 operates as follows: receiving OTP data or other data at the first terminal 152. If OTP data is received, the write interface 156 writes the OTP data to the first storage area 166 of the memory 162 and clears the storage of the write interface 156 used to write the OTP data. If other data is received, the write interface 156 writes it to the second storage area 168 of the memory 162. In addition, the memory subsystem 150 may also operate as follows: receiving a read request at the second terminal 154. If the read request corresponds to the OTP data in the first area 166 of the memory 162, the memory subsystem 150 retrieves the OTP data from the first area 166 of the memory 162 and provides it to the second terminal 154; if the read request corresponds to some other data in the second area 168 of the memory 162, the memory subsystem 150 retrieves the requested data from the second area 168 of the memory 162 and provides it to the second terminal 154. In some cases, by using a read firewall ( Figure 1 (not shown) to restrict access to memory at 150. In this example, the read firewall restricts reading of the first storage area 166 of memory at 162 to a specific component (e.g., HSM 102) based on a component identifier and / or other protection scheme.
[0027] Figure 2 2 is a schematic diagram showing another example system 200. As shown in the figure, the system 200 includes the HSM 102, the processor 106, the controller 110, the flash memory subsystem 150A, the first interface 170, the second interface 172, the system bus 174, the system crossbar 204 and the read firewall 218. The flash memory subsystem 150A is Figure 1 1. The system 200 is an example of a memory subsystem 150 in FIG. 1. In one example, the system 200 is a system on a chip (SoC). In another example, the system 200 includes multiple integrated circuits (ICs). For example, the HSM 102, the processor 106, and the controller 110A may be components of a first IC, while the flash subsystem 150A and the read firewall 218 are components of a second IC. If different ICs are used, an encrypted link and / or cryptographic credentials can be used to maintain the security of the OTP write and subsequent read operations.
[0028] exist Figure 2 In the example of FIG. 1 , HSM 102, processor 106, and controller 110 have Figure 1 The flash memory subsystem 150A has terminals for Figure 1The terminals of the memory subsystem 150 described in FIG. 2 are shown in FIG. 2. The read firewall 218 has a first terminal 220 and a second terminal 222. The system crossbar 204 has a first terminal 206, a second terminal 208, a third terminal 210, a fourth terminal 212, a fifth terminal 214, and a sixth terminal 216.
[0029] exist Figure 2 In the example, the controller 110 includes Figure 1 The flash memory subsystem 150A includes a write interface 156A and a memory 162. The write interface 156A is Figure 1 An example of writing interface 156 is shown in FIG. Figure 2 In the example of FIG. 1 , the write interface 156A includes a memory mapped register (MMR) I / F 226 and a flash controller 232. The MMR I / F 226 has a first terminal 228 and a second terminal 230. In some examples, the MMR I / F 226 includes a set of MMRs. The flash controller 232 has a first terminal 234 and a second terminal 236. The memory 238 has a Figure 1 The terminal.
[0030] exist Figure 2 In the example of FIG. 1 , a first terminal 206 of the system cross bar 204 is coupled to the terminal 104 of the HSM 102. A second terminal 208 of the system cross bar 204 is coupled to the first terminal 112 of the controller 110. A third terminal 210 of the system cross bar 204 is coupled to the second terminal 114 of the controller 110. A fourth terminal 212 of the system cross bar 204 is coupled to the first terminal 108 of the processor 106. A fifth terminal 214 of the system cross bar 204 is coupled to the fourth terminal 118 of the controller 110. A sixth terminal 216 of the system cross bar 204 is coupled to the first terminal 220 of the read firewall 218. A second terminal 222 of the read firewall 218 is coupled to the second terminal 154 of the flash subsystem 150A. A first terminal 228 of the MMR I / F 226 is coupled to the first terminal 158 of the write I / F 156, which is coupled to the first terminal 152 of the flash subsystem 150A. The second terminal 230 of the MMR I / F 226 is coupled to the first terminal 234 of the flash controller 232. The second terminal 236 of the flash controller 232 is coupled to the first terminal 164 of the memory 162. The second terminal 165 of the memory 162 is coupled to the second terminal 154 of the flash subsystem 150A.
[0031] In some examples, HSM 102, processor 106, and controller 110 perform Figure 1 The flash memory subsystem 150A performs the corresponding operations described in Figure 1156A stores information for write operations. Example registers of the MMR I / F 226 may include: an address register, a write data register (multiple), an enable register, a control command register, an execution register, and a status register. The address register stores the write location to be programmed. The write data register (multiple) stores the write data to be programmed to the address. The enable register stores a byte mask of valid bytes in the write data. In some examples, only data bytes marked as valid can be written. The control command register stores the flash controller program commands for the write operation. The execution register stores the execution trigger that starts the write operation. The status register tracks the status of the write operation.
[0032] The flash controller 232 operates as follows: it receives information for a write operation from the MMR I / F 226, and performs a write operation to the memory 162 according to the received information. The memory 162 operates as follows: it writes data to an address indicated by the flash controller 232, and reads data at an address indicated by the read interface included in the memory 162 or the flash subsystem 150A.
[0033] exist Figure 2 In some examples, the system crossbar 204 selectively connects different ports or interfaces of the system 200 in a manner that minimizes switching delays and propagation delays. The read firewall 218 is used to manage reads to the flash subsystem 150A. In some examples, the read firewall 218 allows certain areas of the memory 162 (e.g., Figure 1 The second area 168 in the memory 162 is read without restriction, while other areas of the memory 162 (e.g., Figure 1 In various examples, the read firewall 218 may allow reading of the restricted area of the memory 162 based on a correct component identifier provided by the component requesting the read, a verification process for the component requesting the read, or other restriction techniques.
[0034] In some examples, HSM 102 is inserted into a Figure 2 In these examples, OTP operation is implemented with minimal or no impact on other functions of the SoC. Figure 2 In the example of FIG. 1 , controller 110 and flash memory subsystem 150A perform the following operations by using a first area of memory 162 (eg, in Figure 1166 in the first area 166) to emulate secure OTP. In some examples, the flash memory subsystem 150A has a direct parallel interface for reading, while writing is controlled by the flash memory controller 232. In some examples, the flash memory controller 232 interacts with other components of the system 200 through the MMR I / F 226 and the second interface 172. In some examples, the MMR I / F 226 includes storage for addresses, write data, enable indicators, control commands, execution triggers, and status indications as described herein. In some examples, the registers of the MMR I / F 226 are written in sequence through the second interface 172, and the controller 110 monitors the completion by polling the status register of the MMR I / F 226.
[0035] In some examples, the controller 110 converts a single write access on the first interface 170 into a programming sequence on the second interface 172. For example, the first interface 170 can be an advanced high-performance bus (AHB) or an advanced peripheral bus (APB). The flash subsystem 150A is a shared resource, and in some examples, only a portion of the memory 162 is simulated as an OTP area. In this example, the second interface 172 is not specifically used for OTP writing. For security reasons, system components other than the HSM 102 may be blocked from programming access to the OTP area of the memory 162. In some examples, the OTP address / data is confidential, and the controller 110 may clear the MMR after the OTP write operation. In some examples, the OTP write operation does not interfere with the user application. To avoid such interference, the controller 110 may generate an interrupt instruction to the processor 106 to indicate the start and end of the OTP write operation.
[0036] In some examples, a device includes: an HSM (e.g., Figure 1 and Figure 2 HSM 102 in ); processor ( Figure 1 and Figure 2 processor 106 in the processor); memory subsystem (e.g., Figure 1 The memory subsystem 150 or Figure 2 Flash memory subsystem 150A in; and a controller (e.g., Figure 1 and Figure 2 In some examples, the memory subsystem includes a write interface (e.g., Figure 1 and Figure 2 The write interface 156 or Figure 2 ) and having a first region (e.g., Figure 1 166 in the first region) and the second region (e.g., in the Figure 1 168) in the memory (e.g., in Figure 1and Figure 2 The first area is an OTP area. The second area is a shared area. Each of the first area and the second area is defined by a corresponding address range of the memory 162. The controller is located between the HSM, the processor, and the memory subsystem. In some examples, the controller is configured to: receive an OTP write request instruction from a hardware security module; in response to the OTP write request instruction and the confirmation of the processor, prevent the processor from providing a shared memory operation; cause the OTP data associated with the OTP write request instruction to be written to the first area of the memory; clear the storage of the write interface after completing the writing of the OTP data; and stop preventing the provision of the shared memory operation after clearing the storage of the write interface.
[0037] In some examples, the controller includes a write interface firewall (e.g., Figure 1 and Figure 2 The controller may include a write interface firewall 134 located between the processor and the memory subsystem. The write interface firewall is configured to prevent the processor from providing shared memory requests to the write interface during the OTP interval. In some examples, the controller may include a terminal (e.g., Figure 1 and Figure 2 The fifth terminal 120 in the OTP control logic (eg, Figure 1 and Figure 2 OTP control logic 122 in) and multiplexers (e.g., Figure 1 and Figure 2 The multiplexer 140 in the memory subsystem is coupled to the terminal. The multiplexer is configured to selectively forward data from the OTP control logic or the write interface firewall to the terminal.
[0038] In some examples, the device includes a read firewall (e.g., Figure 2 The HSM may include a read firewall 218 in the memory subsystem, which is located between the processor and the memory subsystem. The read firewall is configured to prevent the processor from reading the first area of the memory. In some examples, the HSM is configured to initiate an OTP write request instruction in response to a request from the processor. In some examples, the OTP data includes an encryption certificate or key. In some examples, the OTP data includes a monotonic count value.
[0039] In some examples, the device includes: a first interface (eg, Figure 1 and Figure 2 170); and a second interface (eg, Figure 1 and Figure 2The first interface is located between the hardware security module and the controller. The second interface is located between the controller and the memory subsystem. The controller is configured to: receive OTP data through the first interface using a first communication protocol; and provide the OTP data to the memory subsystem through the second interface using a second communication protocol different from the first communication protocol.
[0040] In some examples, the hardware security module, processor, memory subsystem, and controller are components of a single integrated circuit. In other examples, the hardware security module, processor, and controller are components of a first integrated circuit, and the memory subsystem is a component of a second integrated circuit.
[0041] In some examples, a circuit includes a controller (e.g., Figure 1 and Figure 2 1 ), which is adapted to be coupled to a memory subsystem (e.g., Figure 1 The memory subsystem 150 or Figure 2 In these examples, the controller is configured to: receive an OTP write request; in response to the OTP write request, block the shared memory request from being provided to the memory subsystem; cause OTP data associated with the OTP write request to be provided to the memory subsystem; receive a notification that the OTP data has been written to the memory subsystem; and in response to the notification, stop blocking the shared memory request from being provided to the memory subsystem.
[0042] In some examples, the controller includes OTP control logic (e.g., in Figure 1 and Figure 2 The OTP control logic 122 in the processor is configured to: receive an OTP write request; generate a processor interrupt in response to the OTP write request; receive an acknowledgment in response to the processor interrupt; and generate a control signal in response to the acknowledgment (e.g., Figure 1 and Figure 2 In some examples, the controller includes a write I / F firewall (e.g., in Figure 1 and Figure 2 The write I / F firewall 134 in the memory is coupled to the OTP control logic. The write interface firewall is configured to: receive a control signal; and in response to the control signal, block the shared memory request from being provided to the memory subsystem.
[0043] In some examples, the control signal is a first control signal, and the OTP (one-time programmable) control logic is configured to generate a second control signal in response to the confirmation (e.g., in Figure 1 and Figure 2 The controller includes a multiplexer coupled to the OTP control logic (e.g., Figure 1 and Figure 2 In some examples, the multiplexer is coupled to a write interface firewall, and the multiplexer is configured to receive a shared memory request from the write interface firewall when the first control signal is absent.
[0044] Figure 3 is a schematic diagram 300 showing a first interface (eg, Figure 1 and 2 The first interface 170 in the embodiment of the present invention and the second interface (eg, Figure 1 and 2 Example signaling of the second interface 172 in FIG. Figure 3 , example signaling for the first interface includes CLK, OTP_HADDR, OPT_HTRANS, OTP_HWRITE, OTP_HWDATA, OTP, HSIZE, and OTP_HREADY. CLK is a clock signal for the first interface. OTP_HADDR is an OTP address provided from the HSM 102 to the controller 110. OPT_HTRANS is provided from the HSM 102 to the controller 110 to indicate that the transaction is valid. OTP_HWRITE is an OTP write request provided from the HSM 102 to the controller 110. OTP_HWDATA is OTP data related to the OTP write request provided from the HSM 102 to the controller 110. OPT_HSIZE is a size indicator indicating the amount of data in the OTP write request. OTP_HREADY is an indication from the controller 110 to the HSM 102 indicating that the controller 110 is unavailable or busy.
[0045] exist Figure 3 , example signaling for the second interface includes FLS_HADDR, FLS_WDATA, FLS_RDATA, FLS_HTRANS, and FLS_HWRITE. FLS_HADDR is the MMR address provided from the controller 110 to the write interface 156A (e.g., the flash controller 232). FLS_WDATA is the MMR write data provided from the controller 110 to the write interface 156A (e.g., the flash controller 232). FLS_RDATA is the MMR read data provided from the write interface (e.g., the flash controller 232) to the controller 110. The FLS_HTRANS indicator indicates to the controller 110 that the transaction is valid. FLS_HWRITE indicates to the controller 110 that the transaction is a read / write transaction.
[0046] At time t1, HSM 102 begins a new OTP write transaction on the first interface. At time t2, controller 110 places HSM 102 in a wait state by deasserting OTP_HREADY on the first interface. At time t3, controller 110 begins a series of MMR writes on the second interface to program the specified location in flash subsystem 150A. At time t4, controller 110 reads the status register of write interface 156A through the second interface until flash controller 232 completes the OTP write operation. At time t5, the OTP write operation is indicated as completed by FLS_RDATA on the second interface. At time t6, the OTP transaction is complete and the first interface can be used to start another transaction.
[0047] exist Figure 3 In the example of FIG. 1 , the first interface transmits an address (A0) and OTP data (D0). For example, the address and OTP data can be transmitted from the HSM 102 to the controller 110 via the first interface. The second interface transmits the OTP data, address, and byte enable information, control commands, execution triggers, and status information. In some examples, the OTP data, address, byte enable information, control commands, execution triggers, and status information are formatted for use in Figure 2 The MMR of the MMR I / F 226 in the first interface. In different examples, the number of clock cycles and / or the clock frequency for signaling on the first interface and the second interface may be different.
[0048] Figure 4 is a flow chart showing an example OTP control method 400. The OTP control method 400 may be Figure 1 and Figure 2 As shown in the figure, the OTP control method 400 includes: in block 402, through a first interface (eg Figure 1 and Figure 2 In block 404, the first interface is placed in a waiting state. In block 406, a CPU (e.g., Figure 1 and 2 The processor 106 in the example generates an interrupt requesting a second interface (eg Figure 1 and Figure 2 In block 408, an acknowledgment is received indicating that the CPU has finished using the second interface. In block 410, control of the second interface is acquired, preventing the CPU from using it. In block 412, OTP data is cached. In block 414, the OTP region of the shared memory (e.g., Figure 1 and Figure 2 In block 416, the memory controller (e.g., Figure 2 The flash controller 232 in the shared memory writes the data to the OTP area of the shared memory and waits for completion confirmation. In block 418, write protection is enabled for the OTP area of the shared memory. In some examples, use Figure 2 In block 420, the write interface storage (e.g., the register of MMR I / F 226 or other storage options) is cleared. In block 422, an interrupt to the CPU is generated to indicate that the shared memory is available. After block 422 is completed, the second interface can be used for shared memory operations.
[0049] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action: (a) in the first example, device A is coupled to device B through a direct connection; or (b) in the second example, if the intervening component C does not change the functional relationship between device A and device B, device A is coupled to device B through an intervening component C, so that device A controls device B through the control signal generated by device A.
[0050] Additionally, in this description, the term “based on” means “based at least in part on.” Thus, if X is based on Y, then X may be a function of Y as well as several other factors.
[0051] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform that function, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and other additional or alternative functions. Such configuration may be achieved through firmware and / or software programming of the device, the construction and layout of hardware components and interconnections of the device, or a combination of both.
[0052] In this document, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless otherwise expressly stated, these terms are generally used to refer to connections or terminations between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components.
[0053] Circuits or devices described herein that include certain components may also be implemented by coupling these components to the circuit or device. For example, a structure that includes one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may also include only semiconductor elements in one physical device (e.g., a semiconductor chip and / or an integrated circuit (IC) package), and may be adapted to be coupled with at least some of the passive elements and / or sources to form the structure, for example, by an end user and / or a third party after manufacturing.
[0054] The circuits described herein may be reconfigured to include additional or different components to provide similar functionality to that provided prior to component replacement, at least in part. Unless otherwise noted, resistors shown in the figures generally represent one or more elements connected in series or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors connected in parallel between the same nodes, or connected in series between the same two nodes as a single resistor or capacitor.
[0055] Although examples are described in which some elements are included in an integrated circuit and other elements are located outside the integrated circuit, in other cases, more or fewer features may be incorporated into the integrated circuit. In addition, some or all features described as external to the integrated circuit may be incorporated into the integrated circuit, and some features described as internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are: (i) integrated in / on a semiconductor substrate; (ii) integrated into a single semiconductor package; (iii) integrated into the same module; and / or (iv) integrated in / on the same printed wiring board.
[0056] In the above description, the use of the term "ground" includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and any other form of ground connection that is applicable or suitable for the teachings of this description. In this description, unless otherwise stated, "approximately", "approximately" or "substantially" preceding a parameter means that the parameter is within a range of + / -10%, or if the parameter is zero, within a reasonable range around zero.
[0057] Modifications may be made in the above examples and other examples may exist within the scope of the claims.
Claims
1. A device comprising: Hardware security module; processor; A memory subsystem, comprising a write interface and a memory, wherein the write interface comprises a storage device, the memory comprises a first area and a second area, the first area is a one-time programmable area (OTP area), and the second area is a shared area; A controller located between the hardware security module, the processor, and the memory subsystem, wherein the controller is configured to: Receiving an OTP write request from the hardware security module; In response to the OTP write request and an acknowledgement from the processor, preventing the processor from providing a shared memory request; Allowing OTP data associated with the OTP write request instruction to be written into the first area of the memory; clearing the storage device of the write interface after completing the writing of the OTP data; and Blocking the provide shared memory request ceases after clearing the storage device of the write interface.
2. The device according to claim 1, wherein: The controller includes a write interface firewall located between the processor and the memory subsystem, the write interface firewall configured to block shared memory requests provided by the processor to the write interface during an OTP cycle.
3. The device according to claim 2, wherein: The controller has a terminal, an OTP control logic, and a multiplexer, the terminal being coupled to the memory subsystem, the multiplexer being configured to selectively forward data from the OTP control logic or the write interface firewall to the terminal. 4 . The apparatus of claim 1 , further comprising a read firewall located between the processor and the memory subsystem, the read firewall configured to prevent the processor from reading the first region of the memory.
5. The device according to claim 1, wherein: The hardware security module is configured to initiate the OTP write request in response to a request from the processor.
6. The device according to claim 1, wherein: The OTP data includes an encryption certificate or a key.
7. The device according to claim 1, wherein: The OTP data includes a monotonic count.
8. The apparatus according to claim 1, further comprising: a first interface between the hardware security module and the controller; a second interface between the controller and the memory subsystem, wherein the controller is configured to: Receiving the OTP data through the first interface using a first communication protocol; as well as The OTP data is provided to the memory subsystem through the second interface using a second communication protocol different from the first communication protocol.
9. The device according to claim 1, wherein: The hardware security module, the processor, the memory subsystem, and the controller are components on a single integrated circuit.
10. The device according to claim 1, wherein: The hardware security module, the processor, and the controller are components of a first integrated circuit, and the memory subsystem is a component of a second integrated circuit.
11. A circuit comprising: A controller adapted to be coupled to the memory subsystem, the controller being configured to: Receive one-time programmable (OTP) write request; In response to the OTP write request, preventing a shared memory request from being provided to the memory subsystem; causing OTP data associated with the OTP write request to be provided to the memory subsystem; receiving a notification that the OTP data has been written to the memory subsystem; as well as In response to the notification, blocking of providing the shared memory request to the memory subsystem is stopped.
12. The circuit according to claim 11, wherein The controller includes OTP control logic, which is configured to: Receiving the OTP write request; generating a processor interrupt in response to the OTP write request; receiving an acknowledgement in response to the processor interrupt; as well as In response to the confirmation, a control signal is generated.
13. The circuit of claim 12, wherein: The controller includes a write interface firewall coupled to the OTP control logic, the write interface firewall being configured to: receiving the control signal; and In response to the control signal, the providing of the shared memory request to the memory subsystem is blocked.
14. The circuit according to claim 13, wherein: The control signal is a first control signal, the OTP control logic is configured to generate a second control signal in response to the confirmation, the controller includes a multiplexer coupled to the OTP control logic, the multiplexer is configured to: receiving the second control signal; and In response to the second control signal, data is forwarded from the OTP control logic.
15. The circuit of claim 14, wherein: The multiplexer is coupled to the write interface firewall, the multiplexer being configured to receive a shared memory request from the write interface firewall in the absence of the first control signal.
16. A method comprising: receiving a one-time programmable (OTP) write request via the first interface; In response to the OTP write request and an acknowledgement from the processor, preventing the processor from providing the shared memory operation; allowing OTP data associated with the OTP write request to be written into a first area of a memory via a second interface separate from the first interface; Clear the storage of the write interface after completing the OTP data writing; as well as The blocking of providing the shared memory operation is stopped after clearing the storage of the write interface.
17. The method according to claim 16, further comprising: placing the first interface in a waiting state to respond to the OTP write request; and Acquire control of the second interface.
18. The method according to claim 17, wherein: Acquiring control over the second interface includes: generating a processor interrupt; and An acknowledgement is received from the processor.
19. The method according to claim 16, further comprising: disabling write protection of the first region of the memory; After the write protection is disabled, causing the OTP data associated with the OTP write request to be written into the first area; as well as After completing writing the OTP data into the first area, write protection is enabled for the first area.
20. The method according to claim 16, wherein: Ceasing to prevent providing the shared memory operation after clearing the store to the write interface includes generating a processor interrupt to indicate that a shared memory operation is available.