A RAM multiplexing method for SOC

Abstract

This invention discloses a RAM reuse method for a System-on-a-Chip (SoC). In this invention, IDRAM, which is defaulted to DRAM, is reused as IRAM to meet usage requirements. This design can minimize chip area while improving CPU processing speed, and the reduction in area and firmware overhead also saves costs. The actual area of ​​IRAM, DRAM, and IDRAM can be evaluated based on actual needs; the larger the IDRAM, the more area can be saved. This design, through analysis of the actual application requirements of different CPU buses, cleverly designs an IDRAM time-sharing multiplexing scheme, significantly reducing the area of ​​RAM that does not need to be used simultaneously, achieving reduced power consumption and cost savings, while providing better firmware flexibility and more sufficient hardware resources for some special application scenarios.

Description

Technical Field

[0001] This invention belongs to the field of SOC chip technology, specifically a RAM reuse method for SOC. Background Technology

[0002] In today's era of rapid information technology development, consumer electronics products are emerging in endless streams, driving technological progress and providing consumers with diverse choices. As a system-on-a-chip (SoC), the SOC chip, with its built-in CPU, can meet the needs of various applications in different scenarios.

[0003] However, traditional SOC chips are difficult to apply in mobile phones, tablets, and wearable devices due to their large size. While existing RAM structures offer time-sharing multiplexing of IDRAM in boot mode and normal operating mode, they cannot further reduce RAM overhead. In normal operating mode, they only handle the maximum usage of IRAM and DRAM, without considering actual application scenarios. In practice, both are often not needed simultaneously. Furthermore, current technologies allocate all DRAM space for algorithm calculations, meaning printing can only be done to IRAM. The DRAM usage can be flexibly adjusted through firmware algorithms, not necessarily requiring full DRAM utilization. In this situation, existing technologies result in a certain degree of resource waste.

[0004] To address the aforementioned problems, this invention provides a RAM reuse method for System-on-a-Chip (SoC), reducing the total area of ​​RAM used and thus decreasing the area of ​​the SoC chip. This invention is applied to SoC chips, but is not limited to SoC chips. Summary of the Invention

[0005] The purpose of this invention is to provide a RAM reuse method for a System-on-a-Chip (SoC) in order to solve the problems mentioned above.

[0006] The technical solution adopted in this invention is as follows: a RAM reuse method for a System-on-a-Chip (SoC), the method comprising the following steps:

[0007] S1: Determine the RAM requirements of the SOC chip, including the size of IRAM and DRAM and the use case;

[0008] S2: Design a flexible and reusable IDRAM, the size of which is evaluated based on the requirements of IRAM and DRAM;

[0009] S3: Reserve address space in the operating system so that it can be accessed normally when used as IRAM and DRAM;

[0010] S4: Add an IDRAM_sel register to the operating system to select the function of IDRAM;

[0011] S5: By default, IDRAM is used as DRAM to store the data required by the system;

[0012] S6: Depending on the actual application scenario, the CPU writes a value to the IDRAM_sel register to change the function of IDRAM;

[0013] S7: When IDRAM is used as IRAM, the internal hardware logic redirects the data and communicates with the instruction bus;

[0014] S8: When IDRAM is used as DRAM, the internal hardware logic redirects the data and communicates with the data bus;

[0015] S9: By using time-division multiplexing of IDRAM, it saves hardware overhead, reduces power consumption and cost, and improves the flexibility of firmware operation.

[0016] In a preferred embodiment, in step S1, a flexible and reusable IDRAM is used to expand the capacity of IRAM and DRAM in a time-sharing manner to save hardware overhead. In actual use, because the firmware optimizes the code to a certain extent, IRAM will not frequently exceed its capacity. Therefore, IDRAM will be used as an expansion module for DRAM by default. This is achieved by reserving address space separately (e.g., ... Figure 1 This allows IDRAM to be accessed normally for expansion in both usage scenarios. In some special applications, such as debug mode, a larger IRAM space is required to meet the operational needs of the firmware.

[0017] In a preferred embodiment, in step S2, the size of the IDRAM should be evaluated based on actual needs, and its area should be minimized while ensuring functionality. To achieve time-division multiplexing of the IDRAM, address space needs to be reserved in the IDRAM so that it can be accessed normally when used as both IRAM and DRAM. There are various ways to reserve address space, such as dividing the IDRAM address space into multiple segments, each of which can be mapped to the address space of either IRAM or DRAM.

[0018] In a preferred embodiment, in step S4, a new 1-bit IDRAM_sel register (readable and writable, configurable via the CPU or debug path, etc.) is added to select the actual function of the IDRAM. After system power-on, in the default state without configuring the IDRAM_sel register, the IDRAM is used as DRAM to store data needed by the system. However, the function of the IDRAM can be flexibly changed according to changes in the actual usage scenario. If it is necessary to change the function of the IDRAM, the CPU needs to write a value to the IDRAM_sel register to change the corresponding address space and usage state. After successful writing, the internal hardware logic will combine the IDRAM_sel register with the bus access address to reallocate the data, communicate with the instruction bus or data bus, and complete the conversion between different address spaces of the IRAM, such as... Figure 4 As shown.

[0019] In a preferred embodiment, in step S5, IDRAM is time-multiplexed when the IDRAM_sel register is "0" or "1". Through this design, RAM overhead can be reduced by adding only a small amount of hardware logic and address space, taking into account the actual usage conditions of the SOC chip. This resource exchange not only saves area but also improves the flexibility of firmware operation, providing flexible and variable RAM resources for different application scenarios.

[0020] In a preferred embodiment, reserving address space in the operating system during step S3 is crucial for achieving RAM time-sharing multiplexing. There are various ways to reserve address space, such as dividing the IDRAM address space into multiple segments, each of which can be mapped to either the IRAM or DRAM address space. The advantage of this approach is that the sizes of IRAM and DRAM can be flexibly adjusted to meet the needs of different application scenarios. For example, if an application requires more IRAM space, more address space from IDRAM can be mapped to the IRAM address space.

[0021] In a preferred embodiment, in step S6, the CPU writes a value to the IDRAM_sel register to change the function of the IDRAM. For example, if an application needs more IRAM space, the value of the IDRAM_sel register can be set to "1", using the IDRAM as IRAM. This flexible way of changing the IDRAM function can meet the RAM requirements of different application scenarios.

[0022] In a preferred embodiment, in step S7, when the CPU reads an instruction from the IDRAM, it maps the instruction's address to the address space of the IRAM. This method allows for the expansion of the IRAM from the IDRAM, thereby meeting the application's requirement for instruction storage space.

[0023] In a preferred embodiment, in step S8, when the CPU accesses data in the IDRAM, it maps its address to the address space of the DRAM. This method enables the IDRAM to expand the capacity of the DRAM, thereby meeting the application's data storage space requirements.

[0024] In a preferred embodiment, in step S9, IDRAM can be flexibly allocated to IRAM or DRAM according to the needs of the actual application scenario, thereby avoiding the waste of RAM resources. For example, if an application requires more IRAM space, IDRAM can be used as IRAM, thereby avoiding the need to add additional IRAM chips and saving chip area and cost. At the same time, time-division multiplexing of IDRAM can also improve the flexibility of firmware operation; for example, the function of IDRAM can be easily switched to meet different application scenarios.

[0025] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0026] In this invention, IDRAM, which is defaulted to DRAM, can be reused as IRAM to meet usage requirements. This design minimizes chip area while improving CPU processing speed, and the reduction in area and firmware overhead also saves costs. The actual area of ​​IRAM, DRAM, and IDRAM can be evaluated based on actual needs; the larger the IDRAM, the more area can be saved. This design, through analysis of the actual application requirements of different CPU buses, cleverly designs an IDRAM time-sharing multiplexing scheme, significantly reducing the area of ​​RAM that does not need to be used simultaneously, achieving reduced power consumption and cost savings, while providing better firmware flexibility and more sufficient hardware resources for some special application scenarios. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the IDRAM of the present invention, which is reused as IRAM and DRAM respectively;

[0028] Figure 2 This refers to the RAM processing method of a traditional SOC chip in normal operating mode;

[0029] Figure 3 This is a RAM time-sharing multiplexing method similar to that used in existing SOC chips and this design;

[0030] Figure 4 This is a schematic diagram of the time-division multiplexing gating of the IDRAM in the SOC chip of this invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0032] Reference Figure 1-4 ,

[0033] A method for RAM reuse in a System-on-a-Chip (SoC) includes the following steps:

[0034] S1: Determine the RAM requirements of the SOC chip, including the size of IRAM and DRAM and the use case;

[0035] S2: Design a flexible and reusable IDRAM, the size of which is evaluated based on the requirements of IRAM and DRAM;

[0036] S3: Reserve address space in the operating system so that it can be accessed normally when used as IRAM and DRAM;

[0037] S4: Add an IDRAM_sel register to the operating system to select the function of IDRAM;

[0038] S5: By default, IDRAM is used as DRAM to store the data required by the system;

[0039] S6: Depending on the actual application scenario, the CPU writes a value to the IDRAM_sel register to change the function of IDRAM;

[0040] S7: When IDRAM is used as IRAM, the internal hardware logic redirects the data and communicates with the instruction bus;

[0041] S8: When IDRAM is used as DRAM, the internal hardware logic redirects the data and communicates with the data bus;

[0042] S9: By using time-division multiplexing of IDRAM, it saves hardware overhead, reduces power consumption and cost, and improves the flexibility of firmware operation.

[0043] In step S1, a flexible and reusable IDRAM is used to expand the capacity of IRAM and DRAM in a time-sharing manner to save hardware overhead. In actual use, because the firmware optimizes the code to a certain extent, IRAM will not frequently exceed its capacity. Therefore, IDRAM will be used as an expansion module for DRAM by default. This is achieved by reserving address space separately (e.g., Figure 1 This allows IDRAM to be accessed normally for expansion in both usage scenarios. In some special applications, such as debug mode, a larger IRAM space is required to meet the operational needs of the firmware.

[0044] In step S2, the size of the IDRAM should be evaluated based on actual needs, and its area should be minimized while ensuring functionality. To achieve time-division multiplexing of the IDRAM, address space needs to be reserved in the operating system so that it can be accessed normally when used as both IRAM and DRAM. There are several ways to reserve address space, such as dividing the IDRAM address space into multiple segments, each of which can be mapped to the address space of either IRAM or DRAM.

[0045] In step S4, a new 1-bit IDRAM_sel register (readable and writable, configurable via the CPU or debug path, etc.) is added to select the actual function of the IDRAM. After system power-on, in the default state without configuring the IDRAM_sel register, the IDRAM is used as DRAM to store data needed by the system. However, the function of the IDRAM can be flexibly changed according to changes in the actual usage scenario. If it is necessary to change the function of the IDRAM, the CPU needs to write a value to the IDRAM_sel register to change the corresponding address space and usage status. After successful writing, the internal hardware logic will combine the IDRAM_sel register with the bus access address to reallocate the data, communicate with the instruction bus or data bus, and complete the conversion between different address spaces of the IRAM, such as... Figure 4 As shown.

[0046] In step S5, IDRAM is time-multiplexed when the IDRAM_sel register is "0" or "1". Through this design, RAM overhead can be reduced by adding only a small amount of hardware logic and address space, taking into account the actual usage conditions of the SOC chip. This resource swap not only saves area but also improves the flexibility of firmware operation, providing flexible and variable RAM resources for different application scenarios.

[0047] In step S3, reserving address space in the IDRAM is crucial for implementing RAM time-sharing multiplexing. There are several ways to reserve address space, such as dividing the IDRAM address space into multiple segments, each of which can be mapped to either the IRAM or DRAM address space. The advantage of this approach is the flexibility to adjust the sizes of the IRAM and DRAM to meet the needs of different application scenarios. For example, if an application requires more IRAM space, more address space in the IDRAM can be mapped to the IRAM address space.

[0048] In step S6, the CPU writes a value to the IDRAM_sel register to change the function of the IDRAM. For example, if an application needs more IRAM space, the value of the IDRAM_sel register can be set to "1" to use the IDRAM as IRAM. This flexible way of changing the IDRAM function can meet the RAM needs of different application scenarios.

[0049] In step S7, when the CPU reads instructions from IDRAM, it maps the instruction address to the address space of IRAM. This method allows IDRAM to expand the capacity of IRAM, thereby meeting the application's requirement for instruction storage space.

[0050] In step S8, when the CPU accesses data in the IDRAM, it maps its address to the address space of the DRAM. This method allows the IDRAM to expand the capacity of the DRAM, thereby meeting the application's data storage space requirements.

[0051] In step S9, IDRAM can be flexibly allocated to IRAM or DRAM according to the needs of the actual application scenario, thereby avoiding the waste of RAM resources. For example, if an application requires more IRAM space, IDRAM can be used as IRAM, thus avoiding the need for additional IRAM chips and saving chip area and cost. At the same time, the time-sharing multiplexing of IDRAM can also improve the flexibility of firmware operation. For example, the function of IDRAM can be easily switched to meet different application scenarios.

[0052] In this invention, IDRAM, which is defaulted to DRAM, can be reused as IRAM to meet usage requirements. This design minimizes chip area while improving CPU processing speed, and the reduction in area and firmware overhead also saves costs. The actual area of ​​IRAM, DRAM, and IDRAM can be evaluated based on actual needs; the larger the IDRAM, the more area can be saved. This design, through analysis of the actual application requirements of different CPU buses, cleverly designs an IDRAM time-sharing multiplexing scheme, significantly reducing the area of ​​RAM that does not need to be used simultaneously, achieving reduced power consumption and cost savings, while providing better firmware flexibility and more sufficient hardware resources for some special application scenarios.

[0053] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A RAM reuse method for a System-on-a-Chip (SoC), characterized in that: The method includes the following steps: S1: Determine the RAM requirements of the SOC chip, including the size of IRAM and DRAM and the use case; S2: Design a flexible and reusable IDRAM, the size of which is evaluated based on the requirements of IRAM and DRAM; S3: Reserve address space in IDRAM so that it can be accessed normally when used as both IRAM and DRAM; S4: Add an IDRAM_sel register to the CPU to select the function of IDRAM; S5: By default, IDRAM is used as DRAM to store the data required by the system; S6: Depending on the actual application scenario, the CPU writes a value to the IDRAM_sel register to change the function of IDRAM; S7: When IDRAM is used as IRAM, the internal hardware logic redirects the data and communicates with the instruction bus; S8: When IDRAM is used as DRAM, the internal hardware logic redirects the data and communicates with the data bus; S9: By using time-sharing multiplexing of IDRAM, hardware overhead is saved, power consumption and cost are reduced, and the flexibility of firmware operation is improved. In step S2, the size of the IDRAM should be evaluated according to actual needs, and its area should be minimized as much as possible while ensuring functionality. In order to realize time-division multiplexing of the IDRAM, address space needs to be reserved in the IDRAM so that it can be accessed normally when used as IRAM and DRAM. There are multiple ways to reserve address space, such as dividing the address space of the IDRAM into multiple segments, and each segment is mapped to the address space of IRAM or DRAM respectively. In step S4, a new 1-bit IDRAM_sel register is added to select the actual function of the IDRAM. After the system powers on, in the default case where the IDRAM_sel register is not configured, the IDRAM is used as DRAM to store the data required by the system. However, the function of the IDRAM will be flexibly changed according to the actual usage scenario. If it is necessary to change the function of the IDRAM, the CPU needs to write a value to the IDRAM_sel register to change the corresponding address space and usage status. After the write is correct, the internal hardware logic will combine the IDRAM_sel register and the access address of the bus to redistribute the data and communicate with the instruction bus or data bus to complete the conversion of different address spaces of the IRAM. In step S3, reserving address space in IDRAM is the key to realizing RAM time-sharing multiplexing; there are multiple ways to reserve address space, such as dividing the address space of IDRAM into multiple segments, each segment being mapped to the address space of IRAM or DRAM respectively; In step S6, the CPU writes a value to the IDRAM_sel register to change the function of IDRAM; if an application needs more IRAM space, the value of the IDRAM_sel register is set to "1" and IDRAM is used as IRAM; this is a flexible way to change the function of IDRAM.

2. The RAM reuse method for a System-on-a-Chip (SoC) as described in claim 1, characterized in that: In step S1, a flexible and reusable IDRAM is used to expand the capacity of IRAM and DRAM in a time-sharing manner to save hardware overhead; IDRAM will be used as DRAM expansion by default; by reserving address space separately, IDRAM can be accessed normally as expansion in both usage scenarios.

3. The RAM reuse method for a System-on-a-Chip (SoC) as described in claim 1, characterized in that: In step S5, time-division multiplexing is performed on IDRAM when the IDRAM_sel register is "0" or "1".

4. The RAM reuse method for a System-on-a-Chip (SoC) as described in claim 1, characterized in that: In step S7, when the CPU reads instructions from IDRAM, it maps the address to the address space of IRAM.

5. The RAM reuse method for a System-on-a-Chip (SoC) as described in claim 1, characterized in that: In step S8, when the CPU accesses data in IDRAM, it maps its address to the address space of DRAM.

6. The RAM reuse method for a System-on-a-Chip (SoC) as described in claim 1, characterized in that: In step S9, IDRAM is flexibly allocated to IRAM or DRAM according to the needs of the actual application scenario.

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