Design rule checking tool verification method, apparatus, device, medium, and product

Abstract

The application discloses a design rule checking tool verification method, device, equipment, medium and product, and relates to the technical field of chip layout checking. The design rule checking tool verification method comprises the following steps: constructing a test layout level corresponding to a tool attribute of a chip layout design rule checking tool according to the tool attribute, wherein the tool attribute is used for representing the features of the chip layout level that can be processed by the chip layout design rule checking tool; creating a plurality of test cases corresponding to each layout design parameter at the test layout level according to each layout design parameter included in a layout design rule corresponding to a chip layout, wherein the layout design rule is used for representing a mandatory provision set of the design content of the chip layout; and determining the tool reliability of the chip layout design rule checking tool by executing each test case by the chip layout design rule checking tool.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip layout inspection, and particularly relates to a verification method and device of a design rule check tool, equipment, medium and product. BACKGROUND

[0002] Before batch manufacturing, an integrated circuit chip needs to use a layout inspection tool to perform design rule check (DRC) on the chip layout, and only the chip layout that passes the design rule check can ensure the success of the chip flow. In order to ensure the accuracy of the chip layout inspection result, the reliability of the layout inspection tool needs to be verified in advance.

[0003] In the prior art, test cases are manually inputted, and the reliability of the layout inspection tool is verified according to the test cases.

[0004] However, the types of the manually inputted test cases are relatively single, and the test types are incomplete and the test coverage is low, which results in poor verification reliability of the layout inspection tool. SUMMARY

[0005] The embodiments of the application provide a verification method, device, equipment, medium and product of a design rule check tool, which can improve the verification reliability of the design rule check tool.

[0006] In an aspect of the embodiments of the application, a verification method of a design rule check tool is provided, which includes the following steps.

[0007] According to tool attributes of the chip layout design rule check tool, a test layout hierarchy corresponding to the tool attributes is constructed, and the tool attributes are used to represent features of a chip layout hierarchy that can be processed by the chip layout design rule check tool;

[0008] According to each layout design parameter included in a layout design rule corresponding to the chip layout, a plurality of test cases corresponding to each layout design parameter at the test layout hierarchy are created, and the layout design rule is used to represent a set of mandatory provisions for the design content of the chip layout;

[0009] The tool reliability of the chip layout design rule check tool is determined by executing each test case by the chip layout design rule check tool.

[0010] In an aspect of the embodiments of the application, a verification device of a design rule check tool is provided, which includes the following steps.

[0011] The hierarchy construction module is configured to construct a test layout hierarchy corresponding to tool attributes of the chip layout design rule check tool according to the tool attributes, and the tool attributes are used to represent features of a chip layout hierarchy that can be processed by the chip layout design rule check tool;

[0012] a use case creation module, configured to create a plurality of test use cases corresponding to each layout design parameter in the test layout level according to each layout design parameter included in the layout design rule corresponding to the chip layout, the layout design rule being used to represent a set of mandatory provisions for the design content of the chip layout;

[0013] a use case execution module, configured to execute each test use case by the chip layout design rule checking tool respectively, and determine the tool reliability of the chip layout design rule checking tool.

[0014] In an aspect of the embodiments of the present application, an electronic device is provided, which includes a memory and a program or instructions stored in the memory and executable on a processor, and the program or instructions are executed by the processor to implement the verification method of the design rule checking tool provided in any one of the aspects of the embodiments of the present application.

[0015] In an aspect of the embodiments of the present application, a readable storage medium is provided, and the program or instructions are stored in the readable storage medium and executable by a processor, and the program or instructions are executed by the processor to implement the verification method of the design rule checking tool provided in any one of the aspects of the embodiments of the present application.

[0016] In an aspect of the embodiments of the present application, a computer program product is provided, and the instructions in the computer program product are executed by a processor of an electronic device to enable the electronic device to perform the verification method of the design rule checking tool provided in any one of the aspects of the embodiments of the present application.

[0017] In the verification method of the design rule checking tool provided in the embodiments of the present application, the test layout level corresponding to the tool attribute of the chip layout design rule checking tool is first constructed according to the tool attribute, so that each chip layout level applicable to the layout checking tool can be verified subsequently. Meanwhile, a plurality of test use cases corresponding to each layout design parameter in the test layout level are created according to each layout design parameter included in the layout design rule corresponding to the chip layout. Starting from the layout design rule of the chip layout, the corresponding test use cases are created for each layout design parameter involved in the layout design rule, so that each layout design parameter involved in the layout design rule is comprehensively verified. In this way, the embodiments of the present application comprehensively verify each chip layout level applicable to the layout checking tool and each layout design parameter involved in the layout design rule. The function and performance of the layout checking tool are verified in the hierarchy of various features, so that the problem of incomplete test type and low test coverage is avoided, thereby improving the verification reliability of the layout checking tool. BRIEF DESCRIPTION OF DRAWINGS

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the verification method of the first design rule checking tool provided in one embodiment of this application;

[0020] Figure 2 This is a flowchart illustrating the verification method of the second design rule checking tool provided in one embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the structure of a verification device for a design rule checking tool provided in one embodiment of this application;

[0022] Figure 4 This is a schematic diagram of the structure of a verification device for a design rule checking tool provided in one embodiment of this application. Detailed Implementation

[0023] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0024] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0025] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations.

[0026] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0027] Existing methods rely on manually inputting test cases to verify the reliability of layout inspection tools. However, manually input test cases are relatively limited in type, easily leading to incomplete test types and low test coverage, resulting in poor verification reliability of layout inspection tools.

[0028] The purpose of this application is to provide a verification method, apparatus, device, medium, and product for a design rule checking tool. The verification method for the design rule checking tool provided in this application first constructs a test layout hierarchy corresponding to the tool attributes of the chip layout design rule checking tool, enabling subsequent verification of each chip layout hierarchy to which the layout checking tool is applicable. Simultaneously, based on the layout design parameters included in the layout design rules corresponding to the chip layout, multiple test cases are created for each layout design parameter at the test layout hierarchy. Starting from the layout design rules of the chip layout, corresponding test cases are created for each layout design parameter involved in the layout design rules, enabling comprehensive verification of each layout design parameter involved in the layout design rules. Thus, this application comprehensively verifies each chip layout hierarchy to which the layout checking tool is applicable, as well as each layout design parameter involved in the layout design rules. This allows for verification of the functionality and performance of the layout checking tool under various feature hierarchical structures, avoiding problems such as incomplete test types and low test coverage, thereby improving the verification reliability of the layout checking tool.

[0029] The following describes specific embodiments of the verification method, apparatus, equipment, medium, and product of the design rule checking tool provided in this application. The verification method of the design rule checking tool will be described first.

[0030] Figure 1 A flowchart illustrating a verification method for a design rule checking tool is provided. This verification method can be applied to the server side and may include the following steps S101 to S103.

[0031] S101, Based on the tool attributes of the chip layout design rule checking tool, construct a test layout hierarchy corresponding to the tool attributes. The tool attributes are used to characterize the chip layout hierarchy that the chip layout design rule checking tool can handle.

[0032] In this embodiment, the tool attributes are used to reflect the chip layout hierarchy that the DRC tool can handle. For example, the chip layout hierarchy may include orthogonally rotated chip cells and non-orthogonally rotated chip cells, chip cells mirrored along the x-axis and chip cells mirrored along the y-axis, and chip cells with a scaling factor greater than 1 and chip cells with a scaling factor less than 1.

[0033] The test layout level is used to characterize the chip layout levels set for verification by the DRC tool. For example, the test layout level can be all chip layout levels that the DRC tool can handle, or it can be a subset of chip layout levels that the DRC tool can handle.

[0034] As an example, the technical documentation and user manual of the server-side analysis DRC tool list all the layout levels it supports, such as the maximum / minimum supported sizes, spacing rules, alignment requirements, etc.

[0035] Then, based on the above information, a series of test layout hierarchies are constructed in the electronic design automation (EDA) software. Each test layout hierarchy should be specifically designed to highlight the performance of the DRC tool on a particular attribute. For example, one hierarchy might focus on testing minimum spacing rules, while another focuses on testing alignment requirements.

[0036] S102, based on the layout design parameters included in the layout design rules corresponding to the chip layout, create multiple test cases corresponding to each layout design parameter at the test layout level. The layout design rules are used to characterize the set of mandatory provisions for the design content of the chip layout.

[0037] In this embodiment, layout design rules are a set of mandatory regulations governing the design content of the chip layout. For example, layout design rules may include metal linewidth, spacing, via size, power grid requirements, etc.

[0038] As an example, the server designs multiple test cases within the constructed test layout hierarchy for each layout design parameter (such as line width and spacing) included in the layout design rules. For instance, for line width rules, multiple test cases with metal lines of different widths can be created; for spacing rules, metal line pairs with different spacings can be designed.

[0039] Meanwhile, the server marks the expected DRC result for each test case, i.e., whether the test case should trigger a DRC error.

[0040] S103, execute each test case using the chip layout design rule checking tool to determine the tool's reliability.

[0041] In this embodiment, the server uses a DRC tool to perform rule checks on each test case and records the DRC results for each test case.

[0042] Then, compare the output of the DRC tool with the expected DRC results to check whether the DRC tool correctly identified all violations and did not falsely report compliance issues.

[0043] Based on the comparison results, the accuracy (number of correctly identified violations / total number of violations) and false positive rate (number of falsely reported compliance cases / total number of compliance cases) of the DRC tool are calculated. If the accuracy is high and the false positive rate is low, the DRC tool is considered to have high reliability.

[0044] The verification method for the design rule checking tool provided in this embodiment first constructs a test layout hierarchy corresponding to the tool attributes based on the tool attributes of the chip layout design rule checking tool, so that each chip layout hierarchy to which the layout checking tool is applicable can be verified separately. Simultaneously, based on the layout design parameters included in the layout design rules corresponding to the chip layout, multiple test cases are created for each layout design parameter under the test layout hierarchy. Starting from the layout design rules of the chip layout, corresponding test cases are created for each layout design parameter involved in the layout design rules, enabling comprehensive verification of each layout design parameter involved in the layout design rules. Thus, this embodiment comprehensively verifies each chip layout hierarchy to which the layout checking tool is applicable, as well as each layout design parameter involved in the layout design rules. This allows for verification of the functionality and performance of the layout checking tool under various feature hierarchical structures, avoiding problems such as incomplete test types and low test coverage, thereby improving the verification reliability of the layout checking tool.

[0045] As an optional implementation, multiple test cases can be real test cases or extended test cases;

[0046] Real-world use cases are used to characterize the use cases that are actually obtained at the actual design stage of the chip layout;

[0047] Extended use cases are used to characterize use cases generated by extending the layout design parameters included in the layout design rules.

[0048] In this embodiment, the server obtains actual design data from the actual chip layout design. This data includes, but is not limited to, the location, size, and connection relationships of various layout elements (such as transistors, resistors, capacitors, etc.). This actual design data is then organized into real-world use cases for subsequent verification.

[0049] Simultaneously, based on the layout design parameters (such as minimum linewidth, minimum spacing, maximum density, etc.) included in the layout design rules, a series of extended test cases are generated through algorithms. These extended test cases cover possible design boundary conditions and abnormal situations, and are used to test the performance of the layout design under these extreme conditions.

[0050] This embodiment enriches the number and types of test cases based on real-world and extended use cases. This expands the test types available to the DRC tool, improves its test coverage, and ultimately enhances the verification reliability of the layout inspection tool.

[0051] As an optional implementation, multiple test cases are extended test cases;

[0052] S102 may specifically include:

[0053] Repeat the following steps until all layout design parameters included in the layout design rules have been traversed:

[0054] Obtain the range of parameter values ​​corresponding to the target layout design parameters, where the target layout design parameter is any one of the layout design parameters;

[0055] The parameter values ​​of the target layout design parameters are sequentially set to multiple valid values ​​within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values. This constitutes multiple extended test cases corresponding to the target layout design parameters at the test layout level. The reference layout design parameters are the layout design parameters other than the target layout design parameters among the layout design parameters corresponding to the layout design rules.

[0056] In this embodiment, the parameter value range covers all valid values ​​that can be obtained for the layout design parameters in actual design.

[0057] Specifically, the server executes the following steps for each target layout design parameter included in the layout design rules:

[0058] First, obtain the parameter value range corresponding to the target layout design parameters. Then, within this parameter value range, sequentially set the target layout design parameters to multiple valid values. This can be achieved programmatically, for example, by using a loop to iterate through all values ​​within the parameter value range.

[0059] Simultaneously, the parameter values ​​of all reference layout design parameters (excluding the target layout design parameters) corresponding to each layout design rule are set to preset default values. These default values ​​should be based on actual design experience or standard settings to ensure the accuracy and effectiveness of the test.

[0060] Based on the above settings, multiple extended test cases are constructed corresponding to the target layout design parameters at the test layout level. Each extended test case contains specific target layout design parameter values ​​and preset reference layout design parameter values.

[0061] For example, suppose the layout design rules include two layout design parameters: parameter A and parameter B. The value range of parameter A is 1 to 10, and the value range of parameter B is 5 to 20. The default values ​​are parameter A = 5 and parameter B = 10.

[0062] During the loop iteration, parameter A is tested first. The value of parameter A is set to each valid value between 1 and 10, while the value of parameter B is kept at the default value of 10. In this way, 10 extended test cases for parameter A are generated.

[0063] Next, test parameter B. Set the value of parameter B to each valid value between 5 and 20, while keeping the value of parameter A at the default value of 5. This will generate 16 extended test cases for parameter B.

[0064] This embodiment creates multiple extended test cases for each layout design parameter included in the layout design rules, based on the corresponding parameter value range. This allows for a comprehensive evaluation of the DRC tool's verification accuracy for each layout design parameter in the layout design rules, improving the verification reliability of the layout inspection tool.

[0065] As an optional embodiment, the multiple extended test cases include forward extended test cases and reverse extended test cases. Forward test cases are used to characterize extended test cases consisting of valid values ​​that satisfy the layout design rules, and reverse test cases are used to characterize extended test cases consisting of invalid values ​​that do not satisfy the layout design rules.

[0066] After obtaining the parameter value range corresponding to the target layout design parameters, the verification method of this design rule checking tool may also include:

[0067] The parameter values ​​of the target layout design parameters are sequentially set to multiple invalid values ​​that are not within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, thus forming multiple reverse expansion test cases corresponding to the target layout design parameters at the test layout level.

[0068] The target layout design parameters are sequentially set to multiple valid values ​​within their range, while the reference layout design parameters are set to preset default values. This creates multiple extended test cases corresponding to the target layout design parameters at the test layout level, which may include:

[0069] The parameter values ​​of the target layout design parameters are sequentially set to multiple valid values ​​within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, thus forming multiple positive expansion test cases corresponding to the target layout design parameters at the test layout level.

[0070] In this embodiment, in order to verify the behavior of the target layout design parameters when they do not conform to the rules, the server will further construct reverse expansion test cases.

[0071] Specifically, after obtaining the parameter value range corresponding to the target layout design parameters, the server selects multiple invalid values ​​that do not belong to the parameter value range. These invalid values ​​can be lower than the minimum value or higher than the maximum value.

[0072] Then, the parameter values ​​of the target layout design parameters are sequentially set to these invalid values, while keeping the other reference layout design parameters at their default values.

[0073] Based on the above settings, multiple reverse expansion test cases are constructed corresponding to the target layout design parameters at the test layout level.

[0074] This embodiment constructs forward and reverse expansion use cases, comprehensively covering the value range of each target layout design parameter. Simultaneously, the forward and reverse expansion use cases facilitate the identification of false positives / false negatives in the DRC tool. Thus, this embodiment improves the completeness and accuracy of DRC verification.

[0075] As an optional embodiment, the multiple extended use cases include a first extended use case and a second extended use case;

[0076] The first extended use case is used to characterize the extended use case corresponding to the command that generates layout elements corresponding to the layout design parameters;

[0077] The second extended use case is used to characterize the extended use case corresponding to the command that filters out layout elements that correspond to the layout design parameters.

[0078] In this embodiment, the first extended use case is the extended use case of the generate command, which is used to generate or produce data, files or rules related to layout design.

[0079] The first extended use case is the extended use case of the filter command. The filter command is used to filter, screen, or check the layout design to conform to specific design rules.

[0080] This embodiment constructs first and second extended test cases, comprehensively covering test cases corresponding to various commands. Thus, by covering test cases for various commands, this embodiment improves the completeness and accuracy of DRC verification.

[0081] As an optional embodiment, S103 may specifically include:

[0082] Each test case is executed using a chip layout design rule checking tool to obtain the test results for each test case.

[0083] Each test result is compared with the expected result corresponding to the test case to determine whether each test result meets the test expectation.

[0084] The reliability of the chip layout design rule checking tool is determined based on the number of test results that meet the test expectations and the number of test results that do not meet the test expectations.

[0085] In this embodiment, the server uses the DRC tool to execute each test case individually. The DRC tool automatically analyzes the layout design in the test cases and checks it against its built-in design rule library. After the check is complete, the tool generates the test results for each test case.

[0086] Then, the server compares the test results of each test case with the expected results. If the test results match the expected results, the test case is considered to have passed; if the test results do not match the expected results, the test case is considered to have failed, and the specific differences are recorded.

[0087] Finally, the number of test results that met the testing expectations and the number that did not are counted. Based on the statistical results, reliability metrics of the tool, such as pass rate and error rate, are calculated.

[0088] As an example, the server can also automatically send the test results corresponding to each test case to a preset email address so that users can easily view the verification results of the chip layout design rule checking tool.

[0089] In this embodiment, by using the chip layout design rule checking tool to execute each test case, the reliability of the chip layout design rule checking tool can be automatically tested, thereby improving the verification reliability and efficiency of the layout checking tool.

[0090] As an optional embodiment, such as Figure 2 As shown, after S103, the verification method of this design rule checking tool may also include the following S201-S202:

[0091] S201, Obtain test execution information for each test case during execution. The test execution information includes at least one of the following: test execution status, test execution time, peak test execution memory, and number of logs generated during execution.

[0092] S202 compiles the test execution information and test results of each test case and generates a test report corresponding to the chip layout design rule checking tool.

[0093] In this embodiment, the test execution status is used to characterize whether the DRC tool is executing the test cases correctly. It records the execution status of the test cases, such as executing, successful execution, or failed execution. This helps developers understand the execution progress and results of the test cases.

[0094] Test execution time characterizes the time consumed by the DRC tool during the execution of test cases. It records the total time from the start to the end of test case execution. This helps to evaluate the tool's execution efficiency and performance.

[0095] Peak memory usage during test execution characterizes the peak memory consumption of the DRC tool during test case execution. It records the peak memory usage of each test case during execution. This helps in understanding the tool's memory resource requirements and usage.

[0096] The number of log lines generated during execution is used to characterize the number of log lines produced by the DRC tool during the execution of test cases. It records the number of log lines generated by a test case during execution. This helps developers understand the execution details and potential problems of the test cases.

[0097] As an example, after obtaining the test execution information and test results of each test case, the server performs statistical analysis on the obtained test execution information and test results, and generates a detailed test report.

[0098] This embodiment comprehensively acquires test execution information during the test case execution process and generates detailed test reports. The test reports clearly demonstrate the execution status, performance, and test results of each test case, thereby helping developers better understand the tool's performance and stability.

[0099] As an optional embodiment, after S202, the verification method of the design rule checking tool may further include:

[0100] Based on the test report corresponding to the chip layout design rules inspection tool, determine the test deviation value between the test run information of each test case and the preset benchmark run information;

[0101] If the test deviation value is greater than the preset deviation threshold, the cause of the test deviation value is determined according to the test case corresponding to the test deviation value.

[0102] If the cause of the test deviation is not a preset normal cause, a test exception message will be generated.

[0103] In this embodiment, the preset benchmark operating information is the ideal test operating state preset according to the chip design specifications and performance requirements.

[0104] As an example, the server compares the test execution information in the test report with the preset baseline execution information. Through this comparison, the test deviation value for each test case is calculated, which represents the degree of difference between the actual test case execution information and the preset baseline execution information.

[0105] Then, the calculated test deviation value is compared with a preset deviation threshold. The preset deviation threshold is set according to the tolerance range and performance requirements of the chip design and is used to determine whether the test deviation is within an acceptable range.

[0106] If the test deviation value exceeds the preset deviation threshold, it indicates a significant difference between the test results and expectations, requiring further analysis of the cause of the test deviation. Based on the test cases corresponding to the test deviation value, and considering possible factors in the chip layout design and manufacturing process, such as process parameters, material properties, and layout, a comprehensive analysis should be conducted to determine the specific cause of the test deviation.

[0107] The analyzed causes of test deviations are compared with the preset normal causes. Preset normal causes include common and acceptable deviation reasons, such as process fluctuations and measurement errors. If the cause of the test deviation does not belong to the preset normal causes, it indicates that the test deviation is caused by abnormal factors.

[0108] If the cause of the test deviation is not a preset normal cause, a test exception message will be generated. The test exception message should include detailed information about the test case, the test deviation value, and the cause of the test deviation, so that relevant personnel can promptly identify the problem and take appropriate corrective measures.

[0109] This embodiment enables accurate and rapid identification of deviation values ​​and causes in chip layout design rule checking tool tests, providing strong support for quality control during chip design and manufacturing processes. Simultaneously, by generating test anomaly alerts, it improves the efficiency of problem detection and resolution, contributing to enhanced overall performance and reliability of the chip layout design rule checking tool.

[0110] A verification method based on a design rule checking tool. Accordingly, this application also provides specific embodiments of a verification apparatus for the design rule checking tool.

[0111] like Figure 3 As shown, the verification device 300 based on the design rule checking tool provided in this application embodiment includes a hierarchical construction module 310, a test case creation module 320, and a test case execution module 330.

[0112] The hierarchical construction module 310 is used to construct a test layout hierarchy corresponding to the tool attributes based on the tool attributes of the chip layout design rule checking tool. The tool attributes are used to characterize the chip layout hierarchy that the chip layout design rule checking tool can handle.

[0113] The test case creation module 320 is used to create multiple test cases corresponding to each layout design parameter at the test layout level based on the layout design parameters included in the layout design rules corresponding to the chip layout. The layout design rules are used to characterize the set of mandatory provisions for the design content of the chip layout.

[0114] The test case execution module 330 is used to execute each test case separately through the chip layout design rule checking tool to determine the reliability of the chip layout design rule checking tool.

[0115] As an optional implementation, multiple test cases are extended test cases;

[0116] The use case creation module 320 specifically includes the following units:

[0117] The loop execution unit is used to repeatedly execute the following units until all layout design parameters included in the layout design rules have been traversed:

[0118] The range acquisition unit is used to obtain the parameter value range corresponding to the target layout design parameter, where the target layout design parameter is any one of the layout design parameters.

[0119] The parameter value setting unit is used to sequentially set the parameter values ​​of the target layout design parameters to multiple valid values ​​within the parameter value range, and to set the parameter values ​​of the reference layout design parameters to preset default values, thereby forming multiple extended test cases corresponding to the target layout design parameters at the test layout level. The reference layout design parameters are the layout design parameters other than the target layout design parameters among the layout design parameters corresponding to the layout design rules.

[0120] As an optional embodiment, the multiple extended test cases include forward extended test cases and reverse extended test cases. Forward test cases are used to characterize extended test cases consisting of valid values ​​that satisfy the layout design rules, and reverse test cases are used to characterize extended test cases consisting of invalid values ​​that do not satisfy the layout design rules.

[0121] After obtaining the parameter value range corresponding to the target layout design parameters, the use case creation module 320 also includes the following units:

[0122] The parameter value setting unit is also used to sequentially set the parameter values ​​of the target layout design parameters to multiple invalid values ​​that are not within the parameter value range, and to set the parameter values ​​of the reference layout design parameters to preset default values, thereby forming multiple reverse expansion test cases corresponding to the target layout design parameters at the test layout level.

[0123] The parameter value setting unit is also used to sequentially set the parameter values ​​of the target layout design parameters to multiple valid values ​​within the parameter value range, and to set the parameter values ​​of the reference layout design parameters to preset default values, thereby forming multiple positive expansion test cases corresponding to the target layout design parameters at the test layout level.

[0124] As an optional embodiment, the use case execution module 330 specifically includes the following units:

[0125] The test case execution unit is used to execute each test case separately through the chip layout design rule checking tool and obtain the test results corresponding to each test case.

[0126] The result comparison unit is used to compare each test result with the expected result corresponding to the test case to determine whether each test result meets the test expectation.

[0127] The reliability determination unit is used to determine the reliability of the chip layout design rule checking tool based on the number of test results that meet the test expectations and the number of test results that do not meet the test expectations.

[0128] As an optional embodiment, after determining the reliability of the chip layout design rule checking tool by executing each test case using the chip layout design rule checking tool, the verification device 300 based on the design rule checking tool may further include the following modules:

[0129] The information acquisition module is used to acquire test execution information of each test case during execution. The test execution information includes at least one of the following: test execution status, test execution time, peak test execution memory, and number of logs generated during execution.

[0130] The report generation module is used to statistically analyze the test execution information and test results of each test case and generate a test report corresponding to the chip layout design rule checking tool.

[0131] As an optional embodiment, after statistically analyzing the test execution information and test results of each test case to generate a test report corresponding to the chip layout design rule checking tool, the verification device 300 based on the design rule checking tool may further include the following modules:

[0132] The deviation value determination module is used to check the test report corresponding to the chip layout design rules and determine the test deviation value between the test run information of each test case and the preset benchmark run information.

[0133] The cause determination module is used to determine the cause of the test deviation value based on the test case corresponding to the test deviation value when the test deviation value is greater than the preset deviation threshold.

[0134] The exception prompt module is used to generate test exception prompt information when the test deviation is not due to a preset normal cause.

[0135] A verification method based on a design rule checking tool. Accordingly, this application also provides specific embodiments of a verification device for the design rule checking tool.

[0136] Figure 4 A schematic diagram of the hardware structure of the verification device for the design rule checking tool provided in an embodiment of this application is shown.

[0137] The verification device for the design rule checking tool may include a processor 401 and a memory 402 storing computer program instructions.

[0138] Specifically, the processor 401 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0139] Memory 402 may include mass storage for data or instructions. For example, and not limitingly, memory 402 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 402 may include removable or non-removable (or fixed) media. Where appropriate, memory 402 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 402 is non-volatile solid-state memory.

[0140] The processor 401 reads and executes computer program instructions stored in the memory 402 to implement the verification method of any of the design rule checking tools in the above embodiments.

[0141] In one example, the verification device for the design rule checking tool may also include a communication interface 403 and a bus 410. Wherein, as Figure 4 As shown, the processor 401, memory 402, and communication interface 403 are connected through bus 410 and complete communication with each other.

[0142] The communication interface 403 is mainly used to realize communication between various modules, devices, layout units and / or equipment in the embodiments of this application.

[0143] Bus 410 includes hardware, software, or both, that couples components of a verification device for a design rule checking tool together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 410 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0144] Furthermore, in conjunction with the verification method of the design rule checking tool in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the verification methods of the design rule checking tool in the above embodiments.

[0145] In addition, in conjunction with the verification method of the design rule checking tool in the above embodiments, this application embodiment can provide a computer program product to implement the method. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device executes the verification method of the design rule checking tool provided in any aspect of the above embodiments of this application.

[0146] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0147] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0148] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0149] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0150] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and layout units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A verification method for a design rule checking tool, characterized in that, include: Based on the tool attributes of the chip layout design rule checking tool, a test layout hierarchy corresponding to the tool attributes is constructed. The tool attributes are used to characterize the features of the chip layout hierarchy that the chip layout design rule checking tool can process. Based on the layout design parameters included in the layout design rules corresponding to the chip layout, multiple test cases are created for each layout design parameter at the test layout level. The layout design rules are used to characterize the set of mandatory provisions for the design content of the chip layout. The multiple test cases are real test cases or extended test cases. The reliability of the chip layout design rule checking tool is determined by executing each of the test cases using the chip layout design rule checking tool. The step of creating multiple test cases corresponding to each layout design parameter at the test layout level based on the layout design rules corresponding to the chip layout includes: when the multiple test cases are the extended test cases, sequentially setting the parameter value of the target layout design parameter to multiple valid values, and setting the parameter value of the reference layout design parameter to a preset default value, thereby constituting multiple extended test cases corresponding to the target layout design parameter at the test layout level. The target layout design parameter is any one of the layout design parameters, and the reference layout design parameter is the layout design parameter other than the target layout design parameter among the layout design parameters corresponding to the layout design rules.

2. The method according to claim 1, characterized in that, The real-world use cases are used to characterize the use cases that are actually obtained at the actual design end of the chip layout. The extended use cases are used to characterize use cases generated by extending the layout design parameters included in the layout design rules.

3. The method according to claim 1, characterized in that, The multiple test cases mentioned above are the extended test cases; The step of creating multiple test cases corresponding to each layout design parameter at the test layout level based on the layout design rules corresponding to the chip layout includes: The following steps are executed repeatedly until all the layout design parameters included in the layout design rules are traversed: Obtain the parameter value range corresponding to the target layout design parameters; The parameter values ​​of the target layout design parameters are sequentially set to multiple valid values ​​within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, thereby constituting multiple extended test cases corresponding to the target layout design parameters at the test layout level.

4. The method according to claim 3, characterized in that, The multiple extended use cases include forward extended use cases and reverse extended use cases. The forward extended use cases are used to characterize extended use cases consisting of valid values ​​that satisfy the layout design rules, and the reverse extended use cases are used to characterize extended use cases consisting of invalid values ​​that do not satisfy the layout design rules. After obtaining the parameter value range corresponding to the target layout design parameters, the method further includes: The parameter values ​​of the target layout design parameters are sequentially set to multiple invalid values ​​that are not within the range of parameter values, and the parameter values ​​of the reference layout design parameters are set to preset default values, thereby forming multiple reverse expansion test cases corresponding to the target layout design parameters at the test layout level. The step of sequentially setting the parameter values ​​of the target layout design parameters to multiple valid values ​​within the parameter value range, and setting the parameter values ​​of the reference layout design parameters to preset default values, constitutes multiple extended test cases corresponding to the target layout design parameters at the test layout level, including: The parameter values ​​of the target layout design parameters are sequentially set to multiple valid values ​​within the parameter value range, and the parameter values ​​of the reference layout design parameters are set to preset default values, thereby constituting multiple positive expansion test cases corresponding to the target layout design parameters at the test layout level.

5. The method according to claim 2, characterized in that, The extended use cases include a first extended use case and a second extended use case; The first extended use case is used to characterize the extended use case corresponding to the command that generates layout elements corresponding to the layout design parameters; The second extended use case is used to characterize the extended use case corresponding to the command that filters out the layout elements corresponding to the layout design parameters.

6. The method according to claim 1, characterized in that, The step of determining the reliability of the chip layout design rule checking tool by executing each of the test cases through the chip layout design rule checking tool includes: The chip layout design rule checking tool is used to execute each test case to obtain the test results corresponding to each test case. Each test result is compared with the expected result corresponding to the test case to determine whether each test result meets the test expectation. The reliability of the chip layout design rule checking tool is determined based on the number of test results that meet the test expectations and the number of test results that do not meet the test expectations.

7. The method according to any one of claims 1-6, characterized in that, After determining the reliability of the chip layout design rule checking tool by executing each of the test cases using the chip layout design rule checking tool, the method further includes: Obtain test execution information for each test case during execution, including at least one of test execution status, test execution time, peak test execution memory, and number of logs generated during execution; The test execution information and test results of each test case are statistically analyzed to generate a test report corresponding to the chip layout design rule checking tool.

8. The method according to claim 7, characterized in that, After statistically analyzing the test execution information and test results of each test case to generate a test report corresponding to the chip layout design rule checking tool, the method further includes: Based on the test report corresponding to the chip layout design rule inspection tool, determine the test deviation value between the test run information of each test case and the preset benchmark run information; If the test deviation value is greater than a preset deviation threshold, the cause of the test deviation value is determined according to the test case corresponding to the test deviation value. If the cause of the test deviation does not belong to the preset normal cause, a test abnormality prompt message will be generated.

9. An electronic device, characterized in that, The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, it implements the verification method of the design rule checking tool as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the verification method of the design rule checking tool as described in any one of claims 1-8.

11. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the verification method of the design rule checking tool as described in any one of claims 1-8.

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