Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, and relate to the technical field of display, and aim to alleviate the problem that a display panel is prone to horizontal horizontal lines in the related art. The display panel comprises a gate drive circuit, a power signal line and a clock signal line group arranged in sequence on one side of the gate drive circuit; the power signal line is electrically connected with the gate drive circuit, and the power signal line extends along a first direction. The clock signal line group comprises a first clock signal line and a second clock signal line arranged in sequence in a direction away from the gate drive circuit; the first clock signal line is electrically connected with the gate drive circuit through a first connecting line, and the second clock signal line is electrically connected with the gate drive circuit through a second connecting line. The power signal line has a recess, and an opening of the recess faces the gate drive circuit or the clock signal line group. The first connecting line comprises a main body part and a bending part connected with the main body part, and the bending part is located in a region where the recess is located in a thickness direction of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] GOA (Gate Driver on Array) technology refers to integrating a gate driving circuit on an array substrate of a display panel, so that the gate driving circuit can replace an external integrated circuit board (IC) to complete driving of horizontal scanning lines.

[0003] In a large-size display panel, a gate driving circuit is usually connected to a plurality of clock signal lines. However, due to the position difference of the clock signal lines, the connection lines for connecting the gate driving circuit and the clock signal lines have length difference, which causes resistance difference of the connection lines, and further causes the display panel to easily have horizontal horizontal lines and other problems. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device to alleviate the problem that the display panel easily has horizontal horizontal lines in the related art.

[0005] In an aspect, the present application provides a display panel, which comprises a gate driving circuit, a power signal line and a clock signal line group; the power signal line is located at one side of the gate driving circuit and is electrically connected to the gate driving circuit, and the power signal line extends along a first direction; the clock signal line group is located at a side of the power signal line away from the gate driving circuit, and the clock signal line group comprises at least one first clock signal line and a second clock signal line arranged in sequence in a direction away from the gate driving circuit; the first clock signal line is electrically connected to the gate driving circuit through a first connection line, and the second clock signal line is electrically connected to the gate driving circuit through a second connection line; wherein the power signal line has at least one recess, and an opening of the recess faces one of the gate driving circuit and the clock signal line group; the first connection line comprises a main body part and a bending part connected to the main body part, and the bending part is located in a region where the recess is located in a thickness direction of the display panel.

[0006] In some embodiments, lengths of at least part of the first connection lines are equal.

[0007] In some embodiments, lengths of each of the first connection lines are equal to a length of the second connection line.

[0008] In some embodiments, along the first direction, the plurality of first connection lines are divided into a plurality of connection line groups arranged in sequence, wherein the lengths of different first connection lines in the same connection line group are equal, and the lengths of the first connection lines in the plurality of connection line groups gradually change along the first direction.

[0009] In some embodiments, the resistance difference of the first connection lines in any two adjacent connection line groups is the same.

[0010] In some embodiments, the length of the second connection line is equal to the length of a first connection line in the connection line group close to the second connection line.

[0011] In some embodiments, the power signal line comprises a first part, a second part and a third part connected in sequence along the first direction, the width of the first part and the width of the third part are greater than the width of the second part to form the recess.

[0012] In some embodiments, the first part and the third part each comprise M first sub-traces spaced apart and arranged in parallel, the second part comprises N second sub-traces spaced apart and arranged in parallel, M is greater than N, and the N first sub-traces and the N second sub-traces are connected one by one in sequence.

[0013] In some embodiments, each first connection line further comprises an extension part at an end away from the gate drive circuit, the extension part is connected to the main body part; for different first connection lines, the sum of the lengths of the main body part and the extension part connected thereto is equal.

[0014] In some embodiments, the display panel further comprises a first capacitance balancing part connected to the second connection line, and a second capacitance balancing part connected to each bending part, the power signal line further has an auxiliary recess, the first capacitance balancing part is located in the region where the auxiliary recess is located in the thickness direction of the display panel; the second capacitance balancing part is located in the region where the recess is located in the thickness direction of the display panel; wherein along the first direction, the sum of the sizes of the bending part and the second capacitance balancing part is equal to the sum of the sizes of the second connection line and the first capacitance balancing part.

[0015] In some embodiments, the power signal line is adjacent to the gate drive circuit, and the opening of the recess faces the gate drive circuit.

[0016] In some embodiments, the power signal line includes a first power sub-signal line and a second power sub-signal line, the first power sub-signal line and the second power sub-signal line are sequentially arranged in a direction away from the clock signal line group; the first power sub-signal line has the recess, and an opening of the recess faces the gate drive circuit, the second power sub-signal line has at least one opposite recess, the opposite recess is oppositely arranged with the recess, and the bending portion is also located in a region where the opposite recess is located in a thickness direction of the display panel.

[0017] In another aspect, the embodiments of the present application also provide a display device, which includes the display panel as described in any of the above embodiments.

[0018] For the display panel provided by the embodiments of the present application, since the power signal line has at least one recess, and the first connection line is bent and forms a bending portion in a region corresponding to the recess, the length of the first connection line can be effectively compensated, so that the length of the first connection line matches the length of the second connection line, and the resistance difference between the first connection line and the second clock signal line is reduced, so as to alleviate the problem of horizontal horizontal lines and the like of the display panel. In addition, the bending portion does not overlap with the power signal line in the region of the recess K, so as to avoid crosstalk between the signal transmitted in the first connection line and the signal in the power signal line. In addition, since the power signal line has the recess K for realizing partial bending of the first connection line, the problem that the first connection line has no enough space to realize partial bending in the frame area of the narrow frame or ultra-narrow frame display panel can be alleviated, so that the display panel can be applied to the narrow frame or ultra-narrow frame display panel. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a partial structure schematic diagram of a display panel in the related art;

[0020] Figure 2 is a structure schematic diagram of a display panel provided by some embodiments of the present application;

[0021] Figure 3 is Figure 2 is a structure schematic diagram of a partial structure in

[0022] Figure 4 is Figure 2 is another structure schematic diagram of a partial structure in

[0023] Figure 5 is a partial structure schematic diagram of a connection line according to some embodiments of the present application;

[0024] Figure 6 is Figure 2 is still another structure schematic diagram of a partial structure in

[0025] Figure 7 is Figure 2 is another structural schematic view of a partial configuration in

[0026] Figure 8 is Figure 2 is another structural schematic view of a partial configuration in DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The described technical solutions are only used to explain and describe the ideas of the present application, and should not be regarded as a limitation on the protection scope of the present application.

[0028] In the description of the present application, it should be understood that the terms "first", "second" and similar words do not represent any order, number or importance, but are only used to distinguish different technical features. The term "multiple" and similar words represent two or more than two, unless otherwise explicitly limited.

[0029] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0030] The use of "adapted for" or "configured for" in the present application means open and inclusive language, which does not exclude devices adapted for or configured to perform additional tasks or steps. In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values can be based on additional conditions or beyond the stated values in practice.

[0031] In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment described as "exemplary" in the present application is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the present application.

[0032] Various embodiments of the present application are similar, and features in different embodiments and / or different examples can be combined with each other.

[0033] In the related art, the connection lines for connecting the gate driving circuit and the clock signal line have different lengths, resulting in different resistances of the connection lines, which in turn causes the display interface of the display panel to be prone to horizontal horizontal lines and other problems. In order to reduce the resistance difference, the current commonly used winding method is used to increase the length of part of the connection lines, thereby reducing the resistance difference between different signal lines.

[0034] The wire winding method requires sufficient space in the display panel's border area to accommodate the wire winding requirements. Conventional display panels can achieve wire winding by increasing the width of the border area. However, for display panels with narrow or ultra-narrow borders, the border area lacks sufficient area to meet the wire winding requirements.

[0035] like Figure 1 As shown, a display panel 100' in the related art includes a gate drive circuit 11', multiple clock signal lines 13', and connecting lines 12' connecting the clock signal lines 13' and the gate drive circuit 11'. Due to the limited border area of ​​the display panel 100' with a narrow or ultra-narrow border, it is difficult to bend the connecting lines 12' for winding, which can cause problems such as horizontal stripes on the display panel 100'.

[0036] Based on this, some embodiments of the present application provide a display panel, such as Figure 2 As shown, the display panel 100 may include an effective display area AA and a bezel area BA.

[0037] The effective display area AA includes a pixel array composed of a plurality of pixels, and the pixel array can be used to realize image display on the display panel.

[0038] In addition, signal lines for providing various signals (such as clock signals, high-level signals, low-level signals, etc.) are provided in the frame area BA. Figure 3 The specific details of the local structure P located in the border area BA are described in detail.

[0039] like Figure 3 As shown, the display panel 100 includes a gate drive circuit 11, a power signal line 12, and a clock signal line group 13. The power signal line 12 is located on a side of the gate drive circuit 11 away from the active display area AA, and the clock signal line group 13 is located on a side of the power signal line 12 away from the gate drive circuit 11. That is, the gate drive circuit 11, the power signal line 12, and the clock signal line group 13 are arranged in sequence in a direction away from the active display area AA.

[0040] The power signal line 12 is electrically connected to the gate drive circuit 11 and extends along the first direction X. The power signal line 12 has at least one recess K, the opening of which faces at least one of the gate drive circuit 11 and the clock signal line group 13 ( Figure 3 Only the opening of the recess K is shown facing the gate drive circuit 11).

[0041] In the embodiment, the clock signal line group 13 includes at least one (for example, multiple) first clock signal line 131 and a second clock signal line 132 arranged side by side in sequence in a direction away from the gate drive circuit 11. Figure 3 Seven first clock signal lines 131 and one second clock signal line 132 are shown in FIG. 7, and the second clock signal line 132 is located on the side of all the first clock signal lines 131 away from the gate drive circuit 11. The first clock signal line 131 is electrically connected to the gate drive circuit 11 through the first connecting line 14, and the second clock signal line 132 is electrically connected to the gate drive circuit 11 through the second connecting line 15. The first connecting line 14 includes a main body portion 141 and a bending portion 142 connected to the main body portion 141, and the bending portion 142 is located in the area of the recess K in the thickness direction of the display panel 100. The bending portion 142 can be used to compensate for the length of the first connecting line 14 to increase the length of the first connecting line 14.

[0042] For the display panel 100 provided by the embodiment of the present application, since the power signal line 12 has at least one recess K, and the first connecting line 14 is bent and forms a bending portion 142 in the area corresponding to the recess K, the length of the first connecting line 14 can be effectively compensated, so that the length of the first connecting line 14 matches the length of the second connecting line 15, thereby reducing the resistance difference between the first connecting line 14 and the second connecting line 15, and alleviating the problem of horizontal horizontal lines and the like in the display panel 100. In addition, the bending portion 142 does not overlap the power signal line 12 in the area of the recess K, so as to avoid crosstalk between the signals transmitted in the first connecting line 14 and the signals in the power signal line 12. In addition, since the power signal line 12 has a recess K for realizing partial bending of the first connecting line 14, it is also applicable to narrow frame or ultra-narrow frame display panels, thereby alleviating the problem of horizontal horizontal lines and the like in the narrow frame or ultra-narrow frame display panel 100.

[0043] In some examples, the extension direction of the main body portion 141 of the first connecting line 14 and the extension direction of the second connecting line 15 are the same.

[0044] In some examples, the sum of the lengths of the main body portion 141 and the bending portion 142 is substantially equal to the length of the second connecting line 15. That is, the length of the first connecting line 14 is substantially equal to the length of the second connecting line 15. In this way, the resistance of the first connecting line 14 and the second connecting line 15 can be equalized, thereby avoiding the problem of horizontal horizontal lines and the like in the display panel 100.

[0045] It should be noted that "A and B are substantially equal" mentioned herein can mean that A and B are exactly equal, or the difference between A and B is within a certain range. For example, the absolute value of the difference between A and B is less than 10% of A.

[0046] In some embodiments, the gate driving circuit 11 can be a GOA circuit. As shown in Figure 3 and Figure 4 The gate driving circuit 11 includes a plurality of shift register units 111 arranged along a first direction X and connected in cascade. Different clock signal lines are electrically connected to different shift register units 111, respectively. For example, the first clock signal line 131 is electrically connected to one shift register unit 111 in the gate driving circuit 11 through the first connection line 14, and the second clock signal line 132 is electrically connected to another shift register unit 111 in the gate driving circuit 11 through the second connection line 15.

[0047] In some examples, the clock signal line group 13 includes a plurality of clock signal lines (i.e., the first clock signal line 131 and the second clock signal line 132), and the plurality of clock signal lines are arranged along a second direction Y intersecting the first direction X. For example, the second direction Y and the first direction X can be perpendicular to each other.

[0048] In some examples, the first connection line 14 and the second connection line 15 are arranged in the same layer, and the metal layer where the first connection line 14 and the second connection line 15 are arranged is different from the metal layer where the clock signal line group 13 is arranged. An insulating layer is arranged between the two metal layers to separate them, and a via is arranged in the insulating layer. One end of the first connection line 14 is electrically connected to the corresponding first clock signal line 131 through the via, and the other end of the first connection line 14 is used to electrically connect to the corresponding shift register unit 111, thereby realizing the transmission of the clock signal. In addition, one end of the second connection line 15 is electrically connected to the second clock signal line 132 through the via, and the other end of the second connection line 15 is used to electrically connect to the corresponding shift register unit 111, thereby realizing the transmission of the clock signal.

[0049] In some embodiments, as shown in Figure 4 and Figure 5 The power signal line 12 includes a first portion 121, a second portion 122 and a third portion 123 arranged in sequence along the first direction X and connected to each other. In the second direction Y, the size of the first portion 121 and the size of the third portion 123 are respectively greater than the size of the second portion 122 to form a recess K. That is, the width of the first portion 121 and the width of the third portion 123 are respectively greater than the width of the second portion 122, so that the second portion 122 is recessed compared to the first portion 121 and the third portion 123 to form the recess K.

[0050] In some examples, the size of the first portion 121 and the size of the third portion 123 can be equal, so that the shape of the recess K is relatively uniform, thereby having a relatively large opening area to facilitate the arrangement of the bending portion 142.

[0051] It is worth mentioning that the "recess" in the present application not only includes the recess composed of the first portion 121, the second portion 122 and the third portion 123, but also includes at least the following cases. The power signal line 12 includes the first portion 121 and the second portion 122 arranged in sequence and connected with each other in the first direction X, and the size of the first portion 121 is greater than the size of the second portion 122 in the second direction Y to form a recess K. That is, the recess can also be in the form of a step. Therefore, as long as the size of the power signal line 12 portion position in the second direction Y is reduced, and the bending portion 142 can be arranged in the area where the recess is located, it is within the scope of the present application.

[0052] In some embodiments, as shown in Figure 4 and Figure 5 the first portion 121 and the third portion 123 each include M first sub-traces 1210 arranged in parallel and spaced apart from each other, and the second portion 122 includes N second sub-traces 1220 arranged in parallel and spaced apart from each other.

[0053] By arranging the first portion 121, the second portion 122 and the third portion 123 as a plurality of sub-traces spaced apart from each other, not only the stress of the power signal line 12 can be reduced, but also the overlapping area of the power signal line 12 and other traces (such as the first connection line 14) in the thickness direction of the display panel 100 can be reduced, thereby reducing the interference between different signals.

[0054] In some examples, M is greater than N, and the N first sub-traces 1210 and the N second sub-traces 1220 are connected in a one-to-one correspondence. In this way, the N first sub-traces 1210 can be gathered to expand the depth of the recess K, thereby increasing the opening area of the recess K to facilitate the arrangement of the bending portion 142.

[0055] In some examples, N is greater than or equal to M / 2. For example, when M = 6, N can be 3, 4 or 5.

[0056] By setting N to be greater than or equal to M / 2, the width of the second portion 122 can be at least half the width of the power signal line 12, thereby ensuring the stability of the structure of the power signal line 12 and the effective transmission of the power signal.

[0057] In some embodiments, as shown in Figure 3 in the case where the clock signal line group 13 includes a plurality of first clock signal lines 131, the plurality of first clock signal lines 131 are electrically connected to the gate drive circuit 11 through a plurality of first connection lines 14. At least part of the plurality of first connection lines 14 have equal lengths.

[0058] In some examples, the lengths of all the first connection lines 14 are equal, so that the resistances of all the first connection lines 14 are equal, thereby effectively avoiding the problem of horizontal horizontal stripes of the display panel 100.

[0059] In this case, the lengths of each first connection line 14 and the lengths of the second connection lines 15 are equal, so that the resistances of all the connection lines are equal, thereby further avoiding the problem of horizontal horizontal stripes of the display panel 100.

[0060] In some examples, the lengths of part of the first connection lines 14 in the plurality of first connection lines 14 are equal. In this case, in the area of the display panel 100 corresponding to the part of the first connection lines 14, since the lengths of the part of the first connection lines 14 are equal, the resistances of the part of the first connection lines 14 are equal, thereby effectively avoiding the problem of horizontal horizontal stripes of the display panel 100 in the area corresponding to the part of the first connection lines 14.

[0061] In some cases, the size of the power signal line 12 in the second direction Y is limited, so that the depth of the recess K of the power signal line 12 is limited, thereby causing the length of the first connection line 14 that can be compensated by the bending portion 142 to be limited.

[0062] Based on this, in some embodiments of the present application, as shown in Figure 6 In the first direction X, the plurality of first connection lines 14 are divided into a plurality of connection line groups 140 arranged in sequence, wherein the lengths of different first connection lines 14 in the same connection line group 140 are equal. And in the first direction X, the lengths of the first connection lines 14 in the plurality of connection line groups 140 gradually change.

[0063] For example, Figure 6 As shown in FIG. 5, 5 first connection lines 14 are divided into 2 connection line groups 140, in the same connection line group 140, the lengths of each first connection line 14 are equal, while in different connection line groups 140, the lengths of the first connection lines 14 are not equal, and in the first direction X, the lengths of the first connection lines 14 in different connection line groups 140 gradually increase or decrease.

[0064] By making the lengths of the first connection lines 14 in different connection line groups 140 change regularly, this can avoid the problem that the difference between the first connection lines 14 in different connection line groups 140 is too large, causing the display panel 100 to have significant horizontal horizontal stripes. And this can also effectively reduce the length difference of the first connection lines 14, thereby reducing the resistance difference of the first connection lines 14, and further effectively reducing the risk of horizontal horizontal stripes of the display panel 100.

[0065] In some embodiments, as shown in Figure 6As shown, the length of the second connection line 15 is equal to the length of the first connection line 14 in the connection line group 140 close to the second connection line 15. That is, the second connection line 15 can be divided into the connection line group 140, so as to have the same length as the first connection line 14 in the connection line group 140. In this case, the resistance of the second connection line 15 is equal to the resistance of the first connection line 14 in the connection line group 140. This is conducive to reducing the resistance difference between different connection lines, thereby effectively reducing the risk of horizontal horizontal lines of the display panel 100.

[0066] In some embodiments, as shown in FIG. 1, the display panel 100 includes a plurality of connection lines, and the plurality of connection lines includes a plurality of first connection lines 14 and a plurality of second connection lines 15. Figure 6 As shown, the resistance difference of the first connection line 14 in any two adjacent connection line groups 140 is the same.

[0067] In this way, the resistance of the first connection line 14 in different connection line groups 140 changes little, which is conducive to controlling the resistance difference of different first connection lines 14, thereby effectively reducing the risk of horizontal horizontal lines of the display panel 100.

[0068] In order to further embody the beneficial effects of the above-mentioned embodiments, the following is an example of a display panel including 12 clock signal lines, and the connection lines for connecting the clock signal lines and the gate drive circuit also have 12 connection lines. As shown in Table 1, Table 1 shows the resistance of the connection lines in different display panels. In Table 1, CK1 to CK12 correspond to the connection lines for connecting each clock signal line, Example 1 represents the resistance of each connection line in the display panel 100' in the related art, and Example 2 represents the resistance of each connection line in the display panel 100 provided by the embodiments of the present application.

[0069] Table 1

[0070] Connection line Example 1 Example 2 CK1 3.4 4.2 CK2 3.5 4.2 CK3 3.6 4.2 CK4 3.7 4.3 CK5 3.8 4.3 CK6 3.9 4.4 CK7 4.0 4.4 CK8 4.1 4.4 CK9 4.2 4.5 CK10 4.3 4.5 CK11 4.4 4.6 CK12 4.5 4.6

[0071] Since all the connection lines of the display panel 100' in the related art have length differences, the resistance of each connection line gradually changes, so that the overall resistance difference eventually reaches 1.2; and for the display panel 100 provided by the embodiments of the present application, since the first connection line includes a bending portion, the length of different first connection lines is compensated, thereby enabling the overall resistance difference to be reduced to 0.4, which can effectively alleviate or even overcome the problem of horizontal horizontal lines.

[0072] In some embodiments, as shown in FIG. 1, the display panel 100 includes a plurality of connection lines, and the plurality of connection lines includes a plurality of first connection lines 14 and a plurality of second connection lines 15. Figure 4 As shown, the power signal line 12 is adjacent to the gate drive circuit 11, and the opening of the recess K faces the gate drive circuit 11.

[0073] It is worth mentioning that the power signal line 12 usually has a large width, so the power signal line 12 can have a relatively large area to set the recess K to meet the requirement of the first connection line 14 to form the bending part 142.

[0074] In some examples, the power signal line 12 can be a low-level power signal line VSS. As an implementation, a plurality of (for example, 2) low-frequency clock signal lines LS can also be arranged between the power signal line 12 and the clock signal line group 13.

[0075] In some embodiments, as shown in Figure 7 The power signal line 12 includes a first power sub-signal line 121 and a second power sub-signal line 122, which are arranged in sequence in a direction away from the clock signal line group 13; the first power sub-signal line 121 has the recess K, and the opening of the recess K faces the gate drive circuit 11, and the second power sub-signal line 122 has at least one opposite recess M, which is arranged opposite to the recess K, and the bending part 142 is also located in the area of the opposite recess M in the thickness direction of the display panel 100. That is, in the case that the second power sub-signal line 122 has the opposite recess M, the bending part 142 is located in the recess K and the opposite recess M at the same time.

[0076] In this case, the opposite recess M can further expand the area that can be used to arrange the bending part 142, so as to further improve the use scenario of the display panel 100, that is, the display panel 100 can be suitable for the scenario requirement of 12 clock signal lines (12CK), 16 clock signal lines (16CK) or even more clock signal lines.

[0077] In some examples, the first power sub-signal line 121 and the second power sub-signal line 122 can be high-level power signal lines VDD and low-level power signal lines VSS, respectively; or, the first power sub-signal line 121 and the second power sub-signal line 122 can both be high-level power signal lines VDD; or, the first power sub-signal line 121 and the second power sub-signal line 122 can both be low-level power signal lines VSS. The present application does not limit this.

[0078] In some embodiments, as shown in Figure 8 Each first connection line 14 further has an extension part 16 at one end away from the gate drive circuit 11, and the extension part 16 is connected with the main body part 141. For different first connection lines 14, the sum of the lengths of the main body part 141 and the extension part 16 connected therewith is equal.

[0079] In this way, the length of the first connection line 14 can be extended by the extension part 16, so that different first connection lines 14 all cross the same number of clock signal lines, and the capacitances of different first connection lines 14 are kept the same, which can effectively avoid the problem that the display panel is prone to horizontal horizontal lines due to different capacitances of the first connection lines 14.

[0080] In some examples, the second connection line 15 connects the first end point of the second clock signal line 132 and the second end point of the extension part 16 away from the main part 141 flush, and the line between the first end point and the second end point extends along the first direction X.

[0081] In this case, the number of clock signal lines crossed by the first connection line 14 is equal to the number of clock signal lines crossed by the second connection line 15, which can further avoid the problem that the display panel is prone to horizontal horizontal lines due to different capacitances of the second connection line 15 and the first connection line 14.

[0082] In some embodiments, as shown in Figure 8 The second connection line 15 is also connected with a first capacitance balancing part 17, and the power signal line 12 also has an auxiliary recess N, the first capacitance balancing part 17 is located in the area where the auxiliary recess N is located in the thickness direction of the display panel 100; each bending part 142 is also connected with a second capacitance balancing part 18, and the second capacitance balancing part 18 is located in the area where the recess K is located in the thickness direction of the display panel 100.

[0083] Among them, along the first direction X, the sum of the size of the bending part 142 and the second capacitance balancing part 18 is equal to the size of the second connection line 15 and the first capacitance balancing part 17. As shown in Figure 7 Along the first direction X, the size of the bending part 142 is D1, the size of the second capacitance balancing part 18 is D2, the size of the second connection line 15 is D3, and the size of the first capacitance balancing part 17 is D4, that is, D1+D2=D3+D4.

[0084] In this case, the capacitance formed between the first capacitance balancing part 17 and the power signal line 12 is equal to the capacitance formed between the bending part 142 and the second capacitance balancing part 18 and the power signal line 12, which can effectively improve the capacitance difference caused by the bending part 142 of the first connection line 14, so that the uniformity at each position on the display panel 100 is good, and the display effect of the display panel 100 is effectively guaranteed.

[0085] In some examples, the bending part 142 includes two first bending segments extending along the first direction X and a first connecting segment located between the two first bending segments, and the two ends of the first connecting segment are connected with the two first bending segments respectively, so as to realize the bending of the bending part 142.

[0086] In some examples, the second capacitance balancing portion 18 includes two second bent segments extending along the first direction X and a second connecting segment between the two second bent segments, the second connecting segment is opposite to the first connecting segment, and the two second bent segments, the second connecting segment and the first connecting segment form a rectangle.

[0087] In some examples, the first capacitance balancing portion 17 includes two third bent segments extending along the first direction X and a third connecting segment between the two third bent segments, the third connecting segment is opposite to the second connecting line 15, and the third connecting segment and the second connecting line 15 are respectively located at two ends of any third bent segment.

[0088] It is worth noting that, Figure 3 , Figure 4 and Figure 6 to Figure 8 are only exemplary illustrations of the partial structure P in the display panel 100. The partial structure P can also include other signal lines, and the embodiments of the present application are not limited thereto. Figure 2

[0089] In addition, for the display panel with an ultra-narrow frame, the frame region usually has a width of about 2.7 mm, and the width of the connecting line at the bending position usually needs to be several tens or even hundreds of microns. In general, the gap between the two adjacent tracks in the frame region cannot meet the bending requirement of the connecting line. Therefore, the display panel provided in the present application sets a recess in the power signal line to meet the bending requirement of the connecting line, so as to effectively alleviate or even avoid the problem of horizontal horizontal lines in the display panel with an ultra-narrow frame.

[0090] The embodiments of the present application are described in detail above, and the specific examples are applied to explain the principles and implementation modes of the present application. The above description of the embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as a limitation of the present application.​

Claims

1. A display panel, characterized by, The display panel comprises: a gate drive circuit; a power signal line located on one side of the gate drive circuit and electrically connected with the gate drive circuit, the power signal line extending along a first direction; a clock signal line group located on the side of the power signal line away from the gate drive circuit, the clock signal line group comprising at least one first clock signal line and one second clock signal line arranged in sequence away from the gate drive circuit; the first clock signal line is electrically connected with the gate drive circuit through a first connecting line, and the second clock signal line is electrically connected with the gate drive circuit through a second connecting line; wherein the power signal line has at least one recess, the opening of the recess is directed to one of the gate drive circuit and the clock signal line group; the first connecting line comprises a main body part and a bending part connected with the main body part, and the bending part is located in the area where the recess is located in the thickness direction of the display panel. The lengths of at least part of the first connecting lines are equal.

2. The display panel of claim 1, wherein, The length of each first connecting line is equal to the length of the second connecting line.

3. The display panel of claim 2, wherein, In the first direction, a plurality of first connecting lines are divided into a plurality of connecting line groups arranged in sequence, wherein the lengths of different first connecting lines in the same connecting line group are equal, and the lengths of the first connecting lines in a plurality of connecting line groups gradually change along the first direction.

4. The display panel of claim 2, wherein, The resistance difference of the first connecting lines in any two adjacent connecting line groups is the same.

5. The display panel of claim 4, wherein, The length of the second connecting line is equal to the length of the first connecting line in the connecting line group close to the second connecting line.

6. The display panel of claim 4, wherein, The power signal line comprises a first part, a second part and a third part connected in sequence along the first direction, the width of the first part and the width of the third part are greater than the width of the second part to form the recess.

7. The display panel of any one of claims 1-6, wherein, The first part and the third part respectively comprise M first sub-traces spaced apart and arranged in parallel, the second part comprises N second sub-traces spaced apart and arranged in parallel, M is greater than N, and the continuous N first sub-traces and the N second sub-traces are connected one by one.

8. The display panel of claim 7, wherein, Each first connecting line further comprises an extension part at the end away from the gate drive circuit, the extension part is connected with the main body part; for different first connecting lines, the sum of the lengths of the main body part and the extension part connected therewith is equal.

9. The display panel of any one of claims 1-6, wherein, The display panel further comprises:

10. The display panel of any one of claims 1-6, wherein, a first capacitance balancing part connected with the second connecting line, the power signal line further has an auxiliary recess, the first capacitance balancing part is located in the area where the auxiliary recess is located in the thickness direction of the display panel; a second capacitance balancing part connected with each bending part, the second capacitance balancing part is located in the area where the recess is located in the thickness direction of the display panel; wherein along the first direction, the sum of the sizes of the bending part and the second capacitance balancing part is equal to the sum of the sizes of the second connecting line and the first capacitance balancing part. The power signal line is adjacent to the gate drive circuit, and the opening of the recess is directed to the gate drive circuit.

11. The display panel of any one of claims 1-6, wherein, ​ 12. The display panel of any one of claims 1-6, wherein, The power signal line comprises a first power sub-signal line and a second power sub-signal line, the first power sub-signal line and the second power sub-signal line are sequentially arranged in a direction away from the clock signal line group; The first power sub-signal line has the recess, and an opening of the recess faces the gate drive circuit, the second power sub-signal line has at least one opposite recess, the opposite recess and the recess are oppositely arranged, and the bending part is also located in a region where the opposite recess is located in a thickness direction of the display panel.

13. A display device comprising: Comprising: The display panel of any one of claims 1-12.

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