Display device

Abstract

A display device is provided. The display device includes: a display panel including a plurality of pixels connected to a plurality of scan lines; a scan driving circuit including a plurality of scan stages respectively corresponding to the plurality of scan lines, in which each of the plurality of scan stages receives the mask signal and the carry signal and outputs a scan signal; and a driving controller that divides the display panel into a first display area and a second display area, controls the scan driving circuit such that the first display area and the second display area operate at different frequencies, and outputs a plurality of start signals provided at different timings. A first scan stage arranged in the first display area among the plurality of scan stages receives a first start signal of the plurality of start signals as a carry signal, and a first scan stage arranged in the second display area among the plurality of scan stages receives a second start signal of the plurality of start signals as a carry signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0101205, filed on August 2, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The disclosed embodiments described herein relate to a display device capable of reducing power consumption. Background Art

[0004] An organic light emitting display device among a plurality of display devices displays an image by using an organic light emitting diode that generates light through recombination of electrons and holes. The organic light emitting display device generally has various desirable characteristics such as fast response speed and low power consumption.

[0005] An organic light emitting display device may include a plurality of pixels connected to a plurality of data lines and a plurality of scan lines. Each of the plurality of pixels generally includes an organic light emitting diode and a circuit unit for controlling the amount of current flowing to the organic light emitting diode. In response to a data signal, the circuit unit controls the amount of current flowing from a first driving voltage through the organic light emitting diode to a second driving voltage. In this case, light of a brightness corresponding to the amount of current flowing through the organic light emitting diode is generated. Summary of the invention

[0006] As display devices are used in various fields, nowadays, a plurality of different images can be simultaneously displayed in one display device. Therefore, in the case of displaying a plurality of images, a technology for reducing power consumption of the display device may be desired.

[0007] Embodiments of the present disclosure provide a display device capable of reducing power consumption.

[0008] According to an embodiment, a display device includes: a display panel including a plurality of pixels connected to a plurality of scan lines, wherein a display area including a first display area and a second display area is defined in the display panel; a scan drive circuit including a plurality of scan stages corresponding to the plurality of scan lines, wherein each of the plurality of scan stages receives a mask signal and a carry signal and outputs a scan signal; and a drive controller that controls the scan drive circuit and outputs a plurality of start signals including a first start signal and a second start signal. In this embodiment, the plurality of pixels include a plurality of first pixels arranged in the first display area and a plurality of second pixels arranged in the second display area. In this embodiment, the plurality of scan stages include a plurality of first scan stages connected to the plurality of first pixels and a plurality of second scan stages connected to the plurality of second pixels. In this embodiment, the first first scan stage among the plurality of first scan stages receives a first start signal as a carry signal from the drive controller, and the first second scan stage among the plurality of second scan stages receives a second start signal as a carry signal from the drive controller.

[0009] In an embodiment, when the scan signal is output from the last scanning stage among the plurality of first scanning stages, the second start signal may be output to the first second scanning stage.

[0010] In an embodiment, a first second display area and a second second display area adjacent to the first second display area may be defined in the second display area, and during the multi-frequency mode, the driving controller may control the first second display area and the second second display area by operating the first second display area and the second second display area at different driving frequencies using a masking signal.

[0011] In an embodiment, the first driving frequency of the first display area may be lower than the first second driving frequencies of the first second display area, and the second second driving frequency of the second second display area may be lower than the first second driving frequencies of the first second display area.

[0012] In an embodiment, during the multi-frequency mode, at least one of the plurality of second scanning stages may mask the scanning signal provided to the plurality of second pixels arranged in the second display area among the plurality of second pixels based on the masking signal.

[0013] In an embodiment, the number of the plurality of start signals may be half of the maximum number of regions operable at driving frequencies different from each other in the display region.

[0014] In an embodiment, when the mask signal provided to the first scanning stage is enabled, the driving controller may disable the first start signal.

[0015] In an embodiment, when the mask signal provided to the first and second scanning stages is enabled, the driving controller may disable the second start signal.

[0016] In an embodiment, when a mask signal provided to a scanning stage among a plurality of scanning stages is enabled, the scanning stage may mask the scanning signal.

[0017] In an embodiment, each of the remaining first scanning levels except the first first scanning level among the plurality of first scanning levels can receive a scanning signal of a previous first scanning level as a carry signal, and each of the remaining second scanning levels except the first second scanning level among the plurality of second scanning levels can receive a scanning signal of a previous second scanning level as a carry signal.

[0018] In an embodiment, the display area may further include a third display area separated from the first display area, the second display area is between the first display area and the third display area, the multiple start signals may further include a third start signal, the multiple pixels may further include a plurality of third pixels arranged in the third display area, the multiple scanning levels may further include a plurality of third scanning levels connected to the plurality of third pixels, and the first third scanning level among the plurality of third scanning levels may receive the third start signal as a carry signal from the driving controller.

[0019] In an embodiment, a first third display area and a second third display area adjacent to the first third display area may be defined in the third display area, and during a multi-frequency mode, a driving controller may control the first third display area and the second third display area by operating the first third display area and the second third display area at different driving frequencies using a masking signal.

[0020] In an embodiment, during the multi-frequency mode, the first display area, the second display area, and the first and third display areas may be operated at the same driving frequency.

[0021] In an embodiment, during the multi-frequency mode, each of the first display area and the second third display area may be operated at a first driving frequency, the second driving frequency of the second display area may be higher than the first driving frequency of the first display area, and the third driving frequency of the first third display area may be lower than the second driving frequency of the second display area.

[0022] According to an embodiment, a display device includes: a display panel including a plurality of pixels connected to a plurality of scan lines, wherein a display area including a first display area and a second display area is defined in the display panel; a scan drive circuit including a plurality of scan stages corresponding to the plurality of scan lines, wherein each of the plurality of scan stages receives a mask signal and a carry signal and outputs a scan signal; and a drive controller. In this embodiment, in a multi-frequency mode, the drive controller divides the display panel into a first display area and a second display area, controls the scan drive circuit so that the first display area and the second display area operate at frequencies different from each other, and outputs a plurality of start signals including a first start signal and a second start signal. In this embodiment, the first start signal and the second start signal may be provided at different timings from each other, a first scan stage arranged in the first display area among the plurality of scan stages may receive the first start signal as a carry signal, and a first scan stage arranged in the second display area among the plurality of scan stages may receive the second start signal as a carry signal.

[0023] In an embodiment, when the scan signal is output from a last scan stage arranged in the first display area among the plurality of scan stages, the second start signal may be output.

[0024] In an embodiment, a first second display area and a second second display area adjacent to the first second display area may be defined in the second display area, and during the multi-frequency mode, the driving controller may control the first second display area and the second second display area by operating the first second display area and the second second display area at different driving frequencies using a masking signal.

[0025] In an embodiment, when the mask signal provided to the first scanning stage arranged in the first display area is enabled, the driving controller may disable the first start signal.

[0026] In an embodiment, when the mask signal provided to the first scanning stage arranged in the second display area is enabled, the driving controller may disable the second start signal.

[0027] In an embodiment, when a mask signal provided to a scanning stage among a plurality of scanning stages is enabled, the scanning stage may mask the scanning signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the embodiments of the present disclosure will become apparent by describing in detail the embodiments of the present disclosure with reference to the attached drawings.

[0029] Figure 1 is a perspective view illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 and Figure 3 is a perspective view of a display device according to an embodiment of the present disclosure.

[0031] Figure 4 is a diagram for describing an operation in one display area in a normal frequency mode according to an embodiment of the present disclosure.

[0032] Figure 5 is a diagram for describing an operation in one display area in a multi-frequency mode according to an embodiment of the present disclosure.

[0033] Figure 6 is a block diagram of a display device according to an embodiment of the present disclosure.

[0034] Figure 7 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0035] Figure 8 It is used to describe the embodiment according to the present disclosure Figure 7 A timing diagram of the operation of a pixel is shown in FIG.

[0036] Fig. 9 It is a diagram showing an embodiment according to the present disclosure Figure 6 0047 is a block diagram of a first driving circuit shown in FIG.

[0037] Fig.10 It is a diagram showing an embodiment according to the present disclosure Figure 6 0047 is a block diagram of a second driving circuit shown in FIG.

[0038] Fig.11 is a block diagram illustrating a first driving circuit and a second driving circuit according to an embodiment of the present disclosure.

[0039] Fig.12 is a block diagram illustrating a plurality of scanning stages and a display area according to an embodiment of the present disclosure.

[0040] Fig.13 is a timing diagram illustrating a scan signal and a mask signal according to an embodiment of the present disclosure.

[0041] Fig.14 is a flow chart illustrating the operation of a scanning stage according to an embodiment of the present disclosure.

[0042] Fig.15 is a block diagram illustrating a plurality of scanning stages and a display area according to an embodiment of the present disclosure.

[0043] Fig.16 is a timing diagram illustrating a scan signal and a mask signal according to an embodiment of the present disclosure.

[0044] Fig.17is a block diagram illustrating a plurality of scanning stages and a display area according to an embodiment of the present disclosure.

[0045] Fig.18 is a timing diagram illustrating a scan signal and a mask signal according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Now, the present invention will be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art.

[0047] In the specification, the expression that a first component (or region, layer, part, portion, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is arranged therebetween.

[0048] Like reference numerals refer to like components. In addition, in the drawings, the thickness, proportion, and size of components are exaggerated for the effectiveness of description of technical contents.

[0049] Although the terms "first", "second", etc. may be used to describe various components, the components should not be interpreted as being limited by the terms. The terms are only used to distinguish one component from another component. For example, a first component may be referred to as a "second component" without departing from the scope and spirit of the present invention, and similarly, a second component may be referred to as a "first component".

[0050] In addition, the terms "under", "below", "on", "above" and the like are used to describe the relationship between components illustrated in the drawings. Conceptually relative terms are described based on directions shown in the drawings.

[0051] The term used herein is only for the purpose of describing a specific embodiment, and is not intended to limit. Unless otherwise clearly indicated in the context, "a", "an", "the" and "at least one" as used herein do not represent the limitation of quantity, and are intended to include both the singular and the plural. Therefore, the reference to "the" element after the reference to "a" element in the claim includes one element and multiple elements. For example, unless otherwise clearly indicated in the context, "element" has the same meaning as the meaning of "at least one element". "At least one (atleast one)" should not be interpreted as being limited to "a" or "an". "Or (or)" means "and / or (and / or)". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will also be understood that the terms “comprise” and / or “comprising” or “include” and / or “including”, when used in the present specification, indicate the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0052] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those generally understood by those of ordinary skill in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined herein.

[0053] The embodiments described herein should not be construed as being limited to the specific zone shapes as illustrated herein, but rather include deviations in shape resulting from, for example, manufacturing. For example, a zone illustrated or described as flat may typically have rough and / or nonlinear features. In addition, illustrated sharp corners may be rounded. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the zones, and are not intended to limit the scope of the claims.

[0054] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 is a perspective view illustrating a display device according to an embodiment of the present disclosure.

[0056] refer to Figure 1, a portable terminal is illustrated as an example of a display device DD according to an embodiment of the present disclosure. The portable terminal may include a tablet, a personal computer (PC), a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a game console, a wristwatch-type electronic device, etc. However, the present disclosure is not limited thereto. For example, in addition to large display devices such as televisions or external billboards, embodiments of the present disclosure may also be used for small and medium-sized display devices such as personal computers, notebook computers, kiosks, car navigation units, and cameras, and it is understood that embodiments of the display device DD may be applied to any other type of display device or electronic device without departing from the teachings herein.

[0057] In an embodiment, if Figure 1 As shown in the figure, the display surface on which the first image IM1, the second image IM2 and the third image IM3 are displayed is parallel to the plane defined by the first direction DR1 and the second direction DR2. The display device DD may include a plurality of areas distinguished from each other on the display surface. The display surface may include a display area DA in which the first image IM1, the second image IM2 and the third image IM3 are displayed and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be referred to as a frame area. In an embodiment, for example, the display area DA may be in the shape of a quadrilateral. The non-display area NDA may surround the display area DA. In an embodiment, although not shown, the display device DD may include a partially bent shape. In such an embodiment, an area of ​​the display area DA may have a bent shape.

[0058] The display area DA of the display device DD may include a first display area DA1, a second display area DA2, and a third display area DA3 sequentially arranged in a direction opposite to the second direction DR2.

[0059] In a specific application, the first image IM1 may be displayed in the first display area DA1, the second image IM2 may be displayed in the second display area DA2, and the third image IM3 may be displayed in the third display area DA3. In an embodiment, for example, the first image IM1 may be a status image, the second image IM2 may be a video, and the third image IM3 may be a video, a still image, or text information with a long change (or refresh) cycle.

[0060] According to an embodiment of the present disclosure, the display device DD may drive the first display area DA1 in which a still image such as a status image is displayed by using a relatively low frequency, may drive the second display area DA2 in which a video is displayed by using a normal frequency, and may drive the third display area DA3 in which a still image is displayed by using a frequency lower than the normal frequency. The display device DD may reduce power consumption by reducing the driving frequency of each of the first display area DA1 and the third display area DA3.

[0061] The size of each of the first to third display areas DA1 to DA3 may be predetermined or may be changed by an application. In an embodiment, the display area DA may be divided into four or more partial display areas, not limited to the first display area DA1, the second display area DA2, and the third display area DA3. The driving frequency of each of the plurality of partial display areas may be determined according to the type of image displayed therein (for example, according to whether the image displayed therein is a still image or a video).

[0062] Figure 2 and Figure 3 is a perspective view of a display device according to an embodiment of the present disclosure. Figure 2 An embodiment of the display device in a state in which the display device is unfolded is shown, and Figure 3 An embodiment of the display device is shown in a state in which the display device is folded.

[0063] refer to Figure 2 and Figure 3 , an embodiment of the display device DD-1 may include a display area DA and a non-display area NDA. The display device DD-1 may display an image through the display area DA. The display area DA may include a plane defined by a first direction DR1 and a second direction DR2 when the display device DD-1 is unfolded. The thickness direction of the display device DD-1 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. The front surface (or upper surface) and the rear surface (or lower surface) of the components constituting the display device DD-1 may be defined relative to the third direction DR3. The non-display area NDA may be referred to as a frame area. In an embodiment, for example, the display area DA may be in the shape of a quadrilateral. The non-display area NDA may surround the display area DA.

[0064] The display area DA may include a first non-folding area NFA1, a folding area FA, and a second non-folding area NFA2. The folding area FA may be bent about a folding axis FX extending in the first direction DR1.

[0065] When the display device DD-1 is folded, the first non-folding area NFA1 and the second non-folding area NFA2 may face each other. Therefore, in a state in which the display device DD-1 is completely folded, the display area DA may not be exposed to the outside, which may be referred to as "folding inward". This is only an example, and the operation of the display device DD-1 is not limited thereto.

[0066] For example, in an embodiment of the present disclosure, when the display device DD-1 is folded, the first non-folding area NFA1 and the second non-folding area NFA2 may be opposite to each other. Therefore, the first non-folding area NFA1 may be exposed to the outside in the folded state, which may be referred to as "outward folding".

[0067] In an embodiment, the display device DD-1 may be configured to operate in a manner of folding inward or outward. Alternatively, the display device DD-1 may be configured to operate in both a manner of folding inward and folding outward. In an embodiment, the same area of ​​the display device DD-1 (e.g., the folding area FA) may be folded inward or outward (or may be folded inward and outward). Alternatively, a partial area of ​​the display device DD-1 may be folded inward, and the remaining area of ​​the display device DD-1 may be folded outward.

[0068] exist Figure 2 and Figure 3 , an embodiment in which a single folding area (e.g., folding area FA) and two non-folding areas (e.g., first non-folding area NFA1 and second non-folding area NFA2) are defined is illustrated as an example, but the number of folding areas and the number of non-folding areas are not limited thereto. In an embodiment, for example, the display device DD-1 may include a plurality of non-folding areas whose number is greater than 2 and a plurality of folding areas, and each of the plurality of folding areas may be between non-folding areas adjacent to each other among the plurality of non-folding areas.

[0069] exist Figure 2 and Figure 3 , an embodiment in which the folding axis FX is parallel to the short axis of the display device DD-1 is illustrated as an example, but the present disclosure is not limited thereto. In an embodiment, for example, the folding axis FX may extend in a direction (e.g., the second direction DR2) parallel to the long axis of the display device DD-1. In such an embodiment, the first non-folding area NFA1, the folding area FA, and the second non-folding area NFA2 may be sequentially arranged in the first direction DR1.

[0070] The display area DA of the display device DD-1 may include a plurality of partial display areas. Figure 2 2A and 2B illustrate an embodiment in which three partial display areas are defined as an example, but the number of partial display areas defined in the display area DA is not limited thereto.

[0071] The plurality of partial display areas may include a first display area DA1, a second display area DA2, and a third display area DA3. In an embodiment, for example, the first display area DA1 may be an area in which a first image IM1 is displayed, the second display area DA2 may be an area in which a second image IM2 is displayed, and the third display area DA3 may be an area in which a third image IM3 is displayed. In an embodiment, for example, the first image IM1 may be a state image, the second image IM2 may be a video, and the third image IM3 may be a video, a still image, or an image with a long change cycle (e.g., text information).

[0072] The size of each of the first to third display areas DA1 to DA3 may be predetermined or may be changed through an application program.

[0073] In an embodiment, the first display area DA1 and the second display area DA2 may correspond to the first non-folding area NFA1, and the third display area DA3 may correspond to the second non-folding area NFA2. In an embodiment, the first portion of the folding area FA may correspond to the second display area DA2, and the second portion of the folding area FA may correspond to the third display area DA3.

[0074] In an embodiment, the entire folding area FA may correspond to only one of the second display area DA2 and the third display area DA3.

[0075] In an embodiment, if Figure 3 As shown in FIG. 1 , when the folding area FA is folded, the first display area DA1 and the second display area DA2 may correspond to the first non-folding area NFA1 , and the third display area DA3 may correspond to the folding area FA and the second non-folding area NFA2 .

[0076] exist Figure 2 and Figure 3 , an embodiment in which the display device DD-1 has a single folding area is illustrated as an example of an electronic device, but the present disclosure is not limited thereto. In an embodiment, for example, the present disclosure may be applied to an electronic device having two or more folding areas, a rollable electronic device, or a slidable electronic device.

[0077] In the following, for the convenience of description, Figure 1 The embodiment of the display device DD illustrated in FIG. 1 will be described as an example, but the description given with reference to the display device DD can be equally applied to Figure 2 and Figure 3 Display device DD-1 shown in the figure.

[0078] Figure 4is a diagram for describing an operation in one display area in a normal frequency mode according to an embodiment of the present disclosure, and Figure 5 is a diagram for describing an operation in one display area in a multi-frequency mode according to an embodiment of the present disclosure.

[0079] refer to Figure 1 , Figure 4 and Figure 5 , the display area DA-1 may be one of the first display area DA1, the second display area DA2, and the third display area DA3.

[0080] The display area DA-1 may include a first sub display area AA1 and a second sub display area AA2. The first sub display area AA1 may be a portion of the display area DA-1, and the second sub display area AA2 may be the remaining portion of the display area DA-1.

[0081] The display area DA-1 according to an embodiment may be operated differently according to an operation mode. The operation mode may include a normal frequency mode NFM and a multi-frequency mode MFM (or one of the normal frequency mode NFM and the multi-frequency mode MFM). During the normal frequency mode NFM, the display device DD may drive the first sub-display area AA1 and the second sub-display area AA2 of one display area DA-1 at a normal frequency. In an embodiment, during the multi-frequency mode MFM, the display device DD may drive the first sub-display area AA1 of the display area DA-1 in which the first image IM1-1 is displayed by using a first driving frequency, and may drive the second sub-display area AA2 of the display area DA-1 in which the second image IM2-1 is displayed by a second driving frequency lower than the normal frequency. In an embodiment, the first driving frequency may be the same as the normal frequency.

[0082] In an embodiment, for example, the first image IM1-1 displayed in the first sub display area AA1 may be a video, and the second image IM2-1 displayed in the second sub display area AA2 may be a still image or an image with a long change cycle (e.g., a game control keyboard).

[0083] In the normal frequency mode NFM, the driving frequency of the first sub display area AA1 and the second sub display area AA2 of the display device DD may be a normal frequency. In an embodiment, for example, the normal frequency may be 120 Hz. In the normal frequency mode NFM, images of the first frame F1 to the 120th frame F120 may be displayed in each of the first sub display area AA1 and the second sub display area AA2 of the display device DD for 1 second. However, this is provided as an example, and the normal frequency according to an embodiment of the present disclosure may be determined differently. In an embodiment, for example, the normal frequency may be 60 Hz.

[0084] In the multi-frequency mode MFM, the display device DD may set the driving frequency of the first sub-display area AA1 in which the first image IM1-1 (i.e., video) is displayed to the first driving frequency, and may set the driving frequency of the second sub-display area AA2 in which the second image IM2-1 (i.e., still image) is displayed to the second driving frequency lower than the first driving frequency. The normal frequency may be the same as the first driving frequency. In an embodiment, for example, the first driving frequency may be 120 Hz, and the second driving frequency may be 1 Hz. The first driving frequency and the second driving frequency may be variously changed. In an embodiment, for example, the first driving frequency may be 144 Hz higher than the normal frequency, or may be the same as the normal frequency, that is, may be 120 Hz. In an embodiment, for example, the second driving frequency may be one of 30 Hz, 10 Hz, and 1 Hz lower than the normal frequency.

[0085] In the multi-frequency mode MFM, when the first driving frequency is 120 Hz and the second driving frequency is 1 Hz, within 1 second, the first image IM1-1 corresponding to each of the first frame F1 to the 120th frame F120 may be displayed in the first sub display area AA1 of the display device DD. Only the second image IM2-1 corresponding to the first frame F1 may be displayed in the second sub display area AA2, and the image corresponding to each of the second frame F2 to the 120th frame F120 may not be displayed in the second sub display area AA2. The operation of the display device DD for driving the display area DA-1 in the multi-frequency mode MFM will be described later.

[0086] Figure 6 is a block diagram of a display device according to an embodiment of the present disclosure.

[0087] refer to Figure 6 , an embodiment of the display device DD may include a display panel DP, a driving controller 100 , a data driving circuit 200 , a first driving circuit 300 , a second driving circuit 400 , and a voltage generator 500 .

[0088] The display panel DP according to an embodiment of the present disclosure may be a light-emitting display panel, but the present disclosure is not limited thereto. In an embodiment, for example, the display panel DP may be an organic light-emitting display panel, a quantum dot display panel, a micro light-emitting diode (LED) display panel, or a nano LED display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the quantum dot display panel may include quantum dots, quantum rods, etc. The emission layer of the micro LED display panel may include micro LEDs. The emission layer of the nano LED display panel may include nano LEDs. Hereinafter, for the convenience of description, an embodiment in which the display panel DP is an organic light-emitting display panel will be described. The display area DA and the non-display area NDA adjacent to the display area DA may be defined in the display panel DP.

[0089] In an embodiment, the driving controller 100 may receive an input signal including an image signal RGB and a control signal CTRL. The driving controller 100 may convert the data format of the image signal RGB by conforming to the specification of the interface with the data driving circuit 200, and generate an image data signal DATA. The driving controller 100 may control the data driving circuit 200, the first driving circuit 300, and the second driving circuit 400 so that an image is displayed in the display panel DP. The driving controller 100 may output a first scanning control signal SCS1, a second scanning control signal SCS2, and a data control signal DCS.

[0090] The driving controller 100 may output a plurality of start signals FLM to the first driving circuit 300 and the second driving circuit 400. The driving controller 100 may also be referred to as a "timing controller".

[0091] The data driving circuit 200 may receive a data control signal DCS and an image data signal DATA from the driving controller 100. The data driving circuit 200 may convert the image data signal DATA into a data signal, and may output the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal may refer to an analog voltage corresponding to a grayscale value of the image data signal DATA.

[0092] The voltage generator 500 may generate voltages for operation of the display panel DP. The voltage generator 500 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0093] The display panel DP may include scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. The first drive circuit 300 may be arranged on a first side of the display panel DP, and the second drive circuit 400 may be arranged on a second side of the display panel DP. The scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1 and the emission control lines EML1 to EMLn may be electrically connected to the first drive circuit 300 and the second drive circuit 400, wherein n and m may be natural numbers greater than 0.

[0094] The scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1 and the emission control lines EML1 to EMLn may be arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm may extend from the data driving circuit 200 in a direction opposite to the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1.

[0095] In an embodiment, if Figure 6 , the first driving circuit 300 and the second driving circuit 400 are arranged to face each other with the pixel PX interposed therebetween. However, the present disclosure is not limited thereto. In an embodiment, for example, the display device DD may include only one of the first driving circuit 300 and the second driving circuit 400.

[0096] The plurality of pixels PX may be electrically connected to scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, emission control lines EML1 to EMLn, and data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines and one emission control line. In an embodiment, for example, Figure 6 , the pixels PX belonging to the first row may be electrically connected to the scan lines GIL1, GCL1, GWL1, and GWL2 and the emission control line EML1. In this embodiment, the pixels PX belonging to the jth row may be electrically connected to the scan lines GILj, GCLj, GWLj, and GWLj+1 and the emission control line EMLj, where j may be a natural number greater than 0.

[0097] Each of the plurality of pixels PX may receive a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0098] The first driving circuit 300 may receive a first scan control signal SCS1 from the driving controller 100. In response to the first scan control signal SCS1, the first driving circuit 300 may output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 and GWLn+1, and may output emission signals to the emission control lines EML1 to EMLn.

[0099] The second driving circuit 400 may receive a second scan control signal SCS2 from the driving controller 100. In response to the second scan control signal SCS2, the second driving circuit 400 may output scan signals to the scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, and may output emission signals to the emission control lines EML1 to EMLn.

[0100] The driving controller 100 may divide the display panel DP into a first display area DA1, a second display area DA2, and a third display area DA3 (refer to FIG. 1 ) based on input signals including the image signal RGB and the control signal CTRL. Figure 1 ), the first display area DA1, the second display area DA2 and the third display area DA3 (reference Figure 1 ) is divided into a first sub-display area AA1 (reference Figure 4 ) and the second sub-display area AA2 (reference Figure 4 ), and the first sub display area AA1 (reference Figure 4 ) and the second sub-display area AA2 (reference Figure 4 ) in each of the driving frequencies.

[0101] In an embodiment, for example, in normal frequency mode NFM (refer to Figure 4 ), the driving controller 100 may drive the first display area DA1, the second display area DA2 and the third display area DA3 at a normal frequency (eg, 120 Hz) (refer to Figure 1 ) in each of the first sub display areas AA1 (reference Figure 4 ) and the second sub-display area AA2 (reference Figure 4 In this embodiment, in the multi-frequency mode MFM (refer to Figure 5 ), the driving controller 100 may output a first scanning control signal SCS1, a second scanning control signal SCS2, and a data control signal DCS, the first scanning control signal SCS1, the second scanning control signal SCS2, and the data control signal DCS being used to drive the first display area DA1, the second display area DA2, and the third display area DA3 at a first driving frequency (e.g., 120 Hz) (reference Figure 1 ) in at least one of the first sub-display areas AA1 (reference Figure 5 ); and driving the first display area DA1, the second display area DA2 and the third display area DA3 at a second driving frequency (eg, 1 Hz) (reference Figure 1 ) in at least one of the second sub-display areas AA2 (reference Figure 5 ). This will be described in detail later.

[0102] Figure 7 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0103] exist Figure 7 The diagram shows the data lines DL1 to DLm (refer to Figure 6 ) in the data line DLi (i-th), the scanning lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1 (reference Figure 6 ) and the scanning lines GILj, GCLj, GWLj (jth) and GWLj+1 (j+1th) and the emission control lines EML1 to EMLn (reference Figure 6 ) is taken as an example, where i and j may be natural numbers greater than 0.

[0104] Figure 6 Each of the plurality of pixels PX illustrated in FIG. Figure 7 The circuit configuration of the equivalent circuit diagram of the pixel PXij illustrated in FIG.

[0105] Each of the plurality of pixels PX may include a light emitting diode ED and a pixel circuit unit PXC for controlling emission of the light emitting diode ED. The pixel circuit unit PXC may include one or more transistors and one or more capacitors. The first driving circuit 300 and the second driving circuit 400 may include transistors formed by the same process as that of the pixel circuit unit PXC.

[0106] In the pixel circuit unit PXC of the pixel PXij, each of the third transistor T3 and the fourth transistor T4 among the first transistor T1 to the seventh transistor T7 is an N-type transistor including an oxide semiconductor layer, and each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 is a P-type transistor including a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited to this. In an embodiment, for example, the first transistor T1 to the seventh transistor T7 may all be P-type transistors or N-type transistors. In an embodiment, at least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor, and the remaining transistors may be P-type transistors. In addition, the circuit configuration of the pixel PX according to an embodiment of the present disclosure is not limited to Figure 7 . Figure 7 The pixel circuit unit PXC illustrated in FIG. 1 is provided only as an example, and the configuration of the pixel circuit unit PXC may be modified and implemented.

[0107] refer to Figure 7 , a pixel PXij of a display device DD according to an embodiment may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a capacitor Cst, and at least one light emitting diode ED. In an embodiment, an example in which one pixel PXij includes a single light emitting diode ED will be described.

[0108] In an embodiment, the scan lines GILj, GCLj, GWLj, and GWLj+1 may transmit scan signals GIj, GCj, GWj, and GWj+1, respectively, and the emission control line EMLj may transmit an emission signal EMj. The data line DLi transmits a data signal Di. The data signal Di may have a signal similar to that input to the display device DD (reference signal). Figure 6 ) The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3 and the fourth driving voltage line VL4 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1 and the second initialization voltage VINT2 respectively.

[0109] The first transistor T1 may include a first electrode connected to the first driving voltage line VL1 through a fifth transistor T5, a second electrode electrically connected to the anode of the light emitting diode ED through a sixth transistor T6, and a gate electrode connected to a first end of the capacitor Cst. The first transistor T1 may receive a data signal Di transmitted through the data line DLi according to a switching operation of the second transistor T2, and may supply a driving current Id to the light emitting diode ED.

[0110] The second transistor T2 may include a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GWLj. The second transistor T2 may be turned on according to a scan signal GWj transmitted through the scan line GWLj (or in response to the scan signal GWj having a turn-on level), and may transmit a data signal Di from the data line DLi to the first electrode of the first transistor T1.

[0111] The third transistor T3 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line GCLj. The third transistor T3 may be turned on according to the scan signal GCj transmitted through the scan line GCLj (or in response to the scan signal GCj having a turn-on level), and therefore, the gate electrode and the second electrode of the first transistor T1 may be connected to each other, that is, the first transistor T1 may be diode-connected.

[0112] The fourth transistor T4 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third driving voltage line VL3 through which the first initialization voltage VINT1 is transmitted, and a gate electrode connected to the scan line GILj. The fourth transistor T4 may be turned on according to the scan signal GIj transmitted through the scan line GILj (or in response to the scan signal GIj having a turn-on level), and therefore, the first initialization voltage VINT1 may be transmitted to the gate electrode of the first transistor T1. Thus, the voltage of the gate electrode of the first transistor T1 may be initialized. This operation may be referred to as an "initialization operation".

[0113] The fifth transistor T5 may include a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emission control line EMLj.

[0114] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting diode ED, and a gate electrode connected to the emission control line EMLj.

[0115] The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on according to the emission signal EMj transmitted through the emission control line EMLj (or in response to the emission signal EMj having a turn-on level). Therefore, the first driving voltage ELVDD may be compensated by the diode-connected first transistor T1 to be supplied to the light emitting diode ED.

[0116] The seventh transistor T7 may include a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth driving voltage line VL4, and a gate electrode connected to the scan line GWLj+1. The seventh transistor T7 may be turned on according to the scan signal GWj+1 transmitted through the scan line GWLj+1 (or in response to the scan signal GWj+1 having a turn-on level), and may bypass a portion of the current of the anode of the light emitting diode ED (i.e., a portion of the driving current Id) to the fourth driving voltage line VL4 when turned on.

[0117] As described above, the first end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the second end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting diode ED may be connected to the second driving voltage line VL2 through which the second driving voltage ELVSS is supplied. The structure of the pixel PXij according to the embodiment is not limited to Figure 7 For example, in one pixel PX, the number of transistors, the number of capacitors, and their connection relationships may be variously modified.

[0118] Figure 8 It is used to describe the embodiment according to the present disclosure Figure 7 A timing diagram of the operation of a pixel is shown in FIG.

[0119] refer to Figure 7 and Figure 8 In an embodiment, a high-level scan signal GIj may be provided through the scan line GILj during an initialization period in one frame Fs. When the fourth transistor T4 is turned on in response to the high-level scan signal GIj, the first initialization voltage VINT1 may be transmitted to the gate electrode of the first transistor T1 through the fourth transistor T4, so that the first transistor T1 is initialized.

[0120] Next, when a high-level scan signal GCj is supplied through the scan line GCLj during the data programming and compensation period, the third transistor T3 may be turned on. The first transistor T1 may be diode-connected by the third transistor T3 to be turned on, and may be forward biased. In addition, the second transistor T2 may be turned on by the scan signal GWj having a low level. In this case, a compensation voltage obtained by subtracting a threshold voltage of the first transistor T1 from a voltage of the data signal Di supplied from the data line DLi may be applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 may be the compensation voltage.

[0121] The first driving voltage ELVDD and the compensation voltage may be applied to opposite ends of the capacitor Cst, respectively, and charges corresponding to a voltage difference of the opposite ends of the capacitor Cst may be stored in the capacitor Cst.

[0122] In an embodiment, the seventh transistor T7 may be turned on in response to a low-level scan signal GWj+1 transmitted through the scan line GWLj+1. When the seventh transistor T7 is turned on, a portion of the driving current Id may be discharged through the seventh transistor T7 as a bypass current Ibp.

[0123] In the case where the light emitting diode ED emits light under the condition that the minimum current of the first transistor T1 flows as the driving current Id for the purpose of displaying a black image, a black image may not be displayed normally. In an embodiment of the present disclosure, the seventh transistor T7 of the pixel PXij may allocate a portion of the minimum current of the first transistor T1 to a current path different from the current path to the light emitting diode ED as a bypass current Ibp. In this article, the minimum current of the first transistor T1 may mean a current that flows under the condition that the gate-source voltage of the first transistor T1 is less than the threshold voltage (i.e., under the condition that the first transistor T1 is turned off). When the minimum driving current (e.g., a current of 10 picoamperes (pA) or less) is transmitted to the light emitting diode ED, an image of black brightness may be presented in a state in which the first transistor T1 is turned off. When the minimum driving current for displaying a black image flows, the influence of the bypass transmission of the bypass current Ibp may be large; on the contrary, when a large driving current for displaying an image such as a normal image or a white image flows, there may be almost no influence of the bypass current Ibp. Therefore, when the driving current Id for displaying a black image flows, the light emitting current Ied of the light emitting diode ED corresponding to the result of subtracting the bypass current Ibp discharged by the seventh transistor T7 from the driving current Id can have a minimum current amount to such an extent that a black image is accurately represented. Therefore, the contrast ratio can be improved by accurately realizing an image of black brightness using the seventh transistor T7. In an embodiment, the bypass signal is a low-level scanning signal GWj+1, but it is not necessarily limited thereto.

[0124] Then, during the emission period, the emission signal EMj supplied from the emission control line EMLj may be changed from a high level to a low level. During the emission period, the fifth transistor T5 and the sixth transistor T6 may be turned on by the emission signal EMj having a low level. In this case, the driving current Id may be generated based on the difference between the gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD, and may be supplied to the light emitting diode ED through the sixth transistor T6. That is, the light emitting current Ied may flow through the light emitting diode ED.

[0125] Fig. 9 It is a diagram showing an embodiment according to the present disclosure Figure 6 0047 is a block diagram of a first driving circuit shown in FIG.

[0126] refer to Figure 6 and Fig. 9 In an implementation, the first driving circuit 300 may include an emission driving circuit 310 , a first scan driving circuit 320 , a second scan driving circuit 330 , and a third scan driving circuit 340 .

[0127] The emission driving circuit 310 may output emission signals EM1 to EMk to be provided to the emission control lines EML1 to EMLn in response to the first scan control signal SCS1. In an embodiment, n may be greater than k, that is, n>k, where k is a natural number greater than 0. That is, each of the emission signals EM1 to EMk may be provided to two or more corresponding emission control lines among the emission control lines EML1 to EMLn.

[0128] The first scan driving circuit 320 may output scan signals GI1 to GIk to be provided to the scan lines GIL1 to GILn in response to the first scan control signal SCS1. In an embodiment, n may be greater than k, that is, n>k, where k is a natural number greater than 0. That is, each of the scan signals GI1 to GIk may be provided to two or more corresponding scan lines among the scan lines GIL1 to GILn.

[0129] The second scan driving circuit 330 may output scan signals GC1 to GCs to be provided to the scan lines GCL1 to GCLn in response to the first scan control signal SCS1. In an embodiment, n may be greater than s, that is, n>s, where s is a natural number greater than 0. That is, each of the scan signals GC1 to GCs may be provided to two or more corresponding scan lines among the scan lines GCL1 to GCLn.

[0130] The third scan driving circuit 340 may output scan signals GW1 to GWn+1 to be provided to the scan lines GWL1 to GWLn+1 in response to the first scan control signal SCS1.

[0131] Fig.10 It is a diagram showing an embodiment according to the present disclosure Figure 6 0047 is a block diagram of a second driving circuit shown in FIG.

[0132] refer to Figure 6 and Fig.10 In an implementation, the second driving circuit 400 may include an emission driving circuit 410 , a first scan driving circuit 420 , a second scan driving circuit 430 , and a third scan driving circuit 440 .

[0133] The emission driving circuit 410 may output emission signals EM1 to EMk to be provided to the emission control lines EML1 to EMLn in response to the second scan control signal SCS2. In an embodiment, n may be greater than k, ie, n>k, where k is a natural number greater than 0.

[0134] The first scan driving circuit 420 may output scan signals GI1 to GIk to be provided to the scan lines GIL1 to GILn in response to the second scan control signal SCS2. In an embodiment, n may be greater than k, ie, n>k, where k is a natural number greater than 0.

[0135] The second scan driving circuit 430 may output scan signals GC1 to GCs to be provided to the scan lines GCL1 to GCLn in response to the second scan control signal SCS2. In an embodiment, n may be greater than s, ie, n>s, where s is a natural number greater than 0.

[0136] The third scan driving circuit 440 may output scan signals GW1 to GWn+1 to be provided to the scan lines GWL1 to GWLn+1 in response to the second scan control signal SCS2.

[0137] Fig.11 is a block diagram illustrating a first driving circuit and a second driving circuit according to an embodiment of the present disclosure.

[0138] refer to Figures 9 to 11 , pixels PX11 to PX14, PX21 to PX24, PX31 to PX34, PX41 to PX44, PX51 to PX54, PX61 to PX64, PX71 to PX74 and PX81 to PX84 (with Figure 6 The pixels PX in the display area DA may be arranged in the display area DA.

[0139] For the convenience of illustration and description, Fig.11 , an example of a display area DA in which the pixels PX are arranged in a matrix having eight rows and four columns (or in a matrix in which four pixels PX are arranged in a first direction DR1 for each row and eight pixels PX are arranged in a second direction DR2 for each column) is illustrated, but the number of pixels PX included in the display panel DP may be changed or modified differently.

[0140] Pixels PX11, PX23, PX31, PX43, PX51, PX63, PX71 and PX83 may be first color pixels (e.g., red pixels); pixels PX13, PX21, PX33, PX41, PX53, PX61, PX73 and PX81 may be second color pixels (e.g., blue pixels); and the remaining pixels PX12, PX14, PX22, PX24, PX32, PX34, PX42, PX44, PX52, PX54, PX62, PX64, PX72, PX74, PX82 and PX84 may be third color pixels (e.g., green pixels).

[0141] The emission driving circuit 310 in the first driving circuit 300 includes emission stages EMD1 and EMD2. The first scanning driving circuit 320 in the first driving circuit 300 includes first scanning stages GID1 and GID2. The second scanning driving circuit 330 in the first driving circuit 300 includes second scanning stages GCD1 to GCD4. The third scanning driving circuit 340 in the first driving circuit 300 includes third scanning stages GWD1 to GWD8.

[0142] Each of the emission stages EMD1 and EMD2 may drive four rows of pixels PX11 to PX14, PX21 to PX24, PX31 to PX34, PX41 to PX44, PX51 to PX54, PX61 to PX64, PX71 to PX74, and PX81 to PX84.

[0143] Each of the first scanning stages GID1 and GID2 may drive four rows of pixels PX11 to PX14 , PX21 to PX24 , PX31 to PX34 , PX41 to PX44 , PX51 to PX54 , PX61 to PX64 , PX71 to PX74 , and PX81 to PX84 .

[0144] Each of the second scanning stages GCD1 to GCD4 may drive two rows of pixels PX11 to PX14 , PX21 to PX24 , PX31 to PX34 , PX41 to PX44 , PX51 to PX54 , PX61 to PX64 , PX71 to PX74 , and PX81 to PX84 .

[0145] Each of the third scanning stages GWD1 to GWD8 may drive one row of pixels PX11 to PX14 , PX21 to PX24 , PX31 to PX34 , PX41 to PX44 , PX51 to PX54 , PX61 to PX64 , PX71 to PX74 , and PX81 to PX84 .

[0146] In an embodiment, a plurality of lengths in the second direction DR2 of a plurality of circuit regions in which the emitting stages EMD1 and EMD2, the first scanning stages GID1 and GID2, and the second scanning stages GCD1 to GCD4 are respectively arranged may be substantially consistent with each other. In an embodiment, a plurality of sizes (e.g., plane areas) of a plurality of circuit regions in which the emitting stages EMD1 and EMD2, the first scanning stages GID1 and GID2, and the second scanning stages GCD1 to GCD4 are respectively arranged may be substantially consistent with each other.

[0147] In an embodiment, the length of the circuit area occupied by the third scanning levels GWD1 to GWD8 in the second direction DR2 may be half the length of the circuit area occupied by the second scanning levels GCD1 to GCD4 in the second direction DR2. In an embodiment, the size of each of the plurality of circuit areas in which the third scanning levels GWD1 to GWD8 are respectively arranged may be smaller than the size of each of the plurality of circuit areas in which the emission levels EMD1 and EMD2, the first scanning levels GID1 and GID2, and the second scanning levels GCD1 to GCD4 are respectively arranged.

[0148] The emission driving circuit 410 in the second driving circuit 400 includes emission stages EMS1 and EMS2. The first scanning driving circuit 420 in the second driving circuit 400 includes first scanning stages GIS1 and GIS2. The second scanning driving circuit 430 in the second driving circuit 400 includes second scanning stages GCS1 to GCS4. The third scanning driving circuit 440 in the second driving circuit 400 includes third scanning stages GWS1 to GWS8.

[0149] Each of the emission stages EMS1 and EMS2 may drive four rows of pixels PX11 to PX14 , PX21 to PX24 , PX31 to PX34 , PX41 to PX44 , PX51 to PX54 , PX61 to PX64 , PX71 to PX74 , and PX81 to PX84 .

[0150] Each of the first scanning stages GIS1 and GIS2 may drive four rows of pixels PX11 to PX14 , PX21 to PX24 , PX31 to PX34 , PX41 to PX44 , PX51 to PX54 , PX61 to PX64 , PX71 to PX74 , and PX81 to PX84 .

[0151] Each of the second scanning stages GCS1 to GCS4 may drive two rows of pixels PX11 to PX14 , PX21 to PX24 , PX31 to PX34 , PX41 to PX44 , PX51 to PX54 , PX61 to PX64 , PX71 to PX74 , and PX81 to PX84 .

[0152] Each of the third scanning stages GWS1 to GWS8 may drive one row of pixels PX11 to PX14 , PX21 to PX24 , PX31 to PX34 , PX41 to PX44 , PX51 to PX54 , PX61 to PX64 , PX71 to PX74 , and PX81 to PX84 .

[0153] In an embodiment, a plurality of lengths in the second direction DR2 of a plurality of circuit regions in which the emitting stages EMS1 and EMS2, the first scanning stages GIS1 and GIS2, and the second scanning stages GCS1 to GCS4 are respectively arranged may be substantially consistent with each other. In an embodiment, a plurality of sizes of circuit regions in which the emitting stages EMS1 and EMS2, the first scanning stages GIS1 and GIS2, and the second scanning stages GCS1 to GCS4 are respectively arranged may be substantially consistent with each other.

[0154] The length of the circuit area occupied by the third scanning stages GWS1 to GWS8 in the second direction DR2 may be half the length of the circuit area occupied by the second scanning stages GCS1 to GCS4 in the second direction DR2.

[0155] A size of each of the plurality of circuit areas in which the third scanning stages GWS1 to GWS8 are respectively arranged may be smaller than a size of each of the plurality of circuit areas in which the emission stages EMS1 and EMS2 , the first scanning stages GIS1 and GIS2 , and the second scanning stages GCS1 to GCS4 are respectively arranged.

[0156] In an embodiment, if Fig.11 As shown in FIG. 1 , the first scanning stages GID1 and GID2 and the second scanning stages GCD1 to GCD4 may be implemented by independent circuits. In this embodiment, the first scanning stages GIS1 and GIS2 and the second scanning stages GCS1 to GCS4 may be implemented by independent circuits.

[0157] Fig.12 is a block diagram illustrating a plurality of scanning stages and a display area according to an embodiment of the present disclosure, Fig.13 is a timing diagram illustrating a scan signal and a mask signal according to an embodiment of the present disclosure, and Fig.14 is a flow chart illustrating the operation of a scanning stage according to an embodiment of the present disclosure.

[0158] refer to Figure 1 , Figure 6 as well as Figures 11 to 14 In an embodiment, the display panel DP may be operated in units of frames. The driving controller 100 may determine the driving frequency of the display panel DP by each of the plurality of frames. In an embodiment, 120 frames may be provided within 1 second. The plurality of frames may include a first frame FR1, a second frame FR2, and a third frame FR3 provided sequentially.

[0159] Each of the first scanning stages GID1 and GID2 and the second scanning stages GCD1 to GCD4 in the first driving circuit 300 and the first scanning stages GIS1 and GIS2 and the second scanning stages GCS1 to GCS4 in the second driving circuit 400 may include a plurality of scanning stages ST.

[0160] The plurality of pixels PX may include a plurality of first pixels PX1 arranged in the first display area DA1 , a plurality of second pixels PX2 arranged in the second display area DA2 , and a plurality of third pixels PX3 arranged in the third display area DA3 .

[0161] The plurality of scan stages ST may correspond to and be connected to the plurality of scan lines GIL1 to GILn and GCL1 to GCLn, respectively.

[0162] The plurality of scanning stages ST may include a plurality of first scanning stages, a plurality of second scanning stages, and a plurality of third scanning stages.

[0163] The plurality of first scanning stages may be connected to the plurality of first pixels PX1, respectively. The plurality of first scanning stages may correspond to the first display area DA1 and may output scanning signals SS1 and SS2, respectively. Each of the scanning signals SS1 and SS2 may be one of the scanning signals GIj and GCj.

[0164] Each of the plurality of first scan stages may receive the carry signal CRY and the first mask signal MFD_EN1 .

[0165] When the first masking signal MFD_EN1 is enabled, the plurality of first scan stages may respectively mask the scan signals SS1 and SS2. Masking of the scan signals SS1 and SS2 may mean that the scan signals SS1 and SS2 are output in a disabled state.

[0166] The plurality of first scanning stages may include a first first scanning stage ST10 and a second first scanning stage ST11. Fig.12 , two first scanning levels are illustrated as an example of the plurality of first scanning levels, but the number of first scanning levels according to an embodiment of the present disclosure is not limited thereto. In an embodiment, for example, the number of first scanning levels may be determined according to the first display area DA1.

[0167] The start signal FLM output from the driving controller 100 may include a first start signal FLM1 , a second start signal FLM2 , and a third start signal FLM3 .

[0168] The first first scanning stage ST10 among the plurality of first scanning stages may receive the first start signal FLM1 as the carry signal CRY from the driving controller 100 .

[0169] The first scanning stage ST10 may output a scanning signal SS1.

[0170] Each of the remaining first scanning stages except the first first scanning stage ST10 among the plurality of first scanning stages may receive a scanning signal of a previous first scanning stage as the carry signal CRY.

[0171] The second first scanning stage ST11 may receive the scan signal SS1 output from the first first scanning stage ST10 as the carry signal CRY.

[0172] The second first scanning stage ST11 may output a scanning signal SS2 .

[0173] In an embodiment of the present disclosure, the driving frequency of the first display area DA1 may be 1 Hz.

[0174] During the first frame FR1, the first first scanning stage ST10 may receive the first start signal FLM1. The first first scanning stage ST10 may output the scanning signal SS1 in response to the first start signal FLM1.

[0175] The second first scanning stage ST11 may receive the scan signal SS1 as the carry signal CRY. The second first scanning stage ST11 may output the scan signal SS2 in response to the scan signal SS1.

[0176] That is, during the first frame FR1, the first image IM1 may be displayed in the first display area DA1.

[0177] After the first frame FR1, during the second frame FR2, the driving controller 100 may drive the first display area DA1 at a driving frequency of 1 Hz. In this case, the first masking signal MFD_EN1 may be enabled (S100).

[0178] During the time period PD11 corresponding to the first display area DA1 in the second frame FR2 , the first masking signal MFD_EN1 may be enabled.

[0179] In an implementation, the driving controller 100 may enable the first masking signal MFD_EN1 provided to the first scanning stage ST10 to drive the entire first display area DA1 at 1 Hz.

[0180] The scanning stage in which the first masking signal MFD_EN1 is enabled may be the first first scanning stage ST10 receiving the first start signal FLM1 (S200). In this case, the driving controller 100 may mask the first start signal FLM1 (S300). That is, the first start signal FLM1 may be disabled and may be provided to the first first scanning stage ST10.

[0181] After the second frame FR2 , during the third frame FR3 , the driving controller 100 may enable the first masking signal MFD_EN1 for the purpose of driving the first display area DA1 by using a driving frequency of 1 Hz ( S100 ).

[0182] During the time period PD12 corresponding to the first display area DA1 of the third frame FR3 , the first masking signal MFD_EN1 may be enabled.

[0183] In an embodiment, the driving controller 100 may enable the first masking signal MFD_EN1 provided to the first scanning stage ST10 , which is the foremost first scanning stage among the plurality of first scanning stages, to drive the entire first display area DA1 at 1 Hz.

[0184] The scanning stage in which the first masking signal MFD_EN1 is enabled may be the first first scanning stage ST10 receiving the first start signal FLM1 (S200). In this case, the driving controller 100 may mask the first start signal FLM1 (S300). That is, the first start signal FLM1 may be disabled and may be provided to the first first scanning stage ST10.

[0185] That is, the first image IM1 may be displayed in the first display area DA1 only in the first frame FR1, and the first image IM1 may not be displayed in the remaining second frame FR2 and third frame FR3. The first image IM1 may be a state image indicating state information having a long change cycle. In an embodiment, for example, the first image IM1 may be displayed only in the first frame FR1 among 120 frames (e.g., the first frame FR1, the second frame FR2, the third frame FR3, etc.) provided within 1 second; in the remaining frames, the first display area DA1 in which the first image IM1 is not displayed may be driven substantially at a driving frequency of 1 Hz.

[0186] According to an embodiment of the present disclosure, the driving controller 100 may drive the first display area DA1 in which the first image IM1 having a long variation period is displayed at a driving frequency lower than the driving frequency of the display area DA in which the video is displayed. Since the display device DD makes the driving frequency of the first display area DA1 low, during the time period in which the first image IM1 is not displayed, the display device DD may not generate the image data signal DATA and may not perform the compensation process. In addition, in this case, the data driving circuit 200 may operate in a power saving mode. Therefore, a display device DD in which power consumption is reduced may be provided.

[0187] A plurality of second scanning stages (e.g., the first second scanning stage ST20 and the second second scanning stage ST21 to the k+1 second scanning stage ST2k) may be connected to the plurality of second pixels PX2. The plurality of second scanning stages may correspond to the second display area DA2 and may output scanning signals SS3, SS4, and SS5. The scanning signals SS3, SS4, and SS5 may be one of the scanning signals GIj and GCj. In this case, "k" may be a natural number greater than 1.

[0188] Each of the plurality of second scan stages may receive the carry signal CRY and the second mask signal MFD_EN2 .

[0189] When the second masking signal MFD_EN2 is enabled, the plurality of second scan stages may respectively mask the scan signals SS3, SS4, and SS5. Masking of the scan signals SS3, SS4, and SS5 may mean that the scan signals SS3, SS4, and SS5 are output in a disabled state.

[0190] The plurality of second scanning stages may include a first second scanning stage ST20, a second second scanning stage ST21, and a k+1th second scanning stage (or the last or rearmost second scanning stage) ST2k arranged in order. Fig.12 , three second scanning levels are illustrated as an example of the plurality of second scanning levels, but the number of second scanning levels according to an embodiment of the present disclosure is not limited thereto. In an embodiment, for example, the number of second scanning levels may be determined according to the second display area DA2.

[0191] The first second scanning stage ST20 among the plurality of second scanning stages may receive the second start signal FLM2 as the carry signal CRY from the driving controller 100 .

[0192] When the scan signal is output from the last first scanning stage among the plurality of first scanning stages, the second start signal FLM2 may be output to the first second scanning stage ST20.

[0193] The first and second scanning stages ST20 may output a scanning signal SS3.

[0194] Each of the remaining second scanning stages except the first second scanning stage ST20 among the plurality of second scanning stages may receive a scanning signal of a previous second scanning stage as the carry signal CRY.

[0195] The second second scanning stage ST21 may receive the scan signal SS3 output from the first second scanning stage ST20 as the carry signal CRY.

[0196] The second scanning stage ST21 may output a scanning signal SS4 .

[0197] The (k+1)th second scanning stage ST2k may receive a scan signal output from a previous second scanning stage as the carry signal CRY.

[0198] The (k+1)th second scanning stage ST2k may output the scanning signal SS5.

[0199] In an embodiment of the present disclosure, the driving frequency of the second display area DA2 may be 120 Hz.

[0200] During the first frame FR1, when the scan signal is output from the last first scan stage of the first display area DA1, the first second scan stage ST20 may receive the second start signal FLM2. The first second scan stage ST20 may output the scan signal SS3 in response to the second start signal FLM2.

[0201] The second second scanning stage ST21 may receive the scan signal SS3 as the carry signal CRY. The second second scanning stage ST21 may output the scan signal SS4 in response to the scan signal SS3.

[0202] The second to k+1th second scanning stages ST21 to ST2k may be sequentially driven.

[0203] The (k+1)th second scanning stage ST2k may receive the scan signal output from the previous second scanning stage as the carry signal CRY. The (k+1)th second scanning stage ST2k may output the scan signal SS5 in response to the scan signal.

[0204] After the first frame FR1, during the second frame FR2, the driving controller 100 may drive the second display area DA2 at a driving frequency of 120 Hz. In this case, the second masking signal MFD_EN2 may be disabled.

[0205] When the scan signal is output from the last first scan stage of the first display area DA1, the first second scan stage ST20 may receive the second start signal FLM2. The first second scan stage ST20 may output the scan signal SS3 in response to the second start signal FLM2.

[0206] The second second scanning stage ST21 may receive the scan signal SS3 as the carry signal CRY. The second second scanning stage ST21 may output the scan signal SS4 in response to the scan signal SS3.

[0207] The (k+1)th second scanning stage ST2k may receive the scan signal output from the previous second scanning stage as the carry signal CRY. The (k+1)th second scanning stage ST2k may output the scan signal SS5 in response to the scan signal.

[0208] After the second frame FR2, during the third frame FR3, the driving controller 100 may drive the second display area DA2 at a driving frequency of 120 Hz. In this case, the second masking signal MFD_EN2 may be disabled.

[0209] When the scan signal is output from the last first scan stage of the first display area DA1, the first second scan stage ST20 may receive the second start signal FLM2. The first second scan stage ST20 may output the scan signal SS3 in response to the second start signal FLM2.

[0210] The second second scanning stage ST21 may receive the scan signal SS3 as the carry signal CRY. The second second scanning stage ST21 may output the scan signal SS4 in response to the scan signal SS3.

[0211] The second to k+1th second scanning stages ST21 to ST2k may be sequentially driven.

[0212] The (k+1)th second scanning stage ST2k may receive the scan signal output from the previous second scanning stage as the carry signal CRY. The (k+1)th second scanning stage ST2k may output the scan signal SS5 in response to the scan signal.

[0213] That is, in each of the first frame FR1 to the third frame FR3, the second image IM2 may be displayed in the second display area DA2. The second image IM2 may be a video. In an embodiment, for example, the second image IM2 may be displayed in all 120 frames (e.g., the first frame FR1, the second frame FR2, the third frame FR3, etc.) provided within 1 second. This may mean that the second display area DA2 is driven substantially at a driving frequency of 120 Hz.

[0214] According to an embodiment of the present disclosure, the driving controller 100 can allow the second display area DA2 in which the second image IM2 having a short change cycle is displayed to operate at a relatively high driving frequency. The second image IM2 can be smoothly provided to the user through the display device DD. Therefore, a display device DD with improved display quality can be provided.

[0215] A plurality of third scanning stages may be connected to a plurality of third pixels PX3. The plurality of third scanning stages may correspond to the third display area DA3 and may output scanning signals SS6, SS7, SS8, and SS9. Each of the scanning signals SS6, SS7, SS8, and SS9 may be one of the scanning signals GIj and GCj. In this case, "n" may be a natural number greater than 1.

[0216] Each of the plurality of third scan stages may receive the carry signal CRY and the third masking signal MFD_EN3 .

[0217] When the third masking signal MFD_EN3 is enabled, the plurality of third scan stages may respectively mask the scan signals SS6, SS7, SS8, and SS9. Masking of the scan signals SS6, SS7, SS8, and SS9 may mean that the scan signals SS6, SS7, SS8, and SS9 are output in a disabled state.

[0218] The plurality of third scanning stages may include a first third scanning stage ST30, a second third scanning stage ST31, an n+1th third scanning stage ST3n, and an n+2th third scanning stage ST3n+1 arranged in order. Fig.124 illustrates four third scanning levels as an example of the plurality of third scanning levels, but the number of the third scanning levels according to an embodiment of the present disclosure is not limited thereto. In an embodiment, for example, the number of the third scanning levels may be determined according to the third display area DA3.

[0219] The first third scanning stage ST30 among the plurality of third scanning stages may receive the third start signal FLM3 as the carry signal CRY from the driving controller 100 .

[0220] When the scan signal is output from the (k+1)th second scanning stage ST2k among the plurality of second scanning stages, the third start signal FLM3 may be output to the first third scanning stage ST30.

[0221] The first to third scanning stages ST30 may output a scan signal SS6.

[0222] Each of the remaining third scanning stages except the first third scanning stage ST30 among the plurality of third scanning stages may receive a scanning signal of a previous third scanning stage as the carry signal CRY.

[0223] The second third scanning stage ST31 may receive the scan signal SS6 output from the first third scanning stage ST30 as the carry signal CRY.

[0224] The second to third scanning stage ST31 may output a scanning signal SS7.

[0225] The (n+1)th third scanning stage ST3n may receive the scan signal output from the previous third scanning stage as the carry signal CRY.

[0226] The (n+1)th third scanning stage ST3n may output the scanning signal SS8.

[0227] The (n+2)th third scanning stage ST3n+1 may receive the scan signal SS8 output from the (n+1)th third scanning stage ST3n as the carry signal CRY.

[0228] The (n+2)th third scanning stage ST3n+1 may output the scanning signal SS9.

[0229] In an embodiment of the present disclosure, a first third display area DA3-1 and a second third display area DA3-2 adjacent to the first third display area DA3-1 may be defined in the third display area DA3. In an embodiment, for example, the first scanning level of the first third display area DA3-1 may be the first third scanning level ST30, and the first scanning level of the second third display area DA3-2 may be the n+1 third scanning level ST3n. In an embodiment, for example, the first third display area DA3-1 may be adjacent to the first sub-display area AA1 (reference Figure 5), and the second third display area DA3-2 may correspond to the second sub-display area AA2 (reference Figure 5 ) corresponding to.

[0230] During the multi-frequency mode MFM, the driving controller 100 may control the first and second third display areas DA3 - 1 and DA3 - 2 to operate at different driving frequencies by using the third masking signal MFD_EN3 .

[0231] In an embodiment of the present disclosure, the driving frequency of the first to third display areas DA3 - 1 may be 60 Hz.

[0232] During the first frame FR1, when the scan signal SS5 is output from the k+1th second scanning stage ST2k as the last second scanning stage of the second display area DA2, the first third scanning stage ST30 may receive the third start signal FLM3. The first third scanning stage ST30 may output the scan signal SS6 in response to the third start signal FLM3.

[0233] The second-third scanning stage ST31 may receive the scan signal SS6 as the carry signal CRY from the first-third scanning stage ST30. The second-third scanning stage ST31 may output the scan signal SS7 in response to the scan signal SS6.

[0234] The second to n-1th third scanning stages ST31 to ST31 may be sequentially driven.

[0235] After the first frame FR1, during the second frame FR2, the driving controller 100 may drive the first to third display area DA3-1 at a driving frequency of 60 Hz. In this case, the third masking signal MFD_EN3 may be enabled (S100).

[0236] In the second frame FR2, during the time period PD21 corresponding to the first third display area DA3-1, the third masking signal MFD_EN3 may be enabled.

[0237] In an implementation, the driving controller 100 may enable the third masking signal MFD_EN3 provided to the first third scanning stage ST30 to drive the first third display area DA3 - 1 with 60 Hz.

[0238] The scanning stage in which the third masking signal MFD_EN3 is enabled may be the first third scanning stage ST30 (S200) receiving the third start signal FLM3. In this case, the driving controller 100 may mask the third start signal FLM3 (S300). That is, the third start signal FLM3 may be disabled and provided to the first third scanning stage ST30.

[0239] After the second frame FR2, during the third frame FR3, the driving controller 100 may disable a portion of the third masking signal MFD_EN3 for the purpose of driving the first third display area DA3-1 at the driving frequency of 60 Hz.

[0240] When the scan signal SS5 is output from the (k+1)th second scanning stage ST2k as the last second scanning stage of the second display area DA2, the first third scanning stage ST30 may receive the third start signal FLM3. The first third scanning stage ST30 may output the scan signal SS6 in response to the third start signal FLM3.

[0241] The second-third scanning stage ST31 may receive the scan signal SS6 as the carry signal CRY from the first-third scanning stage ST30. The second-third scanning stage ST31 may output the scan signal SS7 in response to the scan signal SS6.

[0242] The second to n-1th third scanning stages ST31 to ST31 may be sequentially driven.

[0243] In the first third display area DA3-1, a portion of the third image IM3 may be displayed only in the odd first frame FR1 and the third frame FR3, and the third image IM3 may not be displayed in the remaining frames including the second frame FR2. The third image IM3 may be an image with a long change cycle, such as a keyboard image or a controller image. In an embodiment, for example, the third image IM3 may be alternately displayed in 120 frames (e.g., the first frame FR1, the second frame FR2, the third frame FR3, etc.) provided within 1 second. This may mean that the first third display area DA3-1 is substantially driven by using a driving frequency of 60 Hz.

[0244] According to an embodiment of the present disclosure, the driving controller 100 may drive the first to third display area DA3-1 in which a portion of the third image IM3 having a long variation period is displayed at a driving frequency lower than the driving frequency of the display area DA in which the video is displayed. Since the display device DD makes the driving frequency of the first to third display area DA3-1 low, during a time period in which a portion of the third image IM3 is not displayed, the display device DD may not generate the image data signal DATA and may not perform compensation processing. In addition, in this case, the data driving circuit 200 may operate in a power saving mode. Therefore, a display device DD in which power consumption is reduced may be provided.

[0245] In an embodiment of the present disclosure, the driving frequency of the second and third display areas DA3 - 2 may be 1 Hz.

[0246] During the first frame FR1, the (n+1)th third scanning stage ST3n may receive a scan signal from a previous third scanning stage. The (n+1)th third scanning stage ST3n may output a scan signal SS8 in response to the scan signal.

[0247] The (n+2)th third scanning stage ST3n+1 may receive the scan signal SS8 as the carry signal CRY. The (n+2)th third scanning stage ST3n+1 may output the scan signal SS9 in response to the scan signal SS8.

[0248] The n+2th third scanning stage ST3n+1 to the last third scanning stage may be sequentially driven.

[0249] After the first frame FR1, during the second frame FR2, the driving controller 100 may drive the second third display area DA3-2 at a driving frequency of 1 Hz. In this case, the third masking signal MFD_EN3 may be enabled (S100).

[0250] In the second frame FR2, during the time period PD22 corresponding to the second third display area DA3-2, the third masking signal MFD_EN3 may be enabled.

[0251] In an implementation, the driving controller 100 may enable the third masking signal MFD_EN3 provided to the (n+1)th third scanning stage ST3n to drive the entire second-third display area DA3-2 at 1 Hz.

[0252] The scanning stage in which the third masking signal MFD_EN3 is enabled may be the n+1th third scanning stage ST3n that does not receive the third start signal FLM3. In this case, the driving controller 100 may mask the scanning signal SS8 based on the third masking signal MFD_EN3 (S400).

[0253] After the second frame FR2, during the third frame FR3, the driving controller 100 may enable the third masking signal MFD_EN3 for the purpose of driving the second third display area DA3-2 at a driving frequency of 1 Hz (S100).

[0254] In the third frame FR3, during the time period PD23 corresponding to the second third display area DA3-2, the third masking signal MFD_EN3 may be enabled.

[0255] The scanning stage in which the third masking signal MFD_EN3 is enabled may be the n+1th third scanning stage ST3n that does not receive the third start signal FLM3. In this case, the driving controller 100 may mask the scanning signal SS8 based on the third masking signal MFD_EN3 (S400).

[0256] That is, in the second to third display area DA3-2, the remaining portion of the third image IM3 may be displayed only in the first frame FR1, and the third image IM3 may not be displayed in the remaining second frame FR2 and third frame FR3. The remaining portion of the third image IM3 may be a bottom information bar indicating status information having a long change cycle. In an embodiment, for example, the remaining portion of the third image IM3 may be displayed only in the first frame FR1 among 120 frames (e.g., the first frame FR1, the second frame FR2, the third frame FR3, etc.) provided within 1 second; in the remaining frames, the second to third display area DA3-2 in which the third image IM3 is not displayed may be substantially driven by using a driving frequency of 1 Hz.

[0257] According to an embodiment of the present disclosure, the driving controller 100 may drive the second to third display area DA3-2 in which the remaining portion of the third image IM3 having a long variation period is displayed, at a driving frequency lower than the driving frequency of the display area DA in which the video is displayed. Since the display device DD makes the driving frequency of the second to third display area DA3-2 low, during the time period in which the remaining portion of the third image IM3 is not displayed, the display device DD may not generate the image data signal DATA and may not perform the compensation process. In addition, in this case, the data driving circuit 200 may operate in a power saving mode. Therefore, a display device DD in which power consumption is reduced may be provided.

[0258] According to an embodiment of the present disclosure, the driving frequency of the first display area DA1 may be lower than the driving frequency of the second display area DA2. The driving frequency of the second display area DA2 may be higher than the driving frequency of the first to third display areas DA3-1. The driving frequency of the first to third display areas DA3-1 may be higher than the driving frequency of the second to third display areas DA3-2. The second to third display areas DA3-2 may be operated by using the same driving frequency as the driving frequency of the first display area DA1.

[0259] Fig.15 is a block diagram illustrating a plurality of scanning stages and a display area according to an embodiment of the present disclosure, and Fig.16 is a timing diagram illustrating a scan signal and a mask signal according to an embodiment of the present disclosure. Fig.15 and Fig.16 In the description of the embodiments shown in FIG. 1 , the same reference numerals / symbols as those in the above reference are used to mark Fig.12 Those components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0260] refer to Figure 1 , Figure 6 as well as Figures 14 to 16 In an embodiment of the present disclosure, the driving frequency of the first display area DA1 may be 120 Hz.

[0261] In each of the first, second, and third frames FR1, FR2, and FR3, the first first scanning stage ST10 may receive the first start signal FLM1. The first first scanning stage ST10 may output the scanning signal SS1-1 in response to the first start signal FLM1. In this case, the first masking signal MFD_EN1 may be disabled.

[0262] The second first scanning stage ST11 may receive the scan signal SS1-1 as the carry signal CRY. The second first scanning stage ST11 may output the scan signal SS2-1 in response to the scan signal SS1-1.

[0263] That is, in each of the first frame FR1 , the second frame FR2 , and the third frame FR3 , the first image IM1 may be displayed in the first display area DA1 .

[0264] In an embodiment of the present disclosure, the driving frequency of the second display area DA2 may be 120 Hz. In this case, the second masking signal MFD_EN2 may be disabled.

[0265] In each of the first, second, and third frames FR1, FR2, and FR3, when the scan signal is output from the last first scan stage of the first display area DA1, the first second scan stage ST20 may receive the second start signal FLM2. The first second scan stage ST20 may output the scan signal SS3-1 in response to the second start signal FLM2.

[0266] The second second scanning stage ST21 may receive the scan signal SS3-1 as the carry signal CRY. The second second scanning stage ST21 may output the scan signal SS4-1 in response to the scan signal SS3-1.

[0267] The second to k+1th second scanning stages ST21 to ST2k may be sequentially driven.

[0268] The (k+1)th second scanning stage ST2k, which is the last second scanning stage, may receive the scan signal from the previous second scanning stage as the carry signal CRY. The (k+1)th second scanning stage ST2k may output the scan signal SS5-1 in response to the scan signal.

[0269] That is, in each of the first frame FR1, the second frame FR2, and the third frame FR3, the second image IM2 may be displayed in the second display area DA2.

[0270] During the multi-frequency mode MFM, the driving controller 100 may control the first and second third display areas DA3 - 1 and DA3 - 2 to operate at different driving frequencies by using the third masking signal MFD_EN3 .

[0271] In an embodiment of the present disclosure, the driving frequency of the first to third display areas DA3 - 1 may be 120 Hz.

[0272] In each of the first frame FR1, the second frame FR2, and the third frame FR3, when the scan signal SS5-1 is output from the k+1th second scanning stage ST2k of the second display area DA2, the first third scanning stage ST30 may receive the third start signal FLM3. The first third scanning stage ST30 may output the scan signal SS6-1 in response to the third start signal FLM3.

[0273] The second-third scanning stage ST31 may receive the scan signal SS6-1 as the carry signal CRY from the first-third scanning stage ST30. The second-third scanning stage ST31 may output the scan signal SS7-1 in response to the scan signal SS6-1.

[0274] The second to n-1th third scanning stages ST31 to ST31 may be sequentially driven.

[0275] That is, in the multi-frequency mode MFM, the first display area DA1, the second display area DA2, and the first to third display areas DA3-1 may be operated by using the same driving frequency.

[0276] In an embodiment of the present disclosure, the driving frequency of the second and third display areas DA3 - 2 may be 1 Hz.

[0277] During the first frame FR1, the (n+1)th third scanning stage ST3n may receive a scan signal from a previous third scanning stage. The (n+1)th third scanning stage ST3n may output a scan signal SS8-1 in response to the scan signal.

[0278] The (n+2)th third scanning stage ST3n+1 may receive the scan signal SS8-1 as the carry signal CRY. The (n+2)th third scanning stage ST3n+1 may output the scan signal SS9-1 in response to the scan signal SS8-1.

[0279] The n+2th third scanning stage ST3n+1 to the last third scanning stage may be sequentially driven.

[0280] After the first frame FR1, during the second frame FR2, the driving controller 100 may drive the second third display area DA3-2 at a driving frequency of 1 Hz. In this case, the third masking signal MFD_EN3 may be enabled (S100).

[0281] In the second frame FR2, during the time period PD21a corresponding to the second third display area DA3-2, the third masking signal MFD_EN3 may be enabled.

[0282] In an implementation, the driving controller 100 may enable the third masking signal MFD_EN3 provided to the (n+1)th third scanning stage ST3n to drive the entire second to third display area DA3-2 with 1 Hz.

[0283] The scanning stage in which the third masking signal MFD_EN3 is enabled may be the n+1th third scanning stage ST3n that does not receive the third start signal FLM3. In this case, the driving controller 100 may mask the scanning signal SS8-1 based on the third masking signal MFD_EN3 (S400).

[0284] After the second frame FR2, during the third frame FR3, the driving controller 100 may enable the third masking signal MFD_EN3 for the purpose of driving the second third display area DA3-2 at a driving frequency of 1 Hz (S100).

[0285] In the third frame FR3, during the time period PD22a corresponding to the second third display area DA3-2, the third masking signal MFD_EN3 may be enabled.

[0286] The scanning stage in which the third masking signal MFD_EN3 is enabled may be the n+1th third scanning stage ST3n that does not receive the third start signal FLM3. In this case, the driving controller 100 may mask the scanning signal SS8-1 based on the third masking signal MFD_EN3 (S400).

[0287] That is, in the second to third display area DA3-2, only a portion of the third image IM3 may be displayed in the first frame FR1, and the remaining portion of the third image IM3 may not be displayed in the remaining second frame FR2 and third frame FR3. In an embodiment, for example, only a portion of the third image IM3 may be displayed in the first frame FR1 among 120 frames (e.g., the first frame FR1, the second frame FR2, the third frame FR3, etc.) provided within 1 second; in the remaining frames, the second to third display area DA3-2 in which the third image IM3 is not displayed may be driven substantially at a driving frequency of 1 Hz.

[0288] According to an embodiment of the present disclosure, the driving controller 100 may drive a portion of the display area DA at a relatively low driving frequency. During a time period in which the display device DD operates at a low driving frequency, the display device DD may not generate an image data signal DATA and may not perform a compensation process. In addition, in this case, the data driving circuit 200 may operate in a power saving mode. Therefore, a display device DD in which power consumption is reduced may be provided.

[0289] The image display area DAa according to an embodiment of the present disclosure may include a first display area DA1, a second display area DA2, and a first to third display area DA3-1. The driving frequency of the first display area DA1 may be the same as the driving frequency of the second display area DA2 and the first to third display area DA3-1. That is, the image display area DAa may be operated at a driving frequency of 120 Hz. The driving frequency of the first to third display area DA3-1 may be higher than the driving frequency of the second to third display area DA3-2.

[0290] Fig.17 is a block diagram illustrating a plurality of scanning stages and a display area according to an embodiment of the present disclosure, and Fig.18 is a timing diagram illustrating a scan signal and a mask signal according to an embodiment of the present disclosure. Fig.17 and Fig.18 In the description of the embodiments of the present invention, the same reference numerals / symbols as those in the above reference are used to mark Fig.12 Those components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0291] refer to Figure 1 , Figure 6 , Fig.14 , Fig.17 and Fig.18 In an embodiment of the present disclosure, the first display area DA1 may be divided into a first first display area DA1-1 and a second first display area DA1-2. During the multi-frequency mode MFM, the driving controller 100 may control the first first display area DA1-1 and the second first display area DA1-2 to operate at different driving frequencies by using the first masking signal MFD_EN1.

[0292] In an embodiment of the present disclosure, the driving frequency of the first display area DA1 - 1 may be 120 Hz.

[0293] In each of the first, second, and third frames FR1, FR2, and FR3, the first first scanning stage ST10 may receive the first start signal FLM1. The first first scanning stage ST10 may output the scanning signals SS1-2 in response to the first start signal FLM1. In this case, the first masking signal MFD_EN1 may be disabled.

[0294] In an embodiment of the present disclosure, the driving frequency of the second first display area DA1-2 may be 1 Hz.

[0295] During the first frame FR1, the second first scanning stage ST11 may receive the scan signal SS1-2. The second first scanning stage ST11 may output the scan signal SS2-2 in response to the scan signal SS1-2.

[0296] After the first frame FR1, during the second frame FR2 and the third frame FR3, the driving controller 100 may drive the second first display area DA1-2 at a driving frequency of 1 Hz. In this case, the first masking signal MFD_EN1 may be enabled (S100).

[0297] In the second frame FR2 and the third frame FR3 , the first masking signal MFD_EN1 may be enabled during time periods PD11 b and PD12 b corresponding to the second first display area DA1 - 2 .

[0298] In an implementation, the driving controller 100 may enable the first masking signal MFD_EN1 provided to the second first scanning stage ST11 to drive the entire second first display area DA1 - 2 at 1 Hz.

[0299] The scanning stage in which the first masking signal MFD_EN1 is enabled may be the second first scanning stage ST11 that does not receive the first start signal FLM1. In this case, the driving controller 100 may mask the scanning signals SS1-2 based on the first masking signal MFD_EN1 (S400).

[0300] The second display area DA2 may be divided into a first second display area DA2-1 and a second second display area DA2-2. During the multi-frequency mode MFM, the driving controller 100 may control the first second display area DA2-1 and the second second display area DA2-2 to operate at different driving frequencies by using the second masking signal MFD_EN2.

[0301] In an embodiment of the present disclosure, the driving frequency of the first and second display areas DA2 - 1 may be 120 Hz.

[0302] In each of the first, second, and third frames FR1, FR2, and FR3, the first second scanning stage ST20 may receive the second start signal FLM2. The first second scanning stage ST20 may output the scanning signal SS3-2 in response to the second start signal FLM2. In this case, the second masking signal MFD_EN2 may be disabled.

[0303] The second second scanning stage ST21 may receive the scan signal SS3-2. The second second scanning stage ST21 may output the scan signal SS4-2 in response to the scan signal SS3-2.

[0304] In an embodiment of the present disclosure, the driving frequency of the second display area DA2-2 may be 60 Hz.

[0305] In the first frame FR1 and the third frame FR3, the (k+1)th second scanning stage ST2k may receive the scan signal from the previous second scanning stage. The (k+1)th second scanning stage ST2k may output the scan signal SS5-2 in response to the scan signal.

[0306] After the first frame FR1, during the second frame FR2, the driving controller 100 may drive the second second display area DA2-2 at a driving frequency of 60 Hz. In this case, the second masking signal MFD_EN2 may be enabled (S100).

[0307] In the second frame FR2, during the time period PD31b corresponding to the second second display area DA2-2, the second masking signal MFD_EN2 may be enabled.

[0308] In an implementation, the driving controller 100 may enable the second masking signal MFD_EN2 provided to the third second scanning stage to drive the entire second second display area DA2 - 2 with 60 Hz.

[0309] The scanning stage in which the second masking signal MFD_EN2 is enabled may be the third second scanning stage that does not receive the second start signal FLM2. In this case, the driving controller 100 may mask the scanning signal SS4-2 based on the second masking signal MFD_EN2 (S400).

[0310] The third display area DA3 may be divided into first and second third display areas DA3-1 and DA3-2. During the multi-frequency mode MFM, the driving controller 100 may control the first and second third display areas DA3-1 and DA3-2 to operate at different driving frequencies by using the third masking signal MFD_EN3.

[0311] In an embodiment of the present disclosure, the driving frequency of the first to third display areas DA3 - 1 may be 120 Hz.

[0312] In each of the first frame FR1, the second frame FR2, and the third frame FR3, when the scan signal SS5-2 is output from the k+1th second scanning stage ST2k of the second display area DA2, the first third scanning stage ST30 may receive the third start signal FLM3. The first third scanning stage ST30 may output the scan signal SS6-2 in response to the third start signal FLM3.

[0313] The second-third scanning stage ST31 may receive the scan signal SS6-2 as the carry signal CRY from the first-third scanning stage ST30. The second-third scanning stage ST31 may output the scan signal SS7-2 in response to the scan signal SS6-2.

[0314] The first to n-1th third scanning stages ST30 to ST30 may be sequentially driven.

[0315] In an embodiment of the present disclosure, the driving frequency of the second and third display areas DA3 - 2 may be 1 Hz.

[0316] During the first frame FR1, the (n+1)th third scanning stage ST3n may receive a scan signal from a previous third scanning stage. The (n+1)th third scanning stage ST3n may output a scan signal SS8-2 in response to the scan signal.

[0317] The (n+2)th third scanning stage ST3n+1 may receive the scan signal SS8-2 as the carry signal CRY. The (n+2)th third scanning stage ST3n+1 may output the scan signal SS9-2 in response to the scan signal SS8-2.

[0318] The n+2th third scanning stage ST3n+1 to the last third scanning stage may be sequentially driven.

[0319] After the first frame FR1, during the second frame FR2 and the third frame FR3, the driving controller 100 may drive the second third display area DA3-2 at a driving frequency of 1 Hz. In this case, the third masking signal MFD_EN3 may be enabled (S100).

[0320] In the second frame FR2 and the third frame FR3, the third masking signal MFD_EN3 may be enabled during time periods PD21b and PD22b corresponding to the second to third display area DA3-2.

[0321] In an implementation, the driving controller 100 may enable the third masking signal MFD_EN3 provided to the (n+1)th third scanning stage ST3n to drive the entire second-third display area DA3-2 at 1 Hz.

[0322] The scanning stage in which the third masking signal MFD_EN3 is enabled may be the n+1th third scanning stage ST3n that does not receive the third start signal FLM3. In this case, the driving controller 100 may mask the scanning signal SS8-2 based on the third masking signal MFD_EN3 (S400).

[0323] The number of the plurality of start signals may be equal to half of the maximum number of regions that can be operated at frequencies different from each other in the display area DA. In an embodiment, for example, the number of the plurality of start signals may be "3"; in such an embodiment, the display area DA may be divided into a maximum of 6 regions that can be operated at driving frequencies different from each other.

[0324] In an embodiment, for example, the first display area DA1-1 may be connected to the first sub-display area AA1 (refer to Figure 5 ), and the second first display area DA1-2 may correspond to the second sub-display area AA2 (reference Figure 5 ) corresponds to the first and second display areas DA2-1 and the first sub-display area AA1 (refer to Figure 5 ), and the second second display area DA2-2 may correspond to the second sub-display area AA2 (reference Figure 5 ) corresponds to the first third display area DA3-1. The first third display area DA3-1 may correspond to the first sub-display area AA1 (refer to Figure 5 ), and the second third display area DA3-2 may correspond to the second sub-display area AA2 (reference Figure 5 ) corresponding to.

[0325] According to an embodiment of the present disclosure, as described herein, a drive controller may drive a portion of a display area by using a relatively low drive frequency. During a time period in which the display device operates at a low drive frequency, the display device may not generate an image data signal and may not perform compensation processing. In addition, in such an embodiment, a data drive circuit may be operated in a power saving mode, thereby providing a display device in which power consumption is reduced.

[0326] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0327] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope or spirit of the invention as defined in the following claims.

Claims

1. A display device, comprising: a display panel including a plurality of pixels connected to a plurality of scan lines, wherein a display area including a first display area and a second display area is defined in the display panel; a scan driving circuit including a plurality of scan stages respectively corresponding to the plurality of scan lines, wherein each of the plurality of scan stages receives a mask signal and a carry signal and outputs a scan signal; and a driving controller that controls the scan driving circuit and outputs a plurality of start signals including a first start signal and a second start signal, The plurality of pixels include a plurality of first pixels arranged in the first display area and a plurality of second pixels arranged in the second display area. wherein the plurality of scanning stages include a plurality of first scanning stages connected to the plurality of first pixels and a plurality of second scanning stages connected to the plurality of second pixels, wherein a first first scanning stage among the plurality of first scanning stages receives the first start signal from the driving controller as the carry signal, and The first second scanning stage among the plurality of second scanning stages receives the second start signal as the carry signal from the driving controller.

2. The display device according to claim 1, wherein: When the scanning signal is output from a last scanning stage among the plurality of first scanning stages, the second start signal is output to the first second scanning stage.

3. The display device according to claim 1, wherein: A first second display area and a second second display area adjacent to the first second display area are defined in the second display area, and Wherein, during the multi-frequency mode, the driving controller controls the first second display area and the second second display area by operating the first second display area and the second second display area at different driving frequencies using the masking signal.

4. The display device according to claim 3, wherein: The first driving frequency of the first display area is lower than the first second driving frequencies of the first second display areas, and The second second driving frequency of the second second display area is lower than the first second driving frequency of the first second display area.

5. The display device according to claim 3, wherein: During the multi-frequency mode, at least one of the plurality of second scanning stages masks the scanning signal provided to a plurality of second pixels arranged in the second second display area among the plurality of second pixels based on the masking signal.

6. The display device according to claim 1, wherein: The number of the plurality of start signals is half the maximum number of regions operable at driving frequencies different from each other in the display area.

7. The display device according to claim 1, wherein: The driving controller disables the first start signal when the mask signal provided to the first first scanning stage is enabled.

8. The display device according to claim 7, wherein: The driving controller disables the second start signal when the mask signal provided to the first second scanning stage is enabled.

9. The display device according to claim 1, wherein: When the mask signal provided to a scanning stage among the plurality of scanning stages is enabled, the scanning stage masks the scanning signal.

10. The display device according to claim 1, wherein: Each of the remaining first scanning stages except the first first scanning stage among the plurality of first scanning stages receives the scanning signal of the previous first scanning stage as the carry signal, and Each of the remaining second scanning stages except the first second scanning stage among the plurality of second scanning stages receives the scanning signal of the previous second scanning stage as the carry signal.

11. The display device according to claim 1, wherein: The display area further includes a third display area spaced apart from the first display area, and the second display area is between the first display area and the third display area. The plurality of start signals further include a third start signal. The plurality of pixels further include a plurality of third pixels arranged in the third display area. wherein the plurality of scanning stages further comprises a plurality of third scanning stages connected to the plurality of third pixels, and The first third scanning stage among the plurality of third scanning stages receives the third start signal from the driving controller as the carry signal.

12. The display device according to claim 11, wherein: A first third display area and a second third display area adjacent to the first third display area are defined in the third display area, and Wherein, during the multi-frequency mode, the driving controller controls the first third display area and the second third display area by operating the first third display area and the second third display area at different driving frequencies using the masking signal.

13. The display device according to claim 12, wherein: During the multi-frequency mode, the first display area, the second display area, and the first third display area are operated at the same driving frequency.

14. The display device according to claim 12, wherein: During the multi-frequency mode, each of the first display area and the second third display area operates at a first driving frequency, The second driving frequency of the second display area is higher than the first driving frequency of the first display area, and Wherein, the third driving frequency of the first to third display areas is lower than the second driving frequency of the second display area.

15. A display device, comprising: a display panel including a plurality of pixels connected to a plurality of scan lines, wherein a display area including a first display area and a second display area is defined in the display panel; a scan driving circuit including a plurality of scan stages respectively corresponding to the plurality of scan lines, wherein each of the plurality of scan stages receives a mask signal and a carry signal and outputs a scan signal; and Drive controller, Wherein, in the multi-frequency mode, the driving controller divides the display panel into the first display area and the second display area, controls the scan driving circuit so that the first display area and the second display area operate at frequencies different from each other, and outputs a plurality of start signals including a first start signal and a second start signal, wherein the first start signal and the second start signal are provided at different timings from each other, wherein a first scanning stage arranged in the first display area among the plurality of scanning stages receives the first start signal as the carry signal, and The first scanning stage arranged in the second display area among the plurality of scanning stages receives the second start signal as the carry signal.

16. The display device according to claim 15, wherein: The second start signal is output when the scan signal is output from a last scan stage arranged in the first display area among the plurality of scan stages.

17. The display device according to claim 15, wherein: A first second display area and a second second display area adjacent to the first second display area are defined in the second display area, and Wherein, during the multi-frequency mode, the driving controller controls the first second display area and the second second display area by operating the first second display area and the second second display area at different driving frequencies using the masking signal.

18. The display device according to claim 15, wherein: The driving controller disables the first start signal when the mask signal provided to the first scanning stage arranged in the first display area is enabled.

19. The display device according to claim 18, wherein: The driving controller disables the second start signal when the mask signal provided to the first scanning stage arranged in the second display area is enabled.

20. The display device according to claim 15, wherein: When the mask signal provided to a scanning stage among the plurality of scanning stages is enabled, the scanning stage masks the scanning signal.

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