Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof, the display panel at least comprises a first display subarea and a second display subarea, each display subarea comprises a plurality of pixel rows, and the plurality of pixel rows are driven by a driving module connected with a pixel circuit; the driving method comprises the following steps: inputting a first light-emitting control initial signal, a first reset initial signal and a first line scanning initial signal to a driving module connected with a first pixel line of a first display partition; inputting a second light-emitting control starting signal which differs from the phase of the first light-emitting control starting signal by half frame to a driving module connected with a first pixel row of the second display subarea, a second reset start signal differing from the phase of the first reset start signal by half a frame; and a second line scan start signal differing from the phase of the first line scan start signal by half a frame. The pixel rows are controlled to emit light in a staggered manner, so that the actual light emitting time of the display area is prolonged, the brightness drop is reduced, and the problem of screen flicker under a low-frequency picture is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method thereof. Background Art

[0002] In pixel circuits of some low-temperature polycrystalline silicon organic light-emitting diode (LTPS OLED) display panels, some P-type thin-film transistors are often used. However, these P-type thin-film transistors will generate leakage current, resulting in a large current drop.

[0003] In the related art, some P-type thin-film transistors such as compensation transistors and reset transistors are replaced with dual-gate thin-film transistors to reduce leakage current. However, in low-frequency images with low refresh rates, the gate voltage of the driving transistor of the pixel circuit may remain in a certain state for a long time. Since the compensation transistor and the reset transistor are electrically connected to the gate of the driving transistor, the gate of the driving transistor will continue to accumulate leakage current to the middle node of the dual-gate thin-film transistor, which will cause a large change in the luminous current within a frame. This will be reflected in the display screen, causing large fluctuations in the luminous brightness within a frame, resulting in screen flicker visible to the naked eye. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a driving method thereof to solve the problem in the related art that the display panel may generate screen flickering under low-frequency images.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] In a first aspect, the present application provides a display panel, comprising:

[0007] The display area includes at least a first display subarea and a second display subarea;

[0008] A pixel array is arranged in the display area; wherein each display subarea includes a plurality of pixel rows, each of the pixel rows includes a plurality of sub-pixels and a plurality of pixel circuits, and each of the sub-pixels is electrically connected to one of the pixel circuits; and

[0009] A driving module, used for inputting a driving signal to the pixel circuit;

[0010] The driving module connected to the first pixel row of the first display partition receives a first light emission control start signal, a first reset start signal and a first row scanning start signal;

[0011] The driving module connected to the first pixel row of the second display partition is connected to a second light-emitting control start signal whose phase is half a frame different from that of the first light-emitting control start signal, a second reset start signal whose phase is half a frame different from that of the first reset start signal, and a second row scanning start signal whose phase is half a frame different from that of the first row scanning start signal.

[0012] In one embodiment, the driving module further includes:

[0013] A plurality of row driving circuits, each of which is connected to one of the pixel rows, and the plurality of row driving circuits comprises:

[0014] a first type of row driving circuit, wherein an input end of the first type of row driving circuit is electrically connected to a first type of clock signal line, and an output end of the first type of row driving circuit is electrically connected to a pixel circuit located in the first display subarea; and

[0015] The second type of row driving circuit, the input end of the second type of row driving circuit is electrically connected to the second type of clock signal line, and the output end of the second type of row driving circuit is electrically connected to the pixel circuit located in the second display partition.

[0016] In one embodiment, the driving module further includes:

[0017] A plurality of reset circuits, each reset circuit being connected to one of the pixel rows, the plurality of reset circuits comprising:

[0018] a first type reset circuit, wherein an input end of the first type reset circuit is electrically connected to the second type clock signal line, and an output end of the first type reset circuit is electrically connected to a pixel circuit located in the first display partition; and

[0019] A second type reset circuit, wherein the input end of the second type reset circuit is electrically connected to the first type clock signal line, and the output end of the second type reset circuit is electrically connected to the pixel circuit located in the second display partition.

[0020] In one embodiment, the driving module further includes:

[0021] A plurality of light emitting control circuits, each of which is connected to one of the pixel rows; or

[0022] Each of the light emitting control circuits is connected to two adjacent pixel rows.

[0023] In one embodiment, the plurality of light emitting control circuits include:

[0024] A first type of light emitting control circuit, wherein an input end of the first type of light emitting control circuit is electrically connected to a third type of clock signal line, and an output end of the first type of light emitting control circuit is electrically connected to a pixel circuit located in the first display partition;

[0025] The second type of light emitting control circuit, the input end of the second type of light emitting control circuit is electrically connected to the fourth type of clock signal line, and the output end of the second type of light emitting control circuit is electrically connected to the pixel circuit located in the second display partition.

[0026] In one embodiment, the first type of clock signal lines and the second type of clock signal lines each include four clock signal lines, each of the row driving circuits is electrically connected to two clock signal lines, and each of the reset circuits is electrically connected to two clock signal lines.

[0027] In a second aspect, the present application provides a method for driving a display panel, comprising:

[0028] The display panel comprises at least two display partitions, each of the display partitions comprises a plurality of pixel rows, and the two display areas comprise a first display partition and a second display partition;

[0029] The driving method comprises:

[0030] Inputting a first light emission control start signal, a first reset start signal and a first row scanning start signal to a first pixel row of the first display subarea;

[0031] A second light emitting control start signal having a phase difference of half a frame with that of the first light emitting control start signal, a second reset start signal having a phase difference of half a frame with that of the first reset start signal, and a second row scanning start signal having a phase difference of half a frame with that of the first row scanning start signal are input to the first pixel row of the second display partition.

[0032] In one embodiment, the driving method further includes:

[0033] outputting a first type of row scanning signal to the first display partition according to a first type of clock signal;

[0034] outputting a first type of reset signal to the first display partition according to a second type of clock signal;

[0035] A first type of light emitting control signal is output to the first display partition according to a third type of clock signal.

[0036] In one embodiment, the driving method further includes:

[0037] outputting a second type of reset signal to the second display partition according to the first type of clock signal;

[0038] outputting a second type of row scanning signal to the second display partition according to the second type of clock signal;

[0039] The second type light emitting control signal is output to the second display partition according to the fourth type clock signal.

[0040] In one embodiment, the driving method further includes:

[0041] The period of the first-type clock signal and the period of the second-type clock signal are controlled to be four times of the horizontal scanning period.

[0042] In one embodiment, the driving method further includes:

[0043] The period of the third type of clock signal and the period of the fourth type of clock signal are both controlled to be eight times of the horizontal scanning period.

[0044] In one embodiment, the driving method further includes:

[0045] Control the row scanning signal connected to any pixel row to be delayed by one horizontal scanning cycle time compared to the reset signal connected to the same pixel row;

[0046] The row scanning signals include the first type of row scanning signals and the second type of row scanning signals, and the reset signals include the first type of reset signals and the second type of reset signals.

[0047] In one embodiment, the moment when the first pixel row of the second display partition is connected to the second type of reset signal is controlled to lag behind the moment when the first pixel of the first display partition is connected to the first type of reset signal by twice the horizontal scanning period;

[0048] The moment when the first pixel row of the second display partition is connected to the second type of row scanning signal is controlled to lag behind the moment when the first pixel row of the first display partition is connected to the first type of row scanning signal by twice the horizontal scanning period.

[0049] The present application provides a display panel including: a pixel array, the pixel array including at least two display partitions, each of the display partitions including a plurality of pixel rows, each of the pixel rows including a plurality of sub-pixels and a plurality of pixel circuits, each of the sub-pixels being electrically connected to one of the pixel circuits; and a driving module for inputting a driving signal to the pixel circuit; wherein the two display partitions include a first display partition and a second display partition, the driving module connected to the first pixel row of the first display partition is connected to a first light-emitting control start signal, a first reset start signal and a first row scan start signal; the driving module connected to the first pixel row of the second display partition is connected to a second light-emitting control start signal with a phase difference of half a frame with the first light-emitting control start signal, a second reset start signal with a phase difference of half a frame with the first reset start signal, and a second row scan start signal with a phase difference of half a frame with the first row scan start signal. Through the above scheme, the present application makes the light-emitting row pixels in the display area staggered, that is, the actual light-emitting time in the display area becomes longer and the brightness drop becomes smaller, thereby improving the screen flickering problem under low-frequency images. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0051] Attached Figure 1 This is a schematic diagram of an optional display panel structure in an embodiment of the present application;

[0052] Attached Figure 2 A schematic diagram of the structure of another optional display panel in an embodiment of the present application;

[0053] Attached Figure 3 This is a schematic diagram of the structure of an optional display panel in an embodiment of the present application;

[0054] Attached Figure 4 This is a schematic diagram of an optional pixel circuit in an embodiment of the present application;

[0055] Attached Figure 5 Based on Figure 4 A schematic diagram showing the timing of the pixel circuit, i.e., the change in luminous brightness;

[0056] Attached Figure 6 This is a working timing diagram of the first type of row driving circuit in the embodiment of the present application;

[0057] Attached Figure 7 This is a working timing diagram of the first type of reset circuit in the embodiment of the present application;

[0058] Attached Figure 8 This is a working timing diagram of the first type of light emitting control circuit in this application;

[0059] Attached Fig. 9 This is an overall working timing diagram of the first display partition in the embodiment of the present application;

[0060] Attached Fig.10 This is a working timing diagram of the second type of row driving circuit in the embodiment of the present application;

[0061] Attached Fig.11 This is a working timing diagram of the second type of reset circuit in the embodiment of the present application;

[0062] Attached Fig.12 This is a working timing diagram of the second type of light emitting control circuit in the embodiment of the present application;

[0063] Attached Fig.13 This is an overall working timing diagram of the second display partition in the embodiment of the present application;

[0064] Attached Fig.14 This is an overall working timing diagram of the display panel in the embodiment of the present application;

[0065] Attached Fig.15 is a brightness variation diagram of a pixel row in the related art;

[0066] Attached Fig.16 This is a brightness change diagram of a pixel row in an embodiment of the present application;

[0067] Attached Fig.17 This is a comparison chart of power consumption of display panels in the embodiments of the present application.

[0068] Description of reference numerals in the figures:

[0069] 10. Display panel;

[0070] 100, pixel array; 100a, first display subarea; 100b, second display subarea; 101, subpixel; 102, pixel circuit;

[0071] 200, driving module; 210, row driving circuit; 210a, first type of row driving circuit; 210b, second type of row driving circuit; 220, reset circuit; 220a, first type of reset circuit; 220b, second type of reset circuit; 230, light-emitting control circuit; 230a, first type of light-emitting control circuit; 230b, second type of light-emitting control circuit. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0073] In addition, the terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0074] Reference Figures 1 to 4 As shown, according to the first aspect of the present application, the present application provides a display panel 10, including a pixel array 100 and a driving module 200, wherein the pixel array 100 includes at least two display partitions, each display partition includes a plurality of pixel rows, each pixel row includes a plurality of sub-pixels 101 and a plurality of pixel circuits 102, and each sub-pixel 101 is electrically connected to a pixel circuit 102.

[0075] The driving module 200 is used to input a driving signal to the pixel circuit 102. Specifically, in some embodiments of the present application, the driving module 200 includes a plurality of row driving circuits 210, a plurality of reset circuits 220, and a plurality of light-emitting driving circuits. Each row driving circuit 210 is connected to a pixel circuit 102 of a pixel row, and each reset circuit 220 is also connected to a pixel circuit 102 of a pixel row. Figure 1 As shown, in some embodiments, the display panel 10 of the present application can be an EM one-drive one architecture, that is, each light-emitting driving circuit of the present application can be connected to a pixel row; or refer to Figure 2 As shown, the display panel 10 of the present application may also be an EM one-drive two architecture, that is, each light-emitting driving circuit of the present application may be connected to two adjacent pixel rows. The display panel 10 using the EM one-drive two architecture is beneficial to reducing the CK frequency of the display panel 10, and is also beneficial for the display panel 10 to achieve low refresh rate display. At the same time, in this embodiment, in order to reduce the power consumption of the display panel 10, a display panel 10 with a left and right side drive architecture may also be used. In subsequent embodiments, the present application will be described with the display panel 10 of the EM one-drive two architecture.

[0076] Specifically, the two display partitions include a first display partition 100a and a second display partition 100b. In some embodiments, the first display partition 100a and the second display partition 100b have the same number of pixel rows, and the driving module 200 connected to the first pixel row of the first display partition 100a receives a first light emission control start signal, a first reset start signal, and a first row scanning start signal;

[0077] The driving module 200 connected to the first pixel row of the second display partition 100b is connected to a second light-emitting control start signal whose phase is half a frame different from the first light-emitting control start signal, a second reset start signal whose phase is half a frame different from the first reset start signal, and a second row scan start signal whose phase is half a frame different from the first row scan start signal.

[0078] Through the above settings, the present application can stagger the light emission of pixel rows in the display area, thereby reducing brightness drops and avoiding screen flickering.

[0079] Reference Figure 3 As shown, more specifically, in some embodiments of the present application, the plurality of row driving circuits 210 include a first type of row driving circuit 210a and a second type of row driving circuit 210b, wherein the input end of the first type of row driving circuit 210a is electrically connected to the first type of clock signal line, and the output end of the first type of row driving circuit 210a is electrically connected to the pixel circuit 102 located in the first display partition 100a; the input end of the second type of row driving circuit 210b is electrically connected to the second type of clock signal line, and the output end of the second type of row driving circuit 210b is electrically connected to the pixel circuit 102 located in the second display partition 100b.

[0080] In some embodiments of the present application, the multiple reset circuits 220 include a first type reset circuit 220a and a first type reset circuit 220a, wherein the input end of the first type reset circuit 220a is electrically connected to the second type clock signal line, and the output end of the first type reset circuit 220a is electrically connected to the pixel circuit 102 located in the first display partition 100a; the input end of the first type reset circuit 220a is electrically connected to the first type clock signal line, and the output end of the first type reset circuit 220a is electrically connected to the pixel circuit 102 located in the second display partition 100b.

[0081] In some embodiments of the present application, multiple light-emitting control circuits 230 include a first type of light-emitting control circuit 230a and a second type of light-emitting control circuit 230b, wherein the input end of the first type of light-emitting control circuit 230a is electrically connected to the third type of clock signal line, and the output end of the first type of light-emitting control circuit 230a is electrically connected to the pixel circuit 102 located in the first display partition 100a; the input end of the second type of light-emitting control circuit 230b is electrically connected to the fourth type of clock signal line, and the output end of the second type of light-emitting control circuit 230b is electrically connected to the pixel circuit 102 located in the second display partition 100b.

[0082] It should be noted that, in the above embodiment, the first type of clock signal lines and the second type of clock signal lines each include four clock signal lines, each row driving circuit is electrically connected to two clock signal lines, each reset circuit 220 is electrically connected to two clock signal lines, and each of the light emitting control circuits 230 is electrically connected to two clock signal lines. Through this arrangement, the frequency of the clock signal is reduced on the basis of keeping the number of clock signal lines corresponding to the row driving circuit 210 and the reset circuit 220 unchanged, and by doubling the number of clock signals corresponding to the light emitting control circuit 230, the frequency and capacitance of the clock signal corresponding to the light emitting control circuit 230 can be halved, which is conducive to reducing the power consumption of the clock signal corresponding to the driving module 200.

[0083] In some embodiments of the present application, each light emitting control circuit 230 is electrically connected to two clock signal lines.

[0084] In addition, in the above embodiment, the pixel circuit 102 may be a 7T1C, 8T1C or 9T1C circuit, wherein 7T1C is taken as an example, indicating a pixel circuit 102 having 7 thin film transistors and 1 capacitor. Figure 1 As shown, the structure of the pixel circuit 102 of the present application 7T1C is shown, and the pixel circuit 102 includes: a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6 and a second reset transistor T7.

[0085] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present application, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode and the other electrode is called the second electrode. In addition, the gate of the transistor is called the control electrode.

[0086] In addition, transistors can be divided into N-type and P-type according to their characteristics. The following embodiments are described with P-type transistors. When a P-type transistor is used, the first pole is the source of the P-type transistor, the second pole is the drain of the P-type transistor, and when the gate inputs a low level, the source and drain are turned on, and the N-type is the opposite. It can be imagined that the use of N-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the protection scope of the embodiments of the present application.

[0087] Among them, since the transistors used in the embodiments of the present application are all P-type transistors, the working level signal in the embodiments of the present application refers to a low-level signal, and the non-working level signal is a high-level signal.

[0088] Reference Figure 4 As shown, specifically, the control electrode of the driving transistor T1 is connected to the first node Q, and the driving transistor is configured to generate a driving current signal.

[0089] The first electrode of the data writing transistor T2 is connected to the data signal Data, the second electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, and the control electrode of the data writing transistor T2 is connected to the row scanning signal Pscan. The data writing transistor T2 is configured to transmit the data signal Data to the driving transistor T1 in response to the row scanning signal.

[0090] The compensation transistor T3 is a dual-gate transistor, the first electrode of which is connected to the first node Q, the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1, and the control electrode of the compensation transistor T3 is connected to the row scanning signal Pscan. The compensation transistor T3 is configured to reset or threshold compensate the driving transistor T1 in response to the row scanning signal.

[0091] The first reset transistor T4 is a dual-gate transistor, with a first electrode connected to a first initial voltage signal VI1, a second electrode connected to the first node Q, and a control electrode connected to the reset signal. The first reset transistor T4 is configured to reset the potential of the first node Q in response to the reset signal.

[0092] The first electrode of the first light-emitting control transistor T5 is connected to the power signal VDD, the second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1, and the control electrode of the first light-emitting control transistor T5 is connected to the light-emitting control signal EM. The first light-emitting control transistor T5 is configured to transmit the power signal VDD to the driving transistor T1 in response to the light-emitting control signal EM.

[0093] The first electrode of the second light emitting control transistor T6 is connected to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T6 is connected to the input terminal of the organic light emitting diode, and the control electrode of the second light emitting control transistor T6 is connected to the light emitting control signal EM. The second light emitting control transistor T6 is configured to transmit the voltage of the second electrode of the driving transistor T1 to the input terminal of the organic light emitting diode in response to the light emitting control signal EM.

[0094] The first electrode of the second reset transistor T7 is connected to a second initial voltage signal VI2, the second electrode thereof is connected to the input terminal of the organic light emitting diode, and the control electrode of the second reset transistor T7 is connected to the row scanning signal. The second reset transistor T7 is configured to transmit the second initial voltage signal VI2 to the organic light emitting diode in response to the row scanning signal to reset the organic light emitting diode.

[0095] It should be noted that in the circuits provided in the above embodiments of the present application, the nodes do not represent actual components, but rather represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0096] In the above-mentioned pixel circuit 102, referring to Figure 5 As shown in the figure, under low-brightness screen, Pscan is turned on, and Data is written to Q point through T2, T1 and T3. At this time, the potential is recorded as Q0 (voltage is about 2V). Under low-brightness screen, the potential of Q point is higher, and Q point mainly continues to leak to N4 node (VI1 voltage is -3.5V, N4 node voltage is about 0V), so that the potential of Q point continues to decrease to Q1, resulting in the continuous increase of luminous brightness. When the next frame arrives, RST turns on Q point and writes it to VI1 potential first, and then Pscan turns on and rewrites it to Q0 potential.

[0097] In the highlighted screen, Pscan is turned on, and Data is written to the Q point through T2, T1 and T3. At this time, the potential is recorded as Q0" (the voltage is about 0.5V). The potential of the Q point is lower in the highlighted screen, and the Q point mainly continues to leak electricity to the N3 node (the voltage of the N3 node is about 5V), causing the Q point potential to continue to increase to Q1", resulting in the luminous brightness continuing to decrease. When the next frame arrives, RST turns on the Q point and writes it to the VI1 potential first, and then Pscan is turned on and re-written to the Q0" potential.

[0098] In summary, even though T3 and T4 have adopted dual-gate TFTs to reduce leakage, under low refresh rates, i.e., low-frequency images, the potential at the gate Q point of T1 is refreshed for a long period of time, and the Q point will leak electricity to the intermediate nodes N3 and N4 of the dual-gate T3 and T4 through T3 and T4, respectively. This leakage phenomenon is difficult to avoid, so in the related art, it will cause a relatively large change in the luminous current within a frame (large current corresponds to the current drop of the pixel, and small current corresponds to the current increase of the pixel), which is reflected in the large fluctuation of the luminous brightness of the display panel 10 within a frame, and the human eye can see the screen flickering, and the low-frequency display of the display panel 10 cannot be achieved.

[0099] In response to the brightness fluctuation, in the present application, the display panel 10 is divided into two display partitions. In the first display partition 100a, the first row scanning start signal Pscan_STV1 is input to indicate that the first type of row driving circuit 210a starts scanning row by row, the first reset start signal RST_STV1 is input to indicate that the first type of reset circuit 220a starts resetting, and the first light emission control start signal EM_STV1 is input to indicate that the first type of light emission control circuit 230a starts working; in the second display partition 100b, the second row scanning start signal Pscan_STV2 is input to indicate that the second type of row driving circuit 210b starts scanning row by row, and the second reset start signal RST_STV2 is input to indicate that the first type of reset circuit 220a starts resetting. , and by inputting the second light-emitting control start signal EM_STV2, the second type of light-emitting control circuit 230b is instructed to start working, wherein the phase difference between the Pscan_STV2 / RST_STV2 / EM_STV2 signal and the Pscan_STV1 / RST_STV1 / EM_STV1 signal is half a frame. Specifically, the Pscan_STV2 / RST_STV2 / EM_STV2 signal lags behind the Pscan_STV1 / RST_STV1 / EM_STV1 signal by half a frame, so that the pixel rows in the display area displayed by the human eye and the device brightness capture can emit light staggered, that is, the brightness drop of the display picture becomes smaller, thereby improving the screen flicker problem of the display panel 10. At the same time, by using the first type of clock signal to drive the first type of row driving circuit 210a, using the second type of clock signal to drive the first type of reset circuit 220a, and using the third type of clock signal to drive the first type of light-emitting control module in the first display partition 100a, and using the first type of clock signal to drive the first type of reset circuit 220a, using the second type of clock signal to drive the second type of row driving circuit 210b, and using the fourth type of clock signal to drive the first type of light-emitting control module in the second display partition 100b, the number of rows different between the reset circuit 220 and the row driving circuit corresponding to each pixel row remains the same, and the time interval between the row driving circuit and the light-emitting control circuit 230 of the odd pixel rows or the even pixel rows remains unchanged, thereby avoiding an increase in the number of driving modules 200 in the display panel 10, which is beneficial to cost saving.

[0100] Reference Figures 6 to 14 As shown, according to the second aspect of the present application, the present application further provides a method for driving a display panel 10, wherein the display panel 10 includes at least two display partitions, each display partition includes a plurality of pixel rows, the two display areas include a first display partition 100a and a second display partition 100b, and the plurality of pixel rows are driven by a driving module 200 connected to a pixel circuit 102, that is, the driving method can be used to drive the display panel 10 of any of the aforementioned embodiments, and specifically, the driving method includes:

[0101] S1: inputting a first light emission control start signal, a first reset start signal and a first row scanning start signal to the driving module 200 connected to the first pixel row of the first display partition 100a.

[0102] In this step, refer to Figures 6 to 9 As shown, the first pixel row, the second pixel row, the third pixel row and the fourth pixel row in the first display subarea 100a are taken as an example for explanation:

[0103] Reference Figure 8 and Fig. 9 As shown, after the first type of light-emitting control circuit 230a receives the first light-emitting control start signal, the first type of light-emitting control circuit 230a starts to output the first type of light-emitting control signals EM_1&2 (corresponding to the first pixel row and the second pixel row) and EM3&4 (corresponding to the third pixel row and the fourth pixel row) to the first display partition 100a according to the third type of clock signals EM_CK1 and EM_CK2, wherein the period of the third type of clock signal is set to 8H, the light-emitting control signals EM_1&2 start to be emitted under the control of the clock signal EM_CK2, the light-emitting control signals EM_3&4 start to be emitted under the control of the clock signal EM_CK1, and the emission time of the light-emitting control signals EM_3&4 lags behind the emission time of the light-emitting control signals EM_1&2 by 4H.

[0104] Next, refer to Figure 7 and Fig. 9 As shown, the first type of reset circuit 220a will receive a first reset start signal, and under the drive of the second type of clock signals CK7, CK8, CK5 and CK6, the first type of reset circuit 220a will sequentially input the first type of reset signals RST_1, RST_2, RST_3, and RST_4 to the first pixel row, the second pixel row, the third pixel row and the fourth pixel row, wherein the time interval between CK7 and CK8 and the time interval between CK5 and CK6 are both 1H, and the time interval between CK8 and CK5 is 3H.

[0105] Then, refer to Figure 6 and Fig. 9 As shown, the first type of row driving circuit 210a will receive the first row scanning initial signal. Under the drive of the first type of clock signals CK1, CK2, CK3 and CK4, the first row scanning initial signal will input the first type of row driving signals Pscan_1, Pscan_2, Pscan_3 and Pscan_4 to the first pixel row, the second pixel row, the third pixel row and the fourth pixel row in turn, wherein the time interval between CK1 and CK2 and the time interval between CK3 and CK4 are both 1H, and the time interval between CK2 and CK3 is 3H.

[0106] S2: Input a second light emitting control start signal whose phase is half a frame different from the first light emitting control start signal, a second reset start signal whose phase is half a frame different from the first reset start signal, and a second row scanning start signal whose phase is half a frame different from the first row scanning start signal to the driving module 200 connected to the first pixel row of the second display partition 100b.

[0107] In this step, refer to Figures 10 to 13 As shown, the row resolution of the display panel 10 of the present application is N rows, N is an even number, and when the number of pixel rows in the first display partition 100a and the second display partition 100b is the same, the first four pixel rows in the second display partition 100b are recorded as the (N / 2+1)th pixel row, the (N / 2+2)th pixel row, the (N / 2+3)th pixel row, and the (N / 2+4)th pixel row, respectively. In some embodiments, the number of pixel rows included in the first display partition 100a and the second display partition 100b may be different. If the first display partition 100a includes X pixel rows, the first four pixel rows in the second display partition 100b may also be recorded as the (X+1)th pixel row, the (X+2)th pixel row, the (X+3)th pixel row, and the (X+4)th pixel row. The following is an example of the first four pixel rows in the second display partition 100b:

[0108] Reference Fig.12 and Fig.13 As shown, when the second type of light-emitting control circuit 230b receives the second light-emitting control start signal, the second type of light-emitting control circuit 230b starts to output the second type of light-emitting control signals EM_N / 2+1&N / 2+2 and EM_N / 2+3&N / 2+4 to the second display partition 100b according to the fourth type of clock signals EM_CK3 and EM_CK4, wherein the period of the fourth type of clock signal is set to 8H, the light-emitting control signals EM_N / 2+1&N / 2+2 are started to be emitted under the control of the clock signal EM_CK4, the light-emitting control signals EM_N / 2+3&N / 2+4 are started to be emitted under the control of the clock signal EM_CK3, and the emission time of the light-emitting control signals EM_N / 2+3&N / 2+4 lags behind the emission time of the light-emitting control signals EM_N / 2+1&N / 2+2 by 4H.

[0109] Next, refer to Fig.11 and Fig.13As shown, the first type reset circuit 220a will receive a second reset start signal, and under the drive of the first type clock signals CK1, CK2, CK3 and CK4, the first type reset circuit 220a will sequentially input the second type reset signals RST_N / 2+1, RST_N / 2+2, RST_N / 2+3, and RST_N / 2+4 to the (N / 2+1)th pixel row, the (N / 2+2)th pixel row, the (N / 2+3)th pixel row and the (N / 2+4)th pixel row, wherein the time interval between CK1 and CK2 and the time interval between CK3 and CK4 are both 1H, and the time interval between CK2 and CK3 is 3H.

[0110] Then, refer to Fig.10 and Fig.13 As shown, the second type of row driving circuit 210b will receive the second row scanning initial signal, and under the drive of the second type of clock signals CK5, CK6, CK7 and CK8, the second row scanning initial signal will successively input the second type of row driving signals Pscan_1, Pscan_2, Pscan_3 and Pscan_4 to the (N / 2+1)th pixel row, the (N / 2+2)th pixel row, the (N / 2+3)th pixel row and the (N / 2+4)th pixel row, wherein the time interval between CK5 and CK6 and the time interval between CK7 and CK8 are both 1H, and the time interval between CK6 and CK7 is 3H.

[0111] It should be noted that, in the above embodiment, the row scan signal connected to any pixel row is controlled to be delayed by 1H compared to the reset signal connected to the same pixel row. It can be understood that the row scan signal includes a first type of row scan signal and a second type of row scan signal, and the reset signal includes a first type of reset signal and a second type of reset signal.

[0112] Reference Fig.14 As shown in FIG. 1 , it is a timing diagram of the reset signal and the scan signal of the first display partition 100a and the second display partition 100b of the present application. Through the above configuration, the pixel rows in the display area can emit light separately. The actual light emission sequence is as follows: Fig.14As shown, the first pixel row, the second pixel row, the (N / 2+1)th pixel row, the (N / 2+2)th pixel row, the third pixel row, the fourth pixel row, the (N / 2+3)th pixel row and the (N / 2+4)th pixel row... and so on. In order to keep the number of rows different between the reset signal and the row scan signal of each row of sub-pixels 101 the same and the time interval between the odd or even rows to the row scan signal and the light-emitting control signal remains unchanged, the moment when the first pixel row of the second display partition 100b is connected to the second type of reset signal lags behind the moment when the first pixel of the first display partition 100a is connected to the first type of reset signal by twice the horizontal scanning period; similarly, the moment when the first pixel row of the second display partition 100b is connected to the second type of row scan signal lags behind the moment when the first pixel of the first display partition 100a is connected to the first type of row scan signal by twice the horizontal scanning period. It should be noted that the periods of all the above clock signals can be controlled and changed by a timing controller connected to the display panel 10, and the specific change method is a commonly used method in the art, so the embodiment of the present application will not be described in detail.

[0113] In the above embodiment, the period of the first type of clock signal and the period of the second type of clock signal are both 4H, that is, four times the horizontal scanning period, and the period of the third type of clock signal and the period of the fourth type of clock signal are both 8H, eight times the horizontal scanning period. Compared with the display panel 10 in the related art, the period of the light emitting control circuit 230 of the display panel 10 of the present application is larger, so that the actual light emitting time of the display area can be prolonged. Combined with the staggered light emitting setting of the pixel rows of the display panel 10, the brightness fluctuation of the display panel 10 within a frame can be smoother, that is, the screen flickering problem of the display panel 10 can be improved, thereby realizing the low-frequency display of the display panel 10. The effect achieved by the present application will be described in detail in conjunction with the accompanying drawings.

[0114] Reference Fig.15 As shown, it is a brightness change diagram of the sub-pixel 101 in the related technology, and the maximum value of the row luminous brightness Lv is defined as Lmax, the minimum value is Lmin, and the middle value Lmid is approximately recorded as (Lmax+Lmin) / 2. Then, in one frame, at time T1, the brightness perceived by the human eye or captured by the device is L=(L1+L2) / 2=(Lmin+Lmin) / 2=Lmin; at time T2, the brightness perceived by the human eye or captured by the device is L”=(L1”+L2”) / 2=(Lmax+Lmax) / 2=Lmax; therefore, the brightness difference from time T1 to time T2 is △L=L”-L=Lmax-Lmin.

[0115] Reference Fig.16As shown, this is the brightness change diagram of the sub-pixel 101 in the present application. Similarly, the maximum value of the row luminous brightness Lv is defined as Lmax, the minimum value is Lmin, and the middle value Lmid is approximately recorded as (Lmax+Lmin) / 2. Then, in one frame, at time T1, the brightness perceived by the human eye or captured by the device is L=(L1+L2+L3+L4) / 4=(Lmin+Lmin+Lmax+Lmax) / 4=Lmax / 2+Lmin / 2; at time T2, the brightness perceived by the human eye or captured by the device is L”=(L1”+L2”+L3”+L4”) / 4=(Lmax+Lmax+Lmid+Lmid) / 4=Lmax / 2+Lmid / 2; therefore, the brightness difference from time T1 to time T2 is △L=L”-L=(Lmax-Lmin) / 4. By comparison, it can be seen that the brightness difference of the sub-pixel 101 of the present application is reduced by 75% compared with the brightness difference of the sub-pixel 101 in the related art, which can effectively reduce the brightness drop of the display area and greatly improve the screen flicker problem under low frequency. And from the waveform diagram, it can be seen that the row drive circuit 210 and the reset circuit 220 in the present application have a total of 8 CKs and the period is increased to 7H, that is, the frequency is reduced to 4 / 7 times of the original, which also improves the power consumption of the display panel 10 to a certain extent.

[0116] Specifically, when the present application adopts the EM one-drive-two architecture, the power consumption can be further reduced compared to the EM one-drive-one architecture. Fig.17 As shown, assuming that the capacitance of a single driving unit composed of a single row driving circuit and a single reset circuit 220 is C0, and the capacitance of a single light-emitting control circuit 230 is C1, the power consumption caused by C0 in the display panel 10 of the present application is reduced by 42.86% compared with the power consumption caused by C0 in the related art, and the power consumption caused by C1 in the display panel 10 of the present application is reduced by 50% compared with the power consumption caused by C1 in the related art.

[0117] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A display panel, characterized in that: include: The display area includes at least a first display subarea and a second display subarea; A pixel array is arranged in the display area; wherein each display subarea includes a plurality of pixel rows, each of the pixel rows includes a plurality of sub-pixels and a plurality of pixel circuits, and each of the sub-pixels is electrically connected to one of the pixel circuits; and A driving module, used for inputting a driving signal to the pixel circuit; The driving module connected to the first pixel row of the first display partition receives a first light emission control start signal, a first reset start signal and a first row scanning start signal; The driving module connected to the first pixel row of the second display partition is connected to a second light-emitting control start signal whose phase is half a frame different from that of the first light-emitting control start signal, a second reset start signal whose phase is half a frame different from that of the first reset start signal, and a second row scanning start signal whose phase is half a frame different from that of the first row scanning start signal.

2. The display panel according to claim 1, characterized in that: The driving module comprises: A plurality of row driving circuits, each of which is connected to one of the pixel rows, and the plurality of row driving circuits comprises: a first type of row driving circuit, wherein an input end of the first type of row driving circuit is electrically connected to a first type of clock signal line, and an output end of the first type of row driving circuit is electrically connected to a pixel circuit located in the first display subarea; and The second type of row driving circuit, the input end of the second type of row driving circuit is electrically connected to the second type of clock signal line, and the output end of the second type of row driving circuit is electrically connected to the pixel circuit located in the second display partition.

3. The display panel according to claim 2, characterized in that: The driving module further includes: A plurality of reset circuits, each reset circuit being connected to one of the pixel rows, the plurality of reset circuits comprising: a first type reset circuit, wherein an input end of the first type reset circuit is electrically connected to the second type clock signal line, and an output end of the first type reset circuit is electrically connected to a pixel circuit located in the first display partition; and A second type reset circuit, wherein the input end of the second type reset circuit is electrically connected to the first type clock signal line, and the output end of the second type reset circuit is electrically connected to the pixel circuit located in the second display partition.

4. The display panel according to claim 3, characterized in that: The first type of clock signal lines and the second type of clock signal lines each include four clock signal lines, each of the row driving circuits is electrically connected to two clock signal lines, and each of the reset circuits is electrically connected to two clock signal lines.

5. The display panel according to any one of claims 1 to 4, characterized in that: The driving module further includes: A plurality of light emitting control circuits, each of which is connected to one of the pixel rows; or Each of the light emitting control circuits is connected to two adjacent pixel rows.

6. The display panel according to claim 5, characterized in that: The plurality of light emitting control circuits include: A first type of light emitting control circuit, wherein an input end of the first type of light emitting control circuit is electrically connected to a third type of clock signal line, and an output end of the first type of light emitting control circuit is electrically connected to a pixel circuit located in the first display partition; The second type of light emitting control circuit, the input end of the second type of light emitting control circuit is electrically connected to the fourth type of clock signal line, and the output end of the second type of light emitting control circuit is electrically connected to the pixel circuit located in the second display partition.

7. The display panel according to claim 5, characterized in that: Each of the light emitting control circuits is electrically connected to two clock signal lines.

8. A method for driving a display panel, characterized in that: The display panel comprises at least two display partitions, each of the display partitions comprises a plurality of pixel rows, the two display areas comprise a first display partition and a second display partition, and the plurality of pixel rows are driven by a driving module connected to the pixel circuit; The driving method comprises: Inputting a first light emission control start signal, a first reset start signal and a first row scanning start signal to a driving module connected to a first pixel row of the first display partition; A second light-emitting control start signal whose phase is half a frame different from that of the first light-emitting control start signal, a second reset start signal whose phase is half a frame different from that of the first reset start signal, and a second row scan start signal whose phase is half a frame different from that of the first row scan start signal are input to a driving module connected to the first pixel row of the second display partition.

9. The driving method according to claim 8, characterized in that: The driving method further includes: outputting a first type of row scanning signal to the first display partition according to a first type of clock signal; outputting a first type of reset signal to the first display partition according to a second type of clock signal; A first type of light emitting control signal is output to the first display partition according to a third type of clock signal.

10. The driving method according to claim 9, characterized in that: The driving method further includes: outputting a second type of reset signal to the second display partition according to the first type of clock signal; outputting a second type of row scanning signal to the second display partition according to the second type of clock signal; The second type light emitting control signal is output to the second display partition according to the fourth type clock signal.

11. The driving method according to claim 10, characterized in that: The driving method further includes: The period of the first-type clock signal and the period of the second-type clock signal are controlled to be four times of the horizontal scanning period.

12. The driving method according to claim 10, characterized in that: The driving method further includes: The period of the third type of clock signal and the period of the fourth type of clock signal are both controlled to be eight times of the horizontal scanning period.

13. The driving method according to claim 10, characterized in that: The driving method further includes: Control the row scanning signal connected to any pixel row to be delayed by one horizontal scanning cycle time compared to the reset signal connected to the same pixel row; The row scanning signals include the first type of row scanning signals and the second type of row scanning signals, and the reset signals include the first type of reset signals and the second type of reset signals.

14. The driving method according to claim 10, characterized in that: Control the moment when the first pixel row of the second display partition is connected to the second type of reset signal to lag behind the moment when the first pixel of the first display partition is connected to the first type of reset signal by twice the horizontal scanning period; The moment when the first pixel row of the second display partition is connected to the second type of row scanning signal is controlled to lag behind the moment when the first pixel row of the first display partition is connected to the first type of row scanning signal by twice the horizontal scanning period.

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