Display panel and its driving method

Abstract

This application provides a display panel and its driving method. The display panel includes at least a first display zone and a second display zone. Each display zone includes multiple pixel rows, which are driven by a driving module connected to pixel circuits. The driving method includes inputting a first light emission control start signal, a first reset start signal, and a first line scan start signal to a driving module connected to the first pixel row of the first display zone; and inputting a second light emission control start signal, a second reset start signal, and a second line scan start signal that are phase-differentiated by half a frame from the first light emission control start signal, half a frame from the first reset start signal, and half a frame from the first line scan start signal to a driving module connected to the first pixel row of the second display zone. This application improves screen flicker in low-frequency scenes by controlling the staggered light emission of pixel rows, thereby increasing the actual light emission time of the display area and reducing brightness drop.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and its driving method. Background Technology

[0002] In the pixel circuits of some low-temperature polycrystalline silicon organic light-emitting diode (LTPS OLED) display panels, some P-type thin-film transistors are often used, but these P-type thin-film transistors will cause leakage current, resulting in a large current drop.

[0003] In related technologies, some P-type thin-film transistors, such as compensation transistors and reset transistors, are replaced with dual-gate thin-film transistors to reduce leakage current. However, in low-frequency images with low refresh rates, the gate voltage of the driving transistor in the pixel circuit may remain in a certain state for a long time. Since the compensation transistor and reset transistor are electrically connected to the gate of the driving transistor, leakage current will continuously accumulate at the middle node of the dual-gate thin-film transistor, resulting in a large change in the luminous current within a frame. This manifests as a large fluctuation in the luminous brightness within a frame, producing visible screen flicker. Summary of the Invention

[0004] Embodiments of this application provide a display panel and its driving method to solve the problem of screen flickering in low-frequency images in related technologies.

[0005] To solve the above problems, the technical solution provided in this application is as follows:

[0006] In a first aspect, this application provides a display panel, comprising:

[0007] The display area includes at least a first display partition and a second display partition;

[0008] A pixel array is disposed in the display area; wherein each display area includes multiple pixel rows, each pixel row includes multiple sub-pixels and multiple pixel circuits, and each sub-pixel is electrically connected to one of the pixel circuits; and

[0009] The driving module is used to input driving signals to the pixel circuit;

[0010] Among them, the driving module connected to the first pixel row of the first display partition is connected to the first light emission control start signal, the first reset start signal and the first row scan start signal;

[0011] The driving module connected to the first pixel row of the second display partition receives a second light emission control start signal that is half a frame out of phase with the first light emission control start signal, a second reset start signal that is half a frame out of phase with the first reset start signal, and a second line scan start signal that is half a frame out of phase with the first line scan start signal.

[0012] In one embodiment, the driving module further includes:

[0013] Multiple row driving circuits, each of which is connected to one of the pixel rows, the multiple row driving circuits comprising:

[0014] A first type of row driving circuit, wherein the input terminal of the first type of row driving circuit is electrically connected to a first type of clock signal line, and the output terminal of the first type of row driving circuit is electrically connected to a pixel circuit located in the first display partition; and

[0015] The second type of row driving circuit has its input terminal electrically connected to the second type of clock signal line, and its output terminal electrically connected to the pixel circuit located in the second display partition.

[0016] In one embodiment, the driving module further includes:

[0017] Multiple reset circuits, each connected to one of the pixel rows, the multiple reset circuits comprising:

[0018] A first type of reset circuit, wherein the input terminal of the first type of reset circuit is electrically connected to the second type of clock signal line, and the output terminal of the first type of reset circuit is electrically connected to the pixel circuit located in the first display partition; and

[0019] The second type of reset circuit has its input terminal electrically connected to the first type of clock signal line, and its output terminal electrically connected to the pixel circuit located in the second display partition.

[0020] In one embodiment, the driving module further includes:

[0021] Multiple light-emitting control circuits, each of which is connected to one of the pixel rows; or

[0022] Each of the light-emitting control circuits is connected to two adjacent rows of pixels.

[0023] In one embodiment, the plurality of light-emitting control circuits include:

[0024] The first type of light-emitting control circuit has its input terminal electrically connected to the third type of clock signal line, and its output terminal electrically connected to the pixel circuit located in the first display partition.

[0025] The second type of light-emitting control circuit has its input terminal electrically connected to the fourth type of clock signal line, and its output terminal electrically connected to the pixel circuit located in the second display partition.

[0026] In one embodiment, both the first type of clock signal line and the second type of clock signal line include four clock signal lines, each of the row driving circuits is electrically connected to two clock signal lines, and each of the reset circuits is electrically connected to two clock signal lines.

[0027] Secondly, this application provides a method for driving a display panel, comprising:

[0028] The display panel includes at least two display zones, each display zone including multiple pixel rows, and the two display zones include a first display zone and a second display zone;

[0029] The driving method includes:

[0030] A first light emission control start signal, a first reset start signal, and a first line scan start signal are input to the first pixel row of the first display partition;

[0031] A second light emission control start signal that is half a frame out of phase with the first light emission control start signal, a second reset start signal that is half a frame out of phase with the first reset start signal, and a second line scan start signal that is half a frame out of phase with the first line scan start signal are input to the first pixel row of the second display partition.

[0032] In one embodiment, the driving method further includes:

[0033] A first type of row scan signal is output to the first display partition according to the first type of clock signal;

[0034] A first type of reset signal is output to the first display partition according to the second type of clock signal;

[0035] The first type of light emission control signal is output to the first display partition according to the third type of clock signal.

[0036] In one embodiment, the driving method further includes:

[0037] A second type of reset signal is output to the second display partition according to the first type of clock signal;

[0038] A second type of row scan signal is output to the second display partition according to the second type of clock signal;

[0039] The second type of light control signal is output to the second display partition according to the fourth type of clock signal.

[0040] In one embodiment, the driving method further includes:

[0041] The period of the first type of clock signal and the period of the second type of clock signal are both controlled to be four times the horizontal scan period.

[0042] In one embodiment, the driving method further includes:

[0043] The period of the third type of clock signal and the period of the fourth type of clock signal are both controlled to be eight times the horizontal scan period.

[0044] In one embodiment, the driving method further includes:

[0045] The row scan signal that is controlled to be connected to any pixel row is delayed by one horizontal scan cycle time compared to the reset signal connected to the same pixel row;

[0046] The row scan signal includes the first type of row scan signal and the second type of row scan signal, and the reset signal includes the first type of reset signal and the second type of reset signal.

[0047] In one embodiment, the timing of the first pixel row of the second display partition being connected to the second type of reset signal is delayed by twice the horizontal scan cycle from the timing of the first pixel of the first display partition being connected to the first type of reset signal.

[0048] The timing of the first pixel row of the second display partition being connected to the second type of line scan signal is delayed by twice the horizontal scan cycle from the timing of the first pixel row of the first display partition being connected to the first type of line scan signal.

[0049] This application provides a display panel comprising: a pixel array, the pixel array including at least two display partitions, each display partition including multiple pixel rows, each pixel row including multiple sub-pixels and multiple pixel circuits, each sub-pixel being electrically connected to one of the pixel circuits; and a driving module for inputting driving signals to the pixel circuits; wherein the two display partitions include a first display partition and a second display partition, the driving module connected to the first pixel row of the first display partition is connected to a first light emission control start signal, a first reset start signal, and a first line scan start signal; the driving module connected to the first pixel row of the second display partition is connected to a second light emission control start signal that is half a frame out of phase with the first light emission control start signal, a second reset start signal that is half a frame out of phase with the first reset start signal, and a second line scan start signal that is half a frame out of phase with the first line scan start signal. Through the above solution, this application enables staggered light emission of pixels in the display area, thereby increasing the actual light emission time and reducing brightness drop in the display area, thus improving screen flicker problems in low-frequency scenes. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Appendix Figure 1 This is a schematic diagram of the architecture of an optional display panel in an embodiment of this application;

[0052] Appendix Figure 2 This is a schematic diagram of the architecture of another optional display panel in the embodiments of this application;

[0053] Appendix Figure 3 This is a schematic diagram of the structure of an optional display panel in an embodiment of this application;

[0054] Appendix Figure 4 This is a schematic diagram of an optional pixel circuit in an embodiment of this application;

[0055] Appendix Figure 5 Based on Figure 4 A schematic diagram of the timing of pixel circuitry, i.e., the change in light emission brightness;

[0056] Appendix Figure 6 This is a timing diagram of the first type of row driving circuit in the embodiments of this application;

[0057] Appendix Figure 7 This is a timing diagram of the first type of reset circuit in the embodiments of this application;

[0058] Appendix Figure 8 This is a timing diagram of the first type of light-emitting control circuit in this application;

[0059] Appendix Figure 9 This is a timing diagram of the overall operation of the first display partition in this embodiment of the application;

[0060] Appendix Figure 10 This is a timing diagram of the second type of row driving circuit in the embodiments of this application;

[0061] Appendix Figure 11 This is a timing diagram of the second type of reset circuit in the embodiments of this application;

[0062] Appendix Figure 12 This is a timing diagram of the second type of light-emitting control circuit in the embodiments of this application;

[0063] Appendix Figure 13 This is a timing diagram of the overall operation of the second display partition in this embodiment of the application;

[0064] Appendix Figure 14 This is a timing diagram of the overall operation of the display panel in the embodiments of this application;

[0065] Appendix Figure 15 This is a graph showing the brightness variation of pixel rows in related technologies;

[0066] Appendix Figure 16 This is a brightness variation diagram of pixel rows in an embodiment of this application;

[0067] Appendix Figure 17 This is a comparison chart of the power consumption of the display panel in the embodiments of this application.

[0068] Explanation of the reference numerals in the figure:

[0069] 10. Display panel;

[0070] 100, Pixel array; 100a, First display zone; 100b, Second display zone; 101, Subpixel; 102, Pixel circuit;

[0071] 200. Driver module; 210. Horizontal drive circuit; 210a. Type I horizontal drive circuit; 210b. Type II horizontal drive circuit; 220. Reset circuit; 220a. Type I reset circuit; 220b. Type II reset circuit; 230. Light emission control circuit; 230a. Type I light emission control circuit; 230b. Type II light emission control circuit. Detailed Implementation

[0072] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0073] Furthermore, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms "multiple" and similar words indicate two or more unless otherwise expressly specified.

[0074] Reference Figures 1 to 4 As shown, according to a first aspect of this application, this application provides a display panel 10, including a pixel array 100 and a driving module 200, wherein the pixel array 100 includes at least two display partitions, each display partition includes multiple pixel rows, each pixel row includes multiple sub-pixels 101 and multiple pixel circuits 102, and each sub-pixel 101 is electrically connected to a pixel circuit 102.

[0075] The driving module 200 is used to input driving signals to the pixel circuit 102. Specifically, in some embodiments of this application, the driving module 200 includes multiple row driving circuits 210, multiple reset circuits 220, and multiple light-emitting driving circuits. Each row driving circuit 210 is connected to the pixel circuit 102 of one pixel row, and each reset circuit 220 is also connected to the pixel circuit 102 of one pixel row. Furthermore, referring to... Figure 1 As shown, in some embodiments, the display panel 10 of this application can be an EM-driver-emulator architecture, that is, each light-emitting driving circuit of this application can be connected to a pixel row; or refer to Figure 2 As shown, the display panel 10 of this application can also be an EM-driven dual-architecture, meaning that each light-emitting driving circuit of this application can connect to two adjacent pixel rows. Using an EM-driven dual-architecture display panel 10 is beneficial for reducing the CK frequency of the display panel 10 and also for enabling the display panel 10 to achieve a low refresh rate display. Meanwhile, in this embodiment, to reduce the power consumption of the display panel 10, a left-right driven architecture display panel 10 can also be used. In subsequent embodiments, this application will describe a display panel 10 with an EM-driven dual-architecture.

[0076] Specifically, the two display partitions include a first display partition 100a and a second display partition 100b. In some embodiments, the number of pixel rows in the first display partition 100a and the second display partition 100b is the same. The driving module 200 connected to the first pixel row of the first display partition 100a is connected to a first light emission control start signal, a first reset start signal and a first line scan start signal.

[0077] The driving module 200, which is connected to the first pixel row of the second display partition 100b, receives a second light emission control start signal that is half a frame out of phase with the first light emission control start signal, a second reset start signal that is half a frame out of phase with the first reset start signal, and a second line scan start signal that is half a frame out of phase with the first line scan start signal.

[0078] With the above settings, this application can stagger the light distribution of pixels in the display area, thereby reducing brightness drops and avoiding screen flicker.

[0079] Reference Figure 3 As shown, more specifically, in some embodiments of this application, the plurality of line driving circuits 210 include a first type of line driving circuit 210a and a second type of line driving circuit 210b, wherein the input terminal of the first type of line driving circuit 210a is electrically connected to a first type of clock signal line, and the output terminal of the first type of line driving circuit 210a is electrically connected to the pixel circuit 102 located in the first display partition 100a; the input terminal of the second type of line driving circuit 210b is electrically connected to a second type of clock signal line, and the output terminal of the second type of line driving circuit 210b is electrically connected to the pixel circuit 102 located in the second display partition 100b.

[0080] In some embodiments of this application, the plurality of reset circuits 220 include a first type of reset circuit 220a and a second type of reset circuit 220b. The input terminal of the first type of reset circuit 220a is electrically connected to a second type of clock signal line, and the output terminal of the first type of reset circuit 220a is electrically connected to the pixel circuit 102 located in the first display partition 100a. The input terminal of the first type of reset circuit 220a is electrically connected to the first type of clock signal line, and the output terminal of the first type of reset circuit 220a is electrically connected to the pixel circuit 102 located in the second display partition 100b.

[0081] In some embodiments of this application, the plurality of light-emitting control circuits 230 include a first type of light-emitting control circuit 230a and a second type of light-emitting control circuit 230b. The input terminal of the first type of light-emitting control circuit 230a is electrically connected to a third type of clock signal line, and the output terminal of the first type of light-emitting control circuit 230a is electrically connected to the pixel circuit 102 located in the first display partition 100a. The input terminal of the second type of light-emitting control circuit 230b is electrically connected to a fourth type of clock signal line, and the output terminal of the second type of light-emitting control circuit 230b is electrically connected to the pixel circuit 102 located in the second display partition 100b.

[0082] It should be noted that in the above embodiments, both the first type of clock signal line and the second type of clock signal line include four clock signal lines. Each row driving circuit is electrically connected to two clock signal lines, each reset circuit 220 is electrically connected to two clock signal lines, and each of the light-emitting control circuits 230 is electrically connected to two clock signal lines. With this configuration, while keeping the number of clock signal lines corresponding to the row driving circuit 210 and the reset circuit 220 constant, the frequency of the clock signal is reduced. Furthermore, by doubling the number of clock signals corresponding to the light-emitting control circuit 230, the frequency and capacitance of the clock signal corresponding to the light-emitting control circuit 230 can be halved, which helps to reduce the power consumption of the clock signal corresponding to the driving module 200.

[0083] In some embodiments of this application, each light-emitting control circuit 230 is electrically connected to two clock signal lines.

[0084] Furthermore, in the above embodiments, the pixel circuit 102 can be a 7T1C, 8T1C, or 9T1C circuit, with 7T1C as an example, representing a pixel circuit 102 having 7 thin-film transistors and 1 capacitor. Specifically, refer to... Figure 1 The image shows the structure of the pixel circuit 102 of this application 7T1C. The pixel circuit 102 includes: a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a second reset transistor T7.

[0085] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between their source and drain. In the embodiments of this application, to distinguish between the source and drain of the transistor, one of them is called the first electrode, and the other is called the second electrode. In addition, the gate of the transistor is called the control electrode.

[0086] Furthermore, transistors can be classified into N-type and P-type based on their characteristics. The following embodiments are illustrated using P-type transistors. When using a P-type transistor, the first electrode is the source, and the second electrode is the drain. When the gate input is low, the source and drain are conducting. The opposite is true for N-type transistors. It is conceivable that using an N-type transistor is something that those skilled in the art can easily conceive of without inventive effort, and therefore falls within the scope of protection of the embodiments in this application.

[0087] Since the transistors used in this embodiment are all P-type transistors, the working level signal in this embodiment refers to a low level signal, and the non-working level signal refers to a high level signal.

[0088] Reference Figure 4 As shown, specifically, the control electrode of the driving transistor T1 is connected to the first node Q, and the driving transistor is configured to generate a driving current signal.

[0089] The first terminal of the data writing transistor T2 is connected to the data signal Data, the second terminal of the data writing transistor T2 is electrically connected to the first terminal of the driving transistor T1, and the control terminal of the data writing transistor T2 is connected to the row scan signal Pscan. The data writing transistor T2 is configured to transmit the data signal Data to the driving transistor T1 in response to the row scan signal.

[0090] The compensation transistor T3 is a dual-gate transistor, with its first terminal connected to the first node Q and its second terminal connected to the second terminal of the driving transistor T1. The control terminal of the compensation transistor T3 is connected to the row scan signal Pscan. The compensation transistor T3 is configured to reset or perform threshold compensation on the driving transistor T1 in response to the row scan signal.

[0091] The first reset transistor T4 is a dual-gate transistor, with its first terminal connected to a first initial voltage signal VI1, its second terminal connected to the first node Q, and its control terminal connected to a reset signal. The first reset transistor T4 is configured to reset the potential of the first node Q in response to the reset signal.

[0092] The first terminal of the first light-emitting control transistor T5 is connected to the power supply signal VDD, the second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T1, and the control terminal of the first light-emitting control transistor T5 is connected to the light-emitting control signal EM. The first light-emitting control transistor T5 is configured to transmit the power supply signal VDD to the driving transistor T1 in response to the light-emitting control signal EM.

[0093] The first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T1. The second terminal of the second light-emitting control transistor T6 is connected to the input terminal of the organic light-emitting diode (OLED). The control terminal of the second light-emitting control transistor T6 is connected to the light-emitting control signal EM. The second light-emitting control transistor T6 is configured to transmit the voltage of the second terminal of the driving transistor T1 to the input terminal of the OLED in response to the light-emitting control signal EM.

[0094] The first terminal of the second reset transistor T7 is connected to a second initial voltage signal VI2, and its second terminal is connected to the input terminal of the organic light-emitting diode (OLED). The control terminal of the second reset transistor T7 is connected to a horizontal scan signal. The second reset transistor T7 is configured to transmit the second initial voltage signal VI2 to the OLED in response to the horizontal scan signal to reset the OLED.

[0095] It should be noted that in the circuits provided in the above embodiments of this application, nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0096] In the pixel circuit 102 described above, refer to Figure 5 As shown, in low-brightness conditions, Pscan is enabled, and Data is written to point Q via T2, T1, and T3, at which point the potential is recorded as Q0 (voltage approximately 2V). In low-brightness conditions, the potential of point Q is relatively high, and point Q primarily leaks current to node N4 (VI1 voltage is -3.5V, and node N4 voltage is approximately 0V), causing the potential of point Q to continuously decrease to Q1, resulting in a continuous increase in luminous intensity. When the next frame arrives, RST is enabled, and point Q is first written to potential VI1, then Pscan is enabled again, and the data is rewritten to potential Q0.

[0097] In a bright scene, Pscan is activated, and Data is written to point Q via T2, T1, and T3, at which point the potential is recorded as Q0 (voltage approximately 0.5V). Under bright conditions, the potential at point Q is low, and point Q primarily leaks current to node N3 (node ​​N3 voltage approximately 5V), causing the potential at point Q to continuously rise to Q1, resulting in a continuous decrease in luminous intensity. When the next frame arrives, RST is activated, and point Q is first written to potential VI1, then Pscan is activated again, and the data is rewritten to potential Q0.

[0098] In summary, even though T3 and T4 employ dual-gate TFTs to reduce leakage current, at low refresh rates (i.e., low-frequency displays), the Q-point potential of the T1 gate is refreshed over a long period. This causes leakage from the Q-point to the intermediate nodes N3 and N4 of the dual-gate T3 and T4, respectively. This leakage is difficult to avoid, resulting in significant variations in the luminous current within a frame (larger current corresponds to a drop in pixel current, and smaller current corresponds to a rise in pixel current). This manifests as large fluctuations in the brightness of the display panel 10 within a frame, resulting in visible screen flicker and hindering the low-frequency display capability of the display panel 10.

[0099] To address this brightness fluctuation, this application divides the display panel 10 into two display zones. In the first display zone 100a, the first type of line drive circuit 210a is instructed to start line-by-line scanning by inputting the first line scan start signal Pscan_STV1, the first type of reset circuit 220a is instructed to start reset operation by inputting the first reset start signal RST_STV1, and the first type of light emission control circuit 230a is instructed to start operation by inputting the first light emission control start signal EM_STV1. In the second display zone 100b, the second type of line drive circuit 210b is instructed to start line-by-line scanning by inputting the second line scan start signal Pscan_STV2, and the first type of reset circuit 220a is instructed to start reset operation by inputting the second reset start signal RST_STV2. The second type of light emission control circuit 230b is instructed to start working by inputting the second light emission control start signal EM_STV2. The Pscan_STV2 / RST_STV2 / EM_STV2 signal and the Pscan_STV1 / RST_STV1 / EM_STV1 signal are out of phase by half a frame. Specifically, the Pscan_STV2 / RST_STV2 / EM_STV2 signal lags behind the Pscan_STV1 / RST_STV1 / EM_STV1 signal by half a frame, so that the pixel rows in the display area visible to the human eye and the brightness capture of the device can emit light in a staggered manner, that is, the brightness drop of the display screen is reduced, and the screen flicker problem of the display panel 10 is improved. Meanwhile, by using a first type of clock signal to drive the first type of row driving circuit 210a, a second type of clock signal to drive the first type of reset circuit 220a, and a third type of clock signal to drive the first type of light emission control module in the first display partition 100a, and using a first type of clock signal to drive the first type of reset circuit 220a, a second type of clock signal to drive the second type of row driving circuit 210b, and a fourth type of clock signal to drive the first type of light emission control module in the second display partition 100b, the number of rows between the reset circuit 220 and the row driving circuit corresponding to each pixel row remains the same, and the time interval between the row driving circuit and the light emission control circuit 230 of odd-numbered or even-numbered pixel rows remains unchanged, thus avoiding increasing the number of driving modules 200 in the display panel 10 and saving costs.

[0100] Reference Figures 6 to 14 As shown, according to a second aspect of this application, this application also provides a driving method for a display panel 10, wherein the display panel 10 includes at least two display zones, each display zone including multiple pixel rows, the two display zones including a first display zone 100a and a second display zone 100b, and the multiple pixel rows are driven by a driving module 200 connected to a pixel circuit 102. That is, this driving method can be used to drive the display panel 10 of any of the foregoing embodiments. Specifically, the driving method includes:

[0101] S1: Input a first light emission control start signal, a first reset start signal, and a first line scan start signal to the drive module 200 connected to the first pixel row of the first display partition 100a.

[0102] In this step, refer to Figures 6 to 9 As shown, the first pixel row, second pixel row, third pixel row, and fourth pixel row in the first display partition 100a are used as examples for illustration:

[0103] Reference Figure 8 and Figure 9 As shown, when the first type of light emission control circuit 230a receives the first light emission control start signal, the first type of light emission control circuit 230a starts to output the first type of light emission control signals EM_1&2 (corresponding to the first pixel row and the second pixel row) and EM3&4 (corresponding to the third pixel row and the fourth pixel row) to the first display partition 100a according to the third type of clock signals EM_CK1 and EM_CK2. The period of the third type of clock signal is set to 8H. The light emission control signal EM_1&2 is controlled by the clock signal EM_CK2 to start being emitted, and the light emission control signal EM_3&4 is controlled by the clock signal EM_CK1 to start being emitted. The emission time of the light emission control signal EM_3&4 is delayed by 4H compared with the emission time of the light emission control signal EM_1&2.

[0104] Next, refer to Figure 7 and Figure 9 As shown, the first type of reset circuit 220a receives the first reset start signal. Driven by the second type of clock signals CK7, CK8, CK5 and CK6, the first type of reset circuit 220a sequentially inputs the first type of reset signals RST_1, RST_2, RST_3 and RST_4 to the first pixel row, the second pixel row, the third pixel row and the fourth pixel row. The time interval between CK7 and CK8 and the time interval between CK5 and CK6 are both 1H, and the time interval between CK8 and CK5 is 3H.

[0105] Then, refer to Figure 6 and Figure 9 As shown, the first type of row driving circuit 210a receives the first row scan initial signal. Driven by the first type of clock signals CK1, CK2, CK3 and CK4, the first row scan initial signal will sequentially input the first type of row driving signals Pscan_1, Pscan_2, Pscan_3 and Pscan_4 to the first pixel row, the second pixel row, the third pixel row and the fourth pixel row. The time interval between CK1 and CK2 and the time interval between CK3 and CK4 are both 1H, and the time interval between CK2 and CK3 is 3H.

[0106] S2: Input a second light emission control start signal that is half a frame out of phase with the first light emission control start signal, a second reset start signal that is half a frame out of phase with the first reset start signal, and a second line scan start signal that is half a frame out of phase with the first line scan start signal to the drive module 200 connected to the first pixel row of the second display partition 100b.

[0107] In this step, refer to Figures 10 to 13 As shown, the row resolution of the display panel 10 in this application is denoted as N rows, where N is an even number. When the number of pixel rows in the first display partition 100a and the second display partition 100b is the same, the first four pixel rows in the second display partition 100b are sequentially denoted as the (N / 2+1)th pixel row, the (N / 2+2)th pixel row, the (N / 2+3)th pixel row, and the (N / 2+4)th pixel row. In some embodiments, the number of pixel rows in the first display partition 100a and the second display partition 100b may be different. If the first display partition 100a contains X pixel rows, then the first four pixel rows in the second display partition 100b can also be denoted as the (X+1)th pixel row, the (X+2)th pixel row, the (X+3)th pixel row, and the (X+4)th pixel row. The following explanation uses the first four pixel rows in the second display partition 100b as an example:

[0108] Reference Figure 12 and Figure 13 As shown, when the second type of light emission control circuit 230b receives the second light emission control start signal, the second type of light emission control circuit 230b starts to output the second type of light emission control signals EM_N / 2+1&N / 2+2 and EM_N / 2+3&N / 2+4 to the second display partition 100b according to the fourth type of clock signals EM_CK3 and EM_CK4. The period of the fourth type of clock signal is set to 8H. The light emission control signals EM_N / 2+1&N / 2+2 are started to be emitted under the control of the clock signal EM_CK4, and the light emission control signals EM_N / 2+3&N / 2+4 are started to be emitted under the control of the clock signal EM_CK3. The emission time of the light emission control signals EM_N / 2+3&N / 2+4 is 4H later than the emission time of the light emission control signals EM_N / 2+1&N / 2+2.

[0109] Next, refer to Figure 11 and Figure 13As shown, the first type of reset circuit 220a receives the second reset start signal. Driven by the first type of clock signals CK1, CK2, CK3 and CK4, the first type of reset circuit 220a sequentially inputs the second type of reset signals RST_N / 2+1, RST_N / 2+2, RST_N / 2+3 and RST_N / 2+4 to the (N / 2+1)th pixel row, the (N / 2+2)th pixel row, the (N / 2+3)th pixel row and the (N / 2+4)th pixel row. The time interval between CK1 and CK2 and the time interval between CK3 and CK4 are both 1H, and the time interval between CK2 and CK3 is 3H.

[0110] Then, refer to Figure 10 and Figure 13 As shown, the second type of row driving circuit 210b receives the second row scan initial signal. Driven by the second type of clock signals CK5, CK6, CK7 and CK8, the second row scan initial signal will sequentially input the second type of row driving signals Pscan_1, Pscan_2, Pscan_3 and Pscan_4 to the (N / 2+1)th pixel row, the (N / 2+2)th pixel row, the (N / 2+3)th pixel row and the (N / 2+4)th pixel row. The time interval between CK5 and CK6 and the time interval between CK7 and CK8 are both 1H, and the time interval between CK6 and CK7 is 3H.

[0111] It should be noted that in the above embodiments, the row scan signal controlled to access any pixel row is delayed by 1H compared to the reset signal accessed to the same pixel row. It is understood that the row scan signal includes a first type of row scan signal and a second type of row scan signal, and the reset signal includes a first type of reset signal and a second type of reset signal.

[0112] Reference Figure 14 The diagram shown is a timing diagram of the reset signal and scan signal for the first display partition 100a and the second display partition 100b of this application. Through the above settings, the pixel rows in the display area can emit light separately. The actual light emission sequence is as follows: Figure 14As shown, the rows are arranged sequentially as follows: first pixel row, second pixel row, (N / 2+1)th pixel row, (N / 2+2)th pixel row, third pixel row, fourth pixel row, (N / 2+3)th pixel row, and (N / 2+4)th pixel row, and so on. To maintain the same number of rows between the reset signal and the row scan signal for each row of sub-pixels 101, and to keep the time interval between the row scan signal and the light emission control signal constant for odd or even rows, the timing of the first pixel row of the second display partition 100b receiving the second type of reset signal lags behind the timing of the first pixel row of the first display partition 100a receiving the first type of reset signal by twice the horizontal scan cycle; similarly, the timing of the first pixel row of the second display partition 100b receiving the second type of row scan signal lags behind the timing of the first pixel row of the first display partition 100a receiving the first type of row scan signal by twice the horizontal scan cycle. It should be noted that the periods of all the above clock signals can be controlled and changed by a timing controller connected to the display panel 10. The specific method of change is a common method in the art, therefore, it will not be described in detail in this embodiment.

[0113] In the above embodiments, the periods of the first type of clock signal and the second type of clock signal are both 4H, which is four times the horizontal scan period. The periods of the third type of clock signal and the fourth type of clock signal are both 8H, which is eight times the horizontal scan period. Compared with the display panel 10 in the related art, the period of the light emission control circuit 230 of the display panel 10 in this application is larger, thereby enabling the actual light emission time of the display area to be longer. Combined with the staggered light emission setting of the pixel rows of the display panel 10, the brightness fluctuation of the display panel 10 within a frame can be smoother, which can improve the screen flicker problem of the display panel 10, thereby realizing the low-frequency display of the display panel 10. The effects achieved by this application will be described in detail below with reference to the accompanying drawings.

[0114] Reference Figure 15 The image shows the brightness variation of sub-pixel 101 in the related technology. The maximum value of the row luminance Lv is defined as Lmax, the minimum value as Lmin, and the intermediate value Lmid is approximately denoted as (Lmax+Lmin) / 2. Then, within a frame, at time T1, the brightness perceived by the human eye or captured by the device is L=(L1+L2) / 2=(Lmin+Lmin) / 2=Lmin; at time T2, the brightness perceived by the human eye or captured by the device is L”=(L1”+L2”) / 2=(Lmax+Lmax) / 2=Lmax; therefore, the brightness difference from time T1 to time T2 is △L=L”-L=Lmax-Lmin.

[0115] Reference Figure 16The image shows the brightness variation of sub-pixel 101 in this application. Similarly, the maximum value of the row luminance Lv is defined as Lmax, the minimum value as Lmin, and the intermediate value Lmid is approximately denoted as (Lmax+Lmin) / 2. Then, within one frame, at time T1, the brightness perceived by the human eye or captured by the device is L=(L1+L2+L3+L4) / 4=(Lmin+Lmin+Lmax+Lmax) / 4=Lmax / 2+Lmin / 2; at time T2, the brightness perceived by the human eye or captured by the device is L”=(L1”+L2”+L3”+L4”) / 4=(Lmax+Lmax+Lmid+Lmid) / 4=Lmax / 2+Lmid / 2; therefore, the brightness difference from time T1 to time T2 is △L=L”-L=(Lmax-Lmin) / 4. As can be seen from the comparison, the brightness difference of sub-pixel 101 in this application is reduced by 75% compared with the brightness difference of sub-pixel 101 in related technologies, which can effectively reduce the brightness drop in the display area and significantly improve the screen flicker problem at low frequencies. Furthermore, as can be seen from the waveform diagram, the eight CK cycles of the horizontal drive circuit 210 and the reset circuit 220 in this application are all increased to 7H, that is, the frequency is reduced to 4 / 7 times the original, which also improves the power consumption of the display panel 10 to a certain extent.

[0116] Specifically, when this application adopts an EM-1-drive-2 architecture, power consumption can be further reduced compared to an EM-1-drive-1 architecture, as shown in the reference. Figure 17 As shown, let C0 be the capacitor of a single driving unit composed of a single row driving circuit and a single reset circuit 220, and C1 be the capacitor of a single light-emitting control circuit 230. Then, the power consumption caused by C0 in the display panel 10 of this application is 42.86% lower than the power consumption caused by C0 in the related technology, and the power consumption caused by C1 in the display panel 10 of this application is 50% lower than the power consumption caused by C1 in the related technology.

[0117] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A display panel, characterized by, The display panel comprises: a display area, at least comprising a first display sub-area and a second display sub-area; a pixel array arranged in the display area; wherein each display sub-area comprises a plurality of pixel rows, each pixel row comprises a plurality of sub-pixels and a plurality of pixel circuits, and each sub-pixel is electrically connected to a pixel circuit; and a driving module for inputting driving signals to the pixel circuits; the driving module connected to the first pixel row of the first display sub-area is connected to a first light-emitting control start signal, a first reset start signal and a first row scanning start signal; the driving module connected to the first pixel row of the second display sub-area is connected to a second light-emitting control start signal with a phase difference of half a frame from the first light-emitting control start signal, a second reset start signal with a phase difference of half a frame from the first reset start signal, and a second row scanning start signal with a phase difference of half a frame from the first row scanning start signal; the driving module comprises: a plurality of row driving circuits, each of which is connected to a pixel row, and the plurality of row driving circuits comprise: a first type of row driving circuit, the input end of which is electrically connected to a first type of clock signal line, and the output end of which is electrically connected to a pixel circuit located in the first display sub-area; and a second type of row driving circuit, the input end of which is electrically connected to a second type of clock signal line, and the output end of which is electrically connected to a pixel circuit located in the second display sub-area; a plurality of reset circuits, each of which is connected to a pixel row, and the plurality of reset circuits comprise: a first type of reset circuit, the input end of which is electrically connected to the second type of clock signal line, and the output end of which is electrically connected to a pixel circuit located in the first display sub-area; and a second type of reset circuit, the input end of which is electrically connected to the first type of clock signal line, and the output end of which is electrically connected to a pixel circuit located in the second display sub-area.

2. The display panel of claim 1, wherein: the first type of clock signal line and the second type of clock signal line each comprise four clock signal lines, each row driving circuit is electrically connected to two clock signal lines, and each reset circuit is electrically connected to two clock signal lines.

3. The display panel of claim 1 or 2, wherein, the driving module further comprises: a plurality of light-emitting control circuits, each of which is connected to a pixel row; or each light-emitting control circuit is connected to two adjacent pixel rows.

4. The display panel of claim 3, wherein, the plurality of light-emitting control circuits comprise: a first type of light-emitting control circuit, the input end of which is electrically connected to a third type of clock signal line, and the output end of which is electrically connected to a pixel circuit located in the first display sub-area; and a second type of light-emitting control circuit, the input end of which is electrically connected to a fourth type of clock signal line, and the output end of which is electrically connected to a pixel circuit located in the second display sub-area.

5. The display panel of claim 3, wherein each of the light emitting control circuits is electrically connected to two clock signal lines.

6. A driving method of a display panel, comprising: providing at least two display sub-regions, each of the display sub-regions comprising a plurality of pixel rows, the two display sub-regions comprising a first display sub-region and a second display sub-region, and the plurality of pixel rows being driven by driving modules connected to pixel circuits; and inputting a first light emitting control start signal, a first reset start signal and a first row scanning start signal to a driving module connected to a first pixel row of the first display sub-region; inputting a second light emitting control start signal having a phase difference of half a frame from the first light emitting control start signal, a second reset start signal having a phase difference of half a frame from the first reset start signal and a second row scanning start signal having a phase difference of half a frame from the first row scanning start signal to a driving module connected to a first pixel row of the second display sub-region; wherein the driving method further comprises: outputting a first type of row scanning signal to the first display sub-region according to a first type of clock signal; outputting a first type of reset signal to the first display sub-region according to a second type of clock signal; outputting a first type of light emitting control signal to the first display sub-region according to a third type of clock signal; outputting a second type of reset signal to the second display sub-region according to the first type of clock signal; outputting a second type of row scanning signal to the second display sub-region according to the second type of clock signal; and outputting a second type of light emitting control signal to the second display sub-region according to a fourth type of clock signal. The driving method further comprises: controlling a period of the first type of clock signal and a period of the second type of clock signal to be four times of a horizontal scanning period. The driving method further comprises: controlling a period of the third type of clock signal and a period of the fourth type of clock signal to be eight times of the horizontal scanning period. The driving method further comprises: controlling a row scanning signal accessing to any one of the pixel rows to be delayed from a reset signal accessing to the same pixel row by one horizontal scanning period. The row scanning signal comprises the first type of row scanning signal and the second type of row scanning signal, and the reset signal comprises the first type of reset signal and the second type of reset signal.

10. The driving method of claim 6, wherein: a time when a first pixel row of the second display sub-region accesses the second type of reset signal is controlled to lag behind a time when a first pixel of the first display sub-region accesses the first type of reset signal by two times of the horizontal scanning period; and a time when the first pixel row of the second display sub-region accesses the second type of row scanning signal is controlled to lag behind a time when the first pixel of the first display sub-region accesses the first type of row scanning signal by two times of the horizontal scanning period. ​ ​ ​ ​ ​ ​ ​ 7. The driving method according to claim 6, wherein ​ ​ 8. The driving method according to claim 6, wherein ​ ​ 9. The driving method according to claim 6, wherein ​ ​ ​ ​ ​ ​

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