A display driving circuit, a display panel and a display device

Abstract

The application discloses a display driving circuit, a display panel and a display device. The display driving circuit comprises a signal generation module, a frequency multiplication module, and a pixel driving module. The signal generation module is configured to generate a first clock signal. The frequency multiplication module is connected to the signal generation module and is configured to perform frequency multiplication on the first clock signal to output a second clock signal after frequency multiplication. The pixel driving module comprises a light-emitting unit and at least one switch tube arranged on a current path of the light-emitting unit. The control end of the switch tube is connected to the frequency multiplication module to input the second clock signal. In this way, the aging of the transistor in the signal generation module can be slowed down, and the service life of the display driving circuit can be prolonged.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driving circuit, a display panel, and a display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) display devices are active-matrix self-emissive display devices based on organic light-emitting diode materials. Compared with LCD (Liquid Crystal Display), they have the characteristics of high brightness, wide operating temperature range, wide color gamut, high contrast and thinness, and are receiving increasing attention in the display field, especially in the consumer electronics field.

[0003] However, because OLEDs use thin-film transistors (TFTs) for driving, and the driving transistors operate in the saturation region, the output current is significantly affected by Vgs (gate-source voltage) and Vds (drain-source voltage). Furthermore, due to process uniformity issues, the subthreshold swing (SS) is uneven and exhibits certain differences. Therefore, OLED display devices generally employ pulse width modulation (PWM).

[0004] Under normal circumstances, pulse width modulation is achieved by using the timing signal output by the scan drive circuit. However, since the output timing signal is high-frequency, it will inevitably increase the switching frequency of the TFT in the scan drive circuit, thus accelerating the aging of the TFT in the scan drive circuit. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a display driving circuit, a display panel, and a display device that can slow down the aging of transistors in the signal generation module and extend the lifespan of the display driving circuit.

[0006] One technical solution of this application is: providing a display driving circuit, the display driving circuit comprising: a signal generation module configured to generate a first clock signal; a frequency multiplier module connected to the signal generation module, the frequency multiplier module configured to multiply the first clock signal to output a frequency-multiplied second clock signal; and a pixel driving module comprising a light-emitting unit and at least one switching transistor disposed on the current path of the light-emitting unit, the control terminal of the switching transistor being connected to the frequency multiplier module to input the second clock signal.

[0007] In one embodiment, the frequency multiplication module includes: a logic processing unit, the first input terminal of which is connected to a signal generation module to input a first clock signal, and the output terminal of which is connected to a pixel driving module to output a second clock signal; and a level triggering unit, the synchronization terminal of which is connected to the output terminal of the logic processing unit, and the input and output terminals of which are connected to the second input terminal of the logic processing unit.

[0008] In one embodiment, there are multiple signal generation modules and multiple logic processing units, with each of the multiple signal generation modules, multiple logic processing units, and multiple scan lines corresponding one-to-one. The synchronization terminal of the level trigger unit is connected to the output terminal of the multiple logic processing units, and the input terminal and output terminal of the level trigger unit are connected to the second input terminal of the multiple logic processing units.

[0009] In one embodiment, the frequency multiplier module further includes multiple diodes, wherein, according to the scanning order of the scan lines, the cathode of each diode is connected to the output terminal of the preceding logic processing unit in the two adjacent logic processing units, and the anode of each diode is connected to the output terminal of the following logic processing unit in the two adjacent logic processing units.

[0010] In one embodiment, the signal generation module and the logic processing unit are disposed on the side of at least one end of the corresponding scan line; and / or the level triggering unit is disposed on the side of at least one end of the corresponding data line.

[0011] In one embodiment, the display driving circuit further includes a compensation module. The input terminal of the compensation module is connected to the output terminal of the frequency multiplier module to input a second clock signal, and the output terminal of the compensation module is connected to the control terminal of the switching transistor. The compensation module is configured to compensate and adjust the potential of the second clock signal to output an adjusted third clock signal to the control terminal of the switching transistor.

[0012] In one embodiment, the compensation module includes: a first transistor, the first terminal of which is configured to input a first level signal, and the control terminal of the first transistor is connected to the output terminal of the frequency multiplier module to input a second clock signal; and a second transistor, the first terminal of which is configured to input a second level signal, and the control terminal of the second transistor is connected to the output terminal of the frequency multiplier module to input the second clock signal, and the second terminal of the second transistor is connected to the second terminal of the first transistor and the control terminal of the switching transistor to output a third clock signal.

[0013] In one embodiment, at least one switching transistor includes a third transistor and a fourth transistor, and the pixel driving module further includes a driving transistor; wherein, the first terminal of the third transistor is configured to input a high voltage signal, the second terminal of the third transistor is connected to the first terminal of the driving transistor, the first terminal of the fourth transistor is connected to the second terminal of the driving transistor, the second terminal of the fourth transistor is connected to the first terminal of the light-emitting unit, and the second terminal of the light-emitting unit is configured to input a low voltage signal.

[0014] Another technical solution adopted in this application is: providing a display panel, which includes the display driving circuit as described above.

[0015] Another technical solution adopted in this application is: to provide a display device, which includes a display panel as described above and a power supply for supplying power to the display panel.

[0016] The display driving circuit provided in this application includes: a signal generation module configured to generate a first clock signal; a frequency multiplier module connected to the signal generation module, configured to multiply the first clock signal to output a frequency-multiplied second clock signal; and a pixel driving module including a light-emitting unit and at least one switching transistor disposed on the current path of the light-emitting unit, the control terminal of the switching transistor being connected to the frequency multiplier module to input the second clock signal. In this embodiment, no improvement is needed to the signal generation module and pixel driving module in related embodiments; instead, a frequency multiplier module is added between the signal generation module and the pixel driving module to increase the signal frequency. This approach, on the one hand, avoids the problem of the signal generation module generating high-frequency signals and accelerating transistor aging, thus reducing the load on the signal generation module and extending its lifespan; on the other hand, using the frequency-multiplied second clock signal to control the switching transistor for high-frequency dimming can reduce visual fatigue and minimize eye strain caused by the display device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1 This is a schematic diagram of the structure of an embodiment of the pixel driving circuit provided in this application;

[0019] Figure 2 This is a schematic diagram of the structure of an embodiment of the signal generation circuit provided in this application;

[0020] Figure 3 This is a schematic diagram of the structure of an embodiment of the display driving circuit provided in this application;

[0021] Figure 4 This is a schematic diagram of the first structure of the frequency multiplier module in one embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the second structure of the frequency multiplier module in one embodiment of this application;

[0023] Figure 6 yes Figure 5 A circuit diagram corresponding to the XOR logic processing module;

[0024] Figure 7 yes Figure 6 Corresponding timing diagram;

[0025] Figure 8 This is a schematic diagram of the third structure of the frequency multiplier module in one embodiment of this application;

[0026] Figure 9 This is a schematic diagram of another embodiment of the display driver circuit provided in this application;

[0027] Figure 10 This is a schematic diagram of the compensation module in one embodiment;

[0028] Figure 11 This is a schematic diagram of another embodiment of the display driving circuit provided in this application;

[0029] Figure 12 This is a schematic diagram of the structure of an embodiment of the display panel provided in this application;

[0030] Figure 13 This is a schematic diagram of the structure of an embodiment of the display device provided in this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0033] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0034] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the pixel driving circuit provided in this application. The driving of this circuit mainly includes the following three stages:

[0035] Reset phase: The N-Scan(nx) signal and the P-Scan signal control transistors T4 and T7 to turn on. The reset signal Vint is input to the gate of transistor T1 and the anode of the light-emitting diode OLED. The reset signal Vint is a low-level signal used to perform the reset operation.

[0036] Compensation phase: The N-Scan signal controls transistors T2 and T3 to turn on. At this time, the voltage at the first terminal of transistor T1 is Vdata. Since the gate and the second terminal of transistor T1 are shorted, transistor T1 is equivalent to a diode. Therefore, the gate voltage of transistor T1 is Vdata-Vth, where Vdata is the voltage of the data signal Data and Vth is the threshold voltage of transistor T1.

[0037] Light-emitting stage: The EM signal controls transistors T5 and T6 to conduct, forming a current path between the power supply voltage ELVDD, transistors T5, T1, and T6, the light-emitting diode OLED, and the ground voltage ELVSS, causing the light-emitting diode OLED to emit light.

[0038] It is understood that the above embodiments are merely examples of a "7T1C" pixel driving circuit. Other pixel driving circuits may be used in other embodiments, and no limitation is made here.

[0039] In the above embodiments, since OLEDs are driven by thin-film transistors (TFTs), and the driving transistors operate in the saturation region, the output current is significantly affected by Vgs and Vds. Furthermore, due to process uniformity issues, the subthreshold swing (SS) is uneven and exhibits certain differences. Therefore, OLED display devices generally employ pulse-width modulation (PWM). Because PWM dimming is more likely to cause eye strain than direct current dimming (DC), this embodiment uses high-frequency PWM for dimming. That is, with a constant duty cycle, the higher the flicker frequency, the less noticeable it is to the human eye, thus reducing eye strain. This is the principle behind the relatively eye-friendly nature of high-frequency PWM dimming. Specifically, for the above... Figure 1 In one embodiment, the EM signal is replaced with a high-frequency PWM signal.

[0040] In one embodiment, the above Figure 1 The N-Scan, P-Scan, and EM signals are timing signals generated by signal generation circuits, such as GOA (Gate Driven on Array) circuits.

[0041] like Figure 2 As shown, Figure 2 This is a schematic diagram of an embodiment of the signal generation circuit provided in this application. The GOA circuit includes cascaded GOA units, each GOA unit including as follows: Figure 2 The circuit structure shown consists of numerous transistors and capacitors. It receives input clock signals CK / XCK, high-level signal H, low-level signal L, and LED control signal EMO, ultimately outputting the required first clock signal CLK1. The clock signals CK / XCK are input, H, L are high-level signal, L is low-level signal, and a reset signal is output. The latter also handles the upstream reset and downstream input. Through cascading, the GOA is driven line by line, with the first line triggered by STV and the last line reset by redundant units, ensuring system stability and efficiency.

[0042] It is understood that the above embodiments are merely examples of one signal generation circuit, and other circuit structures may be used in other embodiments, which are not limited here.

[0043] Understandably, in the relevant embodiments, the above... Figure 1 The EM signal required in the embodiment is as described above. Figure 2 The first clock signal CLK1 output in the embodiment is provided. Since it is necessary to increase the frequency of the EM signal, then, if... Figure 2 The signal generation circuit has been improved, in which a large number of transistors will switch on and off at higher frequencies, accelerating transistor aging.

[0044] See Figure 3 , Figure 3 This is a schematic diagram of an embodiment of the display driving circuit provided in this application. The display driving circuit 100 includes a signal generation module 10, a frequency multiplication module 20, and a pixel driving module 30.

[0045] The signal generation module 10 is configured to generate a first clock signal CLK1; the frequency multiplier module 20 is connected to the signal generation module 10 and is configured to multiply the first clock signal CLK1 to output a second clock signal CLK2 after frequency multiplication; the pixel driving module 30 includes a light-emitting unit and at least one switching transistor disposed on the current path of the light-emitting unit, and the control terminal of the switching transistor is connected to the frequency multiplier module 20 to input the second clock signal CLK2.

[0046] Optionally, in one embodiment, the signal generation module 10 may be as follows: Figure 1 The circuit structure described in the embodiment.

[0047] Alternatively, in one embodiment, the pixel driving module 30 may be as follows: Figure 2 The circuit structure described in the embodiment. The light-emitting unit of the pixel driving module 30 can be as follows: Figure 2 The OLED shown can have a switching transistor as follows: Figure 2 Transistors T5 and T6 are shown in the diagram, with the second clock signal CLK2 serving as the EM signal.

[0048] Optionally, the frequency multiplier module 20 in this embodiment can be a double frequency multiplier, a triple frequency multiplier, a quadruple frequency multiplier, etc. There is no limitation here. As long as the frequency of the second clock signal CLK2 is greater than the frequency of the first clock signal CLK1, it should be included within the scope of this embodiment.

[0049] Understandably, this embodiment does not require improvements to the signal generation module 10 and pixel driving module 30 in related embodiments; for example, it does not require improvements to... Figure 1 The pixel driving circuit shown or the pixel driving circuit shown is as follows: Figure 2 The signal generation circuit shown is improved by adding a frequency multiplier module 20 between the signal generation module 10 and the pixel driving module 30 to increase the signal frequency. In this way, on the one hand, by adding a frequency multiplier module 20 at the end of the signal generation module 10 to adjust the frequency, the problem of the signal generation module 10 generating high-frequency signals and accelerating transistor aging is avoided, thus reducing the load on the signal generation module 10 and extending its lifespan. On the other hand, using the frequency-multiplied second clock signal to control the switching transistor for high-frequency dimming can reduce visual fatigue and minimize the harm of the display device to the eyes.

[0050] Further reading Figure 4 , Figure 4 This is a schematic diagram of the first structure of a frequency multiplier module in one embodiment of this application. The frequency multiplier module 20 includes a logic processing unit 21 and a level triggering unit 22.

[0051] The logic processing unit 21 has its first input terminal connected to the signal generation module 10 to input the first clock signal CLK1, and its output terminal connected to the pixel driving module 30 to output the second clock signal CLK2. The synchronization terminal of the level triggering unit 22 is connected to the output terminal of the logic processing unit 21, and the input and output terminals of the level triggering unit 22 are connected to the second input terminal of the logic processing unit 21.

[0052] The logic processing unit 21 performs logic processing on the input first clock signal CLK1 and the output signal of the level trigger unit 22. Taking frequency doubling as an example, the logic processing unit 21 can perform XOR logic processing or XNOR logic processing. The level trigger unit 22 generates an output signal (1 or 0) based on the rising or falling edge of the first clock signal CLK1. Taking frequency doubling as an example, the level trigger unit 22 can be a D flip-flop, an RS flip-flop, or a JK flip-flop, etc.

[0053] Taking double frequency as an example, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the second structure of a frequency multiplier module in one embodiment of this application. The frequency multiplier module 20 includes an XOR logic processing module and an RS flip-flop.

[0054] In this circuit, the first input of the XOR logic processing module is configured to receive the first clock signal CLK1, and the synchronization terminal of the RS flip-flop is connected to the S input of the RS flip-flop and Q* (i.e., ...). The output terminal is connected to the second input terminal of the XOR logic processing module.

[0055] Further reading Figure 6 , Figure 7 And Table 1, Figure 6 yes Figure 5 The circuit diagram corresponding to the XOR logic processing module. Figure 7 yes Figure 6 The corresponding timing diagram is shown in Table 1, which is the truth table of the RS flip-flop.

[0056] Table 1:

[0057] CP S R <![CDATA[Q n ]]> <![CDATA[Q n+1 ]]> Function 0 × × 0 0 Keep 0 × × 1 1 Keep 1 0 0 0 0 Keep 1 0 0 1 1 Keep 1 0 1 0 0 Set to 0 1 0 1 1 0 Set to 0 1 1 0 0 1 Set 1 1 1 0 1 1 Set 1 1 1 1 0 1* indefinite 1 1 1 1 1* indefinite

[0058] In combination with the above Figure 6 , Figure 7 And Table 1, Figure 6 The principle of the frequency doubling circuit is as follows (within one cycle of the first clock signal CLK1):

[0059] Phase 1: When the first clock signal CLK1 and node A are both high, transistors T9, T13, and T14 are turned on, and the second clock signal CLK2 is high (i.e., VGH).

[0060] In the second stage, when the first clock signal CLK1 is high and node A is low, transistors T9, T10, T11, T12, and T15 are turned on, and the second clock signal CLK2 is low (i.e., VGL).

[0061] Third stage: When the first clock signal CLK1 and node A are both low, transistors T8, T10, T11, T12 and T14 are turned on, and the second clock signal CLK2 is high (i.e. VGH).

[0062] In the fourth stage, when the first clock signal CLK1 is low and node A is high, transistors T8, T13, and T15 are turned on, and the second clock signal CLK2 is low (i.e., VGL).

[0063] As can be seen from the above process, within one cycle of the first clock signal CLK1, the second clock signal CLK2 generates two cycles, that is, the frequency of the second clock signal CLK2 is twice that of the first clock signal CLK1.

[0064] The circuit described above, which uses an XOR logic processing unit and an RS flip-flop to form a frequency doubler, is merely an example. In other embodiments, other logic processing units and flip-flops can also be used. For example, an XNOR logic processing unit and a D flip-flop can also form a frequency doubler circuit, which will not be elaborated here.

[0065] Taking triple frequency as an example, such as Figure 8 As shown, Figure 8 This is a schematic diagram of the third structure of a frequency multiplier module in one embodiment of this application. The frequency multiplier module 20 includes two JK flip-flops.

[0066] In this configuration, the synchronization terminals of the two JK flip-flops are configured to input the first clock signal CLK1. The Q output of the first JK flip-flop is connected to the J input of the second JK flip-flop, and the J input of the first JK flip-flop is connected to the Q* (i.e.,...) of the second JK flip-flop. The Q output of the second JK flip-flop is used to output the second clock signal CLK2.

[0067] See Figure 9 , Figure 9 This is a schematic diagram of another embodiment of the display driving circuit provided in this application. The display driving circuit 100 includes a signal generation module 10, a frequency multiplication module 20, a compensation module 40, and a pixel driving module 30.

[0068] The signal generation module 10 is configured to generate a first clock signal CLK1; the frequency multiplier module 20 is connected to the signal generation module 10 and is configured to multiply the first clock signal CLK1 to output a frequency-multiplied second clock signal CLK2; the input terminal of the compensation module 40 is connected to the output terminal of the frequency multiplier module 20 to input the second clock signal, and the compensation module is configured to compensate and adjust the potential of the second clock signal CLK2 to output an adjusted third clock signal CLK3; the output terminal of the compensation module 40 is connected to the control terminal of the switching transistor in the drive module 30 to output the third clock signal CLK3 to the control terminal of the switching transistor.

[0069] Understandably, the second clock signal CLK2, after frequency multiplication, may have an unstable potential. For example, the high-level potentials of different cycles may not be equal, or glitches may appear in the signal. This will affect the display of the pixel driving module 30, leading to display abnormalities. The compensation module 40 aims to make the potential more stable.

[0070] Further reading Figure 10 , Figure 10 This is a schematic diagram of the compensation module in one embodiment. The compensation module 40 includes a first transistor T16 and a second transistor T17. The first terminal of the first transistor T16 is configured to input a first level signal, and the control terminal of the first transistor T16 is connected to the output terminal of the frequency multiplier module to input a second clock signal CLK2. The first terminal of the second transistor T17 is configured to input a second level signal, and the control terminal of the second transistor T17 is connected to the output terminal of the frequency multiplier module to input the second clock signal CLK2. The second terminal of the second transistor T17 is connected to the second terminal of the first transistor T16 and the control terminal of the switching transistor (not shown) to output a third clock signal CLK3.

[0071] In one embodiment, the first transistor T16 is an NMOS transistor, and the second transistor T17 is a PMOS transistor. When the second clock signal CLK2 is high, the first transistor T16 is turned on and the second transistor T17 is turned off, and the third clock signal CLK3 is low (i.e., VGL). When the second clock signal CLK2 is low, the first transistor T16 is turned off and the second transistor T17 is turned on, and the third clock signal CLK3 is high (i.e., VGH). Understandably, the levels of the second clock signal CLK2 and the third clock signal CLK3 are opposite.

[0072] By adjusting the voltages of VGL and VGH, the level of the third clock signal CLK3 can be adjusted in the above manner. For example, the high-level voltage of the first clock signal CLK1 output by the signal generation module 10 can be set lower, while the high-level voltage of the third clock signal CLK3 can be set higher according to actual needs. This can reduce the load on the signal generation module 10, thereby slowing down the aging of the transistors in the signal generation module 10 and extending the lifespan of the signal generation module 10.

[0073] See Figure 11 , Figure 11 This is a schematic diagram of another embodiment of the display driving circuit provided in this application. The display driving circuit 100 includes a signal generation module 10, a frequency multiplication module 20, a compensation module 40, and a pixel driving module (not shown).

[0074] The frequency multiplier module 20 includes a logic processing unit and a level triggering unit. There are multiple signal generation modules 10, logic processing units, and compensation modules 40. Each signal generation module 10, logic processing unit, and compensation module 40 corresponds to a multiple scan line. The synchronization terminal of the level triggering unit is connected to the output terminal of the multiple logic processing units, and the input and output terminals of the level triggering unit are connected to the second input terminals of the multiple logic processing units.

[0075] The frequency multiplier module 20 also includes multiple diodes. According to the scanning order of the scan lines, the cathode of each diode is connected to the output terminal of the preceding logic processing unit in the two adjacent logic processing units, and the anode of each diode is connected to the output terminal of the following logic processing unit in the two adjacent logic processing units.

[0076] The above method uses an XOR logic processing unit and an RS flip-flop as an example. There are multiple signal generation modules 10, XOR logic processing units, and compensation modules 40. Each of these modules corresponds to a specific scan line. The synchronization terminal of the RS flip-flop is connected to the output terminals of the multiple XOR logic processing units, and the input terminal S and output terminal Q* of the RS flip-flop are connected to the second input terminals of the multiple XOR logic processing units. The cathode of each diode is connected to the output terminal of the preceding XOR logic processing unit in two adjacent XOR logic processing units, and the anode of each diode is connected to the output terminal of the following XOR logic processing unit in two adjacent XOR logic processing units.

[0077] Understandably, since the display circuit uses a line-by-line scanning method, when a certain line is being scanned, the unidirectional conduction principle of the diode is used to prevent the current from flowing to the next line.

[0078] In addition, the display panel generally includes an AA area for display, a driving circuit area disposed on the left and right sides of the AA area, and a circuit board area disposed on the lower side of the AA area. In one embodiment, the signal generation module 10 and the logic processing unit (e.g., the XOR logic processing unit) are disposed on the side of at least one end of the corresponding scan line, i.e., on the left and right sides of the AA area, and the level triggering unit (e.g., the RS trigger) is disposed on the side of at least one end of the corresponding data line, i.e., on the lower side of the AA area.

[0079] Optionally, the level triggering unit can be specifically located on the circuit board below, or inside the TDDI (Touch and Display Driver Integration).

[0080] See Figure 12 , Figure 12 This is a schematic diagram of the structure of an embodiment of the display panel provided in this application. The display panel 120 includes a display driving circuit 100, which is the display driving circuit 100 described in the above embodiment.

[0081] Optionally, the display panel 120 is an OLED display panel. The signal generation module in the display driving circuit 100 and the logic processing unit in the frequency multiplier module can be located on the left and right sides of the AA area of ​​the display panel 120, and the level triggering unit in the frequency multiplier module can be located on the lower side of the AA area of ​​the display panel 120.

[0082] See Figure 13 , Figure 13 This is a schematic diagram of the structure of an embodiment of the display device provided in this application. The display device 130 includes a display panel 120 and a power supply 131. The display panel 120 is the display panel 120 described in the above embodiment. The power supply 131 is connected to the display panel 120 to supply power to the display panel 120.

[0083] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0084] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0085] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0086] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display drive circuit, characterized by comprising: The display driving circuit comprises: a signal generation module configured to generate a first clock signal; a frequency multiplication module connected to the signal generation module, the frequency multiplication module being configured to perform frequency multiplication on the first clock signal to output a second clock signal after frequency multiplication; a pixel driving module comprising a light emitting unit and at least one switch tube arranged on a current path of the light emitting unit, a control end of the switch tube being connected to the frequency multiplication module to input the second clock signal; wherein the frequency multiplication module comprises: a logic processing unit, a first input end of the logic processing unit being connected to the signal generation module to input the first clock signal, and an output end of the logic processing unit being connected to the pixel driving module to output the second clock signal; a level trigger unit, a synchronization end of the level trigger unit being connected to the output end of the logic processing unit, and an input end and an output end of the level trigger unit being connected to a second input end of the logic processing unit. The number of the signal generation modules and the logic processing units is multiple, a plurality of the signal generation modules, a plurality of the logic processing units and a plurality of scan lines correspond to each other, the synchronization end of the level trigger unit being connected to the output ends of the plurality of logic processing units, and the input end and the output end of the level trigger unit being connected to the second input ends of the plurality of logic processing units.

2. The display driving circuit according to claim 1, wherein The frequency multiplication module further comprises a plurality of diodes, according to a scanning sequence of the scan lines, a cathode of each diode being connected to an output end of a previous logic processing unit among two adjacent logic processing units, and an anode of each diode being connected to an output end of a subsequent logic processing unit among the two adjacent logic processing units.

3. The display driving circuit according to claim 1, wherein The signal generation module and the logic processing unit are arranged at a side of at least one end of a corresponding scan line; and / or The level trigger unit is arranged at a side of at least one end of a corresponding data line.

4. The display driving circuit according to claim 1, wherein The display driving circuit further comprises a compensation module, an input end of the compensation module being connected to an output end of the frequency multiplication module to input the second clock signal, and an output end of the compensation module being connected to a control end of the switch tube; wherein the compensation module is configured to compensate and adjust a potential of the second clock signal to output an adjusted third clock signal to the control end of the switch tube.

5. The display driving circuit according to claim 4, wherein The compensation module comprises: a first transistor, a first end of the first transistor being configured to input a first level signal, and a control end of the first transistor being connected to the output end of the frequency multiplication module to input the second clock signal; a second transistor, a first end of the second transistor being configured to input a second level signal, a control end of the second transistor being connected to the output end of the frequency multiplication module to input the second clock signal, and a second end of the second transistor being connected to a second end of the first transistor and the control end of the switch tube to output the third clock signal.

6. The display driving circuit according to claim 1, wherein The at least one switch tube comprises a third transistor and a fourth transistor, and the pixel driving module further comprises a driving tube. The first end of the third transistor is configured to input a high voltage signal, the second end of the third transistor is connected to the first end of the drive tube, the first end of the fourth transistor is connected to the second end of the drive tube, the second end of the fourth transistor is connected to the first end of the light emitting unit, and the second end of the light emitting unit is configured to input a low voltage signal.

7. A display panel, characterized by, The display panel comprises the display driving circuit according to any one of claims 1-6.

8. A display device, characterized by comprising: The display device comprises the display panel according to claim 7, and a power supply for supplying power to the display panel.

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