Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, and the method for manufacturing the semiconductor element mainly comprises the steps: providing a substrate which comprises a non-MOSCAP region and an MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doping layer on the substrate of the non-MOSCAP region and the first fin-shaped structure of the MOSCAP region, and forming a second fin-shaped structure on the substrate of the MOSCAP region. And removing the doping layer in the non-MOSCAP region, and performing a heat treatment manufacturing process to drive a dopant in the doping layer into the first fin-shaped structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a metal-oxide-semiconductor capacitor (MOSCAP) element and a manufacturing method thereof by applying solid state doping (SSD) technology. Background Art

[0002] The capacitor structure of the semiconductor device may be a metal-oxide-semiconductor capacitor (MOSCAP) structure, which is commonly used in the gate structure of a metal oxide semiconductor field effect transistor (MOSFET). The manufacture of this capacitor structure includes depositing an oxide layer on one side of a substrate layer, depositing a metal layer (as a bottom electrode layer) on the other side of the substrate layer, and depositing a binary metal layer (as a top electrode layer) on the oxide layer to obtain a stacked layer.

[0003] Since this binary metal layer does not have a work function that can be applied to the capacitor structure of MOS, it must be subjected to thermal annealing treatment to give it an appropriate work function before it can be applied to the capacitor structure of MOS. For example, the work functions of the capacitor structures suitable for P-type MOS and N-type MOS can be not less than 4.7eV and not more than 4.3eV, respectively. However, this thermal annealing treatment may cause changes in other layers outside the binary metal layer, such as chemical deterioration or physical embrittlement. In addition, the heat treatment (such as heating treatment or thermal annealing treatment) performed on other layers may also cause damage to the binary metal layer with poor thermal stability. Accordingly, the existing MOS capacitor structure must adjust and strictly control the temperature, time and atmosphere of the thermal annealing treatment, which increases the difficulty of the manufacturing process and increases the manufacturing cost. In view of this, it is urgent to develop a new MOSCAP component to improve the above-mentioned shortcomings. Summary of the invention

[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly provides a substrate including a non-MOSCAP area and a MOSCAP area, then forms a first fin structure in the MOSCAP area, forms a doped layer on the substrate in the non-MOSCAP area and on the first fin structure in the MOSCAP area, removes the doped layer in the non-MOSCAP area, and then performs a heat treatment process to drive the dopants in the doped layer into the first fin structure.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate including a non-MOSCAP region and a MOSCAP region, a first fin structure disposed in the MOSCAP region, a liner layer disposed on the first fin structure, a gate oxide layer disposed in the non-MOSCAP region and the MOSCAP region, and a gate electrode disposed on the gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 6 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0007] Figure 7 Schematic diagram of concentration distribution of non-MOSCAP area components and MOSCAP area components.

[0008] Explanation of symbols

[0009] 12: Base

[0010] 14: Non-MOSCAP area

[0011] 16: MOSCAP area

[0012] 18: Base

[0013] 20: Fin structure

[0014] 22: Shallow Trench Isolation

[0015] 24: Doping layer

[0016] 26: Covering layer

[0017] 28: Annealing process

[0018] 30: Gate oxide layer

[0019] 32: Gate electrode

[0020] 34: Gate electrode

[0021] 36: Gate material layer

[0022] 38: Interlayer dielectric layer

[0023] 46: High dielectric constant dielectric layer

[0024] 48: Work function metal layer

[0025] 50: Low impedance metal layer

[0026] 52: Hard mask

[0027] 54: cushion layer

[0028] 56:Metal gate DETAILED DESCRIPTION

[0029] Please refer to Figures 1 to 6 , Figures 1 to 6 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, first, a substrate 12 is provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, on which at least two regions are defined, including a non-MOSCAP region 14 and a MOSCAP region 16, wherein the non-MOSCAP region 14 can be used to prepare input / output (I / O) components or low-voltage components in subsequent manufacturing processes, and the MOSCAP region 16 is preferably used to prepare MOSCAP components.

[0030] Then, a base 18 and a fin structure 20 can be formed on the substrate 12 of the non-MOSCAP area 16, and a plurality of fin structures 20 can be formed on the substrate 12 of the MOSCAP area 18. According to a preferred embodiment of the present invention, the fin structure 20 is preferably obtained by sidewall image transfer (SIT) technology, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers or mandrels can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then the desired patterned structure, such as a strip-shaped patterned fin structure, is obtained by a fin structure cutting process (fin cut).

[0031] In addition, the formation method of the base 18 and the fin-shaped structure 20 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the base 18 and the fin-shaped structure 20. In addition, the formation method of the base 18 and the fin-shaped structure 20 may also include first making a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed to the patterned hard mask layer, and this semiconductor layer can serve as the corresponding base 18 and the fin-shaped structure 20. These embodiments of forming the base 18 and the fin-shaped structure 20 are all within the scope of the present invention.

[0032] Then, a flowable chemical vapor deposition (FCVD) process is performed to form an insulating layer (not shown) made of silicon oxide on the base 18 and the fin structure 20 and fill the groove between the base 18 and the fin structure 20. Then, a planarization process is performed, such as chemical mechanical polishing (CMP) combined with an etching process, to remove a portion of the insulating layer to form a shallow trench isolation (STI) 22.

[0033] Then as Figure 2 As shown, a doping layer 24 is first formed on the substrate 12 in the non-MOSCAP region 14 and the MOSCAP region 16 and covers the base 18 and the fin structure 20, and then a capping layer 26 is formed on the surface of the doping layer 24. In this embodiment, the doping layer 24 preferably includes phosphosilicate glass (PSG) and the capping layer 26 preferably includes silicon oxide.

[0034] like Figure 3 As shown, a photolithography and etching process is then performed. For example, a patterned mask (not shown) such as a patterned photoresist may be first formed on the MOSCAP region 16, and then an etching process is performed using the patterned mask as a mask to remove all the capping layers 26 and doping layers 24 in the non-MOSCAP region 14 and even part of the capping layers 26 and doping layers 24 in the MOSCAP region 16 and expose the base 18 and the fin structure 20 below. Then, the patterned mask of the MOSCAP region 16 is removed.

[0035] like Figure 4 As shown, an annealing process 28 is then performed to introduce dopants such as phosphorus in the doping layer 24 into the fin structure 20 to form a doped region (not shown) and simultaneously convert the doping layer 24 into an undoped liner layer 54, which is preferably used as the bottom electrode of the MOSCAP device. Subsequently, the cap layer 26 and the liner layer 54 with relatively no dopant remaining can be selectively removed or not removed.

[0036] Then, an oxide growth process such as a rapid thermal oxidation (RTO) process or an in-situ steam generation (ISSG) process is performed to form a gate oxide layer 30 composed of silicon oxide on the substrate 12 and the fin structure 20 in the non-MOSCAP region 14 and the MOSCAP region 16. It should be noted that, compared with the gate oxide layer 30 in the non-MOSCAP region 14 being directly disposed on the surface of the substrate 12 or the fin structure 20, the gate oxide layer 30 in the MOSCAP region 16 can be selectively disposed on the surface of the cap layer 26 or directly cover the surface of the fin structure 20 depending on whether the cap layer 26 and the liner layer 54 are removed or not.

[0037] Then Figure 5 As shown, gate electrodes 32 and 34 can be formed on the substrate 12 and the fin structure 20 of the non-MOSCAP region 14 and the MOSCAP region 16, respectively. The gate electrode 32 of the non-MOSCAP region 14 can be used as a gate electrode of an I / O device or a low voltage device, and the gate electrode 34 of the MOSCAP region 16 can be used as an upper electrode of a MOSCAP device. The gate electrodes 32 and 34 can be manufactured by a gate first manufacturing process, a high-k first manufacturing process of a gate last manufacturing process, or a high-k last manufacturing process of a gate last manufacturing process according to the manufacturing process requirements.

[0038] Taking the post-high-k dielectric layer manufacturing process of the present embodiment as an example, a gate material layer 36 composed of polysilicon and a selective hard mask (not shown) can be sequentially formed on the substrate 12, and a pattern transfer manufacturing process is performed using a patterned photoresist (not shown) as a mask to remove a portion of the gate material layer 36 and a portion of the gate oxide layer 30 by a single etching or successive etching steps, and then the patterned photoresist is stripped off to form gate electrodes 32 and 34 composed of the patterned gate material layer 36 on the substrate 12 and the fin structure 20 in the non-MOSCAP area 14 and the MOSCAP area 16.

[0039] Then, at least one spacer (not shown) is formed on the sidewalls of the gate electrodes 32 and 34, respectively, and then a source / drain region (not shown) and / or an epitaxial layer are formed in the fin structure 20 and / or the substrate 12 on both sides of the spacer in the non-MOSCAP region 14, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region and / or the epitaxial layer. In the present embodiment, the spacer may be a single spacer or a composite spacer, for example, the details may include an offset spacer and a main spacer. The offset spacer and the main spacer may include the same or different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. The source / drain region may include different dopants depending on the conductivity type of the transistor to be prepared, for example, it may include P-type dopants or N-type dopants.

[0040] Next, an interlayer dielectric layer 38 is formed to cover the gate electrodes 32 and 34 , and then a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 38 and expose the gate electrodes 32 and 34 made of polysilicon material, so that the upper surface of the gate electrodes 32 and 34 is flush with the upper surface of the interlayer dielectric layer 38 .

[0041] like Figure 6 As shown, a metal gate replacement process is then performed to convert the gate electrodes 32 and 34 made of polysilicon material in the non-MOSCAP region 14 and the MOSCAP region 16 into metal gates 56. For example, a selective dry etching or wet etching process may be performed first, such as using an etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 36 and even the gate oxide layer 30, so as to form a groove in the interlayer dielectric layer 38 (not shown).

[0042] Then, a selective dielectric layer (not shown) or gate dielectric layer, a high dielectric constant dielectric layer 46, a work function metal layer 48 and a low impedance metal layer 50 are sequentially formed in the groove, and then a planarization process is performed, such as using CMP to remove part of the low impedance metal layer 50, part of the work function metal layer 48 and part of the high dielectric constant dielectric layer 46 to form a metal gate 56. Taking the gate structure manufactured by the post high dielectric constant dielectric layer manufacturing process in this embodiment as an example, each formed metal gate 56 preferably includes a dielectric layer or gate dielectric layer 30, a U-shaped high dielectric constant dielectric layer 46, a U-shaped work function metal layer 48 and a low impedance metal layer 50.

[0043] In the present embodiment, the high-k dielectric layer 46 includes a dielectric material with a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and strontium tantalum oxide (strontium bismuth tantalum oxide). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0044] The work function metal layer 48 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 48 and the low resistance metal layer 50, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and other materials. The low resistance metal layer 50 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP) and other materials or combinations thereof. Since converting a dummy gate into a metal gate according to a metal gate replacement manufacturing process is a well-known technique in this field, it will not be further described here. Then, a portion of the high dielectric constant dielectric layer 46, a portion of the work function metal layer 48 and a portion of the low resistance metal layer 50 may be removed to form a groove (not shown), and then a hard mask 52 is filled in the groove and the hard mask 52 is flush with the surface of the interlayer dielectric layer 38, wherein the hard mask 52 may be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon nitride carbide.

[0045] Afterwards, a pattern transfer process may be performed, for example, a pattern mask may be used to remove a portion of the interlayer dielectric layer 38 beside the gate electrode 32 in the non-MOSCAP region to form a plurality of contact holes (not shown) and expose the source / drain region. Then, the required metal material is filled into each contact hole, for example, a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (cobalt tungsten phosphide, CoWP), or a combination thereof. Afterwards, a planarization process is performed, for example, chemical mechanical polishing is used to remove a portion of the metal material to form contact plugs (not shown) in each contact hole to electrically connect the source / drain region. At this point, the fabrication of the semiconductor element of the preferred embodiment 1 of the present invention is completed.

[0046] Please refer to Figure 6 and Figure 7 , Figure 6FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 7 1 is a schematic diagram of the concentration distribution of the non-MOSCAP region 14 components and the MOSCAP region 16 components. Figure 6 As shown, the semiconductor device mainly includes a substrate 12 having a non-MOSCAP region 14 and a MOSCAP region 16, a metal oxide semiconductor transistor is disposed in the non-MOSCAP region 14, and a MOSCAP device is disposed in the MOSCAP region 16. In the present embodiment, the MOSCAP device mainly includes a plurality of fin structures 20 disposed on the substrate 12, at least one insulating layer such as a gate oxide layer 30 and / or a high-k dielectric layer 46 is disposed on the fin structures 20, and a gate electrode 34 is disposed on the gate oxide layer 30, wherein the heavily doped fin structures 20 are preferably used as the bottom electrode of the MOSCAP device, the gate oxide layer 30 and / or the high-k dielectric layer 46 are preferably used as the capacitor dielectric layer of the MOSCAP device, and the gate electrode 34 is used as the top electrode of the MOSCAP device.

[0047] In addition, although the fin structures 20 of the non-MOSCAP region 14 and the MOSCAP region 16 are formed in the same manufacturing process, the overall concentration or the maximum concentration in the fin structure 20 of the non-MOSCAP region 14 is preferably smaller than the overall concentration or the maximum concentration in the fin structure 20 of the MOSCAP region 16. Figure 7 , Figure 7 FIG. 2 is a schematic diagram of the concentration distribution in the fin structure 20 in the non-MOSCAP region 14 and the MOSCAP region 16, wherein the X-axis is the depth of the fin structure and the Y-axis is the dopant concentration in the fin structure. Figure 7 As shown, the non-MOSCAP region 14 (indicated by the dotted line) is generally implanted into the fin structure 20 using an ion implantation process. Therefore, the dopant concentration on the surface of the fin structure 20 is preferably less than the dopant concentration at a first depth but greater than the dopant concentration at a second depth, and the first depth is less than the second depth. For example, in the present embodiment, the dopant concentration on the surface of the fin structure 20 or at a depth of 0 nm in the non-MOSCAP region 14 is approximately less than 1.0×10 20 atoms / cm3 or about 7.0×10 19 atoms / cm3 to 9.0×10 19 atoms / cm3, and the doping concentration at a depth of about 20 nanometers is slightly greater than 1.0×10 20 atoms / cm3 or between 2.0×10 20 atoms / cm3 to 5.0×10 20 atoms / cm3, and the doping concentration at a depth of about 50 nanometers is between 8.0×10 17 atoms / cm3 to 2.0×10 18 atoms / cubic centimeter.

[0048] In the MOSCAP region 16, since the present invention preferably uses solid state doping (SSD) technology to implant dopants into the fin structure 20 according to the above-mentioned embodiment, the maximum concentration of the fin structure 20 in the non-MOSCAP region 14 is at a depth below the surface, and the maximum concentration of the fin structure 20 in the MOSCAP region 16 appears on the surface of the fin structure 20. For example, the doping concentration of the fin structure 20 at the surface or at a depth of 0 nanometers in the MOSCAP region 16 is approximately equal to 5.0×10 20 atoms / cm3 or about 3.0×10 20 atoms / cm3 to 6.0×10 20 atoms / cm3 and the doping concentration at a depth of about 50 nanometers is about 8.0×10 17 atoms / cm3 to 2.0×10 18 In this embodiment, the overall concentration slope in the non-MOSCAP region 14 is preferably smaller than the concentration slope in the MOSCAP region 16, and the expression of the decrease from the maximum concentration to a concentration such as any concentration less than the maximum concentration in the MOSCAP region 16 preferably comprises an exponential decay.

[0049] In summary, the present invention discloses a method for preparing a MOSCAP device using solid state doping (SSD) technology, which mainly forms a plurality of fin structures on a substrate in a MOSCAP region, forms a doping layer on a substrate in a non-MOSCAP region and on a fin structure in the MOSCAP region, removes all doping layers in the non-MOSCAP region, and then performs a heat treatment process to drive the dopants in the doping layer into the fin structure in the MOSCAP region. According to a preferred embodiment of the present invention, the maximum concentration of dopants in the fin structure formed in the MOSCAP region 16 by this method preferably appears on the surface of the fin structure, while the maximum concentration of dopants in the fin structure in the non-MOSCAP region 14 appears at a depth below the surface of the fin structure.

[0050] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: Providing a substrate including a non-metal-oxide-semiconductor capacitor region and a metal-oxide-semiconductor capacitor region; forming a first fin structure in the metal-oxide-semiconductor capacitor region; forming a doping layer on the substrate of the non-metal-oxide-semiconductor capacitor region and on the first fin structure of the metal-oxide-semiconductor capacitor region; removing the doped layer of the non-metal-oxide-semiconductor capacitor region; and Perform heat treatment process.

2. The method of claim 1, further comprising: forming a second fin structure in the non-metal-oxide-semiconductor capacitor region; forming the doping layer on the substrate of the non-metal-oxide-semiconductor capacitor region and the second fin structure; removing the doped layer of the non-metal-oxide-semiconductor capacitor region; forming a gate oxide layer in the non-metal-oxide-semiconductor capacitor region and the metal-oxide-semiconductor capacitor region; as well as The thermal treatment process is performed to drive the dopants in the doping layer into the first fin structure.

3. The method of claim 1, wherein the non-metal-oxide-semiconductor capacitor region comprises an input / output region and a low voltage region. 4 . The method of claim 1 , further comprising performing the thermal treatment process to form a maximum concentration of dopants on a surface of the first fin structure.

5. The method of claim 1, further comprising: The thermal treatment process is performed to form a first concentration of dopants on the surface of the first fin structure and to form a second concentration of dopants at a first depth of the first fin structure, wherein the second concentration is less than the first concentration. The method of claim 5 , wherein decreasing from the first concentration to the second concentration comprises exponential decay.

7. The method of claim 1, wherein the doping layer comprises phosphosilicate glass (PSG).

8. A semiconductor element, characterized in that: Include: A substrate comprising a non-metal-oxide-semiconductor capacitor region and a metal-oxide-semiconductor capacitor region; A first fin structure is provided in the metal-oxide-semiconductor capacitor region; A liner layer is disposed on the first fin structure; A gate oxide layer is provided in the non-metal-oxide-semiconductor capacitor region and the metal-oxide-semiconductor capacitor region; as well as The gate electrode is disposed on the gate oxide layer.

9. The semiconductor device according to claim 8, further comprising: A second fin structure is provided in the non-metal-oxide-semiconductor capacitor region; The liner layer is disposed on the first fin structure; The gate oxide layer is disposed on the substrate and the second fin structure of the non-metal-oxide-semiconductor capacitor region and on the liner layer of the metal-oxide-semiconductor capacitor region; and The gate electrode is arranged on the gate oxide layer. 10 . The semiconductor device as claimed in claim 9 , wherein a doping concentration of the first fin structure is greater than a doping concentration of the second fin structure. 11 . The semiconductor device as claimed in claim 8 , wherein the non-metal-oxide-semiconductor capacitor region comprises an input / output region and a low voltage region. 12 . The semiconductor device as claimed in claim 8 , wherein the first fin structure surface comprises a maximum concentration of dopants. 13 . The semiconductor device as claimed in claim 8 , wherein a surface of the first fin structure comprises a first concentration of dopants, a first depth of the first fin structure comprises a second concentration of dopants, and the second concentration is less than the first concentration. 14 . The semiconductor device as claimed in claim 13 , wherein the decrease from the first concentration to the second concentration comprises exponential decay. The semiconductor device as claimed in claim 8 , wherein the first fin structure comprises phosphorus.

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