Method for preparing an integrated packaging structure with buried power rails

Abstract

The application provides a preparation method of an integrated package structure with a buried power supply track, wherein oxygen ions are implanted on the front surface of a first semiconductor substrate, after high-temperature annealing, the oxygen ions react with silicon to form a first silicon oxide layer, the first silicon oxide layer replaces a germanium-silicon layer as a thinning stop layer when grinding, epitaxial silicon is grown on the front surface of the first semiconductor substrate, STI trenches and the buried power supply track are prepared on the epitaxial silicon, and a nanometer silicon through hole is formed on the back surface of the first semiconductor substrate and electrically connected with the buried power supply track, since the technical requirement of growing epitaxial silicon on the front surface of the first semiconductor substrate is simpler than that of growing a germanium-silicon layer on the front surface of the first semiconductor substrate, it is easier to control in actual production process, in addition, the germanium-silicon layer does not need to be removed by using a wet etching solution, so that the wafer is not damaged, the production yield is greatly improved, further, the requirement of epitaxial silicon to the equipment is relatively low, so that the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method for preparing an integrated packaging structure with a buried power rail. Background Art

[0002] In existing integrated packaging structures, the power supply network is mostly set on the front side of the wafer, thereby providing a steady supply of power and reference voltage (i.e., VDD and VSS) to the active devices on the chip through the power supply network. However, as the size of integrated circuits gradually shrinks, the back-end process flow of integrated circuits is difficult to keep up with the pace of transistor scaling. In addition, there is also a signal network in the front area of ​​the wafer. Therefore, it is becoming increasingly difficult to arrange the power supply network on the front side of the chip.

[0003] Backside power supply technology is expected to solve the above problems. The starting point of backside power supply technology is to separate the power transmission network from the signal network by moving the entire power supply network structure to the back side of the wafer; the wafer is only used as a carrier, and electrons do not need to pass through the complex back-end process stack, so that power can be directly delivered to the standard battery through wider and lower resistance metal wires, which is expected to reduce IR voltage drop, improve power transmission performance, reduce wiring congestion in the back-end process, and further expand the height of standard units.

[0004] Currently, in the commonly used backside power supply technology, when fabricating devices, a layer of SiGe (silicon germanium) is first epitaxially grown on the surface of the wafer. The SiGe layer serves as a stop layer during wafer grinding and thinning. Silicon is then epitaxially grown on the SiGe layer. Devices such as active areas, STI trenches, and buried power rails are fabricated on the epitaxial silicon layer. The wafer with the devices is then front-side bonded to another wafer. The backside of the wafer with the devices is then thinned to the SiGe layer and removed using a wet etch process. Finally, nano-silicon vias (Through Silicon Vias) are fabricated to connect to the buried power rails. However, due to the high technical requirements of epitaxial SiGe layers, they are difficult to control during actual production, resulting in low product yields. Furthermore, epitaxial SiGe layers also require high equipment requirements, which indirectly increases production costs. Furthermore, using a wet etch solution to remove the SiGe layer can easily cause surface unevenness on the wafer, damaging the wafer and further reducing production yields. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a method for preparing an integrated packaging structure with a buried power rail, which is used to solve the problems of the existing back-side power supply technology using an epitaxial germanium silicon layer in the preparation of devices, which is difficult to control during the production process, easily causes damage to the wafer, has a low production yield and high production cost.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing an integrated package structure with a buried power rail, the method comprising:

[0007] Providing a first semiconductor substrate, wherein the first semiconductor substrate includes a front surface and a back surface disposed opposite to each other;

[0008] Performing oxygen ion implantation and high-temperature annealing on the front surface of the first semiconductor substrate to form a first silicon oxide layer in the first semiconductor substrate, wherein the first silicon oxide layer divides the first semiconductor substrate into a first region and a second region;

[0009] forming an epitaxial silicon layer on the upper surface of the first region;

[0010] forming an active area on the epitaxial silicon layer and a plurality of STI trenches for isolating the active area;

[0011] forming a buried power rail between the plurality of STI trenches, and then inverting the first semiconductor substrate;

[0012] Providing a second semiconductor substrate and forming a second silicon oxide layer on a front surface of the second semiconductor substrate;

[0013] bonding the second silicon oxide layer to the epitaxial silicon layer and grinding the back surface of the first semiconductor substrate to remove the second region to expose the first silicon oxide layer;

[0014] etching and removing the first silicon oxide layer to expose the first region;

[0015] The first region is etched to form a through silicon via (TSV), and the TSV is filled with a conductive contact electrically connected to the buried power rail, wherein a top surface of the conductive contact is flush with a top of the first region.

[0016] Optionally, the step of forming the conductive contact includes: first forming a barrier layer in the silicon via, the barrier layer covering the bottom wall of the silicon via, forming a seed layer in the silicon via that completely covers the barrier layer and the bottom wall of the silicon via, growing a conductive material at the bottom of the seed layer and performing a planarization process on the conductive material.

[0017] Optionally, the conductive material and the buried power rail include refractory metals such as tungsten or ruthenium.

[0018] Optionally, the thickness of the first semiconductor substrate is 300 μm to 1000 μm.

[0019] Optionally, the epitaxial silicon layer has a thickness of 5 μm to 100 μm.

[0020] Optionally, the oxygen ion implantation energy for forming the first silicon oxide layer is 1 keV to 50 keV and the implantation dose is 5e13 / cm 2 ~10e13 / cm 2 .

[0021] Optionally, the implantation depth of oxygen ions into the first silicon oxide layer is 0.5 μm to 10 μm.

[0022] Optionally, the spacing between the through silicon vias is 50 μm to 130 μm.

[0023] Optionally, the through silicon via and the buried power rail are arranged opposite to each other and have the same size.

[0024] Optionally, before forming the through silicon via, the first region of the first substrate may be etched to remove the first region of the first substrate.

[0025] As described above, the present invention provides a method for preparing an integrated packaging structure with a buried power rail, which has the following beneficial effects: oxygen ion implantation is performed on the front surface of a first semiconductor substrate, and after high-temperature annealing, the oxygen ions react with silicon to form a first silicon oxide layer within the first semiconductor substrate. During grinding and thinning, the first silicon oxide layer can replace the silicon germanium layer as a grinding and thinning stop layer, while epitaxial silicon is grown on the front surface of the first semiconductor substrate, and STI trenches and buried power rails are prepared on the epitaxial silicon. Nano-silicon vias are formed on the back surface of the first semiconductor substrate to electrically connect to the buried power rail. Because the technical requirements for growing epitaxial silicon on the front surface of the first semiconductor substrate are simpler than those for growing an epitaxial silicon germanium layer on the front surface of the first semiconductor substrate, it is easier to control in the actual production process. In addition, there is no need to use a wet etching solution to remove the silicon germanium layer, which does not damage the wafer, significantly improving the production yield. Furthermore, the epitaxial silicon has relatively low equipment requirements, thereby reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart showing the steps of a method for preparing an integrated package structure with buried power rails according to the present invention.

[0027] Figure 2 It is a cross-sectional schematic diagram of a first semiconductor substrate in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0028] Figure 3 It is a cross-sectional schematic diagram showing the formation of a first silicon oxide layer in the first semiconductor substrate in the method for preparing the integrated package structure with buried power rails according to the present invention.

[0029] Figure 4It is a cross-sectional schematic diagram showing the formation of an epitaxial silicon layer in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0030] Figure 5 It is a cross-sectional schematic diagram showing the formation of STI trenches in the method for preparing an integrated package structure with buried power rails according to the present invention.

[0031] Figure 6 It is a cross-sectional schematic diagram showing the formation of an initial power rail trench in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0032] Figure 7 It is a cross-sectional schematic diagram showing the formation of a buried power rail in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0033] Figure 8 It is a cross-sectional schematic diagram showing the inversion of the first semiconductor substrate in the method for preparing the integrated package structure with buried power rails of the present invention.

[0034] Figure 9 It is a cross-sectional schematic diagram showing the formation of a second silicon oxide layer in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0035] Figure 10 It is a schematic cross-sectional view of the back surface of the first semiconductor substrate after grinding in the method for preparing the integrated package structure with buried power rails of the present invention.

[0036] Figure 11 It is a cross-sectional schematic diagram showing the first region in the method for preparing the integrated package structure with buried power rails of the present invention.

[0037] Figure 12 It is a cross-sectional schematic diagram showing the formation of a through silicon via in the method for preparing an integrated package structure with a buried power rail according to the present invention.

[0038] Figure 13 It is a cross-sectional schematic diagram showing an integrated package structure with buried power rails prepared by the method for preparing the integrated package structure with buried power rails of the present invention.

[0039] Component number description

[0040] 101. First semiconductor substrate; 1011. Front side; 1012. Back side; 1013. First region; 1014. Second region; 102. First silicon oxide layer; 103. Epitaxial silicon layer; 104. Active region; 105. STI trench; 107. Initial power rail trench; 108. Buried power rail; 109. Second semiconductor substrate; 110. Second silicon oxide layer; 111. Through-silicon via; 112. Barrier layer; 113. Conductive contact; Steps S1 to S9. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0043] It should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the above components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0044] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limitations of the present invention. As used herein, unless the context clearly indicates otherwise, the singular form "a (species / one)" is also intended to include the plural form. It will also be understood that when the terms "comprise" and variations thereof, "include" and variations thereof are used in this specification, the description indicates the presence of stated features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0046] See also Figures 1 to 13 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be arbitrarily changed, and the component layout may also be more complex.

[0047] This embodiment provides a method for preparing an integrated package structure with a buried power rail. Figure 1 , which is a flow chart of the steps of the preparation method, the preparation method comprises the following steps:

[0048] S1: providing a first semiconductor substrate 101, wherein the first semiconductor substrate 101 includes a front surface 1011 and a back surface 1012 arranged opposite to each other;

[0049] S2: performing oxygen ion implantation and high-temperature annealing on the front surface 1011 of the first semiconductor substrate 101 to form a first silicon oxide layer 102 in the first semiconductor substrate 101 , wherein the first silicon oxide layer 102 divides the first semiconductor substrate 101 into a first region 1013 and a second region 1014 ;

[0050] S3: forming an epitaxial silicon layer 103 on the upper surface of the first region 1013;

[0051] S4: forming an active area 104 and a plurality of STI trenches 105 for isolating the active area 104 on the epitaxial silicon layer 103;

[0052] S5: forming a buried power rail 108 between the plurality of STI trenches 105 , and then inverting the first semiconductor substrate 101 ;

[0053] S6: providing a second semiconductor substrate 109 and forming a second silicon oxide layer 110 on the front surface of the second semiconductor substrate 109;

[0054] S7: Bonding the second silicon oxide layer 110 with the epitaxial silicon layer 103 and grinding the back surface 1012 of the first semiconductor substrate 101 to remove the second region 1014 to expose the first silicon oxide layer 102;

[0055] S8: Etching to remove the first silicon oxide layer 102 to expose the first region 1013;

[0056] S9: Etching the first region 1013 to form a through-silicon via 111 and filling the through-silicon via 111 to form a conductive contact 113 electrically connected with the buried power rail 108, wherein the top surface of the conductive contact 113 is flush with the top of the first region 1013.

[0057] The method for manufacturing the integrated package structure with the buried power rail is further described below in combination with the accompanying drawings, and specifically as follows:

[0058] In step S1, referring to Figure 1 and Figure 2 , a first semiconductor substrate 101 is provided, which includes oppositely arranged front surface 1011 and back surface 1012.

[0059] Optionally, the material of the first semiconductor substrate 101 includes but is not limited to one of bare silicon (Si) wafer, gallium nitride, silicon carbide or glass, and the thickness of the first semiconductor substrate 101 is 300 μm to 1000 μm, for example, 300 μm, 650 μm or 1000 μm, and the shape thereof can be circular, square or any other desired shape.

[0060] Specifically, in the embodiment, the first semiconductor substrate 101 is a bare silicon (Si) wafer, and the thickness of the first semiconductor substrate 101 is 650 μm.

[0061] In step S2, referring to Figure 1 and Figure 3 , oxygen ion implantation is performed on the front surface 1011 of the first semiconductor substrate 101 and a high-temperature annealing process is performed to form a first silicon oxide layer 102 in the first semiconductor substrate 101, which divides the first semiconductor substrate 101 into a first region 1013 and a second region 1014.

[0062] Optionally, the implantation energy of the oxygen ions forming the first silicon oxide layer 102 is 1 keV to 50 keV and the implantation dose is 5e13 / cm 2 to 10e13 / cm 2 , and the implantation depth of the oxygen ions of the first silicon oxide layer 102 is 0.5 μm to 10 μm.

[0063] Specifically, in this embodiment, oxygen ions are first implanted on the front surface 1011 of the first semiconductor substrate 101. At this time, the silicon layer on the front surface 1011 of the first semiconductor substrate 101 is destroyed due to the implantation of high-energy oxygen ions. Then, a high-temperature annealing process is performed on the first semiconductor substrate 101 so that the silicon inside the first semiconductor substrate 101 reacts with the oxygen ions to form a first silicon oxide layer 102. The silicon layer on the front surface 1011 of the first semiconductor substrate 101 is recrystallized under the action of the high-temperature annealing, so that the formed first silicon oxide layer 102 is located inside the first semiconductor substrate 101. The oxygen ion implantation energy when forming the first silicon oxide layer 102 is 1 keV to 50 keV and the implantation dose is 5e13 / cm 2 ~10e13 / cm 2 In this embodiment, the depth of the formed first silicon oxide layer 102 is 0.5 μm to 10 μm, and the first silicon oxide layer 102 divides the first semiconductor substrate 101 into a first region 1013 and a second region 1014, wherein the first region 1013 is a recrystallized silicon layer. In this embodiment or other embodiments, the high-temperature annealing during the formation of the first silicon oxide layer 102 may include annealing the first semiconductor substrate 101 at a temperature of approximately 650° C. or greater (such as greater than approximately 700° C. or greater than approximately 800° C.).

[0064] In step S3, see Figure 1 and Figure 4 , an epitaxial silicon layer 103 is formed on the upper surface of the first region 1013.

[0065] Optionally, after the oxygen ion implantation is completed, since the first region 1013 is a recrystallized silicon layer, the recrystallized silicon layer may contain certain crystal defects, and thus its crystal quality may not meet the device manufacturing requirements. Therefore, it is necessary to grow another epitaxial silicon layer 103 above the first region 1013 to ensure that the subsequently manufactured devices meet the quality requirements. The thickness of the epitaxial silicon layer 103 is 5 μm to 100 μm, and the thickness of the epitaxial silicon layer 103 is different to meet the requirements of different device manufacturing. In other embodiments, the thickness of the epitaxial silicon layer 103 can also be flexibly selected according to the requirements of device manufacturing.

[0066] In step S4, see Figure 1 and Figure 5 An active area 104 and a plurality of STI trenches 105 for isolating the active area 104 are formed on the epitaxial silicon layer 103 .

[0067] Specifically, ion implantation is performed on the top of the epitaxial silicon layer 103 to form the active region 104, and then a trench isolation process is performed in the active region 104 to form a plurality of STI trenches 105. The shape of the STI trench 105 can be controlled by controlling the etching parameters. For example, a dry etching process with a longitudinal etching rate equivalent to a lateral etching rate can be used to obtain an STI trench 105 with a square cross-sectional shape, and this method does not increase the etching process with additional operations, which is simple and easy to implement. The plurality of STI trenches 105 obtained by the above process are mutually independent structures.

[0068] In step S5, referring to Figure 1 , Figure 6 , Figure 7 and Figure 8 , a buried power rail 108 is formed between the plurality of STI trenches 105, and then the first semiconductor substrate 101 is inverted.

[0069] Specifically, in this embodiment, the step of forming the buried power rail 108 between the plurality of STI trenches 105 is: reserving an initial power rail trench 107 on the active region 104 when forming the plurality of STI trenches 105, as shown in Figure 6 , the initial power rail trench 107 is located between the STI trenches 105 and exposes the epitaxial silicon layer 103. The exposed epitaxial silicon layer 103 is etched using a photomasking process to form a power rail trench in the epitaxial silicon layer 103. The power rail trench is filled with a conductive material, and then a chemical deposition process is performed on the active region 104, so that the buried power rail is completely surrounded or encapsulated by the active region 104, as shown in Figure 7 . After forming the buried power rail 108, the first semiconductor substrate 101 is inverted, so that the front surface 1011 of the first semiconductor substrate 101 can be bonded to other semiconductor substrates that are not patterned.

[0070] In step S6, referring to Figure 1 and Figure 9 , a second semiconductor substrate 109 is provided and a second silicon oxide layer 110 is formed on the front surface of the second semiconductor substrate 109.

[0071] Optionally, the material of the second semiconductor substrate 109 includes but is not limited to one of bare silicon (Si) wafer, gallium nitride, silicon carbide or glass, and the shape can be circular, square or any other desired shape.

[0072] Preferably, the second semiconductor substrate 109 is a bare silicon (Si) wafer, so that the material of the second semiconductor substrate 109 is consistent with the material of the first semiconductor substrate 101, so as to facilitate better bonding effect. The second silicon oxide layer 110 is formed on the front surface of the second semiconductor substrate 109 by thermal oxidation process, so that the second silicon oxide layer 110 can form a silicon / silicon dioxide bond with the active region 104. The second silicon oxide layer 110 can act as an insulating layer on one hand, and on the other hand, it can also improve the bonding strength between the first semiconductor substrate 101 and the second semiconductor substrate 109.

[0073] In step S7, referring to Figure 1 and Figure 10 , the second silicon oxide layer 110 is bonded with the epitaxial silicon layer 103, and the back surface 1012 of the first semiconductor substrate 101 is ground to remove the second region 1014 to expose the first silicon oxide layer 102.

[0074] Specifically, as shown in Figure 10 , the second semiconductor substrate 109 is bonded with the first semiconductor substrate 101, so that the second silicon oxide layer 110 is in contact with the active region 104. Since the first silicon oxide layer 102 is formed inside the first semiconductor substrate 101, the hardness of the first silicon oxide layer 102 is greater than that of the first semiconductor substrate 101. Therefore, the first silicon oxide layer 102 can act as a grinding stop layer. When the back surface 1012 of the first semiconductor substrate 101 is ground, the second region 1014 can be removed to expose the first silicon oxide layer 102.

[0075] In step S8, referring to Figure 1 and Figure 11 , the first silicon oxide layer 102 is etched to expose the first region 1013.

[0076] Specifically, the first silicon oxide layer 102 is continuously removed by dry etching process, so as to expose the first region 1013 of the first semiconductor substrate 101.

[0077] Optionally, the first region 1013 can also be etched to expose the epitaxial silicon layer 103.

[0078] In step S9, referring to Figure 1 , Figure 12 and Figure 13 , the first region 1013 is etched to form a through silicon via 111, and the through silicon via 111 is filled to form a conductive contact 113 electrically connected with the buried power supply rail 108. The top surface of the conductive contact 113 is flush with the top of the first region 1013.

[0079] The steps of forming the conductive contact 113 include: first forming a barrier layer 112 in the silicon via 111, the barrier layer 112 covers the side wall of the silicon via 111, forming a seed layer in the silicon via 111 that completely covers the barrier layer 112 and the bottom wall of the silicon via 111, growing a conductive material at the bottom of the seed layer and performing a planarization process on the conductive material, and finally forming the conductive contact 113.

[0080] Specifically, such as Figure 12 As shown, the first region 1013 is patterned and etched to form through silicon vias 111. The spacing between the through silicon vias 111 is 50 μm to 130 μm, for example, 50 μm, 90 μm or 130 μm. The through silicon vias 111 are arranged opposite to the buried power rail 108 and have the same size as shown. Figure 13 As shown, a barrier layer 112 is first formed in the TSV 111. Forming the barrier layer 112 includes depositing a dielectric material layer on the first region 1013 or thermally oxidizing the first region 1013 of the first semiconductor substrate 101 to form the barrier layer 112. The barrier layer 112 covers the sidewalls of the TSV 111 and the non-TSV 111 region of the first region 1013. Then, a seed layer is deposited on the barrier layer 112. The seed layer completely covers the pad dielectric layer 112 lining the sidewalls of the TSV 111 and the bottom wall of the TSV 111. Finally, a conductive material is grown from the bottom of the seed layer, and a planarization process is performed on the protruding conductive material so that the top of the conductive material is flush with the top of the barrier layer 112. In this embodiment or other embodiments, the conductive material and the buried power rail 108 include a refractory metal such as tungsten or ruthenium, or any other suitable metal.

[0081] In summary, the present invention provides a method for fabricating an integrated package structure with a buried power rail 108. This method involves implanting oxygen ions on the front surface of a first semiconductor substrate. Following high-temperature annealing, the oxygen ions react with silicon to form a first silicon oxide layer within the first semiconductor substrate. During milling and thinning, the first silicon oxide layer can replace the silicon germanium layer as a milling and thinning stop layer. Epitaxial silicon is then grown on the front surface of the first semiconductor substrate, and STI trenches and a buried power rail are formed thereon. Furthermore, nano-silicon vias are formed on the back surface of the first semiconductor substrate to electrically connect the buried power rail. Because the technical requirements for growing epitaxial silicon on the front surface of the first semiconductor substrate are simpler than those for growing an epitaxial silicon germanium layer on the front surface of the first semiconductor substrate, the actual production process is easier to control. Furthermore, a wet etching solution is no longer required to remove the silicon germanium layer, thereby preventing damage to the wafer and significantly improving production yield. Furthermore, epitaxial silicon has relatively low equipment requirements, thereby reducing production costs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0082] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A method for preparing an integrated package structure with a buried power rail, characterized in that: The preparation method comprises: Providing a first semiconductor substrate, wherein the first semiconductor substrate includes a front surface and a back surface disposed opposite to each other; Performing oxygen ion implantation and high-temperature annealing on the front surface of the first semiconductor substrate to form a first silicon oxide layer in the first semiconductor substrate, wherein the first silicon oxide layer divides the first semiconductor substrate into a first region and a second region; forming an epitaxial silicon layer on the upper surface of the first region; forming an active area on the epitaxial silicon layer and a plurality of STI trenches for isolating the active area; forming a buried power rail between the plurality of STI trenches and inverting the first semiconductor substrate; Providing a second semiconductor substrate and forming a second silicon oxide layer on a front surface of the second semiconductor substrate; Bonding the second silicon oxide layer to the active area and grinding the back surface of the first semiconductor substrate to remove the second area to expose the first silicon oxide layer; etching and removing the first silicon oxide layer to expose the first region; The first region is etched to form a through silicon via (TSV), and the TSV is filled with a conductive contact electrically connected to the buried power rail, wherein a top surface of the conductive contact is flush with a top of the first region.

2. The preparation method according to claim 1, characterized in that The steps of forming the conductive contact include: first forming a barrier layer in the silicon via, the barrier layer covering the bottom wall of the silicon via, forming a seed layer in the silicon via that completely covers the barrier layer and the bottom wall of the silicon via, growing a conductive material at the bottom of the seed layer and performing a planarization process on the conductive material.

3. The preparation method according to claim 2, characterized in that The conductive material and the buried power rail include one of tungsten or ruthenium.

4. The preparation method according to claim 1, characterized in that The thickness of the first semiconductor substrate is 300 μm to 1000 μm.

5. The preparation method according to claim 1, characterized in that The thickness of the epitaxial silicon layer is 5 μm to 100 μm.

6. The preparation method according to claim 1, characterized in that The oxygen ion implantation energy for forming the first silicon oxide layer is 1keV~50keV and the implantation dose is 5e13 / cm 2 ~10e13 / cm 2 .

7. The preparation method according to claim 1, characterized in that The oxygen ion implantation depth of the first silicon oxide layer is 0.5 μm to 10 μm.

8. The preparation method according to claim 1, characterized in that The spacing between the through silicon vias is 50 μm to 130 μm.

9. The preparation method according to claim 1, characterized in that The through silicon via and the buried power rail are arranged opposite to each other and have the same size.

10. The preparation method according to claim 1, characterized in that Before forming the through silicon via, the first region of the first semiconductor substrate is etched to remove the first region of the first semiconductor substrate.

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