Back-side powered chip stacking structure and preparation method thereof

Abstract

The present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure comprises two chips bonded together, and the two chips realize signal transmission through a mutually bonded signal connection layer. At the same time, in combination with the setting of the power rail and the embedded power layer, it is only necessary to form a metal interconnection layer as a back power supply layer on the back of the first chip, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can achieve twice the number of transistors in the same area. For example, only a 14nm process can be used to achieve the number of transistors under a 7nm process. At the same time, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, which further reduces the production cost. In addition, the process of making the back power supply channel is moved forward, so that the preparation process is carried out sequentially from bottom to top, and the process rationality is better.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a chip stacking structure and a preparation method thereof. Background Art

[0002] In traditional 2.5D or 3D advanced packaging, wiring is mostly done on the front side of the wafer, with signal lines and power lines stacked and connected vertically to form two or more layers of semiconductor devices with active electronic components in an integrated circuit. Power lines are used to supply power to the chip, forming a power supply network. However, a signal network formed by signal lines also exists on the front side of the chip. Producing the power supply network on the front side of the chip means that the power supply network and signal network within the chip must share the same component space. The power supply network often occupies a large space, making it difficult to further reduce the volume of the entire packaging structure. In addition, the three-dimensional packaging structure with increased chip density may experience a high IR voltage drop, which can lead to increased power consumption and reduced device performance.

[0003] Therefore, the industry has begun exploring the possibility of moving the power supply network to the backside, making backside power delivery (PDN) a hot technical topic. Currently, backside power delivery is commonly used in 2D packaging. Technologists are faced with the challenge of further increasing chip density and transistor count in packaging structures to enhance device performance while optimizing process flows and reducing costs. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip stacking structure and a preparation method thereof, so as to improve chip density and increase the number of transistors.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides a back-side powered chip stacking structure, the chip stacking structure comprising:

[0006] The first chip includes a silicon deposition layer, a buried power layer, a dielectric layer, and a signal connection layer stacked in sequence from bottom to top, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and metal lines are formed in the signal connection layer to achieve signal connection with the transistors;

[0007] a second chip bonded to the first chip, comprising a second substrate, a buried power layer, a dielectric layer, and a signal connection layer stacked in sequence from top to bottom, wherein the dielectric layer has a plurality of transistors electrically connected to the buried power layer, and the signal connection layer has metal lines formed therein for realizing signal connection with the transistors;

[0008] The first chip and the second chip are also respectively formed with power rails, which penetrate the dielectric layer and the signal connection layer to electrically connect the buried power layer; the signal connection layers of the two chips are in contact to achieve signal connection; the power rails of the two chips are in contact to achieve electrical connection.

[0009] Preferably, the chip stacking structure further comprises an isolation layer formed by a shallow trench isolation process, and the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

[0010] Preferably, a plurality of penetrating metal pillars are formed in the silicon deposition layer, and the plurality of metal pillars are electrically connected to the power rail and the buried power layer of the first chip respectively.

[0011] Preferably, a metal interconnection layer is formed on the lower surface of the silicon deposition layer for electrically leading out the metal pillars.

[0012] Preferably, the signal connection layer and the metal interconnection layer are formed based on a copper Damascene process.

[0013] The present invention also provides a method for preparing a back-side powered chip stack structure, the method comprising the following steps:

[0014] S1: providing a first substrate, sequentially forming a metal interconnection layer and a silicon deposition layer on the first substrate, forming a plurality of penetrating metal pillars in the silicon deposition layer, wherein the metal pillars are electrically connected to metal lines of the metal interconnection layer;

[0015] S2: forming a buried power layer and a dielectric layer in sequence on the surface of the silicon deposition layer, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a first chip, and the buried power layer serves as a power supply channel for the transistors;

[0016] S3: forming a signal connection layer on a surface of the dielectric layer of the first chip away from the substrate, wherein a metal line is formed in the signal connection layer to achieve signal connection with the transistor; the first chip also has a power rail formed therein, wherein the power rail passes through the dielectric layer and the signal connection layer to electrically connect to the buried power layer;

[0017] S4: providing a second substrate, forming a buried power layer, a dielectric layer, and a signal connection layer on the second substrate, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a second chip, and the second chip also has a power rail penetrating the dielectric layer and the signal connection layer;

[0018] S5: Bonding the second chip to the first chip to form a stack, so that the signal connection layers of the two chips are in contact with each other to achieve signal connection; and the power rails of the two chips are in contact with each other to achieve electrical connection.

[0019] Preferably, the method further comprises the following steps:

[0020] S6: removing the first substrate of the first chip to expose the metal wires in the metal interconnection layer.

[0021] Preferably, the signal connection layer and the metal interconnection layer are formed based on a copper Damascene process.

[0022] Preferably, the first substrate and the second substrate are both silicon substrates.

[0023] Preferably, steps S2 and S4 further include forming an isolation layer by a shallow trench isolation process, wherein the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

[0024] As described above, the present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure includes two chips bonded together, and the two chips realize signal transmission through a mutually bonded signal connection layer. At the same time, combined with the setting of the power rail and the embedded power layer, it is only necessary to form a metal interconnection layer on the back of the first chip as a back power supply layer, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can achieve twice the number of transistors in the same area. For example, only a 14nm process can be used, and combined with the upper and lower transistor stacking method of the present application, the number of transistors under the 7nm process can be achieved, achieving the same performance, thereby saving process costs. At the same time, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, further reducing the production cost. In addition, the process of making the back power supply channel is moved forward, so that the preparation process is carried out sequentially from bottom to top, and the process rationality is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1-Figure 7 Shown is a schematic diagram of the process steps of the chip stacking structure of the present invention.

[0026] Figure 8 Shown is a schematic structural diagram of the chip stacking structure of the present invention.

[0027] Component number description

[0028] 101 silicon substrate layer

[0029] 102 Metal Interconnect Layer

[0030] 103 Silicon deposition layer

[0031] 104 buried power layer

[0032] 105 dielectric layer

[0033] 106 Signal Connection Layer

[0034] 201 transistor

[0035] 202 Isolation Layer

[0036] 100 First Chip

[0037] 200 Second Chip

[0038] 16 power rails

[0039] 31 Metal Pillar DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0042] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may be present. As used herein, "between" is inclusive of both endpoints.

[0043] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0044] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0045] like Figure 1-Figure 7 As shown, the present invention provides a method for preparing a back-side powered chip stacking structure, which specifically includes the following steps:

[0046] S1: Provide a first substrate, such as Figure 1-Figure 3 As shown, a metal interconnection layer 102 and a silicon deposition layer 103 are sequentially formed on the first substrate, and a plurality of penetrating metal pillars 31 are formed in the silicon deposition layer 103. The metal pillars 31 are electrically connected to the metal wires of the metal interconnection layer 102;

[0047] S2: forming a buried power layer 104 and a dielectric layer 105 on the surface of the silicon deposition layer 103 in sequence, such as Figure 4 As shown, a plurality of transistors 201 electrically connected to the buried power layer 104 are formed in the dielectric layer 105 to form the first chip 100 . The buried power layer 104 serves as a power supply channel for the transistors 201 .

[0048] Specifically, the first substrate can be a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, preferably a silicon substrate 101. The metal interconnect layer 102 can be prepared using a copper Damascene process. As an example, an insulating layer such as silicon dioxide is first deposited on the surface of the first substrate, then etched to form trenches, and then copper is deposited in the trenches to ultimately form the metal interconnect layer 102. The metal lines in the metal interconnect layer 102 are copper. The process for preparing the metal pillars 31 is as follows: first, a plurality of through-silicon vias (TSVs), more specifically, nano-silicon vias (n-TSVs), are formed in the silicon deposition layer 103, then an oxide layer is coated on the inner wall of the TSVs, and finally, metal filling is used to form the metal pillars 31.

[0049] The buried power layer 104 and dielectric layer 105 are sequentially formed on the silicon deposition layer 103. For example, the transistor 201 may be a FinFET, which may be formed after the buried power layer 104 is formed. The transistor 201 is formed by covering the silicon material with silicon material and then further fabricating the transistor 201 through etching, doping, and other processes. The specific fabrication process of the transistor 201 (FinFET) can be referenced to the prior art and will not be described in detail here. The dielectric layer 105 is used to provide electrical insulation between the transistors 201 and between the upper and lower layers.

[0050] Furthermore, step S2 may also include a shallow trench isolation (STI) process. In some embodiments, the shallow trench isolation process is used to form the buried power layer 104: first, a layer of insulating material is deposited, and a trench is formed by etching, and then the trench is filled with a conductive material to form a patterned conductive structure to provide power to the transistor. Figure 4As shown, in some other embodiments, a shallow trench isolation process is used to form an isolation layer 202 to achieve isolation between multiple buried power layers 104: for example, a chip is provided with multiple buried power rails 104 (Buried Power Rails, BPRs), including a first BPR for providing a first power supply voltage (e.g., VDD) and a second BPR for providing a second power supply voltage (e.g., VSS or GND); or, the transistors are divided into multiple subsets, and the multiple buried power layers include a third BPR for providing the first power supply voltage to the first subset of transistors, and a fourth BPR for providing the first power supply voltage to the second subset of transistors. In some other embodiments, a shallow trench isolation process is used to achieve electrical insulation between transistors, and an isolation layer 202 is provided between transistors 201 to separate them from each other and ensure mutual insulation.

[0051] Next, step S3 is performed: forming a signal connection layer 106 on the surface of the dielectric layer 105 of the first chip away from the substrate, such as Figure 5 As shown, metal lines are formed in the signal connection layer 106 to achieve signal connection with the transistor 201; the first chip 100 also forms a power rail 16, which passes through the dielectric layer 105 and the signal connection layer 106 to electrically connect the buried power layer 104.

[0052] Next, step S4 is performed: providing a second substrate, such as Figure 6 As shown, a buried power layer 104, a dielectric layer 105 and a signal connection layer 106 are formed on the second substrate. A plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105 to form a second chip 200. The second chip 200 also has a power rail 16 that passes through the dielectric layer 105 and the signal connection layer 106.

[0053] Specifically, as an example, the second substrate is the same as the first substrate, and can be a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and is preferably a silicon substrate 101 .

[0054] The signal connection layer 106 can be prepared by a copper Damascene process. As an example, an insulating layer such as silicon dioxide is first deposited on the surface of the dielectric layer 105, then etched to form a groove, and then metallic copper is deposited in the groove to finally form the signal connection layer 106. The metal wires in the signal connection layer 106 are copper.

[0055] It should be noted that the second chip does not have a metal interconnection layer and silicon deposition layer similar to those of the first chip, because the back of the first chip will need to be used as a power supply channel later, and the power supply of the second chip is achieved through the power rail after bonding with the first chip, without the need for additional power supply channels.

[0056] Then, proceed to step S5: Figure 7 As shown, the second chip 200 is bonded to the first chip 100 to form a stack, so that the signal connection layers 106 of the two chips are in contact to achieve signal connection; the power rails 16 of the two chips are in contact to achieve electrical connection;

[0057] Specifically, the two chips are stacked and interconnected through bonding, and the power rail 16 and the buried power layer 104 are provided so that the transistors 201 of the upper and lower chips can both be powered. This doubles the number of transistors in the same area. For example, using only a 14nm process, combined with the upper and lower transistor stacking method of this application, the number of transistors can be achieved at a 7nm process, achieving the same performance. Advanced processes mean expensive process costs, but by stacking the upper and lower chips, while achieving the same performance, process costs can also be saved.

[0058] Then, proceed to step S6: Figure 8 As shown, the first substrate of the first chip is removed to expose the metal wires in the metal interconnection layer 102;

[0059] Specifically, during the process, the first substrate is first thinned by CMP, and then the remaining portion of the first substrate is removed by dry etching.

[0060] It should be noted that during the CMP thinning process, the second chip here acts as a temporary carrier. If the second chip 200 is not available, a temporary carrier is required to support and secure the first chip 100 before subsequent thinning. The temporary carrier is a temporary material and has high manufacturing costs. The bonding of the first chip 100 and the second chip 200 here increases the number of collective tubes, avoids the use of a temporary carrier, and reduces production costs.

[0061] The above-mentioned preparation method is to first prepare the metal interconnection layer 102 and the silicon deposition layer 103 (metal pillar 31) used as the power supply channel, and then bond the two chips; while the existing process is to make the power supply channel on the back side after the first chip is bonded to the second chip. Corresponding to the structure of the present application, specifically, after bonding, the first chip is flipped so that it faces upward, and then TSV is made on the silicon deposition layer of the first chip, and then the metal interconnection layer is covered to realize electrical extraction. The present application moves the process of making the back power supply channel forward, and the preparation process is carried out sequentially from bottom to top. There is no need to flip the TSV to make it, and the process is more reasonable. At the same time, the previously prepared metal interconnection layer 102 can also be used as a barrier layer for the silicon deposition layer 103, eliminating the need for a process; in contrast, the existing process often requires the preparation of an additional barrier layer on the surface of the silicon deposition layer before TSV and covering the metal interconnection layer, usually an oxide material or a nitride material, to play a moisture-proof and anti-static role and protect the internal circuit.

[0062] The present invention also provides a back-side powered chip stacking structure, such as Figure 8 As shown, the chip stacking structure can be based on the above-mentioned preparation method, but is not limited to the above-mentioned preparation method. The chip stacking structure includes:

[0063] The first chip 100 includes a silicon deposition layer 103, a buried power layer 104, a dielectric layer 105, and a signal connection layer 106 stacked in sequence from bottom to top. A plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105. Metal lines are formed in the signal connection layer 106 to achieve signal connections with the transistors 201.

[0064] The second chip 200 is bonded to the first chip 100 and includes a second substrate, a buried power layer 104, a dielectric layer 105, and a signal connection layer 106 stacked in order from top to bottom. The dielectric layer 105 has multiple transistors 201 formed therein and electrically connected to the buried power layer. The signal connection layer 106 has metal lines formed therein to achieve signal connections with the transistors 201.

[0065] The first chip 100 and the second chip 200 are also respectively formed with power rails 16, and the power rails 16 pass through the dielectric layer 105 and the signal connection layer 106 to electrically connect the buried power layer 104; the signal connection layers 106 of the two chips are in contact to achieve signal connection; the power rails 16 of the two chips are in contact to achieve electrical connection.

[0066] Furthermore, the chip stacking structure further includes an isolation layer 202 formed by a shallow trench isolation process. The isolation layer 202 is used for isolation between the multiple buried power layers 104 or for electrical insulation between the transistors 201 .

[0067] Furthermore, a plurality of metal pillars 31 are formed through the silicon deposition layer 103. The metal pillars 31 are electrically connected to the power rail 16 of the first chip 100 and the buried power layer 104. In addition to transmitting power, the metal pillars electrically connected to the buried power layer 104 of the first chip 100 also transmit signals, first transmitting the signal to the first chip, which then transmits the signal to the second chip via the signal connection layer.

[0068] Furthermore, a metal interconnection layer 102 is formed on the lower surface of the silicon deposition layer 103 for electrically leading out the metal pillars 31 .

[0069] For specific details of the chip stacking structure, please refer to the relevant description in the above-mentioned preparation method, which will not be repeated here.

[0070] In summary, the present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure comprises two chips bonded together, and the two chips realize signal transmission through a mutually bonded signal connection layer. At the same time, combined with the setting of the power rail and the embedded power layer, it is only necessary to form a metal interconnection layer on the back of the first chip as a back power supply layer, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can achieve twice the number of transistors in the same area. For example, only a 14nm process can be used, and the upper and lower transistor stacking method of the present application can be combined to achieve the number of transistors under a 7nm process, achieving the same performance, thereby saving process costs. At the same time, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, further reducing the production cost. In addition, the process of making the back power supply channel is moved forward, so that the preparation process is carried out sequentially from bottom to top, and the process rationality is better.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A chip stacking structure with back-side power supply, characterized in that: The chip stacking structure includes: The first chip includes a silicon deposition layer, a buried power layer, a dielectric layer, and a signal connection layer stacked in sequence from bottom to top, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and metal lines are formed in the signal connection layer to achieve signal connection with the transistors; a second chip bonded to the first chip, comprising a second substrate, a buried power layer, a dielectric layer, and a signal connection layer stacked in sequence from top to bottom, wherein the dielectric layer has a plurality of transistors electrically connected to the buried power layer, and the signal connection layer has metal lines formed therein for realizing signal connection with the transistors; The first chip and the second chip are also respectively formed with power rails, which penetrate the dielectric layer and the signal connection layer to electrically connect the buried power layer; the signal connection layers of the two chips are in contact to achieve signal connection; the power rails of the two chips are in contact to achieve electrical connection.

2. The chip stacking structure according to claim 1, wherein: The chip stacking structure further includes an isolation layer formed by a shallow trench isolation process, and the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

3. The chip stacking structure according to claim 1, wherein: A plurality of penetrating metal pillars are formed in the silicon deposition layer, and the plurality of metal pillars are electrically connected to the power rail of the first chip and the buried power layer respectively.

4. The chip stacking structure according to claim 3, wherein: A metal interconnection layer is formed on the lower surface of the silicon deposition layer for electrically leading out the metal pillars.

5. The chip stacking structure according to claim 4, wherein: The signal connection layer and the metal interconnection layer are formed based on a copper Damascene process.

6. A method for preparing a back-side powered chip stacking structure, characterized in that: The preparation method comprises the following steps: S1: providing a first substrate, sequentially forming a metal interconnection layer and a silicon deposition layer on the first substrate, forming a plurality of penetrating metal pillars in the silicon deposition layer, wherein the metal pillars are electrically connected to metal lines of the metal interconnection layer; S2: forming a buried power layer and a dielectric layer in sequence on the surface of the silicon deposition layer, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a first chip, and the buried power layer serves as a power supply channel for the transistors; S3: forming a signal connection layer on a surface of the dielectric layer of the first chip away from the substrate, wherein a metal line is formed in the signal connection layer to achieve signal connection with the transistor; the first chip also has a power rail formed therein, wherein the power rail passes through the dielectric layer and the signal connection layer to electrically connect to the buried power layer; S4: providing a second substrate, forming a buried power layer, a dielectric layer, and a signal connection layer on the second substrate, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a second chip, and the second chip also has a power rail penetrating the dielectric layer and the signal connection layer; S5: Bonding the second chip to the first chip to form a stack, so that the signal connection layers of the two chips are in contact with each other to achieve signal connection; and the power rails of the two chips are in contact with each other to achieve electrical connection.

7. The preparation method according to claim 6, characterized in that The following steps are also included: S6: removing the first substrate of the first chip to expose the metal wires in the metal interconnection layer.

8. The preparation method according to claim 6, characterized in that: The signal connection layer and the metal interconnection layer are formed based on a copper Damascene process.

9. The preparation method according to claim 6, characterized in that: The first substrate and the second substrate are both silicon substrates.

10. The preparation method according to claim 6, characterized in that: Steps S2 and S4 also include forming an isolation layer by a shallow trench isolation process. The isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

Images