A preparation method of an ultra-low on-resistance MOS transistor based on an SGT process

Abstract

The application relates to a preparation method of an ultra-low on-resistance MOS tube based on an SGT process, and relates to the technical field of semiconductors; the method comprises the following steps: performing nitrogen source doping deposition on a substrate to form an N-type drift layer; sequentially growing a gallium nitride buffer layer and an aluminum gallium nitride barrier layer on the N-type drift layer, and cooling to room temperature to form a heterojunction; coating a positive photoresist and exposing to define a three-dimensional groove, then developing with a developing solution after hard baking to form a mask, and etching the three-dimensional groove; performing segmented injection in the main groove to form a gradually-changing super junction and performing high-temperature annealing treatment, performing high-dosage arsenic ion injection to form an N + region, depositing aluminum oxide gate medium, magnetron sputtering deposition of titanium nitride to completely fill the groove, then polishing, and then performing electrode preparation, passivation and metal interconnection; gradient doping epitaxy technology is used to realize gradient optimization of the resistance of the drift region, and a three-dimensional cross-groove array is defined on the surface of the heterojunction layer, so that the on-resistance is less than or equal to 5 m omega*mm2 when the breakdown voltage is greater than or equal to 650 V, which is reduced by more than 40% compared with the traditional SGT process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a preparation method of an ultra-low on-resistance MOS tube based on an SGT process. BACKGROUND

[0002] The traditional SGT process balances the breakdown voltage and on-resistance of a high-voltage MOS tube by constructing an alternating P-type and N-type columnar structure in a drift region, but the on-resistance is still limited by the superposition of the drift region resistance, channel resistance and contact resistance in a high-voltage scenario. In the prior art, the carrier mobility, gate control range and ohmic contact resistance of a single trench structure still have room for optimization, and it is difficult to meet the demand for ultra-low on-resistance in the fields of new energy vehicles, smart grids and the like. SUMMARY

[0003] The present application relates to the technical field of semiconductor technology, and in particular to a preparation method of an ultra-low on-resistance MOS tube based on an SGT process.

[0004] To achieve the above-mentioned purpose, the present application provides the following technical scheme: a preparation method of an ultra-low on-resistance MOS tube based on an SGT process, comprising the following steps:

[0005] forming an N-type drift layer with gradually increasing doping concentration from the substrate to the surface by nitrogen source doping deposition on the 4H-SiC substrate through a low-pressure vapor deposition method;

[0006] growing a gallium nitride buffer layer and an aluminum gallium nitride barrier layer on the N-type drift layer in sequence, and cooling to room temperature to form a gallium nitride / aluminum gallium nitride heterojunction;

[0007] coating a positive photoresist and exposing to define a three-dimensional trench of a main trench+secondary trench cross array, then developing with a developing solution after hard baking to form a mask, and etching the three-dimensional trench;

[0008] performing high-temperature annealing treatment on the main trench to form a gradually changing super junction of a bottom P-type column+middle and upper N-type column by segmented implantation, and performing high-dose arsenic ion implantation to form an N + region;

[0009] depositing aluminum oxide gate dielectric, magnetron sputtering deposition of titanium nitride to completely fill the trench, and then polishing, and then performing electrode preparation, passivation and metal interconnection.

[0010] Further, the 4H-SiC substrate has a diameter of 6-8 inches, a crystal direction of <0001>, and an off-angle of 4°, and the donor concentration of the 4H-SiC substrate is 5×10 18 -1×10 19 cm -3 -1×10

[0011] The 4H-SiC substrate is pretreated before doping deposition: ultrasonic cleaning with acetone, ethanol and deionized water for 10-15 min, immersion in a buffer oxide etching solution of ammonium fluoride and hydrogen fluoride with a volume ratio of 6:1 for 5-8 min, and high-temperature deoxidation treatment at 1100-1200°C in a hydrogen atmosphere for 30-60 min.

[0012] Further, the formation of the N-type drift layer includes the following steps:

[0013] First, a bottom N-type drift layer is grown by chemical vapor deposition at 1500-1550°C, 100-200 Torr, and a flow rate of 50-80 sccm of methane silicon and 2-5 sccm of ammonia, the thickness of the bottom N-type drift layer is 2-3 μm, and the doping concentration is 1×10 15 -2×10 15 cm -3 ;

[0014] Then, a middle N-type drift layer is grown by chemical vapor deposition at 1520-1580°C, 150-250 Torr, and a flow rate of 60-90 sccm of methane silicon and 5-8 sccm of ammonia, the thickness of the middle N-type drift layer is 2-4 μm, and the doping concentration is 5×10 15 -8×10 15 cm -3 ;

[0015] Then, an upper N-type drift layer is grown by chemical vapor deposition at 1560-1600°C, 200-300 Torr, and a flow rate of 80-120 sccm of methane silicon and 8-12 sccm of ammonia, the thickness of the upper N-type drift layer is 1-2 μm, and the doping concentration is 2×10 16 -3×10 16 cm -3 .

[0016] Further, a gallium nitride buffer layer and an aluminum gallium nitride barrier layer are sequentially deposited by a molecular beam epitaxy device, including the following steps:

[0017] First, heat to 850-900°C to grow a gallium nitride buffer layer on the top of the N-type drift layer, the thickness of the gallium nitride buffer layer is 50-80 nm, the growth rate is 0.5-1 nm / s, and the nitrogen flow rate is 30-50 sccm;

[0018] Then, cool to 750-800°C to grow an aluminum gallium nitride barrier layer, the thickness of the aluminum gallium nitride barrier layer is 20-30 nm, the growth rate is 0.2-0.3 nm / s, the flow rate ratio of the aluminum source to the gallium source is (5-7):20, and the nitrogen flow rate is 40-60 sccm.

[0019] Further, the positioning three-dimensional trench includes the following steps:

[0020] First, a positive photoresist is coated, with a coating thickness of 1.5-2 μm, a soft baking temperature of 90-100 °C, and a soft baking time of 60-90 s;

[0021] Then, electron beam lithography exposure is performed, with an electron beam acceleration voltage of 100-150 kV and an electron beam charge density of 50-80 μC / cm 2 ;

[0022] The developer is developed for 30-45 s, the hard baking temperature is 120-130 °C, and the hard baking time is 30-60 s, to form a photoresist mask;

[0023] The three-dimensional trench pattern design parameters are:

[0024] The main trench has a depth of 2.0-2.5 μm, a width of 0.4-0.6 μm, and a pitch of 0.8-1.2 μm;

[0025] The secondary trench has a depth of 0.4-0.6 μm, a width of 0.15-0.25 μm, and a pitch of 0.4-0.6 μm, and the secondary trench is uniformly distributed between the main trenches.

[0026] Further, the three-dimensional trench etching is performed by an inductively coupled plasma etching device, wherein the etching gas is a mixed gas of sulfur hexafluoride and oxygen with a flow ratio of 6:1, and the total flow rate of the etching gas is 50-80 sccm;

[0027] The inductively coupled plasma etching device has a power of 600-800 W, a radio frequency bias power of 100-150 W, a pressure of 10-20 mTorr, and an etching rate of 50-80 nm / min;

[0028] The three-dimensional trench etching includes the following steps:

[0029] First, the secondary trench is etched, and the oxygen plasma is driven at a power of 200 W to remove the sidewall polymer for 10-15 s;

[0030] Then, the main trench is etched, and the oxygen plasma is driven at a power of 200 W to remove the sidewall polymer for 10-15 s;

[0031] Then, deionized water ultrasonic cleaning is performed for 5-10 min to remove residual etching products and ensure that the sidewall roughness of the trench is ≤0.5 nm.

[0032] Further, the main trench is segmented and injected to form a bottom P-type column + middle and upper N-type column gradual super junction, which includes the following steps:

[0033] First, P-type column is implanted at the bottom of the main trench, the depth of the P-type column is 0.5-0.8 μm, the impurity of the P-type column is boron ion, the energy is 80-120 keV, the dose is 4×10 13 -6×10 13 cm -2 , and the implantation angle is 7°;

[0034] Then, N-type column is implanted at the upper part of the main trench, the depth of the N-type column is 1.2-1.8 μm, the impurity of the N-type column is phosphorus ion, the energy is 50-80 keV, the dose is 1.5×10 14 -2.5×10 14 cm -2 , the implantation angle is 7°, and the N-type column doping concentration gradually increases from the bottom to the top to match the drift layer gradient;

[0035] Then, photoresist and silicon oxide hard mask 500-800 nm thick are implanted as a mask to expose only the trench area of the main trench;

[0036] The high-temperature annealing treatment is carried out by a high-temperature inert atmosphere annealing furnace, the annealing temperature is 1600-1650 ℃, the argon flow rate is 500-800 sccm, the pressure is 1-2 atm, and the annealing time is 30-60 min.

[0037] Further, the N + region comprises the following steps:

[0038] The surface area on both sides of the trench array is exposed by a photoresist mask, and arsenic ions are implanted into the exposed area, the energy is 150-200 keV, the dose is 8×10 18 -1×10 19 cm -2 , and the implantation angle is 7°;

[0039] Then, activation annealing is carried out, the annealing temperature is 1100-1200 ℃, the annealing is carried out in a nitrogen atmosphere, the nitrogen flow rate is 300-500 sccm, and the annealing time is 15-30 min.

[0040] In another aspect, the application also provides an ultra-low on-resistance MOS tube based on the SGT process, which is prepared according to the above preparation method.

[0041] In another aspect, the application also provides an application of an ultra-low on-resistance MOS tube based on the SGT process, which is prepared according to the above preparation method and is applied in the field of semiconductors.

[0042] Compared with the prior art, the application has the following beneficial effects:

[0043] The present application can realize a conduction resistance ≤ 5 mΩ·mm when the breakdown voltage ≥ 650V in theory through material system innovation, i.e., silicon carbide+gallium nitride / aluminum gallium nitride heterojunction, and structure optimization, i.e., gradient super junction+three-dimensional trench 2 , which is reduced by more than 40% compared with the traditional SGT process, and the switching loss is reduced by 30%, which is suitable for new energy vehicle inverters, photovoltaic inverters and other high-voltage and high-current scenes. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only some of the embodiments of the present application, not all.

[0045] The present application provides a preparation method of an ultra-low conduction resistance MOS tube based on an SGT process, comprising the following steps:

[0046] A N-type drift layer with gradually increasing doping concentration from the substrate to the surface is formed by nitrogen source doping deposition on the 4H-SiC substrate through a low-pressure vapor deposition method;

[0047] A gallium nitride buffer layer and an aluminum gallium nitride barrier layer are grown on the N-type drift layer in sequence, and a gallium nitride / aluminum gallium nitride heterojunction is formed after cooling to room temperature;

[0048] A positive photoresist is coated and exposed to define a three-dimensional trench of a primary trench+secondary trench cross array, and then developed with a developing solution after hard baking to form a mask, and the three-dimensional trench is etched;

[0049] A gradually changing super junction with a bottom P-type column+middle and upper N-type column is formed by segmented implantation in the primary trench, and high-dose arsenic ion implantation is performed to form an N + region;

[0050] Aluminum oxide gate dielectric is deposited, and titanium nitride is deposited by magnetron sputtering to completely fill the trench, and then polished, and then electrode preparation, passivation and metal interconnection are performed; 4H-SiC has a wide band gap of 3.26 eV, a high thermal conductivity of 2.7 W / (cm·K), and can withstand high-voltage and high-current power density; the pre-treatment removes impurities and oxide layers to provide a smooth and clean interface for epitaxial growth, reducing the influence of interface state on carrier mobility.

[0051] In a further embodiment of the present application, the diameter of the 4H-SiC substrate is 6-8 inches, the crystal direction is <0001>, the off-angle is 4°, the donor concentration of the 4H-SiC substrate is 5×10 18 -1×10 19 cm -3 , and the thickness is 350-500 μm;

[0052] The 4H-SiC substrate is pretreated before doping deposition: ultrasonic cleaning with acetone, ethanol and deionized water for 10-15 min to remove surface organic contaminants, immersion in a buffer oxide etching solution with a volume ratio of ammonium fluoride to hydrogen fluoride of 6:1 for 5-8 min to remove the natural oxide layer, and high-temperature deoxidation treatment at 1100-1200°C in a hydrogen atmosphere for 30-60 min.

[0053] In a further embodiment of the present embodiment, the formation of the N-type drift layer comprises the following steps:

[0054] First, a bottom N-type drift layer is grown by chemical vapor deposition at 1500-1550°C, 100-200 Torr, 50-80 sccm flow rate of methane silicon and 2-5 sccm flow rate of ammonia, the thickness of the bottom N-type drift layer is 2-3 μm, and the doping concentration is 1×10 15 -2×10 15 cm -3 ;

[0055] Then, a middle N-type drift layer is grown by chemical vapor deposition at 1520-1580°C, 150-250 Torr, 60-90 sccm flow rate of methane silicon and 5-8 sccm flow rate of ammonia, the thickness of the middle N-type drift layer is 2-4 μm, and the doping concentration is 5×10 15 -8×10 15 cm -3 ;

[0056] Then, a top N-type drift layer is grown by chemical vapor deposition at 1560-1600°C, 200-300 Torr, 80-120 sccm flow rate of methane silicon and 8-12 sccm flow rate of ammonia, the thickness of the top N-type drift layer is 1-2 μm, and the doping concentration is 2×10 16 -3×10 16 cm -3 ; The gradient doping gradually increases the carrier concentration of the drift region from the substrate to the surface - the low doping of the bottom layer ensures uniform electric field distribution under high voltage (increases breakdown voltage), and the high doping of the top layer provides a low resistance channel for conduction (reduces the resistance of the drift region), and the spatial separation of the "voltage withstanding region" and the "conductive region" balances the voltage withstanding and conduction loss.

[0057] In a further embodiment of the present embodiment, a gallium nitride buffer layer and an aluminum gallium nitride barrier layer are sequentially deposited by a molecular beam epitaxy device, comprising the following steps:

[0058] First, heat to 850-900℃, grow a gallium nitride buffer layer on the top of the N-type drift layer, the thickness of the gallium nitride buffer layer is 50-80nm, the growth rate is 0.5-1nm / s, and the nitrogen flow rate is 30-50sccm;

[0059] Then, cool to 750-800℃ to grow a gallium aluminum nitride barrier layer, the thickness of the gallium aluminum nitride barrier layer is 20-30nm, the growth rate is 0.2-0.3nm / s, the flow rate ratio of the aluminum source to the gallium source is (5-7):20, and the nitrogen flow rate is 40-60sccm; the lattice mismatch and polarization effect of AlGaN (gallium aluminum nitride) and GaN (gallium nitride) form a two-dimensional electron gas at the interface, and the surface density can reach 1×10 13 -2×10 13 cm -2 , and the mobility is ≥2000cm 2 / (V·s), which is 3-5 times that of a traditional Si-based MOS channel, and the two-dimensional electron gas can greatly reduce the channel resistance as a "non-doped conductive channel".

[0060] In a further embodiment of the present embodiment, positioning the three-dimensional trench includes the following steps:

[0061] First, apply a positive photoresist, the coating thickness is 1.5-2μm, the soft baking temperature is 90-100℃, and the soft baking time is 60-90s;

[0062] Then, electron beam lithography exposure is performed, the electron beam acceleration voltage is 100-150kV, and the electron beam charge density is 50-80μC / cm 2 ;

[0063] Developing solution is developed for 30-45s, the hard baking temperature is 120-130℃, and the hard baking time is 30-60s to form a photoresist mask;

[0064] The three-dimensional trench pattern design parameters are as follows:

[0065] The main trench depth is 2.0-2.5μm, the width is 0.4-0.6μm, and the pitch is 0.8-1.2μm;

[0066] The secondary trench depth is 0.4-0.6μm, the width is 0.15-0.25μm, and the pitch is 0.4-0.6μm, and the secondary trench is uniformly distributed between the main trenches; electron beam lithography achieves submicron level pattern accuracy, ensuring the consistency of the trench size; the three-dimensional cross structure increases the channel length in a unit area by more than 50%, the main trench is responsible for high voltage blocking, and the secondary trench increases the carrier transport path during conduction, directly reducing the channel resistance per unit current.

[0067] In a further implementation form of the embodiment, the etching of the three-dimensional trench is performed by an inductively coupled plasma etching device, wherein the etching gas is a mixture of sulfur hexafluoride and oxygen with a flow ratio of 6:1, and the total flow rate of the etching gas is 50-80 sccm;

[0068] The power of the inductively coupled plasma etching device is 600-800 W, the radio frequency bias power is 100-150 W, the pressure is 10-20 mTorr, and the etching rate is 50-80 nm / min;

[0069] The etching of the three-dimensional trench comprises the following steps:

[0070] First, etching the secondary trench, removing the sidewall polymer by driving oxygen plasma at a power of 200 W for 10-15 s;

[0071] Then etching the main trench, and then removing the sidewall polymer by driving oxygen plasma at a power of 200 W for 10-15 s;

[0072] Then removing the residual etching product by ultrasonic cleaning with deionized water for 5-10 min to ensure that the sidewall roughness of the trench is ≤0.5 nm; SF6 provides F radical etching of SiC / AlGaN / GaN, and the chemical reaction formula is: SiC + 4SF6→ SiF4↑ + CF4↑ + 4S↓, O2 inhibits polymer generation and optimizes etching verticality; low-roughness sidewalls reduce carrier scattering and improve channel mobility; step-by-step etching avoids depth errors and ensures functional separation of the main / secondary trench.

[0073] In a further implementation form of the embodiment, the main trench is segmented to form a bottom P-type column + middle and upper N-type column gradual super junction, comprising the following steps:

[0074] First, implanting a P-type column at the bottom of the main trench, the depth of the P-type column is 0.5-0.8 μm, the impurity of the P-type column is boron ions, the energy is 80-120 keV, the dose is 4×10 13 -6×10 13 cm -2 , and the implantation angle is 7°;

[0075] Then implanting an N-type column in the middle and upper part of the main trench, the depth of the N-type column is 1.2-1.8 μm, the impurity of the N-type column is phosphorus ions, the energy is 50-80 keV, the dose is 1.5×10 14 -2.5×10 14 cm -2 , and the implantation angle is 7°, wherein the N-type column doping concentration gradually increases from the bottom to the top to match the drift layer gradient;

[0076] Then, photoresist and a silicon oxide hard mask with a thickness of 500-800 nm are injected as a mask to expose only the trench area of ​​the main trench;

[0077] The high temperature annealing treatment is carried out in a high temperature inert atmosphere annealing furnace at a temperature of 1600-1650° C., an argon flow rate of 500-800 sccm, a pressure of 1-2 atm, and an annealing time of 30-60 min. The surface is covered with a SiC substrate as a cover to prevent Si volatilization at high temperature.

[0078] Segmented implantation creates a graded superjunction consisting of a P-type pillar at the bottom and an N-type pillar in the middle and upper parts. The P-type pillar and the N-type in the drift region form a space charge region, balancing the electric field under high voltage. The breakdown voltage is determined by the charge balance between the P / N pillars. The doping concentration of the N-type pillar gradually increases from bottom to top, matching the gradient of the drift layer, optimizing the electric field distribution, and reducing the resistance of the drift region by more than 30%.

[0079] High temperature annealing makes the implanted B + 、P + The activation rate of impurities migrating from interstitial sites to lattice sites is ≥80%, forming electrically active P-type and N-type columns; Ar atmosphere and cover sheet protection inhibit SiC surface decomposition, ensure uniform distribution of impurities, and avoid increased leakage due to surface damage.

[0080] In a further embodiment of this embodiment, N + The district includes the following steps:

[0081] The surface areas on both sides of the trench array were exposed through a photoresist mask, and arsenic ions were implanted into the exposed areas with an energy of 150-200 keV and a dose of 8×10 18 -1×10 19 cm -2 , the injection angle is 7°;

[0082] Then activation annealing is performed, wherein the annealing temperature is 1100-1200°C, the annealing is in a nitrogen atmosphere, the nitrogen flow rate is 300-500sccm, and the annealing time is 15-30min; high dose As + N + region, doping concentration ≥ 1×10 20 cm -3 , reducing the contact barrier between the source and drain regions and the electrodes; compared with super junction annealing, low-temperature annealing avoids the degradation of the two-dimensional electron gas of the AlGaN / GaN heterojunction and ensures the stability of the channel carrier concentration.

[0083] It should be noted that the following steps are used to deposit aluminum oxide gate dielectric, deposit titanium nitride by magnetron sputtering to completely fill the trenches and then polish, followed by electrode preparation, passivation, and metal interconnection:

[0084] The high-k medium aluminum oxide is used as the medium material of the gate, and the atomic layer deposition device is used to pulse treat the trimethyl aluminum and water for 0.1 s, respectively, and then clean for 2-3 s, and then deposit 10-15 nm at 250-300 DEG C and 1-5 Torr, and then perform rapid thermal annealing treatment after the deposition, wherein the temperature of the rapid thermal annealing is 400-450 DEG C, and the annealing is performed for 30-60 s in a nitrogen atmosphere to repair the deposition defects; the rapid thermal annealing realizes uniform coverage of the trench sidewall and the bottom through self-limiting reaction, the step coverage is greater than or equal to 95%, and the problem of “over-thick top and over-thin bottom” of traditional deposition is avoided; the aluminum oxide high-k medium reduces the gate capacitance (C = εS / d), and simultaneously separates the gate electrode and the channel as an insulating layer, thereby ensuring effective control of the gate on the two-dimensional electron gas, and the threshold voltage drift is less than or equal to 0.2 V.

[0085] Titanium is used as the target material, the argon and nitrogen flow ratio is 9:1, the power is 300-400 W, the deposition speed is 5-10 nm / min, the thickness of the titanium nitride is 2.5-3 microns, and the gate electrode is filled, and then chemical mechanical polishing treatment is performed, and the surface flatness is less than or equal to 5 nm, and the source and drain regions of the AlGaN surface are exposed; the titanium nitride has a low resistivity of less than or equal to 20 mu omega*cm and high stability, and the full-enclosing filling ensures the close contact of the gate and the channel sidewall, and improves the gate control efficiency; the chemical mechanical polishing flattening ensures the interface consistency of the subsequent electrode preparation, and avoids the contact resistance fluctuation caused by the surface undulation.

[0086] The single-layer graphene is grown by chemical vapor deposition, wherein the size of the single-layer graphene is greater than or equal to the substrate area, and the single-layer graphene is transferred to the surface of the source and drain region by PMMA, and the PMMA is removed by soaking in acetone for 30-60 min, the source and drain electrodes are defined by ultraviolet lithography, the excess graphene is removed by oxygen plasma etching, and the ohmic contact annealing is performed; the zero band gap characteristic of the single-layer graphene makes it form a van der Waals contact with the N + region, there is no Schottky barrier of the traditional metal-semiconductor, and the contact resistance can be as low as 1*10 -6 -5*10 -6 Ω*cm 2 , the contact resistance of the traditional Ti / Al electrode is 5*10 -5 -1*10 -4 Ω*cm 2 ; the annealing makes the graphene form a stable electron transfer channel with the N + region, ensures that there is no potential barrier block in the carrier transport of the contact interface, and greatly reduces the contact resistance ratio.

[0087] The SiO2 passivation layer is deposited by plasma enhanced chemical vapor deposition, then the gate, source and drain contact holes are opened by lithography and ICP etching, Ti / Au is sputtered as the lead wire, and the interconnection pattern is defined by lithography and etching.

[0088] In another aspect, the embodiment of the present application also provides an ultra-low on-resistance MOS tube based on the SGT process, which is prepared according to the preparation method.

[0089] In another aspect, the embodiment of the present application also provides an application of the ultra-low on-resistance MOS tube based on the SGT process, which is prepared according to the preparation method.

[0090] Example 1

[0091] A 4H-SiC substrate with a diameter of 6 inches, a crystal direction of <0001>, an off-angle of 4°, a donor concentration of 8×10 18 cm -3 , and a thickness of 400 μm is selected;

[0092] The 4H-SiC substrate is pretreated: ultrasonic cleaning with acetone, ethanol and deionized water for 15 min, immersion in a buffer oxide etching solution with a volume ratio of ammonium fluoride to hydrogen fluoride of 6:1 for 6 min, and high-temperature deoxidation treatment at 1150°C in a hydrogen atmosphere for 40 min.

[0093] A bottom N-type drift layer is grown by chemical vapor deposition at 1520°C, 150 Torr, a flow rate of 60 sccm of methane silicon and a flow rate of 3 sccm of ammonia, the thickness of the bottom N-type drift layer is 2 μm, and the doping concentration is 2×10 15 cm -3 ;

[0094] Then a middle N-type drift layer is grown by chemical vapor deposition at 1550°C, 200 Torr, a flow rate of 80 sccm of methane silicon and a flow rate of 7 sccm of ammonia, the thickness of the middle N-type drift layer is 3 μm, and the doping concentration is 6×10 15 cm -3 ;

[0095] Then an upper N-type drift layer is grown by chemical vapor deposition at 1580°C, 250 Torr, a flow rate of 100 sccm of methane silicon and a flow rate of 10 sccm of ammonia, the thickness of the upper N-type drift layer is 1 μm, and the doping concentration is 2×10 16 cm -3 .

[0096] Gallium nitride buffer layer is grown on the top of the N-type drift layer by heating to 860°C, the thickness of the gallium nitride buffer layer is 70 nm, the growth rate is 0.8 nm / s, and the nitrogen flow rate is 40 sccm;

[0097] Then, the temperature is decreased to 780℃ to grow a gallium aluminum nitride barrier layer, the thickness of the gallium aluminum nitride barrier layer is 25nm, the growth rate is 0.25nm / s, the flow ratio of the aluminum source to the gallium source is 6:20, and the flow of the nitrogen gas is 50sccm.

[0098] The three-dimensional groove is positioned: a positive photoresist is coated first, the coating thickness is 2μm, the soft baking temperature is 100℃, and the soft baking time is 80s;

[0099] Then, electron beam lithography exposure is performed, the electron beam acceleration voltage is 130kV, and the electron beam charge density is 65μC / cm 2 ;

[0100] The developer is developed for 38s, the hard baking temperature is 125℃, and the hard baking time is 45s to form a photoresist mask;

[0101] The three-dimensional groove pattern design parameters are as follows:

[0102] The main groove depth is 2μm, the width is 0.5μm, and the pitch is 1μm;

[0103] The secondary groove depth is 0.5μm, the width is 0.2μm, and the pitch is 0.5μm, and the secondary grooves are uniformly distributed between the main grooves.

[0104] The three-dimensional groove is etched by an inductively coupled plasma etching device: the etching gas is a mixed gas of sulfur hexafluoride and oxygen with a flow ratio of 6:1, and the total flow of the etching gas is 65sccm;

[0105] The power of the inductively coupled plasma etching device is 700W, the radio frequency bias power is 130W, the pressure is 15mTorr, and the etching rate is 65nm / min;

[0106] The etching of the three-dimensional groove includes the following steps:

[0107] The secondary groove is etched first, and the oxygen plasma is driven at a power of 200W to remove the sidewall polymer for 15s;

[0108] Then, the main groove is etched, and then the oxygen plasma is driven at a power of 200W to remove the sidewall polymer for 15s;

[0109] Then, the residual etching products are removed by deionized water ultrasonic cleaning for 8min to ensure that the groove sidewall roughness is ≤0.5nm.

[0110] A gradually changing super junction of a bottom P-type column + a middle and upper N-type column is formed:

[0111] A P-type column is first implanted at the bottom of the main trench, the depth of the P-type column is 0.7 μm, the impurity of the P-type column is boron ion, the energy is 100 keV, the dose is 6 x 1013cm-2, and the implantation angle is 7°. 13 cm -2

[0112] Then an N-type column is implanted in the upper part of the main trench, the depth of the N-type column is 1.6 μm, the impurity of the N-type column is phosphorus ion, the energy is 7 keV, the dose is 1.5 x 1014cm-2, and the implantation angle is 7°, wherein the N-type column doping concentration gradually increases from the bottom to the top to match the drift layer gradient. 14 cm -2

[0113] Then photoresist and 650 nm thick silicon oxide hard mask are implanted as a mask to expose only the trench area of the main trench.

[0114] The high-temperature annealing process is carried out by a high-temperature inert atmosphere annealing furnace, the annealing temperature is 1650 °C, the argon flow rate is 600 sccm, the pressure is 2 atm, and the annealing time is 50 min.

[0115] Forming N + region:

[0116] Exposing the surface area on both sides of the trench array by a photoresist mask, arsenic ions are implanted into the exposed area, the energy is 180 keV, the dose is 1 x 1014cm-2, and the implantation angle is 7°. 19 cm -2

[0117] Then activation annealing is performed, wherein the annealing temperature is 1150 °C, the annealing is carried out in a nitrogen atmosphere, the nitrogen flow rate is 400 sccm, and the annealing time is 25 min.

[0118] Aluminum oxide is used as the dielectric material of the gate electrode, and atomic layer deposition device is used, trimethylaluminum and water are used as precursors, trimethylaluminum and water are respectively pulsed for 0.1 s, and then cleaned for 2 s, and then deposited at 300 °C, 3 Torr for 15 nm, and then rapid thermal annealing is performed, wherein the rapid thermal annealing temperature is 430 °C, and the annealing is carried out in a nitrogen atmosphere for 40 s to repair deposition defects.

[0119] Titanium is used as the target material, the argon and nitrogen flow rate ratio is 9:1, the power is 400 W, the deposition rate is 8 nm / min, and the thickness of the titanium nitride gate electrode is 3 μm, and then chemical mechanical polishing is performed, the polishing surface flatness is ≤5 nm, and the source and drain regions of the AlGaN surface are exposed.

[0120] ​​​Monolayer graphene grown by chemical vapor deposition, wherein the size of the monolayer graphene is ≥ the substrate area, is transferred to the source-drain surface by PMMA-assisted transfer, PMMA is removed by soaking in acetone for 60 min, the source-drain electrode is defined by UV lithography, and the excess graphene is removed by oxygen plasma etching, and ohmic contact annealing is performed.

[0121] A SiO2 passivation layer is deposited by plasma-enhanced chemical vapor deposition, and then a gate, source, and drain contact hole is opened by photolithography and ICP etching, Ti / Au is sputtered as a lead wire, and an interconnection pattern is defined by photolithography and etching.

[0122] Example 2

[0123] The difference from Example 1 is that the main trench depth is 2.2 μm, the width is 0.4 μm, and the pitch is 0.8 μm.

[0124] The secondary trench depth is 0.6 μm, the width is 0.15 μm, and the pitch is 0.4 μm.

[0125] Example 3

[0126] The difference from Example 1 is that the 4H-SiC substrate is selected to be 8 inches in diameter.

[0127] The bottom N-type drift layer is grown by chemical vapor deposition at 1520°C, 150 Torr, 60 sccm flow rate of methane silicon, and 3 sccm flow rate of ammonia, the thickness of the bottom N-type drift layer is 3 μm, and the doping concentration is 2×10 15 cm -3 .

[0128] The middle N-type drift layer is then grown by chemical vapor deposition at 1550°C, 200 Torr, 80 sccm flow rate of methane silicon, and 7 sccm flow rate of ammonia, the thickness of the middle N-type drift layer is 4 μm, and the doping concentration is 6×10 15 cm -3 .

[0129] The upper N-type drift layer is then grown by chemical vapor deposition at 1580°C, 250 Torr, 100 sccm flow rate of methane silicon, and 10 sccm flow rate of ammonia, the thickness of the upper N-type drift layer is 2 μm, and the doping concentration is 2×10 16 cm -3 .

[0130] The main trench depth is 2.5 μm, the width is 0.6 μm, and the pitch is 1.2 μm.

[0131] The secondary trench depth is 0.5 μm, the width is 0.25 μm, and the pitch is 0.6 μm.

[0132] Example 4

[0133] The difference from Example 1 is that the 4H-SiC substrate is selected to be 8 inches in diameter.

[0134] Then, a middle N-type drift layer is grown by a chemical vapor deposition method at 1550 DEG C, 200 Torr, 80 sccm flow rate of methane silicon and 7 sccm flow rate of ammonia, the thickness of the middle N-type drift layer is 2 microns, and the doping concentration is 6*10 15 cm -3 .

[0135] The main trench has a depth of 2 microns, a width of 0.5 microns, and a pitch of 1 micron;

[0136] The secondary trench has a depth of 0.5 microns, a width of 0.2 microns, and a pitch of 0.5 microns.

[0137] Example 5

[0138] The difference from Example 1 is that an upper N-type drift layer is grown by a chemical vapor deposition method at 1580 DEG C, 250 Torr, 100 sccm flow rate of methane silicon and 10 sccm flow rate of ammonia, the thickness of the upper N-type drift layer is 2 microns, and the doping concentration is 2*10 16 cm -3 .

[0139] The main trench has a depth of 2.3 microns, a width of 0.5 microns, and a pitch of 1.1 microns;

[0140] The secondary trench has a depth of 0.55 microns, a width of 0.2 microns, and a pitch of 0.55 microns.

[0141] The super low on-resistance MOS tube prepared in Example 1-Example 5 is respectively detected for performance, and the results are shown in Table 1 below:

[0142] Table 1

[0143] Graphene contact resistance Breakdown voltage On-resistance Example 1 1.2 x 10 -6 Ω·cm 2 ]]> 680V 5.8 mΩ·mm 2 ]]> Example 2 0.9 x 10 -6 Ω·cm 2 ]] 710V 4.9 mΩ·mm 2 ]] Example 3 1.1 x 10 -6 Ω·cm 2 ]]> 1250V 8.2 mΩ·mm 2 ]] Example 4 0.8 x 10 -6 Ω·cm 2 ]]> 690V 4.5 mΩ·mm 2 ]]> Example 5 0.95 x 10 -6 Ω·cm 2 ]]> 705V 5.2 mΩ·mm 2 ]]>

[0144] From Table 1 above, it can be seen that, in terms of comprehensive indexes, Example 4 is the best embodiment of the application, the on-resistance is the lowest: 4.5 mΩ*mm 2 , which is reduced by 22.4% compared with the basic Example 1, meeting the demand for ultra-low loss; the contact resistance ratio is optimal: 4.2%, which is much lower than the 15% of the traditional electrode scheme, reflecting the significant advantages of the graphene electrode; the withstand voltage is sufficient: 690V, which exceeds the target value of 650V, has a certain design margin, and is suitable for new energy vehicle inverters, photovoltaic inverters and other high-voltage and large-current scenes.

[0145] It will be apparent to those skilled in the art that the application is not limited to the details of the above-exemplified embodiments and that the present application can be implemented in other particular forms without departing from the spirit or essential characteristics of the present application. The embodiments should therefore be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the above description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A method for preparing an ultra-low on-resistance MOS transistor based on the SGT process, characterized in that: The following steps are involved: A nitrogen source is doped and deposited on a 4H-SiC substrate by low-pressure vapor deposition to form an N-type drift layer with a gradually increasing doping concentration from the substrate to the surface. A GaN buffer layer and an AlGaN barrier layer are sequentially grown on the N-type drift layer, and the layers are cooled to room temperature to form a GaN / AlGaN heterojunction. Apply positive photoresist and expose to locate the three-dimensional grooves of the main groove + secondary groove cross array, then use developer to develop and hard bake to form a mask, and etch the three-dimensional grooves; The main trench is implanted in sections to form a gradient super junction of a bottom P-type column and an upper middle N-type column. High temperature annealing treatment is performed and high-dose arsenic ion implantation is used to form an N + district; Deposit aluminum oxide gate dielectric, deposit titanium nitride by magnetron sputtering to completely fill the trench and then polish, then carry out electrode preparation, passivation and metal interconnection; Positioning the three-dimensional groove includes the following steps: First, apply positive photoresist with a coating thickness of 1.5-2 μm, a soft baking temperature of 90-100°C, and a soft baking time of 60-90 seconds; Then electron beam lithography exposure is performed, the electron beam acceleration voltage is 100-150kV, and the electron beam charge density is 50-80μC / cm 2 ; The developer is used for developing for 30-45 seconds, the hard baking temperature is 120-130°C, and the hard baking time is 30-60 seconds to form a photoresist mask; The three-dimensional groove pattern design parameters are: The main groove depth is 2.0-2.5μm, the width is 0.4-0.6μm, and the spacing is 0.8-1.2μm; The secondary grooves have a depth of 0.4-0.6 μm, a width of 0.15-0.25 μm, and a spacing of 0.4-0.6 μm. The secondary grooves are evenly distributed between the main grooves.

2. The method for preparing an ultra-low on-resistance MOS transistor based on the SGT process according to claim 1, characterized in that: The diameter of the 4H-SiC substrate is 6-8 inches and the crystal orientation is <0001> , the bias angle is 4°, and the donor concentration of the 4H-SiC substrate is 5×10 18 -1×10 19 cm -3 , thickness of 350-500μm; The 4H-SiC substrate is pretreated before doping deposition: ultrasonic cleaning is performed with acetone, ethanol and deionized water in sequence for 10-15 minutes, soaking in a buffered oxide etching solution with a volume ratio of ammonium fluoride to hydrogen fluoride of 6:1 for 5-8 minutes, and then high-temperature deoxidation treatment is performed at 1100-1200° C. in a hydrogen atmosphere for 30-60 minutes.

3. The method for preparing an ultra-low on-resistance MOS transistor based on the SGT process according to claim 1, characterized in that: The formation of the N-type drift layer comprises the following steps: First, the bottom N-type drift layer is grown by chemical vapor deposition at 1500-1550℃, 100-200Torr, 50-80sccm flow rate of methane silicon and 2-5sccm flow rate of ammonia. The thickness of the bottom N-type drift layer is 2-3μm and the doping concentration is 1×10 15 -2×10 15 cm -3 ; Then, the middle N-type drift layer is grown by chemical vapor deposition at 1520-1580°C, 150-250 Torr, 60-90 sccm flow rate of methane silicon and 5-8 sccm flow rate of ammonia. The thickness of the middle N-type drift layer is 2-4 μm, and the doping concentration is 5×10 15 -8×10 15 cm -3 ; Then, the upper N-type drift layer is grown by chemical vapor deposition at 1560-1600°C, 200-300 Torr, 80-120 sccm flow rate of methane silicon and 8-12 sccm flow rate of ammonia. The thickness of the upper N-type drift layer is 1-2 μm and the doping concentration is 2×10 16 -3×10 16 cm -3 .

4. The method for preparing an ultra-low on-resistance MOS transistor based on the SGT process according to claim 1, characterized in that: The method comprises the following steps: depositing a gallium nitride buffer layer and an aluminum gallium nitride barrier layer in sequence by a molecular beam epitaxy device; First, heat to 850-900°C and grow a gallium nitride buffer layer on the top of the N-type drift layer. The gallium nitride buffer layer has a thickness of 50-80nm, a growth rate of 0.5-1nm / s, and a nitrogen flow rate of 30-50sccm; Then the temperature is lowered to 750-800°C to grow a gallium aluminum nitride barrier layer. The gallium aluminum nitride barrier layer has a thickness of 20-30nm, a growth rate of 0.2-0.3nm / s, a flow ratio of aluminum source to gallium source of (5-7):20, and a nitrogen flow rate of 40-60sccm.

5. The method for preparing an ultra-low on-resistance MOS transistor based on the SGT process according to claim 1, characterized in that: The three-dimensional trench is etched by an inductively coupled plasma etching device, wherein the etching gas is a mixed gas of sulfur hexafluoride and oxygen with a flow ratio of 6:1, and the total flow rate of the etching gas is 50-80 sccm; The power of the inductively coupled plasma etching device is 600-800W, the RF bias power is 100-150W, the pressure is 10-20mTorr, and the etching rate is 50-80nm / min; The three-dimensional trench etching comprises the following steps: First, the secondary trench is etched, and the sidewall polymer is removed by driving an oxygen plasma at 200W power for 10-15s. Etch the main trench again, and then drive oxygen plasma at 200W power to remove the sidewall polymer for 10-15s; Then, the residual etching products were removed by ultrasonic cleaning with deionized water for 5-10 minutes to ensure that the roughness of the trench sidewall was ≤0.5 nm.

6. The method for preparing an ultra-low on-resistance MOS transistor based on the SGT process according to claim 1, characterized in that: The main trench segmented implantation to form a gradient super junction of a bottom P-type column and an upper middle N-type column includes the following steps: First, a P-type column is implanted at the bottom of the main trench. The depth of the P-type column is 0.5-0.8 μm. The impurity of the P-type column is boron ion. The energy is 80-120 keV and the dose is 4×10 13 -6×10 13 cm -2 , the injection angle is 7°; Then, an N-type column is implanted in the upper middle portion of the main trench. The depth of the N-type column is 1.2-1.8 μm. The impurities of the N-type column are phosphorus ions. The energy is 50-80 keV and the dose is 1.5×10 14 -2.5×10 14 cm -2 , the injection angle is 7°, where the N-type pillar doping concentration gradually increases from bottom to top to match the drift layer gradient; Then, photoresist and a silicon oxide hard mask with a thickness of 500-800 nm are injected as a mask to expose only the trench area of ​​the main trench; The high temperature annealing treatment is performed in a high temperature inert atmosphere annealing furnace, with an annealing temperature of 1600-1650° C., an argon gas flow rate of 500-800 sccm, a pressure of 1-2 atm, and an annealing time of 30-60 min.

7. The method for preparing an ultra-low on-resistance MOS transistor based on the SGT process according to claim 1, characterized in that: Formation of N + The district includes the following steps: The surface areas on both sides of the trench array were exposed through a photoresist mask, and arsenic ions were implanted into the exposed areas with an energy of 150-200 keV and a dose of 8×10 18 -1×10 19 cm -2 , the injection angle is 7°; Then, activation annealing is performed, wherein the annealing temperature is 1100-1200° C., the annealing is performed in a nitrogen atmosphere, the nitrogen flow rate is 300-500 sccm, and the annealing time is 15-30 minutes.

8. An ultra-low on-resistance MOS tube based on SGT process, characterized in that: An ultra-low on-resistance MOS transistor prepared by the preparation method according to any one of claims 1 to 7.

9. An application of an ultra-low on-resistance MOS tube based on SGT process, characterized in that: Application of the ultra-low on-resistance MOS transistor prepared by the preparation method according to any one of claims 1 to 7 in the semiconductor field.