Semiconductor device

Abstract

The invention discloses a semiconductor device which comprises a substrate, a gate structure, a plurality of insulating intervals, a plurality of first bonding pads, an insulating layer and a high-dielectric-constant material layer. The insulating spacers and the gate structures are alternately disposed on the substrate. The first pad is disposed on the insulating space. The insulating layer covers the insulating interval and the gate structure, and the insulating layer covering the gate structure is provided with a recess. The high dielectric constant material layer is disposed in the recess, and the bottommost surface of the high dielectric constant material layer is lower than the topmost surface of the first pad. Therefore, by means of the arrangement of the high-dielectric-constant material layer and / or the insulating layer, the structural defect of the top of the gate structure is improved, and the problem of possible short circuit between the gate structure and the metal interconnection line arranged above is avoided.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a gate structure. BACKGROUND

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally, the dynamic random access memory with a recessed gate structure is formed by a large number of memory cells gathered to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from the word line (WL) and the bit line (BL). In response to product demand, the density of the memory cells in the array region must continue to be improved, resulting in increasing difficulty and complexity of related manufacturing processes and designs. Therefore, the existing technology or structure still needs to be further improved to effectively improve the performance and reliability of the related memory device. SUMMARY

[0003] One object of the present invention is to provide a semiconductor device, which additionally provides a high dielectric constant material layer with a recess or a bottom surface lower pad spacer on the gate structure to effectively cover and protect the gate structure. In this way, the structural defects at the top of the gate structure are improved, and the possible short circuit problem between the gate structure and the metal interconnection line arranged above is avoided.

[0004] To achieve the above object, one embodiment of the present invention provides a semiconductor device, which includes a substrate, a gate structure, a plurality of insulating spacers, a plurality of first pads, an insulating layer, and a high dielectric constant material layer. The gate structure is arranged on the substrate. The insulating spacers are arranged on the substrate alternately with the gate structure. The first pads are arranged on the insulating spacers. The insulating layer covers each of the insulating spacers and the gate structure, wherein the insulating layer covering the gate structure has a recess. The high dielectric constant material layer is arranged in the recess, and the bottom surface of the high dielectric constant material layer is lower than the top surface of the first pad.

[0005] To achieve the above object, one embodiment of the present application provides a semiconductor device including a substrate, a gate structure, a first spacer structure, a plurality of insulating spacers, a plurality of first pads, and a plurality of pad spacers. The substrate includes a first region and a second region. The gate structure is disposed on the substrate and located in the first region. The first spacer structure is disposed on a sidewall of the gate structure. The insulating spacers are alternately disposed on the substrate with the gate structure and located in the first region. The first pads are respectively disposed on each of the insulating spacers in the first region. The pad spacers are respectively disposed on sidewalls of each of the first pads in the first region, wherein a bottom surface of the pad spacers is lower than a top surface of the first spacer structure. BRIEF DESCRIPTION OF DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification. The drawings

[0007] Figure 1 FIG. 1 illustrates a cross-sectional view of a semiconductor device according to a first embodiment of the present application.

[0008] Figures 2 to 7 FIG. 2 illustrates a structure obtained by a manufacturing method of a semiconductor device according to a preferred embodiment of the present application.

[0009] Figure 2 FIG. 3 illustrates a cross-sectional view of the semiconductor device after forming a plug hole.

[0010] Figure 3 FIG. 4 illustrates a cross-sectional view of the semiconductor device after forming a metal material layer.

[0011] Figure 4 FIG. 5 illustrates a cross-sectional view of the semiconductor device after forming a pad.

[0012] Figure 5 FIG. 6 illustrates a cross-sectional view of the semiconductor device after forming a first dielectric material layer.

[0013] Figure 6 FIG. 7 illustrates a cross-sectional view of the semiconductor device after forming a second dielectric material layer.

[0014] Figure 7 FIG. 8 illustrates a cross-sectional view of the semiconductor device after forming a capacitor dielectric layer.

[0015] Figure 8 FIG. 9 illustrates a cross-sectional view of a semiconductor device according to a second embodiment of the present application.

[0016] Figure 9 Fig. 3 shows a cross-sectional view of a semiconductor device according to a third embodiment of the present application.

[0017] In the drawings, the following symbols are used:

[0018] 10, 30, 50 semiconductor device

[0019] 100 substrate

[0020] 101 first region

[0021] 102 second region

[0022] 110 shallow trench isolation

[0023] 120 dielectric layer

[0024] 130, 530 gate structure

[0025] 130a gate stack structure

[0026] 132 semiconductor layer

[0027] 134 barrier layer

[0028] 136 metal layer

[0029] 138 cap layer

[0030] 140 first spacer structure

[0031] 140t top surface

[0032] 142 first spacer

[0033] 144 second spacer

[0034] 146 third spacer

[0035] 150 insulating spacer

[0036] 160 first pad

[0037] 160t topmost surface

[0038] 162 barrier layer

[0039] 162a barrier material layer

[0040] 164 metal layer

[0041] 164a metal material layer

[0042] 170, 370, 570 insulating layer

[0043] 172 pad spacer

[0044] 172a first dielectric material layer

[0045] 172b bottom surface

[0046] 174, 374, 574 cap layer

[0047] 174a second dielectric material layer

[0048] 184, 384 high-k material layer

[0049] 184b bottommost surface

[0050] 190 contact structure

[0051] 210 shallow trench isolation

[0052] 220 dielectric layer

[0053] 222 silicon oxide layer

[0054] 224 silicon nitride layer

[0055] 226 silicon oxide layer

[0056] 230 bit line

[0057] 230a bit line plug

[0058] 240 second spacer

[0059] 250 plug

[0060] 250a plug hole

[0061] 252 metal silicide layer

[0062] 260 second pad

[0063] 270 insulating layer

[0064] 272 first dielectric layer

[0065] 274 second dielectric layer

[0066] 280 capacitor structure

[0067] 282 bottom electrode layer

[0068] 284 capacitor dielectric layer

[0069] 286 top electrode layer

[0070] 376 void

[0071] 530a recess

[0072] H height

[0073] R1 recess Detailed Implementation

[0074] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0075] Please refer to Figure 1 As shown, Figure 1 This is a cross-sectional schematic diagram of the semiconductor device 10 according to the first embodiment of the present invention. Figure 1 As shown, the semiconductor device 10 includes a substrate 100, a gate structure 130, a plurality of insulating spacers 150, a plurality of first pads 160, an insulating layer 170, and a high-dielectric-constant material layer 184. The substrate 100 may include, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. In one embodiment, the substrate 100 further includes a first region 101 with relatively low component density, for example, serving as a peripheral region of the semiconductor device 10, and a second region 102 with relatively high component density, for example, serving as a cell region of the semiconductor device 10. The first region 101 and the second region 102 may be arranged adjacent to each other, but are not limited thereto. Furthermore, multiple shallow trench isolation (STI) 110 and 210 are provided in the first region 101 and the second region 102 of the substrate 100, and multiple active areas (AA, not shown) are defined in the substrate 100.

[0076] The gate structure 130 and the insulating spacer 150 are disposed on the substrate 100, and both are located in the first region 101, wherein the insulating spacer 150 is located on both sides of the gate structure 130. The first pad 160 is disposed on the insulating spacer 150, and is covered by the insulating layer 170. The insulating layer 170 also covers the gate structure 130. The high dielectric constant material layer 184 is further disposed on the insulating layer 170. It is particularly noted that the insulating layer 170 covering the gate structure 130 has a recess R1, so that the high dielectric constant material layer 184 is partially disposed in the recess R1, wherein the bottom surface 184b of the high dielectric constant material layer 184 is lower than the top surface 160t of the first pad 160. In this way, the top structure of the gate structure 130 with relatively large line width is protected by the sequential covering of the insulating layer 170 and the high dielectric constant material layer 184, so as to effectively isolate the first pad 160 from physically contacting the gate structure 130, and avoid the possible short circuit problem of the metal interconnection line (such as the contact structure 190) disposed above the first pad 160.

[0077] In one embodiment, the first pad 160 has a height H in a direction perpendicular to the substrate 100 (not shown), and the bottom surface 184b of the high dielectric constant material layer 184 is preferably located below half of the height (i.e., ½H) of the first pad 160, ensuring that the high dielectric constant material layer 184 is completely and effectively covered on the first pad 160 and the gate structure 130, avoiding the two from contacting each other. The semiconductor device 10 further includes a dielectric layer 120 disposed on the bottom of the gate structure 130, and a first spacer structure 140 disposed on the sidewall of the gate structure 130. The dielectric layer 120, for example, includes an insulating material such as silicon oxide, serving as a gate dielectric layer of the gate structure 130, and the first spacer structure 140 is located between the gate structure 130 and the insulating spacer 150, serving as a gate sidewall structure of the gate structure 130. Preferably, the top surface 140t of the first spacer structure 140 is higher than the top surface of the gate structure 130, effectively isolating the gate structure 130 and the first pad 160. In one embodiment, the insulating layer 170 further includes a plurality of pad spacers 172 and a capping layer 174. The pad spacers 172, for example, are disposed on the sidewalls of both sides of the first pad 160 and simultaneously cover the upper half of the sidewall of the first spacer structure 140, and the capping layer 174 is conformally covered on the pad spacers 172 and the first pad 160, such that the insulating layer 170 presents a recess R1 between two adjacent pad spacers 172, but not limited thereto. In addition, a plurality of contact structures 190 are further disposed on the first pad 160, respectively, for example, including a low resistivity metal material such as aluminum (Al), copper (Cu) or tungsten (W), serving as a first layer of metal interconnection of the semiconductor device 10, electrically connected to other conductive structures subsequently disposed above the semiconductor device 10.

[0078] On the other hand, the semiconductor device 10 further includes a plurality of bit lines 230, a plurality of plugs 250, a plurality of second pads 260, and a capacitor structure 280 disposed in the second region 102. The bit lines 230 and the plugs 250 are alternately disposed on the substrate 100 with the second spacer structures 240 disposed therebetween. In an embodiment, the fabrication process of the bit lines 230 is integrated with the fabrication process of the gate structures 130 disposed in the first region 101, such that the bit lines 230 and the gate structures 130 respectively include a semiconductor layer 132, a barrier layer 134, and a metal layer 136 sequentially stacked from bottom to top, and a cap layer 138 is additionally disposed on the metal layer 136 of the bit lines 230. The semiconductor layer 132 includes, for example, a doped polysilicon, a doped amorphous silicon, or other semiconductor materials, the barrier layer 134 includes, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), or other conductive barrier materials, the metal layer 136 includes, for example, copper, aluminum, tungsten, or other suitable low-resistivity conductive materials, and the cap layer 138 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride, or other insulating materials, but not limited thereto. The bit lines 230 are disposed on the dielectric layer 220 in principle, and extend into the substrate 100 through the bit line contacts (BLCs) 230a formed thereunder to electrically connect to the corresponding active regions. In an embodiment, the dielectric layer 220 includes, for example, a silicon oxide layer 222, a silicon nitride layer 224, and a silicon oxide layer 226 sequentially stacked to have an oxide-nitride-oxide (ONO) structure, but not limited thereto. In another embodiment, the fabrication process of the second spacer structures 240 can also be integrated with the fabrication process of the first spacer structures 140 disposed in the first region 101, such that the first spacer structures 140 and the second spacer structures 240 respectively include a first spacer 142, a second spacer 144, and a third spacer 146 sequentially disposed on the sidewalls of the gate structures 130 and the sidewalls of the bit lines 230 in the horizontal direction. The top surface of the second spacer structures 240 is coplanar with the top surface of the bit lines 230, and is higher than the top surface 140t of the first spacer structures 140 located in the first region 101. The first spacer 142 and the third spacer 146 include, for example, the same insulating material, such as silicon nitride, silicon carbon nitride, or the like, and the second spacer 144 includes, for example, an insulating material different from the first spacer 142 and the third spacer 146, such as silicon oxide, silicon oxynitride, or the like, but not limited thereto.

[0079] The plug 250, for example, comprises an epitaxial material such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), and the like, to physically contact the active region as a storage node contact (SN contact) of the semiconductor device 10. The second pads 260 are disposed above the plug 250 as storage node pads (SN pads) of the semiconductor device 10, and the capacitor structure 280 is disposed on the second pads 260. In detail, the adjacent second pads 260 are isolated from each other by the insulating layer 270, and a metal silicide layer 252, for example, comprising a metal silicide material such as cobalt disilicide (CoSi2), titanium silicide (TiSi2), or nickel silicide (Ni2Si), but not limited thereto, is further disposed between the second pads 260 and the plug 250. In an embodiment, the fabrication process of the second pads 260 is integrated with the fabrication process of the first pads 160 disposed in the first region 101, such that the second pads 260 and the first pads 160 respectively comprise a barrier layer 162 and a metal layer 164 stacked in sequence. The barrier layer 162, for example, comprises a conductive barrier material such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and the like, and the metal layer 164, for example, comprises copper, aluminum, tungsten, or other suitable low resistivity conductive material, but not limited thereto.

[0080] In one embodiment, the insulating layer 270 includes a first dielectric layer 272 and a second dielectric layer 274 stacked in sequence, wherein the first dielectric layer 272 and the second dielectric layer 274 can have the same or different insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, etc., preferably both including silicon nitride, but not limited thereto. Also, the fabrication process of the insulating layer 270 can be integrated with the fabrication process of the insulating layer 170 disposed in the first region 101, such that the pad spacer 172 of the insulating layer 170 includes the same material as the first dielectric layer 272, and the cap layer 174 of the insulating layer 170 includes the same material as the second dielectric layer 274, but not limited thereto. The capacitor structure 280 includes a plurality of bottom electrode layers 282, a capacitor dielectric layer 284, and a top electrode layer 286 disposed in sequence, constituting a plurality of vertically-extended capacitors as storage nodes (SN) of the semiconductor device 10 and physically contacting the underlying storage node pads (i.e., the second pads 260), respectively. For example, the bottom electrode layer 282 includes titanium nitride, the top electrode layer 286 includes a composite structure of titanium nitride and silicon germanium, and the capacitor dielectric layer 284 includes a high dielectric constant dielectric material selected from a group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO2), titanium oxide (TiO2), and zirconium-aluminum-zirconium oxide (ZAZ), preferably including zirconium-aluminum-zirconium oxide, but not limited thereto. In a preferred embodiment, the fabrication process of the capacitor dielectric layer 284 can be integrated with the high dielectric constant material layer 184 disposed in the first region 101, for example, by simultaneously forming the capacitor dielectric layer 284 and the high dielectric constant material layer 184 in the first region 101, such that the capacitor dielectric layer 284 and the high dielectric constant material layer 184 include the same material.

[0081] Under this arrangement, the capacitor and a transistor assembly (not shown) disposed in the second region 102 of the substrate 100 can constitute a minimum-constituent memory cell to receive voltage information from the bit line 230 and a word line (not shown), so that the semiconductor device 10 of the present embodiment constitutes a dynamic random access memory (DRAM) device and achieves more optimized operational performance. According to the semiconductor device 10 of the present embodiment, the high-dielectric-constant material layer 184 disposed on the gate structure 130 and the insulating layer 170 thereunder are additionally arranged to cover and protect the top structure of the gate structure 130, so as to ensure that the metal interconnection line subsequently disposed in the first region 101 is electrically connected to the first pad 160 only and does not contact the gate structure 130, thereby avoiding possible short-circuit problems. Moreover, the high-dielectric-constant material layer 184 and the insulating layer 170 disposed in the first region 101 can be formed together with the assembly disposed in the second region 102 in the same manufacturing process, without the need to perform additional operations or processes, so that the semiconductor device 10 of the present embodiment can have more reliable structure and performance under the premise of simplified manufacturing.

[0082] Those of ordinary skill in the art of the present application should easily understand that, in order to meet the requirements of actual products, the semiconductor device of the present application can also have other forms and is not limited to the foregoing. Further embodiments or variations of the semiconductor device of the present application will be described below. For simplicity, the following description mainly focuses on the differences between the embodiments and does not repeat the same parts. In addition, the same components in the embodiments of the present application are denoted by the same reference numerals for the purpose of mutual comparison between the embodiments.

[0083] For example Figure 1As shown, in another embodiment, the semiconductor device 10 may also include a substrate 100, a gate structure 130, a plurality of insulating spacers 150, a first spacer wall structure 140, a plurality of first pads 160, and a plurality of pad spacer walls 172. The gate structure 130 and the insulating spacers 150 are respectively disposed on the substrate 100, both located within the first region 101, such that the insulating spacers 150 are located on both sides of the gate structure 130. The first spacer wall structure 140 is disposed on the sidewall of the gate structure 130 and is located between the gate structure 130 and the insulating spacers 150. The first pads 160 are disposed on the insulating spacers 150. It should be particularly noted that the plurality of pad spacer walls 172 are respectively disposed on the sidewall of the first pads 160, and simultaneously cover the upper half of the sidewall of the first spacer wall structure 140, such that the bottom surface 172b of the pad spacer wall 172 is lower than the top surface 140t of the first spacer wall structure 140. Therefore, the pad gap wall 172 can effectively isolate the physical contact between the first pad 160 and the gate structure 130, ensuring that the subsequent metal interconnects (such as the contact structure 190) are only electrically connected to the first pad 160 and do not contact the gate structure 130, thus avoiding possible short circuit problems.

[0084] To enable those skilled in the art to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.

[0085] Please see Figures 2 to 7 The diagram shown illustrates a method for fabricating the semiconductor device 10 according to a preferred embodiment of the present invention. First, as... Figure 2 As shown, a substrate 100 is provided, and shallow trench isolations 110 and 210 are formed in a first region 101 and a second region 102 of the substrate 100, respectively, while the active regions are defined simultaneously in the first region 101 and the second region 102. In one embodiment, the shallow trench isolations 110 and 210 are formed, for example, by first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then filling the trenches with at least one insulating material (such as silicon oxide, silicon nitride, etc.) to form shallow trench isolations 110 and 210 with surfaces flush with the top surface of the substrate 100, but this is not a limitation.

[0086] Next, a plurality of buried word lines (not shown) are formed on the first region 101 and the second region 102 of the substrate 100. In one embodiment, the buried word lines are formed by a process including, but not limited to, the following steps, for example, forming a plurality of trenches (not shown) that can simultaneously pass through a plurality of the active regions and the shallow trench isolation 210, forming a dielectric layer (not shown) covering the entire surface of the trenches, forming a gate dielectric layer (not shown) covering the lower half of the surface of the trenches, forming a gate (not shown) filling the lower half of the trenches, and forming a cap layer (not shown) filling the upper half of the trenches, but not limited thereto. Also, a dielectric layer 120 and a dielectric layer 220 are formed on the first region 101 and the second region 102 of the substrate 100, respectively. In one embodiment, the dielectric layer 120 and the dielectric layer 220 are formed by a process including, but not limited to, the following steps, for example, forming a dielectric material layer including a first silicon oxide material layer (not shown), a silicon nitride material layer (not shown), and a second silicon oxide material layer (not shown) stacked in sequence on the first region 101 and the second region 102 of the substrate 100, and removing at least the second silicon oxide material layer and the silicon nitride material layer formed on the first region 101 of the substrate 100, so that the first silicon oxide material layer on the first region 101 of the substrate 100 forms the dielectric layer 120, and the dielectric material layer on the second region 102 of the substrate 100 forms the dielectric layer 220. Alternatively, in another embodiment, the dielectric material layer on the first region 101 of the substrate 100 can also be completely removed, and then the dielectric layer 120 is formed again.

[0087] Then, a plurality of gate stack structures 130a and a plurality of bit lines 230 are formed on the first region 101 and the second region 102 of the substrate 100, respectively, by a similar process. The gate stack structures 130a have a relatively larger line width than the bit lines 230, but are not limited thereto. In one embodiment, the gate stack structures 130a and the bit lines 230 are formed by a process including, but not limited to, the following steps. First, a plurality of openings (not shown) are formed in the second region 102 to pass through the dielectric layer 220 and partially expose the substrate 100, a semiconductor material layer (not shown, for example, including a plurality of semiconductor materials such as polysilicon, doped amorphous silicon, etc.) is formed in the first region 101 and the second region 102 to fill the openings, a barrier material layer (not shown, for example, including a plurality of conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal material layer (not shown, for example, including a plurality of low-resistance metal materials such as tungsten, aluminum, or copper, etc.), and a cap material layer (not shown, for example, including a plurality of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, etc.) are formed on the semiconductor material layer, and finally, the gate stack structures 130a and the bit lines 230 are formed simultaneously by a patterning process. Figure 2The gate stack structure 130a and the bit line 230 are shown with an integral bit line plug 230a formed underneath a portion of the bit line 230. The gate stack structure 130a and the bit line 230 each include, from bottom to top, a semiconductor layer 132, a barrier layer 134, a metal layer 136, and a cap layer 138.

[0088] In another embodiment, as shown in FIG. 1C, the first spacer structure 140 and the second spacer structure 240 are formed on the sidewalls of the gate stack structure 130a and the bit line 230, respectively, by a same process. Figure 2 The first spacer structure 140 and the second spacer structure 240 each include, from bottom to top, a first spacer 142 (e.g., including silicon nitride, silicon carbon nitride), a second spacer 144 (e.g., including silicon oxide, silicon oxynitride), and a third spacer 146 (e.g., including silicon nitride, silicon carbon nitride), but are not limited thereto.

[0089] Then, a deposition and etch-back process is performed to form an insulating material between adjacent gate stack structures 130a and between adjacent bit lines 230, such that the insulating material formed in the first region 101 forms an insulating spacer 150. Next, the insulating material between adjacent bit lines 230 is removed through a mask layer (not shown) to form a plurality of plug holes 250a in the second region 102 that partially expose the substrate 100, as shown in FIG. 1D. Figure 2 The mask layer is then completely removed, as shown in FIG. 1E.

[0090] An epitaxial process is performed to form a plug 250 in the plug hole 250a in the second region 102, as shown in FIG. 1F. A metal silicide process is then performed on the plug 250 to form a metal silicide layer 252. In one embodiment, the plug 250 includes an epitaxial material such as silicon, silicon phosphorous, silicon germanium, or germanium, and the metal silicide layer 252 includes a metal silicide material such as cobalt disilicide, titanium silicide, or nickel silicide, but is not limited thereto. Thus, the plug 250 formed can serve as a storage node plug for the semiconductor device 10. Figure 3 A deposition process is then performed to form a barrier material layer 162a (e.g., including a conductive barrier material such as titanium and / or titanium nitride, tantalum and / or tantalum oxide) and a metal material layer 164a (e.g., including copper, aluminum, tungsten, or other suitable low resistivity metal material) on the first region 101 and the second region 102 of the substrate 100 simultaneously, as shown in FIG. 1G. A portion of the barrier material layer 162a is formed in the plug hole 250a, another portion of the barrier material layer 162a is formed outside the plug hole 250a, and the remaining space of the plug hole 250a is filled with a portion of the metal material layer 164a. Figure 2

[0091] An epitaxial process is performed to form a plug 250 in the plug hole 250a in the second region 102, as shown in FIG. 1F. A metal silicide process is then performed on the plug 250 to form a metal silicide layer 252. In one embodiment, the plug 250 includes an epitaxial material such as silicon, silicon phosphorous, silicon germanium, or germanium, and the metal silicide layer 252 includes a metal silicide material such as cobalt disilicide, titanium silicide, or nickel silicide, but is not limited thereto. Thus, the plug 250 formed can serve as a storage node plug for the semiconductor device 10. Figure 4 ​As shown, a first pad 160 and a second pad 260 are formed on the first region 101 and the second region 102 of the substrate 100 respectively through another mask layer (not shown), and then the other mask layer is completely removed. The first pad 160 has a height H, for example, in the direction perpendicular to the substrate 100, but is not limited thereto. It should be noted that the first pad 160 is formed on the insulating spacer 150 and the first spacer wall structure 140, and when forming the first pad 160, the capping layer 138 of the gate stack structure 130a is also removed synchronously by adjusting the etching parameters to form the gate structure 130. On the other hand, the second pad 260 is partially formed on the bit line 230 and the second spacer wall structure 240, and partially formed on, for example, Figure 2 The plug 250 is electrically connected to the metal silicide layer 252 through the plug hole 250a shown. Thus, the second pad 260 formed can serve as the storage node pad of the semiconductor device 10.

[0092] like Figure 5 As shown, a deposition process is performed to simultaneously form a first dielectric material layer 172a on the first region 101 and the second region 102 of the substrate 100. This dielectric material layer may be an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. The first dielectric material layer 172a integrally covers the first pad 160, the first spacer structure 140, and the gate structure 130 within the first region 101, and similarly integrally covers the second pad 260, the second spacer structure 240, and the bit line 230 within the second region 102.

[0093] like Figure 6 As shown, an etch-back fabrication process is performed through a second mask layer (not shown) to partially remove the first dielectric material layer 172a formed in the first region 101, forming a pad spacer wall 172, and then the second mask layer is completely removed. The pad spacer wall 172 partially covers the sidewall of the first pad 160 and partially covers the upper half of the sidewall of the first spacer wall structure 140. In a preferred embodiment, the bottom surface 172b of the pad spacer wall 172 is lower than the top surface 140t of the first spacer wall structure 140, effectively isolating the physical contact between the first pad 160 and the gate structure 130.

[0094] Next, another deposition process is performed to simultaneously form a second dielectric material layer 174a on the first region 101 and the second region 102 of the substrate 100. This layer may contain insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. The second dielectric material layer 174a formed in the first region 101 conformally covers the gate structure 130 with a relatively large linewidth and the pad spacer 172, creating a recess R1 between adjacent pad spacers 172. The bottom of the recess R1 may be lower than the bottom surface of the first pad 160, but is not limited to this. Thus, the fabrication of the second dielectric material layer 174a protects and covers the top structure of the gate structure 130, further isolating the physical contact between the first pad 160 and the gate structure 130. On the other hand, the second dielectric material layer 174a formed in the second region 102 just fills the remaining space between adjacent second pads 260, resulting in an overall flat top surface. In one embodiment, the first dielectric material layer 172a and the second dielectric material layer 174a preferably have different insulating materials. For example, the first dielectric material layer 172a may include silicon oxide or silicon oxynitride, and the second dielectric material layer 174a may include silicon nitride or silicon carbonitride, but this is not a limitation.

[0095] like Figure 7 As shown, a planarization process is performed on the second region 102 of the substrate 100, partially removing the second dielectric material layer 174a and the first dielectric material layer 172a. This results in the second dielectric material layer 174a formed in the first region 101 forming a capping layer 174. The capping layer 174 and the pad spacer 172 in the first region 101 together form an insulating layer 170 with a recess R1. On the other hand, the second dielectric material layer 174a and the first dielectric layer 172a formed in the second region 102 form a second dielectric layer 274 and a first dielectric layer 272 with a U-shaped cross-section after the planarization process. The first dielectric layer 272 and the second dielectric layer 274 in the second region 102 together form an insulating layer 270, wherein the top surface of the insulating layer 270 is flush with the top surface of the second pad 260.

[0096] Then, a bottom electrode layer 282 is formed on the insulating layer 270 and the second pad 260, physically contacting the top surface of the second pad 260. The bottom electrode layer 282 includes, for example, but not limited to, titanium nitride. Next, a capacitor dielectric layer 284 is formed on the bottom electrode layer 282, including, for example, a high dielectric constant dielectric material selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zinc oxide, titanium oxide, and zirconium-aluminum-zirconium oxide, and preferably including zirconium-aluminum-zirconium oxide. It is noted that the capacitor dielectric layer 284 can also be formed to further extend into the first region 101 and cover the insulating layer 170 at the same time. Thus, the capacitor dielectric layer 284 formed in the first region 101 is a high dielectric constant material layer 184 as shown in Figure 1 , partially formed in the recess R1 such that the bottommost surface 184b is lower than the topmost surface 160t of the first pad 160. That is, the high dielectric constant material layer 184 in the first region 101 is a part of the capacitor dielectric layer 284 in the second region 102, and the fabrication process of the high dielectric constant material layer 184 can be integrated with the fabrication process of the capacitor dielectric layer 284 in the second region 102, including the same material.

[0097] Then, a top electrode layer 286 is formed on the capacitor dielectric layer 284, such that the top electrode layer 286, the capacitor dielectric layer 284, and the bottom electrode layer 282 in the second region 102 collectively form a capacitor structure 280 as shown in Figure 1 , and the contact structure 190 as shown in Figure 1 is formed in the first region 101, completing the fabrication of the semiconductor device 10 in this embodiment. The vertical capacitance of the capacitor structure 280 and the transistor components (not shown) formed in the second region 102 of the substrate 100 can constitute a minimum-constituted memory cell to receive voltage information from the bit line 230 and the word line, such that the semiconductor device 10 in this embodiment forms the dynamic random access memory device and achieves more optimized operational performance.

[0098] According to the manufacturing method of the present embodiment, the manufacturing processes of the components on the first region 101 and the second region 102 of the substrate 100 are integrated, and the gate structure 130 with relatively large line width and the bit line 230 are formed in the first region 101 and the second region 102 respectively by similar processes. Moreover, the manufacturing processes of the insulating layer 170 and the insulating layer 270 on the first region 101 and the second region 102 are integrated, and / or the manufacturing processes of the high dielectric constant material layer 184 and the capacitor dielectric layer 284 on the first region 101 and the second region 102 are integrated, so as to protect the top structure of the gate structure 130 by the high dielectric constant material layer 184 and / or the insulating layer 170 formed in the first region 101, and avoid the contact between the first pad 160 and the gate structure 130 caused by the removal of the cap layer 138 formed in the first region 101. In this way, the manufacturing method of the semiconductor device in the present embodiment can simplify the manufacturing process, and form the semiconductor device 10 with reliable structure and performance.

[0099] Please refer to Figure 8 , which is a cross-sectional schematic view of a semiconductor device 30 in a second embodiment of the present application. The semiconductor device 30 in the present embodiment has substantially the same structure as the semiconductor device 10 in the foregoing embodiment, and the same parts are not described again. The main difference between the semiconductor device 30 in the present embodiment and the semiconductor device 10 in the foregoing embodiment is that the cover layer 374 in the present embodiment has an aperture 376 located below the recess R1. Figure 1

[0100] In detail, as shown in Figure 8 , the insulating layer 370 in the present embodiment includes the pad spacer 172 and the cover layer 374. The cover layer 374 is conformally formed on the pad spacer 172, the first pad 160, and the gate structure 130 with relatively large line width, so that the cover layer 374 presents a recess (not shown) between two adjacent pad spacers 172. It should be noted that the high dielectric constant material layer 384 formed later further covers and partially seals the recess, forming the recess R1 and the aperture 376 as shown in Figure 8 . In addition to the above, part of the high dielectric constant material layer 384 is also formed in the aperture 376 and directly contacts the aperture 376, but not limited thereto.

[0101] ​Under this arrangement, the semiconductor device 30 of the present embodiment can effectively protect the top structure of the gate structure 130 by the covering of the insulating layer 370 and / or the high dielectric constant material layer 384, and ensure that the metal interconnection lines (e.g., the contact structure 190) subsequently arranged in the first region 101 only electrically connect the first pad 160 without contacting the gate structure 130, thereby avoiding possible short circuit problems. Thus, the dynamic random access memory device composed of the semiconductor device 30 of the present embodiment can also have reliable structure and performance, and achieve more optimized operation performance.

[0102] Please refer to Figure 9 , which is a schematic cross-sectional view of a semiconductor device 50 in a third embodiment of the present application. The semiconductor device 50 of the present embodiment has substantially the same structure as the semiconductor device 10 in the first embodiment, as shown in Figure 1 . The same parts are not described again here. The main difference between the semiconductor device 50 of the present embodiment and the semiconductor device 10 of the first embodiment is that the gate structure 530 of the present embodiment has a top surface recess 530a, and the covering layer 574 fills the recess 530a.

[0103] In detail, as shown in Figure 9 , the insulating layer 570 of the present embodiment includes the pad spacer 172 and the covering layer 574. The covering layer 574 also covers the pad spacer 172, the first pad 160, and the gate structure 530 with a relatively large line width in a common manner, so that the covering layer 574 presents a recess R1 between two adjacent pad spacers 172. It should be noted that in the present embodiment, the etching conditions of the etching-back manufacturing process are adjusted to partially remove the metal layer 136 of the gate structure 530 when the first dielectric material layer 172a in the first region 101 is partially removed, as shown in Figure 5 . Thus, the recess 530a can be formed between two adjacent pad spacers 172, and the sidewall of the recess 530a can also be optionally vertically cut flush with the sidewall of the pad spacer 172, but not limited thereto. Then, the covering layer 574 subsequently formed fills the recess 530a to cover and protect the top structure of the gate structure 530.

[0104] Under this arrangement, the semiconductor device 50 of the present embodiment can effectively protect the top structure of the gate structure 530 by the covering of the insulating layer 570 and / or the high dielectric constant material layer 184, and ensure that the metal interconnection lines (e.g., the contact structure 190) subsequently arranged in the first region 101 only electrically connect the first pad 160 without contacting the gate structure 530, thereby avoiding possible short circuit problems. Thus, the dynamic random access memory device composed of the semiconductor device 50 of the present embodiment can also have reliable structure and performance, and achieve more optimized operation performance.

[0105] In summary, the semiconductor device of the present application integrates the fabrication processes of components in different regions, and additionally provides a high dielectric constant material layer with a recess or a bottom lower pad spacer on the gate structure in the peripheral region under the premise of process simplification, effectively covering and protecting the gate structure, and isolating the gate structure from the possible physical contact between the gate structure and the pad. Thus, the structural defects at the top of the gate structure are improved, and the possible short circuit problem between the gate structure and the metal interconnection line arranged above is avoided.

[0106] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized by, The application relates to a semiconductor structure, comprising: a substrate comprising a first region and a second region; a gate structure disposed on the substrate and located in the first region; a plurality of insulating intervals disposed on the substrate and located in the first region, and arranged alternately with the gate structure; a plurality of first pads disposed on the plurality of insulating intervals; a plurality of first insulating layers located on the gate structure and isolating the plurality of first pads from each other, the first insulating layers comprising a first dielectric layer and a second dielectric layer; a bit line disposed on the substrate and located in the second region; a plurality of plugs disposed on the substrate and located in the second region, and arranged alternately with the bit line; a plurality of second pads disposed on the plurality of plugs; a plurality of second insulating layers located between the plurality of second pads and isolating the plurality of second pads from each other, the second insulating layers comprising the first dielectric layer and the second dielectric layer; wherein the first dielectric layer located between the first pads is discontinuous, and the first dielectric layer located between the second pads is continuous.

2. The semiconductor device according to claim 1, wherein The top surface of the bit line and the top surface of the gate structure are located on different horizontal planes.

3. The semiconductor device according to claim 1, wherein The first insulating layer is in direct contact with the metal layer of the gate structure.

4. A semiconductor device, characterized by The application relates to a semiconductor structure, comprising: a substrate comprising a first region and a second region; a plurality of gate structures disposed on the substrate and located in the first region; an insulating interval disposed on the substrate and located in the first region, and arranged alternately with the gate structure; a plurality of first pads disposed on the plurality of insulating intervals; a plurality of first insulating layers located on the gate structure and isolating the plurality of first pads from each other, the first insulating layers comprising a first dielectric layer and a second dielectric layer; a bit line disposed on the substrate and located in the second region; a plurality of second pads disposed on the substrate and located in the second region, and arranged alternately with the bit line; a plurality of second insulating layers located between the plurality of second pads and isolating the plurality of second pads from each other, the second insulating layers comprising the first dielectric layer and the second dielectric layer; wherein the second dielectric layer of the first insulating layer is located between the first dielectric layer of the first insulating layer and isolates the first dielectric layer of the first insulating layer from each other, and the first dielectric layer of the second insulating layer is continuously connected to two adjacent second pads.

5. The semiconductor device according to claim 4, wherein The top surface of the bit line and the top surface of the gate structure are located on different horizontal planes.

6. The semiconductor device according to claim 4, wherein The first insulating layer is in direct contact with the metal layer of the gate structure.

7. A semiconductor device, characterized by comprising: The application relates to a semiconductor structure, comprising: a substrate comprising a first region and a second region; a gate structure disposed on the substrate and located in the first region; a plurality of insulating intervals disposed on the substrate and located in the first region, and arranged alternately with the gate structure; a plurality of first pads disposed on the plurality of insulating intervals; a plurality of first insulating layers located on the gate structure and isolating the plurality of first pads from each other, the first insulating layers comprising a first dielectric layer and a second dielectric layer; a bit line disposed on the substrate and located in the second region; a plurality of plugs disposed on the substrate and located in the second region, the plurality of plugs being disposed alternately with the plurality of bit lines; a plurality of second pads disposed on the plurality of plugs; a plurality of second insulating layers located between the plurality of second pads and isolating the plurality of second pads from each other, the second insulating layers comprising the first dielectric layers and the second dielectric layers; wherein the second dielectric layers of the first insulating layers are located between the first dielectric layers of the first insulating layers and isolate the first dielectric layers of the first insulating layers from each other, and the first dielectric layers of the second insulating layers are connected continuously to two adjacent second pads.

8. The semiconductor device according to claim 7, wherein top surfaces of the bit lines and top surfaces of the gate structures are located on different horizontal planes.

9. The semiconductor device according to claim 7, wherein the first insulating layers are in direct contact with metal layers of the gate structures.

10. A semiconductor device, characterized by comprising: comprising: a substrate comprising a first region and a second region; a plurality of first conductive structures disposed on the substrate and located in the first region; a plurality of insulating spacers disposed on the substrate and located in the first region, the plurality of insulating spacers being disposed alternately with the plurality of first conductive structures; a plurality of first pads disposed on the plurality of insulating spacers; a plurality of first insulating layers located on the plurality of first conductive structures and isolating the plurality of first pads from each other, the first insulating layers comprising first dielectric layers and second dielectric layers; a plurality of second conductive structures disposed on the substrate and located in the second region; a plurality of plugs disposed on the substrate and located in the second region, the plurality of plugs being disposed alternately with the plurality of second conductive structures; a plurality of second pads disposed on the plurality of plugs; a plurality of second insulating layers located between the plurality of second pads and isolating the plurality of second pads from each other, the second insulating layers comprising the first dielectric layers and the second dielectric layers; wherein the first dielectric layers located between the first pads are discontinuous, and the first dielectric layers located between the second pads are continuous.

11. The semiconductor device according to claim 10, wherein top surfaces of the first conductive structures and top surfaces of the second conductive structures are located on different horizontal planes.

12. The semiconductor device according to claim 10, wherein the first insulating layers are in direct contact with metal layers of the first conductive structures.

13. A semiconductor device, characterized by comprising: comprising: a substrate comprising a first region and a second region; a gate structure disposed on the substrate and located in the first region; a plurality of insulating spacers disposed on the substrate and located in the first region, the plurality of insulating spacers being disposed alternately with the gate structure; a plurality of first pads disposed on the plurality of insulating spacers; a plurality of first insulating layers located on the gate structure and isolating the plurality of first pads from each other, the first insulating layers comprising first dielectric layers and second dielectric layers; a bit line disposed on the substrate and located in the second region; a plurality of plugs disposed on the substrate and located in the second region, the plurality of plugs being disposed alternately with the bit line; a plurality of second pads located on the plurality of plugs; a plurality of second insulating layers located between the plurality of second pads and isolating the plurality of second pads from each other, the second insulating layers comprising the first dielectric layers and the second dielectric layers; The second dielectric layer between the first pads completely covers the top surface of the first pads and the top surface of the first dielectric layer of the second insulating layer.

14. The semiconductor device according to claim 13, wherein The second dielectric layer of the first insulating layer simultaneously contacts the first pads and the top surface of the first dielectric layer of the first insulating layer.

15. The semiconductor device according to claim 14, wherein The semiconductor device further comprises a metal oxide layer on the second dielectric layer of the first insulating layer.

16. The semiconductor device according to claim 15, wherein The metal oxide layer simultaneously contacts the first dielectric layer of the first insulating layer and the second dielectric layer of the first insulating layer.

17. The semiconductor device of claim 13, wherein The first insulating layer directly contacts the metal layer of the gate structure.

18. A semiconductor device, characterized by comprising: Comprising: a substrate; a gate structure disposed on the substrate; a plurality of insulating spacers disposed on the substrate and located on both sides of the gate structure; a plurality of first pads disposed on the insulating spacers; an insulating layer covering the insulating spacers and the gate structure, wherein the insulating layer covering the gate structure has a recess; and a metal oxide layer disposed in the recess, and the bottommost surface of the metal oxide layer is lower than the topmost surface of the first pads.

19. The semiconductor device of claim 18, wherein The substrate comprises a first region and a second region, the gate structure is located in the first region, and the semiconductor device further comprises a plurality of capacitors located on the substrate and located in the second region, the capacitors comprising the metal oxide layer.

20. The semiconductor device of claim 18, wherein The insulating layer directly contacts the metal layer of the gate structure.

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