Systems and methods for low density parity check (LDPC) codes with 3 / 4 code rates

Abstract

The present disclosure relates to systems and methods for low density parity check (LDPC) codes with 3 / 4 code rates. In some embodiments, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify a first binary parity check matrix for a quasi-cyclic low density parity check (QC-LDPC) code according to a code rate of 3 / 4 and a code block size of 3888 bits. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to each of U.S. Provisional Patent Application No. 63 / 516,688 filed on July 31, 2023, U.S. Provisional Patent Application No. 63 / 516,700 filed on July 31, 2023, U.S. Provisional Patent Application No. 63 / 600,327 filed on November 17, 2023, and U.S. Provisional Patent Application No. 63 / 600,331 filed on November 17, 2023, all of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] The present disclosure generally relates to systems and methods for improving the encoding process and / or decoding process of a communication system using a quasi-cyclic low-density parity-check (QC-LDPC) code. Background Art

[0004] Error correction codes enable information data to be exchanged between a transmitter communication system and a receiver communication system in a reliable manner. The transmitter communication system encodes the information data to obtain a codeword. The codeword is the encoded information data. The transmitter communication system transmits the codeword to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may not be the same as the transmitted codeword. Encoding the information data allows a receiver communication system with an appropriate decoding process to recover the information data from the received transmission despite such noise. For example, the transmitter communication system transmits parity bits to the receiver communication system. The parity bits allow the receiver communication system to verify whether the received transmission is a valid codeword, and if the received transmission is not a valid codeword, then correct the errors in the transmission. In one method, generating parity bits involves a complex process. Summary of the invention

[0005] In one aspect, the present disclosure provides a method, comprising: identifying, by one or more processors of a first device, a first binary parity check matrix for a quasi-cyclic low-density parity check (QC-LDPC) code based on a code rate of 3 / 4 and a code block size of 3888 bits, the first binary parity check matrix corresponding to a first exponential matrix having 144 values; encoding data using the first binary parity check matrix by the one or more processors of the first device; and transmitting the encoded data by the one or more processors of the first device.

[0006] In another aspect, the present disclosure provides a device comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify a first binary parity check matrix for a quasi-cyclic low-density parity check (QC-LDPC) code based on a code rate of 3 / 4 and a code block size of 3888 bits, the first binary parity check matrix corresponding to a first exponential matrix having 144 values; encode data using the first binary parity check matrix; and transmit the encoded data.

[0007] In another aspect, the present disclosure provides an apparatus comprising: a receiver configured to receive encoded data; and one or more processors configured to: identify a first binary parity check matrix for a quasi-cyclic low-density parity check (QC-LDPC) code based on a code rate of 3 / 4 and a code block size of 3888 bits, the first binary parity check matrix corresponding to a first exponential matrix having 144 values; and decode the received encoded data using the first binary parity check matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout the text. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0009] Figure 1 is a diagram depicting an example communication environment having a communication system in accordance with one or more embodiments.

[0010] Figure 2 is a schematic block diagram of a computing system according to an embodiment.

[0011] Figure 3 is a diagram depicting an example index matrix in accordance with one or more embodiments.

[0012] Figure 4 is a diagram depicting an example shifted identity matrix for generating a parity-check matrix in accordance with one or more embodiments.

[0013] Figure 5 is a diagram depicting an example parity-check matrix in accordance with one or more embodiments.

[0014] Fig. 6A and 6B is a diagram depicting an example code design using a prototype enhancement concept / method in accordance with one or more embodiments.

[0015] Fig. 7A , 7B, 7C, and 7D are diagrams depicting example codes for concurrent decoding according to one or more embodiments.

[0016] Figure 8 is a flowchart showing a process of encoding data using an LDPC code according to an embodiment.

[0017] Fig. 9 is a flowchart showing a process of encoding data and / or decoding data using an LDPC code according to an embodiment.

[0018] Fig. 10A , 10B , 10C, 10D, 10E, and 10F are diagrams depicting example simulation results using QC-LDPC codes according to one or more embodiments.

[0019] The details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, a first feature communicates with a second feature or is communicatively coupled to an embodiment in which the first feature directly communicates with the second feature or is directly coupled to the second feature, and may also include an embodiment in which an additional feature may be between the first and second features so that the first feature indirectly communicates with the second feature or is indirectly coupled to the second feature. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Various embodiments disclosed herein relate to a device comprising a transmitter and one or more processors. One or more processors may be configured to determine a quasi-cyclic low-density parity check (QC-LDPC) code in which multiple codebooks are embedded. One or more processors may be configured to select a codebook from multiple codebooks according to a code block size and a code rate. One or more processors may be configured to generate a parity check matrix based on the codebook. A parity check matrix refers to a matrix that can define a relationship between information bits and parity check bits (e.g., a parity check equation or constraint). A binary parity check matrix refers to a parity check matrix in which all entries are 0 or 1. One or more processors may be configured to encode data using the generated parity check matrix. One or more processors may be configured to transmit encoded data to another device via a transmitter.

[0022] In some embodiments, each of the plurality of codebooks may include a plurality of integers, the number of the plurality of integers being equal to the number of elements of the parity check matrix divided by z, where z is an integer representing the lifting size of the QC-LDPC code.

[0023] In some embodiments, each of the plurality of codebooks may represent an exponent matrix of the parity check matrix. In some embodiments, each element of the exponent matrix may correspond to a cyclic shift value of the identity matrix. The size of the identity matrix is z x z, and the cyclic shift value d is an integer such that -1 ≤ d < z, where z is an integer representing the lifting size of the QC-LDPC code. The cyclic shift value d may represent the shifted identity matrix obtained by shifting the identity matrix to the right by d. The cyclic shift value -1 may represent the zero matrix of the identity matrix.

[0024] In some embodiments, when generating a parity check matrix based on the selected codebook, one or more processors may be configured to generate an exponent matrix based on the selected codebook. For each element of the exponent matrix, one or more processors may be configured to generate a shifted identity matrix of the identity matrix based on the value of each element of the exponent matrix. One or more processors may be configured to generate a parity check matrix such that the parity check matrix includes the generated shifted identity matrix as an element corresponding to each element of the exponent matrix.

[0025] In some embodiments, the code block size may be 3888 bits and the code rate may be 3 / 4. The code block size (represented by n) refers to the total number of encoded or transmitted bits as a result of encoding the data using an error correction code (e.g., LDPC). The number of information bits (represented by k) refers to the number of bits that carry data to be encoded using an error correction code. The code rate (represented by R) refers to the ratio of the number of information bits to the code block size (R=k / n). The plurality of codebooks may include a codebook comprising [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 972261-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1 92 790-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0].

[0026] In one aspect, a parity check matrix defines a set of equations satisfied by any valid codeword. Parity check matrices can be used to encode low-density parity check ("LDPC") codes, as described by Richardson and Urbanke in IEEE Transactions on Information Theory, Vol. 47, No. 2 (February 2001). Typically, many wireless and wired communication systems use LDPC as a forward error correction coding scheme. However, the longest block length (in bits) of coded data supported in 802.11 standards (e.g., 802.11n to 802.11be) is 1944. There may be limited gain in a radio channel (e.g., 2x2 multiple-input and multiple-output channels), which can be achieved using a block length of 1944.

[0027] To address this problem, according to certain aspects, embodiments in the present disclosure relate to techniques for supporting or providing LDPC codes having a block length of 3888 and a code rate of 3 / 4. The block length of 3888 is twice the block length of the longest code supported in the 802.11n to 802.11be standards (e.g., a block length of 1944). In some embodiments, the LDPC code has a quasi-cyclic (QC) structure, which facilitates efficient encoding and decoding. In some embodiments, the QC-LDPC code may be a class of structured LDPC codes that can be used in many practical applications, including IEEE 802.11n, 802.11ac, 802.11ax, 802.11be standards. In the QC-LDPC code, the parity check matrix has a cyclic structure that repeats itself in a quasi-cyclic manner, which can simplify the encoding and decoding process, thereby making the QC-LDPC code more efficient.

[0028] In some embodiments, the LDPC encoder may take a block of k bits of information bits and produce n coded bits (with a code rate R = k / n). The LDPC decoder may operate on the n received bits (noise versions) and (ideally) recover k information bits. In some embodiments, the LDPC encoder may take a block of 2916 bits of information bits (k = 2916) as input, encode the block of 2916 bits to produce a block of 3888 coded bits (n = 3888) with a code rate of 3 / 4 (R = k / n).

[0029] Typically, the parity check matrix of a code represents an equation that determines whether an error occurred during transmission. More formally, for all valid codewords (i.e., bits produced by the encoder that do not have errors), the following equation may hold:

[0030] Hc=0………………(Equation 1)

[0031] In Equation 1, "H" is the parity check matrix, "c" is the codeword vector, and "0" is a vector of all zeros. The parity check matrix H is one way to describe the code.

[0032] The code generator matrix G satisfies the following equation:

[0033] sG=c………………(Equation 2)

[0034] In Equation 2, “s” is a vector of information bits, “G” is a generator matrix, and “c” is a codeword corresponding to “s.” In some embodiments, a system (e.g., a communication system 108 including a decoder 160) may decode the codeword c using Equation 2 to obtain decoded data s.

[0035] According to the above matrix equation, the parity check matrix and the generator matrix of the code are relevant. Usually, if the parity check matrix is ​​low-density, the corresponding generator matrix will be high-density, and vice versa. LCPC code is characterized by low-density parity check matrix and high-density generator matrix accordingly. The density of the matrix is ​​related to the number of operations that one of the above equations must perform. Although it has been recognized by 1995 that LDPC code can be used for transmitting data with very few errors, that is, with an error rate as good as or better than turbo code, a shortcoming of LDPC code is that its generator matrix is ​​high-density, and this makes the coding calculation intensive, thereby making the code impractical for many applications.

[0036] In some implementations, the parity check matrix may have a quasi-cyclic structure, such as the parity check matrix for QC-LDPC codes (n=3888, k=2916, R=3 / 4). For example, given a lifting size Z, the parity check matrix may have multiple sub-matrices such that each sub-matrix is ​​a cyclic shifted version of the identity matrix of size (Z x Z), where Z=162. The parity check matrix can be represented in two equivalent forms: (1) a parity check matrix H and (2) a block matrix or exponential matrix P=E(H).

[0037] In some implementations, the parity check matrix H may be a binary matrix of size mxn (each of m and n is an integer). The elements of the parity check matrix are binary values. Given a block length n and a code rate R, an LDPC code (or QC-LDPC code) LDPC (n, R) satisfies the following equation:

[0038] k = nR ... (Equation 3)

[0039] m=n(1-R)……(Equation 4)

[0040] In some embodiments, a block matrix or exponential matrix (QC-LDPC exponential matrix) may be obtained. Given a lifting size Z, the exponential matrix P=E(H) may have a size of m / Z xn / Z. If n=24Z (e.g., n=3888, Z=162), then the size of P=E(H) is 24(1-R)x 24(=n(1-R) / Z xn / Z). The elements of the exponential matrix may be integer values ​​corresponding to the cyclic shift values ​​of the identity matrix of size Z×Z. The parity check matrix H may be a sparse binary matrix that can be derived from the exponential matrix P=E(H). The generator matrix G may have a size of n×k in binary form (e.g., the elements of the generator matrix G are binary values). The exponential matrix P=E(H) may have a structure including multiple sub-matrices (e.g., A, B, C, D, E, T).

[0041] In some embodiments, the binary QC-LDPC code LDPC(n,R) may be characterized by the null space of an n(1-R)×n parity check matrix H. The parity check matrix H may be a binary sparse matrix comprising a set of circulant matrices of size Z×Z. The parity check matrix H of the QC-LDPC code may be equivalently represented by an exponential matrix P=E(H). This representation may help illustrate the graphical structure of the underlying code as a base graph and shifted coefficients.

[0042] In some implementations, multiple codebooks may be provided to generate a parity check matrix. For example, multiple codebooks may include a codebook. A codebook refers to a set of codewords (or code vectors) or error correction codes (e.g., LDPC codes) used in error correction and / or data compression. A codeword refers to an encoded representation generated by applying an error correction code to original data.

[0043] 1-1-1 0 0-1-1-1 171 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1-1 171 131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 108-1-1-1 0 0-1-1-1 171 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1-1 171 131 88 18 109 113 146 69 84-1-1-1 71-1-1-1 92 79 0-1-1 0 0-1 7 124 15 161137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53 151 66 42 138 118 677-1-1-1 70-1 125 72 53-1-12-1-1-1-1 0]……(Codebook 1)

[0044] In some embodiments, a parity-check matrix H can be generated from an exponent matrix P = E(H) using a codebook. The exponent matrix P = E(H) can include (as elements) shift values d in the range 0 <= d < Z and d = -1. For example, if Z = 7, the shift values d can include -1, 0, 1, 2, 3, 4, 5, 6. The shift value d = 0 can correspond to (or map to) the identity matrix of size ZxZ represented by I(Z). The shift value d = -1 can correspond to (or map to) the zero matrix of size ZxZ represented by 0*I(Z) (all elements are zero). Any other integer value d in [1, Z - 1] can correspond to (or map to) a matrix that is cyclically right-shifted from I(Z). The parity-check matrix H can be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element (as the shift value d) of the exponent matrix P is replaced by a matrix corresponding to the shift value.

[0045] In some embodiments, the exponent matrix P = E(H) can include multiple elements P1,1, P1,2, P1,3, ……, P1,ń; P2,1, P2,2, P2,3, ……, P2,ń; ……, P1,1, P1,2, P1,3, ……, which correspond to the values of the codebook, where and ń satisfy the following equation:

[0046]

[0047] ń = n / Z... (Equation 6)

[0048] The exponent matrix (or permutation matrix) P = E(H) can be represented as follows:

[0049]

[0050] The corresponding parity-check matrix H can be obtained by replacing each element (as the shift value d) of the matrix with a matrix C(d) corresponding to the shift value, as follows:

[0051]

[0052] For example, the matrix C(1) can be represented as follows:

[0053]

[0054] In some embodiments, the encoder may use a generator matrix (e.g., using equation 2) to generate codewords. In some embodiments, the encoder may use a parity check matrix (rather than a generator matrix) to generate codewords from a vector of information bits. After obtaining the parity check matrix H (e.g., using a codebook), the parity check matrix H may have sub-matrices A, B, C, D, T, E. The upper region O of the sub-matrix T may correspond to a region where the matrix contains all zeros, and other regions may represent positions that may contain 1s.

[0055] In some embodiments, the codeword c may be obtained by the following expression:

[0056] c=[s p1 p2]……(Equation 10),

[0057] Where "s" is the vector of information bits to be encoded, "p1" is the vector of the first g parity bits, and "p2" is the vector of the remaining mg parity bits.

[0058] The vectors p1 and p2 can be obtained by the following equations:

[0059] Φ=-ET -1 B + D ... (Equation 11);

[0060] p1 T =-Φ -1 (-ET -1 A+C)s T ... (Equation 12); and

[0061] p2 T =-T -1 (As T +Bp1 T )……(Equation 13).

[0062] Although the various embodiments disclosed herein are described as being used to encode data for wireless communications (e.g., a wireless local area network (WLAN) compliant with any IEEE 802.11 standard), the principles disclosed herein are applicable to other types of communications (e.g., wired communications) or any process that performs encoding of LDPC codes.

[0063] In some implementations, an apparatus may include a transmitter and one or more processors.The one or more processors may be configured to generate a first binary parity check matrix for a QC-LDPC code using a first matrix having 144 values ​​according to a code rate of 3 / 4. The first matrix contains at least 142 values ​​selected from the following set of values: [96 59 56 78 18122 -1 -1 -1 126 90 161 -1 -1 -1 74 65 45 2 0 -1 -1 -1 -1 8 98 85 97 22 61 -1-1 -1 98 35 82 74 31 -1 108 -1 -1 -1 0 0 -1 -1 -1 71 153 156 102 74 70 42 -135 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18 131 88 18 109 113 146 6984 -1 -1 -1 71 -1 -1 1 0 0 53 151 66 42 138 118 6 77 -1 -1 -170 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0]. The one or more processors may be configured to encode the data using the generated first binary parity check matrix. The one or more processors may be configured to cause the transmitter to transmit the encoded data. In some embodiments, the first binary parity check matrix may be generated according to a size of 3888 bits. The one or more processors are further configured to shift one or two values ​​of the first matrix by -1 or +1 from one or more corresponding positive values ​​in a set of values. One or more corresponding positive values ​​in the set of values ​​may not be selected as the at least 142 values.

[0064] The embodiments of the present disclosure have at least the following advantages and benefits. First, the embodiments of the present disclosure may provide useful techniques for providing significant gain across all modulation schemes. For example, the block length (e.g., 3888 bits) of the QC-LDPC code according to some embodiments is at least twice the block length (e.g., 1994 bits) of the longest code supported in the 802.11n to 802.11be standards. This QC-LDPC code may provide a gain of about 2dB in a 2x2 MIMO (multiple input multiple output) channel, and the gain is consistent across all modulation schemes with or without beamforming.

[0065] Second, embodiments of the present disclosure may provide useful techniques for providing significant gains (e.g., 0.5 dB to 1.2 dB gain in SNR (signal-to-noise ratio) relative to existing codes) across all modulation schemes. For example, the block length (e.g., 3888 bits) of a QC-LDPC code according to some embodiments is at least twice the block length (e.g., 1994 bits) of the longest code supported in the 802.11n to 802.11be standards. This QC-LDPC code may provide a gain of approximately 2 dB in a 2x2 MIMO channel, and the gain is consistent across all modulation schemes with or without beamforming.

[0066] Third, the embodiments of the present disclosure may provide a codebook and a method for constructing a codebook. In some implementations, a QC-LDPC code may be constructed by slightly nudging the cyclic shift values ​​of a parity check matrix.

[0067] refer to Figure 1 , illustrated is a diagram depicting an example communication environment 100 including communication systems (or communication devices) 105, 108 according to one or more embodiments. In one embodiment, the communication system 105 includes baseband circuitry 110 and transmitter circuitry 120, and the communication system 108 includes baseband circuitry 150 and receiver circuitry 140. In one aspect, the communication system 105 is considered a transmitter communication system, and the communication system 108 is considered a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any combination thereof. In some implementations, the communication systems 105, 108 include more than one embodiment of the present invention. Figure 1 For example, each of the communication systems 105, 108 includes transceiver circuitry to allow two-way communication between the communication systems 105, 108 or with other communication systems. In some implementations, each of the communication systems 105, 108 may have a configuration similar to that shown in FIG. Figure 2 The configuration of the computing system 2000 shown in FIG.

[0068] The baseband circuit system 110 of the communication system 105 is a circuit system that generates baseband data 115 for transmission. The baseband data 115 includes information data (e.g., signal) at a baseband frequency for transmission. In one method, the baseband circuit system 110 includes an encoder 130 that encodes the data and generates or outputs parity bits. In one aspect, the baseband circuit system 110 (or encoder 130) obtains a generator matrix or a parity check matrix, or uses a previously generated generator matrix or a previously generated parity check matrix and encodes the information data by applying the information data to the generator matrix or the parity check matrix to obtain a codeword. In some embodiments, the baseband circuit system 110 stores one or more generator matrices or one or more parity check matrices that comply with any IEEE 802.11 standard for WLAN communication. The baseband circuit system 110 retrieves a stored generator matrix or a stored parity check matrix in response to detecting the information data to be transmitted, or in response to receiving an instruction to encode the information data. In one approach, baseband circuitry 110 generates parity bits based on a portion of a generator matrix or using a parity check matrix and appends the parity bits to the information bits to form a codeword. Baseband circuitry 110 generates baseband data 115 containing the codeword for communication system 108 and provides baseband data 115 to transmitter circuitry 120.

[0069] The transmitter circuit system 120 of the communication system 105 includes or corresponds to a circuit system that receives the baseband data 115 from the baseband circuit system 110 and transmits the wireless signal 125 according to the baseband data 115. In one configuration, the transmitter circuit system 120 is coupled between the baseband circuit system 110 and an antenna (not shown). In this configuration, the transmitter circuit system 120 up-converts the baseband data 115 from the baseband circuit system 110 into a carrier signal to generate the wireless signal 125 at an RF frequency (e.g., 10 MHz to 60 GHz), and transmits the wireless signal 125 through the antenna.

[0070] The receiver circuitry 140 of the communication system 108 is a circuitry that receives the wireless signal 125 from the communication system 105 and obtains baseband data 145 from the received wireless signal 125. In one configuration, the receiver circuitry 140 is coupled between the baseband circuitry 150 and an antenna (not shown). In this configuration, the receiver circuitry 140 receives the wireless signal 125 through the antenna and down-converts the wireless signal 125 at an RF frequency according to a carrier signal to obtain the baseband data 145 from the wireless signal 125. The receiver circuitry 140 then provides the baseband data 145 to the baseband circuitry 150.

[0071] The baseband circuitry 150 of the communication system 108 includes or corresponds to circuitry that receives the baseband data 145 from the receiver circuitry 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain the information data generated by the baseband circuitry 110 of the communication system 105.

[0072] In some implementations, each of baseband circuitry 110 (including encoder 130), transmitter circuitry 120, receiver circuitry 140, and baseband circuitry 150 (including decoder 160) may be one or more processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any combination thereof.

[0073] Figure 2 2000 includes one or more processors 2010 that communicate directly or indirectly with a memory 2060 via a communication system 2040 (e.g., a bus), at least one network interface controller 2030 having a network interface port for connecting to a network (not shown), and other components, such as input / output ("I / O") components 2050. Typically, the processor 2010 will execute instructions (or computer programs) received from the memory. The processor 2010 shown incorporates or is connected to a cache memory 2020. In some examples, instructions are read from the memory 2060 into the cache memory 2020 and executed by the processor 2010 from the cache memory 2020. The computing system 2000 may not necessarily contain Figure 2 All of these components shown in the Figure 2 Other components not shown.

[0074] In more detail, processor 2010 may be any logic circuit system that processes instructions, for example, instructions obtained from memory 2060 or cache 2020. In many embodiments, processor 2010 is a microprocessor unit or a special-purpose processor. Computing system 2000 may be based on any processor or processor set capable of operating as described herein. Processor 2010 may be a single-core or multi-core processor. Processor 2010 may be a plurality of different processors.

[0075] The memory 2060 may be any device suitable for storing computer-readable data. The memory 2060 may be a device with fixed storage or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), nonvolatile memory, media and memory devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic, magneto-optical disks, and optical disks (e.g., CD ROM, DVD-ROM, or The computing system 2000 may have any number of memory devices 2060 .

[0076] Cache memory 2020 is a form of computer memory that is typically placed near processor 2010 for fast read times. In some implementations, cache memory 2020 is part of processor 2010, or is on the same chip as processor 2010. In some implementations, there are multiple levels of cache 2020, for example, L2 and L3 cache layers.

[0077] The network interface controller 2030 manages data exchange via a network interface (sometimes referred to as a network interface port). The network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some embodiments, some of the tasks of the network interface controller are handled by one or more of the processors 2010. In some embodiments, the network interface controller 2030 is part of the processor 2010. In some embodiments, the computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, the computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point for a physical network link (e.g., a Category 5 Ethernet link). In some embodiments, the network interface controller 2030 supports wireless network connections, and the interface port is a wireless (e.g., radio) receiver or transmitter (e.g., for any of IEEE 802.11 protocols, near field communication "NFC", Bluetooth, ANT, or any other wireless protocol). In some embodiments, the network interface controller 2030 implements one or more network protocols, such as Ethernet. Typically, the computing system 2000 exchanges data with other computing devices via a physical or wireless link through a network interface. The network interface may be linked directly to another device or linked to another device via an intermediate device that connects the computing system 2000 to a data network such as the Internet, such as a network device (e.g., such as a hub, bridge, switch, or router).

[0078] The computing system 2000 may include, or provide an interface for, one or more input or output ("I / O") devices. Input devices include, but are not limited to, keyboards, microphones, touch screens, foot pedals, sensors, MIDI devices, and pointing devices such as a mouse or trackball. Output devices include, but are not limited to, video displays, speakers, refreshable Braille terminals, lights, MIDI devices, and 2-D or 3-D printers.

[0079] Other components may include I / O interfaces, external serial device ports, and any additional coprocessors. For example, the computing system 2000 may include an interface (e.g., a universal serial bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., a portable flash drive or an external media drive). In some implementations, the computing system 2000 includes additional devices, such as coprocessors, for example, math coprocessors that can assist the processor 2010 in performing high-precision or complex calculations.

[0080] Component 2050 may be configured to connect to external media, display 2070, input device 2080, or any other component or combination thereof in computing system 2000. Display 2070 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a flat panel display, a solid state display, a cathode ray tube (CRT) display, a projector, a printer, or other now known or later developed display device for outputting determined information. Display 2070 may serve as an interface for a user to view the operation of processor 2010, or in particular, as an interface to interface with software stored in memory 2060.

[0081] The input device 2080 may be configured to allow a user to interact with any of the components of the computing system 2000. The input device 2080 may be a plurality of pads, a keyboard, a cursor control device (such as a mouse), or a joystick. In addition, the input device 2080 may be a remote control, a touch screen display (which may be a combination of the display 2070 and the input device 2080), or any other device operable to interact with the computing system 2000, such as any device operable to act as an interface between a user and the computing system 2000.

[0082] Figure 3 300 . The exponential matrix 300 of the example (QC-LDPC exponential matrix) is depicted in accordance with one or more embodiments. Given a lifting size Z, the exponential matrix 300 may have a size of m / Z xn / Z. If n=24Z (e.g., n=3888, Z=162), then the size of P=E(H) is 24(1-R) ​​x 24(=n(1-R) / Z xn / Z). The elements of the exponential matrix may be integer values ​​corresponding to cyclic shift values ​​of the identity matrix of size Z x Z. The parity check matrix H (see Figure 5 ) can be a sparse binary matrix derivable from the exponent matrix P = E(H). The generator matrix G can have a size n x k in binary form (e.g., the elements of the generator matrix G are binary values). Refer to Figure 3 , the exponent matrix P = E(H) can have a structure that includes multiple sub-matrices (e.g., A310, B 312, C 316, D 318, E 320, T 314).

[0083] Figure 4 FIG. 400 depicts example shifted identity matrices 409, 410, 411, 412, 413, 414, 415, 416 for generating a parity-check matrix according to one or more embodiments. A parity-check matrix H can be generated from the exponent matrix P = E(H) (e.g., exponent matrix 300) using a codebook (e.g., codebook 1). As shown in Equation 7, the exponent matrix P = E(H) can include (as elements) shift values d in the range 0 <= d < Z and d = -1. Referring to the equation, for example, if Z = 7, then the shift values d can include -1, 0, 1, 2, 3, 4, 5, 6 (see Figure 4 ). The shift value d = 0 can correspond to (or map to) the identity matrix of size Z x Z represented by I(Z) (e.g., matrix 410). The shift value d = -1 can correspond to (or map to) the zero matrix of size Z x Z represented by 0*I(Z) (all elements are zero) (e.g., matrix 409). Any other integer value d in [1, Z - 1] can correspond to (or map to) a matrix that is circularly right-shifted from I(Z) (e.g., matrices 411, 412, 413, 414, 415, 416). As shown in Equation 8, the parity-check matrix H can be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element (as the shift value d) of the exponent matrix P is replaced by the matrix corresponding to the shift value.

[0084] Figure 5 FIG. is a diagram depicting an example parity-check matrix 500 according to one or more embodiments. In some embodiments, an encoder (e.g., encoder 130) can generate a codeword using a generator matrix (e.g., using Equation 2). In some embodiments, an encoder (e.g., encoder 130) can use a parity-check matrix (instead of a generator matrix) to generate a codeword from a vector of information bits. After obtaining the parity-check matrix H (e.g., using a codebook), the parity-check matrix H (e.g., parity-check matrix 500) can have sub-matrices A 510, B 512, C 516, D 518, T 514, E 520. The upper region O 515 of the sub-matrix T 514 (e.g., Figure 5 the white region in ) can correspond to the region where the matrix contains all zeros, and the other regions (e.g., Figure 5The gray areas in ) may represent positions that may contain 1. The size of the parity check matrix 500 may be mxn, where the size of the submatrix D 518 is gxg, and the size of the submatrix T is (mg)x(mg). In some implementations, given a vector s of information bits to be encoded, the encoder may obtain a codeword c using Equations 10, 11, 12, and 13.

[0085] In some implementations, a codebook for an R=3 / 4 LDPC code with a block length=3888 bits may provide high performance error correction and / or provide up to 1.2 dB gain relative to existing LDPC codes specified in Wi-Fi standards. In some implementations, a set of LDPC codes with a block length of 3888 bits (2x1944) supports all code rates in Wi-Fi standards (e.g., 802.11be). Codes (e.g., R=3 / 4 LDPC codes with a block length=3888 bits) may be used directly in existing modulations of 64-QAM in IEEE 802.11be, and potentially in combination with more combinations of QAM sizes in IEEE 802.bn.

[0086] The set of LDPC codes with a block length of 3888 bits (2x1944) can provide considerable performance improvements in various communication scenarios with ultra-high reliability (UHR), while maintaining manageable complexity.Performance comparison is performed between these codes and the LDPC codes specified in the IEEE 802.11be standard and the recently proposed code with a block length of 4x1944.The result of the performance comparison shows a comprehensive verifiable gain (e.g., channel, PHY bandwidth, MIMO, modulation and coding scheme (MCS), transmit beamforming).For example, according to some embodiments, the LDPC code with a block length of 3888 bits can provide a gain of 0.5 to 1.0 dB relative to current 802.11 LDPC codes depending on channel conditions.The LDPC code with a block length of 4x1944 bits can provide an additional 0.0 to 0.5 dB gain depending on channel conditions.

[0087] The longest LDPC code specified in the 802.11be standard has a block length = 1944 bits. In terms of performance, the LDPC codes specified in the 802.11be standard are about 2.7 dB away from the optimal random code (e.g., bit interleaved coded modulation (BICM)-additive white Gaussian noise (AWGN)-QAM (quadrature amplitude modulation) R = 3 / 4 limit). According to the finite length scaling law, longer block length random codes (e.g., the asymptotic case when the Shannon limit handles the block length becoming infinite) can lead to enhanced coding gain. Suboptimal deterministic codes can exhibit a scaling gain that is significantly greater than the scaling gain of the optimal random code. For example, in AWGN, it is known that the multiplication effect is true.

[0088] In some embodiments, the LDPC code has a block length = 2x1944 = 3888 bits (which is twice the size of the maximum supported block length in the current 802.11be standard). In some embodiments, the LDPC code with block length = 3888 bits can support all existing code rates (e.g., R = 1 / 2, 2 / 3, 3 / 4, and 5 / 6). In some embodiments, the LDPC code with block length = 3888 bits can keep the structure of the 802.11be code (specifically, QC-LDPC) unchanged, except for the matrix size expansion. This adaptation can promote the reuse of existing implementations and grant concurrent encoding and decoding capabilities.

[0089] Fig. 6A and 6B is a diagram depicting an example code design using a prototype enhancement concept / method in accordance with one or more embodiments.

[0090] Fig. 6A 600 is a diagram depicting the design / generation / creation / definition of an example code design using the protograph lifting concept / method according to one or more embodiments. A "protograph" may refer to a bipartite graph having two disjoint and independent vertex sets (e.g., the left vertex set indicated by circles and the right vertex set indicated by rectangles in the protograph 611) to represent a matrix (e.g., a parity check matrix 611). A system according to some implementations (e.g., a communication system 105 or 108) may use a code with a block length = 1944 as a base code (e.g., the protograph 611 and the corresponding (parity check) matrix 612). The system may lift (e.g., replicate) the base code by 2 (e.g., the protograph 621 and the (parity check) matrix 622 corresponding to the protograph 621). The system may (1) permute / move / shift / migrate the edges of the protograph (e.g., from protograph 621 to protograph 631; equivalently permute the columns of matrix 622 to obtain matrix 632); and / or (2) remove 4 cycles (and possibly all short cycles) from the protograph (e.g., protograph 631 and the (parity-check) matrix 632 corresponding to protograph 631) to obtain protograph 641. For example, Fig. 6A As shown in , the loop represented by submatrix 633 in the original model 631 can be removed in the original model 641 corresponding to the matrix 642 (see submatrix 643). Similarly, the loop represented by submatrix 634 in the original model 631 can be removed in the original model 641 corresponding to the matrix 642 (see submatrix 644).

[0091] In some embodiments, the system may generate / define / design / create (as a design goal) a code that represents a protograph with a perimeter > 6. The "perimeter" of an undirected graph may refer to the length of the shortest cycle contained in the graph. In some embodiments, the system may generate / define / design / create (as a design goal) a code that corresponds to a protograph with a perimeter > 10. For example, Fig. 6A , the original model map 631 (and the corresponding (parity check) matrix 632) has a perimeter of 4, while the original model maps 641, 651 (and their corresponding (parity check) matrix 642) each have a perimeter greater than 6. In some implementations, the system can add and / or delete edges to improve performance without increasing the perimeter. For example, edges can be added to and / or deleted from the parity check matrix 642 to improve performance without increasing the perimeter of the original model maps 641, 651 (or the perimeter of their corresponding (parity check) matrix 642).

[0092] Figure 6B 6 is a diagram 650 depicting an example parity check matrix for a QC-LDPC code according to one or more embodiments. In some implementations, a system according to some implementations (e.g., communication system 105 or 108) can obtain a parity check matrix 642 (see FIG. 6 ) for a new code that is identical to parity check matrix 762 by embedding a 2x2 binary matrix in the original parity check matrix H (e.g., parity check matrix 612 as a base code). For example, the system can (1) replace the 2x2 binary identity matrix with the 2x2 binary identity matrix Replace the element "1" in the original parity check matrix 612; and / or (2) further modify the replaced identity matrix. For example, after embedding the 2x2 binary identity matrix, the system can modify some of the embedded 2x2 binary identity matrices to produce modified binary matrices 651, 652, which correspond to the modified edges in the corresponding original model.

[0093] In some implementations, a system (e.g., communication system 103, 108) may include one or more processors (e.g., one or more processors 2010) configured to select a codebook for a QC-LDPC code from a plurality of codebooks according to a first size (e.g., 1944 bits) and a code rate of 3 / 4. The first size may be the size of a code block as a result of encoding an information block, and the code rate may be a ratio of the size of the information block to the first size. The one or more processors may be configured to generate a first parity check matrix (e.g., Fig. 6A For example, the first parity check matrix may correspond to a block length of 1944 bits and a code rate of 3 / 4. One or more processors may use two instances of the first parity check matrix (e.g., Fig. 6A) to generate a second parity check matrix corresponding to a second size and code rate (eg, Fig. 6A The second size may be twice the first size. For example, the second parity check matrix may correspond to a block length of 3888 bits and a code rate of 3 / 4.

[0094] In some embodiments, the system may generate a second parity check matrix using a first protograph (e.g., protograph 611) corresponding to a first parity check matrix. The system may (1) promote (e.g., copy) the first protograph by 2 (e.g., promote protograph 611 by 2 to create protograph 631); and / or (2) permute / move / shift / migrate the edges of the promoted protograph (e.g., protograph 631) to remove one or more short cycles from the promoted protograph, thereby obtaining a second protograph (e.g., protograph 651) such that the perimeter of the second protograph is greater than 6 (or greater than 10). In some embodiments, the system may further add one or more edges to the second protograph without increasing the perimeter of the protograph, or delete one or more edges from the second protograph. The second protograph (or the protograph as a result of further addition / removal of edges) may correspond to a second parity check matrix (e.g., parity check matrix 642).

[0095] In some embodiments, the system can generate a second parity check matrix by embedding a 2x2 binary matrix in the first parity check matrix. Figure 6B As shown in , the system can replace each element of the first parity check matrix having the value "1" with a 2x2 binary matrix (e.g., a 2x2 binary identity matrix), and / or further modify the replaced binary matrix (e.g., modified binary matrices 651, 652) to obtain a second parity check matrix (e.g., parity check matrix 642).

[0096] Fig. 7A , 7B , 7C, and 7D are diagrams depicting example codes for concurrent decoding according to one or more embodiments. Fig. 7A 700 is a diagram depicting an example sub-matrix structure according to one or more embodiments. There may be four different diagram representations (or prototype diagrams) 701, 702, 703, 704 and corresponding sub-matrix structures 711, 712, 713, 714, respectively. In the sub-matrix structure, the (i, j) element (entry) of the sub-matrix indicates the number of columns in the jth column (e.g., Fig. 7A The vertex v1 or v'1 in the i-th row (e.g., Fig. 7AFor example, submatrix structure 712 indicates (1) there is no edge between v1 and c1; (2) there is no edge between v'1 and c'1; (2) there is an edge between v1 and c'1; and (2) there is an edge between v'1 and c1.

[0097] Figure 7B , 7C 7D are diagrams 720, 740, 760 depicting example codes for concurrent decoding according to one or more embodiments. LDPC codes according to some implementations allow for concurrent decoding using two decoders that each process blocks of 1944 bits simultaneously. Figure 7B A prototype graph 720 is shown indicating edges between a first set of vertices (e.g., {v1, v'1, v2, v'2, v3, v'3, v4, v'4}) and a second set of vertices (e.g., {c1, c'1, c2, c'2, c3, c'3}). Figure 7C A matrix 740 (e.g., a parity check matrix) corresponding to the original model image 720 is shown. A system (e.g., the communication system 108) according to some embodiments may use Fig. 7A The mapping between the original model image and the corresponding sub-matrix structure shown in is obtained from the original model image 720 .

[0098] refer to Fig.7D , Figure 760 shows an example of concurrent decoding by decoder 1 (761) and decoder 2 (762), such that the two decoders can execute two 1944 block runs (as two layers) concurrently. In some implementations, the two decoders can be implemented in a decoder of a communication system (e.g., decoder 160 of communication system 108). For example, a first block run can correspond to a first subgraph 770 of the original model graph 720, which indicates edges between the vertex set {v1, v2, v3, v4} and the vertex set {c1, c2, c3}. A second block run can correspond to a second subgraph 780 of the original model graph 720, which indicates edges between the vertex set {v'1, v'2, v'3, v'4} and the vertex set {c'1, c'2, c'3}. In some implementations, the two decoders 761, 762 can execute cross-layer messages that pass through the connecting edges between the two subgraphs of the original model graph 720 (e.g., the connecting edges in portion 763, the connecting edges in portion 764). The connecting edges in portions 763 and 764 correspond to 2x2 circulant matrices 741 and 742 of matrix 740, respectively (see Figure 7C)。Here, a circulant matrix may refer to a square matrix where all rows consist of the same elements, and each row is rotated one element to the right relative to the previous row. Due to (or using) the sub-matrix structure (e.g., 2x2 circulant matrices 741 and 742), the system can perform such concurrent decoding. In some embodiments, the 2x2 embedding can be changed for performance without affecting concurrent decoding because it is a fixed edge mapping between two decoding layers.

[0099] Figure 8 is a flowchart showing process 800 for encoding data using an LDPC code according to an embodiment. In some embodiments, process 800 is performed by one or more processors (e.g., communication system 105, encoder 130, or processor 2010). In other embodiments, process 800 is performed by other entities. In some embodiments, process 800 includes more, fewer, or different steps than Figure 8 shown therein.

[0100] At step 802, one or more processors may determine a QC-LDPC code in which multiple codebooks (e.g., codebook 1) are embedded. In some embodiments, each codebook of the multiple codebooks may include multiple integers (e.g., P1,1, P1,2, P1,3, ……, P1,ń; P2,1, P2,2, P2,3, ……, P2,ń; ……, P1,1, P1,2, P1,3, ……, as shown in Equation 7), the number of the multiple integers being equal to the number of elements of the parity-check matrix divided by z, where z is an integer representing the lifting size of the QC-LDPC code (e.g., Z = 162). See Equation 5 and Equation 6.

[0101] In some embodiments, each codebook of the multiple codebooks (e.g., codebook 1) may represent an exponent matrix (e.g., matrix 300) of a parity-check matrix (e.g., matrix 500). Each element of the exponent matrix may correspond to a cyclic shift value of an identity matrix. The size of the identity matrix may be z x z, and the cyclic shift value d may be an integer such that -1 ≤ d < z, where Z is an integer representing the lifting size of the QC-LDPC code. The cyclic shift value d may represent a shifted identity matrix obtained by shifting the identity matrix to the right by d (when z = 7, see Figure 4 ). The cyclic shift value -1 may represent the zero matrix of the identity matrix (see matrix 409 in Figure 4 ).

[0102] In some implementations, the code block size may be 3888 bits and the code rate may be 3 / 4. The plurality of codebooks may include a codebook (codebook 1) comprising [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-18 9885 97 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 7470 42-1 35128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-118-1 145-1-1-1-1-10 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0].

[0103] At step 804, one or more processors may select a codebook from a plurality of codebooks according to a code block size (eg, n=3888) and a code rate (eg, R=3 / 4).

[0104] At step 806, one or more processors may generate a parity check matrix (e.g., parity check matrix 500) based on a codebook (e.g., codebook 1). In some embodiments, when generating a parity check matrix based on a selected codebook, one or more processors may generate an exponential matrix (e.g., matrix 300) based on the selected codebook. For each element of the exponential matrix, one or more processors may generate a shifted identity matrix (e.g., matrix 410, 411, 412, 413, 414, 415, 416) of the identity matrix based on the value of each element of the exponential matrix (e.g., d=0, 1, 2, 3, 4, 5, 6). One or more processors may generate a parity check matrix such that the parity check matrix includes the generated shifted identity matrix as an element corresponding to each element of the exponential matrix (see equation 8).

[0105] At step 808, the one or more processors may encode the data using the generated parity check matrix (eg, using Equation 10, Equation 11, Equation 12, and Equation 13).

[0106] At step 810 , the one or more processors may transmit the encoded data to another device (eg, communication system 108 ) via a transmitter of the device (eg, transmitter circuitry 120 of communication system 105 ).

[0107] In one approach, an apparatus may include a transmitter (e.g., transmitter circuitry 120 of communication system 105) and one or more processors (e.g., encoder 130 or processor 2010 of communication system 105). The one or more processors may be configured to identify (e.g., identify / select from a codebook) a first binary parity check matrix (e.g., parity check matrix H) for a QC-LDPC code based on a code rate of 3 / 4 and a code block size of 3888 bits. The first binary parity check matrix may correspond to a first index matrix having 144 values ​​(e.g., index matrix P=E(H)). The one or more processors may be configured to encode data using the first binary parity check matrix (e.g., using equations 10, 11, 12, and 13). The one or more processors may be configured to transmit encoded data. For example, a first device (e.g., communication system 105) may transmit encoded data to a second device (e.g., communication system 108).

[0108] In some implementations, the one or more processors may be further configured to generate the first index matrix by selecting at least 142 values ​​from a second index matrix having the same dimensions as the first index matrix (e.g., 6x24; 6 rows and 24 columns). In some embodiments, the first index matrix may be generated by the one or more processors of the first device (e.g., encoder 130 of communication system 105). In some embodiments, the first index matrix may be generated by another device (e.g., a device other than communication system 105) and transmitted to the first device.

[0109] The one or more processors may be further configured to shift (or perturb) one or two values ​​of the first index matrix by -1 or +1 from one or more corresponding positive values ​​of the second index matrix. The one or more corresponding positive values ​​of the second index matrix may not be selected to be at least 94 values. In some embodiments, the second exponential matrix may include the following set of values: [96 59 56 7818122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 97 22 61-1-1-1 98 358274 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1 92 79 0-1-10 0-1 7 12415 161 137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53 15166 42 138 118 677-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0]. The first exponential matrix (e.g., permutation matrix P) may be generated by perturbing one or two values ​​from the second exponential matrix. For example, based on the second exponential matrix, the first matrix may be generated as [95 59 55 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 9722 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113146 69 84-1-1-1 71-1-1-1 9279 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0], wherein the first value 95 and the third value 55 are shifted from 96 and 56 respectively.

[0110] In some implementations, a first binary parity check matrix (e.g., H matrix) may be generated using a first exponential matrix (e.g., P). For example, the first binary parity check matrix (e.g., H matrix) may be generated by extending the exponential matrix P so that each element (as a shift value d) of the exponential matrix P is replaced by a matrix (e.g., Z x Z matrix; Z = 162) of shift values ​​shifted from an identity matrix (e.g., a Z x Z identity matrix; Z = 162).

[0111] In some embodiments, the one or more processors may be further configured to identify a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted. The second binary parity check matrix may have the same dimension as the first binary parity check matrix. For example, the second binary parity check matrix may be generated by permuting the first column and the second column of the first binary parity check matrix. The second binary parity check matrix may have the same dimension as the first binary parity check matrix (e.g., mxn; n=3888; m=n(1-3 / 4)=972). In some embodiments, the one or more processors may be further configured to encode data using the second binary parity check matrix.

[0112] In some embodiments, the one or more processors may be further configured to identify a third binary parity check matrix corresponding to the second exponential matrix in which one or more columns of the first exponential matrix are permuted. The second exponential matrix may have the same dimensions as the first exponential matrix (e.g., 6x24; 6 rows and 24 columns). For example, the second exponential matrix may be generated by permuting the first column and the second column of the first exponential matrix. The one or more processors may be configured to encode the data using the third binary parity check matrix.

[0113] In some embodiments, the one or more processors may be further configured to generate the first binary parity check matrix (e.g., H matrix) using (1) a matrix product of the first binary parity check matrix and the first index matrix (e.g., H x P), or (2) a matrix product of the first index matrix and the first binary parity check matrix (e.g., P x H). For example, the H matrix may be generated by multiplying the matrix product H x P (right) by the inverse matrix of the first index matrix (e.g., P x H). -1 ) to generate.

[0114] In one approach, an apparatus (e.g., communication system 108) may include a receiver (e.g., receiver circuitry 140) configured to receive encoded data and one or more processors (e.g., processor 2010). The one or more processors may be configured to identify (e.g., identify / select from a codebook) a first binary parity check matrix (e.g., parity check matrix H) for a QC-LDPC code based on a code rate of 3 / 4 and a code block size of 3888 bits. The first binary parity check matrix may correspond to a first index matrix having 144 values ​​(e.g., index matrix P=E(H)). In some implementations, before receiving the encoded data, the second device may identify the first binary parity check matrix. In some implementations, in response to receiving the encoded data or after receiving the encoded data, the one or more processors of the second device may identify (e.g., identify / select from a codebook) the first binary parity check matrix. The one or more processors may be configured to decode the received encoded data using the first binary parity check matrix. For example, the encoded data (eg, codeword c) may be decoded by using Equation 1 and Equations 10-13 to obtain information bits s.

[0115] In some embodiments, the first exponential matrix may include the following set of values: [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 97 22 61-1-1-1 98 35 82 7431-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18131 88 18 109 113 146 69 84-1-1-1 71-1-1 92 79 0-1-1 0 0-17 124 15 161 137 53-1161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53 151 66 42138 118 6 77-1-1-1 70-1125 72 53-1-1 2-1-1-1-1 0].

[0116] In some implementations, the first index matrix may include at least 94 values ​​selected from a second index matrix having the same dimensions as the first index matrix (e.g., 6x24; 6 rows and 24 columns). The first index matrix may include one or two values ​​shifted (or perturbed) by -1 or +1 from one or more corresponding positive values ​​of the second index matrix. The one or more corresponding positive values ​​of the second index matrix may not be selected as the at least 94 values. In some embodiments, the second exponential matrix may include the following set of values: [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-18 98 8597 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-135 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1145-1-1-1

[0117] -1-1 0 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-10]. The first exponential matrix (eg, permutation matrix P) may include one or two values ​​perturbed from the second exponential matrix. For example, the first matrix may contain the following set of values: [95 59 55 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 20-1-1-1-18 98 85 97 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109113 146 69 84-1-1-1 71-1-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1

[0118] -1-1 0 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-10], wherein the first value 95 and the third value 55 are shifted from 96 and 56 respectively.

[0119] In some embodiments, one or more processors may be configured to identify a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted. The second binary parity check matrix may have the same dimension as the dimension of the first binary parity check matrix. For example, the second binary parity check matrix may correspond to a matrix in which the first column and the second column of the first binary parity check matrix are permuted. The second binary parity check matrix may have the same dimension as the dimension of the first binary parity check matrix (e.g., mxn; n=3888; m=n(1-3 / 4)=92). In some embodiments, one or more processors may be configured to decode the received encoded data using the second binary parity check matrix (e.g., using equations 1 and equations 10 to 13).

[0120] In some scenarios, the parity check matrix H may be created / calculated / computed / generated / obtained through a hierarchical lifting process. The hierarchical lifting process may involve generating smaller matrices by applying cyclic shifts of different sizes (e.g., Z / 2, Z / 4, etc.). These smaller matrices may then be selectively grouped together to form an equivalent matrix H.

[0121] Fig. 9 900 is a flow chart showing a process 900 for encoding data and / or decoding data using an LDPC code according to an embodiment. In some implementations, the process 900 is performed by one or more processors (e.g., encoder 130 or processor 2010) of a first device (e.g., communication system 105), or by one or more processors (e.g., decoder 160 or processor 2010) of a second device (e.g., communication system 108). In other embodiments, the process 900 is performed by other entities. In some implementations, the process 900 includes more than one embodiment. Fig. 9 More, fewer, or different steps may be shown in .

[0122] At step 902, one or more processors of the first device may identify (e.g., identify / select from a codebook) a first binary parity check matrix (e.g., parity check matrix H) for a quasi-cyclic low-density parity check (QC-LDPC) code based on a code rate of 3 / 4 and a code block size of 3888 bits. The first binary parity check matrix may correspond to a first exponential matrix (e.g., exponential matrix P=E(H)) having 144 values.

[0123] In some implementations, the first index matrix may be generated by selecting at least 94 values ​​from a second index matrix having the same dimensions as the first index matrix (e.g., 6x24; 6 rows and 24 columns). In some embodiments, the first index matrix may be generated by one or more processors of the first device (e.g., encoder 130 of communication system 105). In some embodiments, the first index matrix may be generated by another device (e.g., a device other than communication system 105) and transmitted to the first device.

[0124] In some embodiments, one or two values ​​of the first index matrix may be shifted (or perturbed) by -1 or +1 from one or more corresponding positive values ​​of the second index matrix. The one or more corresponding positive values ​​of the second index matrix may not be selected to be at least 142 values. In some embodiments, the second exponential matrix may include the following set of values: [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 85 97 22 61-1-1-1 98 35 82 7431-1108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-1 35 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1 92 79 0-1-1 0 0-1 7124 15 161137 53-1 161 110-1 72-1 53-1 18-1 145-1-1-1-1-1 0 0 53 151 66 42138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0]. The first exponential matrix (e.g., permutation matrix P) may be generated by perturbing one or two values ​​from the second exponential matrix. For example, based on the second exponential matrix, the first matrix may be generated as [95 59 55 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 898 85 97 22 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 7470 42-1 35 128-1-1-1118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-1 71-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-118-1 145-1-1-1-1-1 0 0 53 151 6642 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0], wherein the first value 95 and the third value 55 are shifted from 96 and 56 respectively.

[0125] In some implementations, a first binary parity check matrix (e.g., H matrix) may be generated using a first exponential matrix (e.g., P). For example, the first binary parity check matrix (e.g., H matrix) may be generated by extending the exponential matrix P so that each element (as a shift value d) of the exponential matrix P is replaced by a matrix (e.g., Z x Z matrix; Z = 162) of shift values ​​shifted from an identity matrix (e.g., Z x Z identity matrix; Z = 162).

[0126] In some implementations, the first binary parity check matrix (e.g., H matrix) may be generated using (1) a matrix product of the first binary parity check matrix and a first index matrix (e.g., H x P), or (2) a matrix product of the first index matrix and the first binary parity check matrix. In some embodiments, the first binary parity check matrix may be generated by one or more processors of the first device (e.g., P x H). For example, the H matrix may be generated by multiplying the matrix product H x P (right) by the inverse matrix of the first index matrix (e.g., P -1 ) to generate.

[0127] At step 904, one or more processors of the first device may encode the data using the first binary parity check matrix (e.g., using Equation 10, Equation 11, Equation 12, and Equation 13). In some embodiments, a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted may be identified. For example, the second binary parity check matrix may be generated by permuting the first column and the second column of the first binary parity check matrix. The second binary parity check matrix may have the same dimensions as the first binary parity check matrix (e.g., mxn; n=3888; m=n(1-3 / 4)=912). In some embodiments, one or more processors of the first device may encode the data using the second binary parity check matrix.

[0128] In some embodiments, a third binary parity check matrix may be identified that corresponds to the second exponential matrix in which one or more columns of the first exponential matrix are permuted. The second exponential matrix may have the same dimensions as the first exponential matrix (e.g., 6x24; 6 rows and 24 columns). For example, the second exponential matrix may be generated by permuting the first column and the second column of the first exponential matrix. In some embodiments, the one or more processors of the first device may encode the data using the third binary parity check matrix.

[0129] At step 906, the one or more processors of the first device may transmit the encoded data.For example, the first device (eg, communication system 105) may transmit the encoded data to the second device (eg, communication system 108).

[0130] At step 908, the one or more processors of the second device (e.g., the decoder 160 of the communication system 108) may identify a first binary parity check matrix. For example, the one or more processors of the second device may identify (e.g., identify / select from a codebook) a first binary parity check matrix (e.g., parity check matrix H) for the QC-LDPC code based on a code rate of 3 / 4 and a code block size of 3888 bits. The first binary parity check matrix may correspond to a first index matrix having 144 values ​​(e.g., index matrix P=E(H)).

[0131] At step 910, the one or more processors of the second device may receive the encoded data from the first device. In some implementations, prior to receiving the encoded data in step 910, the one or more processors of the second device may identify the first binary parity check matrix in step 908. In some implementations, in response to receiving the encoded data or after receiving the encoded data, the one or more processors of the second device may identify (e.g., identify / select from a codebook) the first binary parity check matrix.

[0132] In some implementations, the first index matrix may include at least 142 values ​​selected from a second index matrix having the same dimensions as the first index matrix (e.g., 6x24; 6 rows and 24 columns). The first index matrix may include one or two values ​​shifted (or perturbed) by -1 or +1 from one or more corresponding positive values ​​of the second index matrix. The one or more corresponding positive values ​​of the second index matrix may not be selected as the at least 142 values. 1 -1 -1 0 0 -1 -1 -1 71 153 156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18 131 88 18 109 113 146 69 84 -1 -1 -1 71 -1 -1 -1 71 153 156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18 131 88 18 109 113 146 69 84 -1 -1 -1 71 92 79 0 -1 -1 0 0-1 7 124 15161 137 53 -1 161 110 -1 72 -1 53 -1 18 -1 145 -1 -1 -1 -1 -1 0 0 53 151 6642 138 118 6 77 -1 -1 -1 70 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0]. The first exponential matrix (e.g., permutation matrix P) may include one or two values ​​perturbed from the second exponential matrix.1 71 153 156 102 74 70 42 -1 35 128 -1 -1 -1 118 14 -1 -1 65 -1 -1 0 0 -1 -1 18 131 88 18 109 113 146 69 84 -1 -1 -1 71 -1 -1 -1 92 79 0 -1 -1 0 0-1 7 124 15161 137 53 -1 161 110 -1 72 -1 53 -1 18 -1 145 -1 -1 -1 -1 -1 0 0 53 151 6642 138 118 6 77 -1 -1 -1 70 -1 125 72 53 -1 -1 2 -1 -1 -1 -1 0], wherein the first value 95 and the third value 55 are shifted from 96 and 56 respectively.

[0133] At step 912, one or more processors of the second device may decode the encoded data using the first binary parity check matrix. For example, the encoded data (eg, codeword c) may be decoded to obtain information bits s by using Equations 1 and 10-13.

[0134] In some embodiments, one or more processors may be configured to identify a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted. The second binary parity check matrix may have the same dimension as the dimension of the first binary parity check matrix. For example, the second binary parity check matrix may correspond to a matrix in which the first column and the second column of the first binary parity check matrix are permuted. The second binary parity check matrix may have the same dimension as the dimension of the first binary parity check matrix (e.g., mxn; n=3888; m=n(1-3 / 4)=912). In some embodiments, one or more processors may be configured to use the second binary parity check matrix (e.g., using equations 1 and equations 10 to 13) to decode the received encoded data.

[0135] Fig. 10A , 10B, 10C, 10D, 10E and 10F are diagrams depicting example simulation results using QC-LDPC codes according to a code rate of 3 / 4 according to one or more embodiments. The results were obtained using the following simulation setup. Packet error rate (PER) values ​​were averaged over 5000 to 10000 independent channel realizations, with a gain reference of PER=1%. One channel example spans 4 orthogonal frequency division multiplexing (OFDM) symbols. The channel model includes (1) "DNLOS" indicating 802.11 MIMO channel model type D for non-line of sight; (2) "BLOS" indicating 802.11 channel model type B for line of sight; and (3) AWGN indicating a flat channel with additive white Gaussian noise. No radio frequency (RF) impairments are included. The payload size remains the same; and thus for block length=1944q, the number of codewords can be inversely proportional to q. Decoding is performed using a Belief Propagation (BP) based decoder (eg, using hierarchical scheduling with a maximum of 20 iterations). The MIMO-2x2 channel uses a near-optimal maximum likelihood detector with reduced complexity. The SISO (Single Input Single Output) 1x1 channel uses a linear detector.

[0136] Fig. 10A , 10C ,10E is a graph showing PER at different SNRs; Fig. 10B , 10D , 10F are the spectral efficiencies (SpecEff) for different SNRs. PER refers to the number of error packets divided by the total number of packets received. SpecEff refers to the information rate (or bit rate or effective data rate) over a given bandwidth in a communication system (in bits / second / Hz). SpecEff can be a normalized transmission rate, such that the actual transmission rate (bits / second) = SpecEff x bandwidth (Hz).

[0137] Fig. 10A and 10B Shows simulation results for a frequency-flat channel with AWGN. Fig. 10A , lines 1001, 1003, 1005, 1007, 1009, 1011 correspond to simulation results (PER versus SNR) of using an LDPC code with a block length of 3888 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, respectively; and lines 1002, 1004, 1006, 1008, 1010, 1012 correspond to simulation results of using an LDPC code with a block length of 1944 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, respectively. Reference Fig. 10B, lines 1021, 1023, 1025, 1027, 1029, and 1031 correspond to the simulation results (SpecEff versus SNR) of an LDPC code with a block length of 3888 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1022, 1024, 1026, 1028, 1030, and 1032 correspond to the simulation results of an LDPC code with a block length of 1944 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively.

[0138] Fig. 10C and 10D Shows simulation results for a 2x2 MIMO channel using D-NLOS signal propagation. Fig. 10C , lines 1041, 1043, 1045, 1047, 1049, 1051 correspond to simulation results (PER versus SNR) of using an LDPC code with a block length of 3888 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, respectively; and lines 1042, 1044, 1046, 1048, 1050, 1052 correspond to simulation results of using an LDPC code with a block length of 1944 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, respectively. Reference Fig. 10D , lines 1061, 1063, 1065, 1067, 1069, and 1071 correspond to the simulation results (SpecEff versus SNR) of an LDPC code with a block length of 3888 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1062, 1064, 1066, 1068, 1070, and 1072 correspond to the simulation results of an LDPC code with a block length of 1944 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively.

[0139] Fig. 10E and 10F Shows simulation results for a 2x2 MIMO channel using BLOS signal propagation. Fig. 10E, lines 1081, 1083, 1085, 1087, 1089, 1091 correspond to simulation results (PER versus SNR) of using an LDPC code with a block length of 3888 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, respectively; and lines 1082, 1084, 1086, 1088, 1090, 1092 correspond to simulation results of using an LDPC code with a block length of 1944 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, respectively. Reference Fig.10F , lines 1101, 1103, 1105, 1107, 1109, and 1111 correspond to the simulation results (SpecEff versus SNR) of an LDPC code with a block length of 3888 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively; and lines 1102, 1104, 1106, 1108, 1110, and 1112 correspond to the simulation results of an LDPC code with a block length of 1944 using modulation of 4-QAM, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, respectively.

[0140] References to "or" may be interpreted as inclusive, such that any item described using "or" may indicate any of a single, more than one, and all of the described items. References to at least one of a concatenated list of items may be interpreted as inclusive or to indicate any of a single, more than one, and all of the described items. For example, reference to "at least one of 'A' and 'B'" includes only 'A', only 'B', and both 'A' and 'B'. Such references used in conjunction with "including" or other open terminology may include additional items.

[0141] The term "coupled" and its variants include two components directly or indirectly joined to each other. The term "electrically coupled" and its variants include two components directly or indirectly joined to each other through a conductive material (e.g., a metal or copper trace). Such joining (for both the terms "coupled" and "electrically coupled") may be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). Such joining (for both the terms "coupled" and "electrically coupled") may be achieved by two components directly coupled to each other, where the two components are coupled to each other using separate intervening components and any additional intermediate components that are coupled to each other, or where the two components are coupled to each other using an intervening component that is integrally formed with one of the two components as a single, unitary body. If "coupled" or its variants are modified by additional terms (e.g., directly coupled), the general definition of "coupled" provided above is modified by the colloquial language meaning of the additional terms (e.g., "directly coupled" means that the two components are joined without any separate intervening components), thereby producing a narrower definition than the general definition of "coupled" provided above. Such coupling may be mechanical, electrical, or fluidic.

[0142] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0143] It should be noted that certain paragraphs of the present disclosure may refer to terms such as "first" and "second" in conjunction with stripes, data blocks, data rows, and devices for the purpose of identifying or distinguishing one from another or others. These terms are not intended to relate entities (e.g., first device and second device) only in time or according to a sequence, although in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities that can operate in a system or environment. It should be understood that the system described above may provide multiple of any one or each of those components, and these components may be provided on a stand-alone machine, or in some embodiments, on multiple machines in a distributed system. In addition, the above-described systems and methods may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (e.g., floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or tapes). The program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any byte code language (e.g., JAVA). A software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0144] Although the foregoing written description of the methods and systems enables one of ordinary skill in the art to make and use embodiments thereof, one of ordinary skill in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited to the embodiments, methods, and examples described above, but should be limited to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A method comprising: identifying, by one or more processors of the first device, a first binary parity check matrix for a quasi-cyclic low-density parity check (QC-LDPC) code according to a code rate of 3 / 4 and a code block size of 3888 bits, the first binary parity check matrix corresponding to a first exponential matrix having 144 values; encoding, by the one or more processors of the first device, data using the first binary parity-check matrix; and The encoded data is transmitted by the one or more processors of the first device.

2. The method according to claim 1, further comprising: The first exponential matrix is ​​generated by selecting at least 142 values ​​from a second exponential matrix having the same dimensions as the first exponential matrix.

3. The method according to claim 2, further comprising: shifting one or two values ​​of the first exponential matrix by -1 or +1 from one or more corresponding positive values ​​of the second exponential matrix, Wherein the one or more corresponding positive values ​​of the second exponential matrix are not selected as the at least 142 values.

4. The method of claim 2, wherein the second exponential matrix comprises the following set of values: [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 859722 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-135 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-171 -1-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1145-1-1-1-1-1 0 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0]。 5. The method according to claim 1, further comprising: identifying a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted, the second binary parity check matrix having the same dimensions as the first binary parity check matrix; and Data is encoded, by the one or more processors, using the second binary parity-check matrix.

6. The method according to claim 1, further comprising: identifying a third binary parity-check matrix corresponding to a second exponential matrix in which one or more columns of the first exponential matrix are permuted, the second exponential matrix having the same dimensions as the first exponential matrix; and Data is encoded, by the one or more processors, using the third binary parity-check matrix.

7. The method according to claim 1, further comprising: The first binary parity check matrix is ​​generated using (1) a matrix product of the first binary parity check matrix and the first exponential matrix, or (2) a matrix product of the first exponential matrix and the first binary parity check matrix.

8. The method according to claim 1, further comprising: identifying, by a second device, the first binary parity check matrix; receiving, by the second device, the encoded data from the first device; and The encoded data is decoded by the second device using the first binary parity-check matrix.

9. A device comprising: A transmitter and one or more processors, wherein the one or more processors are configured to: identifying a first binary parity check matrix for a quasi-cyclic low-density parity check (QC-LDPC) code according to a code rate of 3 / 4 and a code block size of 3888 bits, the first binary parity check matrix corresponding to a first exponential matrix having 144 values; encoding data using the first binary parity check matrix; and The encoded data is transmitted.

10. The apparatus of claim 9, wherein the one or more processors are further configured to: The first exponential matrix is ​​generated by selecting at least 142 values ​​from a second exponential matrix having the same dimensions as the first exponential matrix.

11. The apparatus of claim 10, wherein the one or more processors are further configured to: shifting one or two values ​​of the first exponential matrix by -1 or +1 from one or more corresponding positive values ​​of the second exponential matrix, Wherein the one or more corresponding positive values ​​of the second exponential matrix are not selected as the at least 142 values.

12. The apparatus of claim 10, wherein the second exponential matrix comprises the following set of values: [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 859722 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-135 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-171 -1-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1145-1-1-1-1-1 0 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0]。 13. The apparatus of claim 9, wherein the one or more processors are further configured to: identifying a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted, the second binary parity check matrix having the same dimensions as the first binary parity check matrix; and Data is encoded using the second binary parity-check matrix.

14. The apparatus of claim 9, wherein the one or more processors are further configured to: identifying a third binary parity-check matrix corresponding to a second exponential matrix in which one or more columns of the first exponential matrix are permuted, the second exponential matrix having the same dimensions as the first exponential matrix; and Data is encoded using the third binary parity-check matrix.

15. The apparatus of claim 9, wherein the one or more processors are further configured to: The first binary parity check matrix is ​​generated using (1) a matrix product of the first binary parity check matrix and the first exponential matrix, or (2) a matrix product of the first exponential matrix and the first binary parity check matrix.

16. An apparatus comprising: a receiver configured to receive the encoded data; and The one or more processors are configured to: identifying a first binary parity check matrix for a quasi-cyclic low-density parity check (QC-LDPC) code according to a code rate of 3 / 4 and a code block size of 3888 bits, the first binary parity check matrix corresponding to a first exponential matrix having 144 values; and The received encoded data is decoded using the first binary parity-check matrix. 17 . The apparatus of claim 16 , wherein the first exponential matrix comprises at least 142 values ​​selected from a second exponential matrix having the same dimensions as the first exponential matrix.

18. The apparatus of claim 17, wherein the first exponential matrix comprises one or two values ​​shifted by -1 or +1 from one or more corresponding positive values ​​of the second exponential matrix, Wherein the one or more corresponding positive values ​​of the second exponential matrix are not selected as the at least 142 values.

19. The apparatus of claim 17, wherein the second exponential matrix comprises the following set of values: [96 59 56 78 18 122-1-1-1 126 90 161-1-1-1 74 65 45 2 0-1-1-1-1 8 98 859722 61-1-1-1 98 35 82 74 31-1 108-1-1-1 0 0-1-1-1 71 153 156 102 74 70 42-135 128-1-1-1 118 14-1-1 65-1-1 0 0-1-1 18 131 88 18 109 113 146 69 84-1-1-171 -1-1-1 92 79 0-1-1 0 0-1 7 124 15 161 137 53-1 161 110-1 72-1 53-1 18-1145-1-1-1-1-1 0 0 53 151 66 42 138 118 6 77-1-1-1 70-1 125 72 53-1-1 2-1-1-1-1 0]。 20. The apparatus of claim 16, wherein the one or more processors are further configured to: identifying a second binary parity check matrix in which one or more columns of the first binary parity check matrix are permuted, the second binary parity check matrix having the same dimensions as the first binary parity check matrix; and The received encoded data is decoded using the second binary parity-check matrix.

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