Method, device, medium and system for quality assurance of a complex electronic system rapidio link

Abstract

The application discloses a complex electronic system RapidIO link quality guarantee method, device, medium and system, belongs to the field of spaceflight TT&C communication, and the method comprises the steps of setting at least two redundant connections between system exchange chips; reserving and configuring NVram for each exchange chip; according to the communication demand of a newly-inserted function and the existing routing configuration in the NVram, the management software recalculates the port routing of the newly-inserted function; the newly-calculated port routing is stored in the configuration NVram of the related exchange chip, and takes effect after power-on again. The application provides a simple system and software implementation scheme, and can reduce the high-speed communication interference influence between the existing function and the newly-inserted function.

Description

Technical Field

[0001] The present invention relates to the field of aerospace measurement, control and communication, and more specifically, to a RapidIO link quality assurance method, device, medium and system for a complex electronic system. Background Art

[0002] The RapidIO communication system is usually composed of switching chips, management nodes, and communication nodes. Its end-to-end routing is calculated by the management node and implemented by the switching chip. The switching chip supports port routing and global routing. If the ports of a single switching chip communicate crosswise, the communication processes are independent and do not interfere with each other. If there is a shared port in the communication process, the shared port needs to transmit the data of the source port in a time-sharing manner after arbitration.

[0003] In complex electronic systems, different nodes have varying communication requirements. Some applications require low latency, others high bandwidth, and still others a combination. When only a single application in a system uses the RapidIO bus, the application's communication capabilities are adequate. However, when multiple applications in a complex electronic system use the RapidIO bus, data between applications may interfere with each other, impacting communication performance and potentially causing application failure. This is particularly true in the field of aerospace measurement and control communications, where new functions are constantly being added to existing complex electronic systems. The need to ensure communication between these new functions and existing ones is particularly pressing.

[0004] In complex electronic systems without link quality assurance technology, the application of expanded functions may cause the internal communication of the newly expanded functions to affect the communication of other functions that have been stabilized, or the communication of the newly expanded functions may be affected by the communication of the already stabilized functions, resulting in abnormal operation. Such systems have the following disadvantages:

[0005] (1) Because the communication link quality requirements of newly inserted functions and existing functions are not considered, both new and old functions often fail after the new function is inserted, and the system has poor scalability;

[0006] (2) The system routing needs to be dynamically calculated after the management node is powered on, and the system initialization is slow. Summary of the Invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a RapidIO link quality assurance method, device, medium and system for a complex electronic system, which can reduce the impact of high-speed communication interference between existing functions and newly inserted functions.

[0008] The object of the present invention is achieved through the following solutions:

[0009] A complex electronic system RapidIO link quality assurance system, comprising: a management node, a switching chip, an NVram module and an SRIO device;

[0010] The management node is configured to support SRIO maintenance operation to access the SRIO switching network and IIC to access the switching chip.

[0011] Each of the switching chips is configured with NVram storage configuration parameters; a plurality of links are formed between the switching chips to form a redundant communication system; and the NVram module stores the communication parameter configuration and port routing configuration of the switching chips.

[0012] The functional applications are implemented through one or more of the SRIO devices, and each functional application has different communication requirements for the SRIO.

[0013] A complex electronic system RapidIO link quality assurance method based on the complex electronic system RapidIO link quality assurance system as described above, and the method comprises the following steps:

[0014] Step 1: In the normal operation mode, the system obtains the relevant initialization parameters from the NVram after power-on, realizes the communication parameter configuration and the routing parameter configuration, and can directly use the switching chip for inter-function communication after the functional application initialization is completed.

[0015] Step 2: When a new function is inserted into the system, the network management node enters the function insertion mode, the network management node scans the switching network through the SRIO maintenance operation to obtain the network topology, obtains the existing port routing and the communication requirements of each switching chip through the IIC, and obtains the SRIO device required by the newly inserted function and the communication requirements between the devices.

[0016] After the network topology, the inventory network configuration, the inventory network demand and the incremental network demand of the newly inserted function are obtained, the network management node calculates the routing of the newly inserted function, if the routing calculation fails, it is determined that the newly added function cannot be added to the RapidIO network without changing the existing routing conditions, if the routing calculation succeeds, the network management node records the new port routing and the communication requirements to the Nvram, and the communication requirements are used for subsequent calculation of the routing of the newly inserted function.

[0017] Step 3: After the network management node calculates the routing of the newly inserted function and stores the final routing parameters, the network management node exits the function insertion mode, and the newly inserted function can normally operate after the system is powered on again.

[0018] Further, the plurality of links specifically comprises at least two or more physical links.

[0019] A complex electronic system RapidIO link quality assurance method based on the complex electronic system RapidIO link quality assurance system as described above, performs the following steps:

[0020] S100, the network management node obtains the routing configuration in each switching chip NVram and the communication requirement of the newly inserted function when the new function is inserted,

[0021] S200, after the success of step S100, the network management node scans the current network through SRIO maintenance operation, obtains the network topology, and enters the routing configuration mode;

[0022] S300, after the success of step S200, the network management node calculates the routing for the newly inserted function in combination with the information obtained in step S100 and step S200;

[0023] S400, after the success of step S300, the network management node writes the new routing configuration calculated in step S300 into NVram;

[0024] S500, after the success of step S400, the network management node notifies the switching chip to reset, the switching chip works with the latest parameters, and the network management node exits the routing configuration mode;

[0025] S600, after the failure of step S300, it is informed that the newly added function cannot join the RapidIO network without changing the existing routing conditions, and the network management node exits the routing configuration mode.

[0026] A complex electronic system RapidIO link quality assurance device, comprising a processor and a memory, the memory stores a computer program, when the computer program is loaded by the processor, executes the method as claimed in any one of the above.

[0027] A computer readable storage medium, the computer readable storage medium stores a computer program, the computer program is loaded by a processor to execute the method as claimed in any one of the above.

[0028] The beneficial effects of the present application include:

[0029] (1) The present application has the advantage of high expansibility. The method proposed in the present application considers the communication requirements of multiple functions in the complex electronic system during system design, takes into account the communication requirements of the running functions and the newly inserted functions during function expansion, reduces the communication interference between function applications, and improves the system expansibility.

[0030] (2) The present application has the advantage of strong stability. The method proposed in the present application does not need the network management node to dynamically calculate the communication routing after the function is solidified, the communication routing between functions is clear, and the function runs stably.

[0031] (3) The application has the advantage of short system starting time. The method of the application configures the port routing through the information in the NVram, and is shorter in system starting time and faster in function online than the dynamic calculation of routing after the network management node is powered on. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 It is a schematic diagram of SRIO complex system composition;

[0034] Figure 2 It is a schematic diagram of normal working mode in the embodiment of the present application;

[0035] Figure 3 It is a schematic diagram of new function insertion mode in the embodiment of the present application. DETAILED DESCRIPTION

[0036] All features disclosed in the embodiments of the present application, or all steps in the methods or processes impliedly disclosed, can be combined and / or extended, replaced, unless mutually exclusive features and / or steps are mutually exclusive.

[0037] The specific implementation process of the present application is as follows:

[0038] As shown in Figure 1 , the complex electronic system of the present application includes a management node, a switching chip, an NVram, and an SRIO device.

[0039] Management node: support SRIO maintenance operation to access SRIO switching network and IIC to access switching chip;

[0040] Switching chip: each switching chip needs to be configured with NVram storage configuration parameters; there are 3 links between switching chips to form a redundant communication system.

[0041] NVram: NVram stores communication parameter configuration and port routing configuration of the switching chip;

[0042] SRIO device: one or more SRIO devices are used to realize the function application, and the communication requirements of each function application for SRIO are different.

[0043] As shown in Figure 2As shown, in the normal operation mode, the system obtains the related initialization parameters from the NVram after power on, realizes the communication parameter configuration and the routing parameter configuration, and can directly use the exchange chip for inter-function communication after the function application initialization is completed.

[0044] As shown in the figure, Figure 3 As shown, when a new function is inserted, the network management node enters the function insertion mode, the network management node scans the exchange network through the SRIO maintenance operation, obtains the network topology, obtains the existing port routing and the communication demand of each exchange chip through the IIC, and obtains the SRIO device required by the newly inserted function and the communication demand between the devices.

[0045] Figure 3 After obtaining the network topology, the inventory network configuration, the inventory network demand, and the incremental network demand of the newly inserted function, the network management node calculates the routing of the newly inserted function, and if the routing calculation fails, it is determined that the newly added function cannot be added to the RapidIO network without changing the existing routing conditions; if the routing calculation is successful, the network management node records the new port routing and the communication demand in the Nvram, and the communication demand is used for subsequent routing calculation of the newly inserted function.

[0046] Figure 3 After calculating the routing of the newly inserted function and storing the final routing parameters, the network management node exits the function insertion mode, and the newly inserted function can operate normally after the system is powered on again.

[0047] It should be noted that within the scope of protection defined in the claims of the present application, the following embodiments can be combined and / or extended, replaced, in any logical manner from the specific embodiments described above, such as disclosed technical principles, disclosed technical features or implied disclosed technical features.

[0048] In other embodiments, including but not limited to the following embodiments:

[0049] In one embodiment, the present application provides a complex electronic system RapidIO link quality assurance system, comprising: a management node, an exchange chip, an NVram module and an SRIO device;

[0050] The management node is configured to support SRIO maintenance operation to access the SRIO exchange network and IIC to access the exchange chip.

[0051] Each exchange chip is configured with NVram storage configuration parameters; a plurality of links are formed between the exchange chips to form a redundant communication system; and the NVram module stores the communication parameter configuration and the port routing configuration of the exchange chip.

[0052] The functional applications are implemented by one or several of the SRIO devices, and each functional application has different communication requirements for the SRIO.

[0053] In yet another embodiment, the present application provides a complex electronic system RapidIO link quality assurance method, characterized in that the complex electronic system RapidIO link quality assurance system according to claim 1 is used to perform the following steps:

[0054] Step one, in the normal operation mode, the system obtains the relevant initialization parameters from the NVram after power-on, realizes the communication parameter configuration and the routing parameter configuration, and can directly use the switch chip for inter-function communication after the functional application initialization is completed;

[0055] Step two, when the system has a new function inserted, the network management node enters the function insertion mode, the network management node scans the switch network through the SRIO maintenance operation, obtains the network topology, obtains the existing port routing and the communication requirement of each switch chip through the IIC, and obtains the SRIO device required by the newly inserted function and the communication requirement between the devices;

[0056] After the network management node obtains the network topology, the inventory network configuration, the inventory network requirement, and the incremental network requirement of the newly inserted function, the network management node calculates the routing of the newly inserted function, if the routing calculation fails, it is determined that the newly added function cannot be added to the RapidIO network without changing the existing routing condition, if the routing calculation succeeds, the network management node records the newly added port routing and the communication requirement to the Nvram, and the communication requirement is used for subsequent routing calculation of the newly inserted function;

[0057] Step three, after the network management node calculates the routing of the newly inserted function and stores the final routing parameter, the network management node exits the function insertion mode, and the newly inserted function can normally operate after the system is powered on again.

[0058] Optionally, the plurality of links specifically include at least two or more physical links.

[0059] In one embodiment, the present application provides another complex electronic system RapidIO link quality assurance method, based on the complex electronic system RapidIO link quality assurance system in the above embodiment, the following steps are performed:

[0060] S100, the network management node obtains the routing configuration in the NVram of each switch chip and the communication requirement of the newly inserted function when the new function is inserted,

[0061] S200, after the step S100 is successfully executed, the network management node scans the current network through the SRIO maintenance operation, obtains the network topology, and enters the routing configuration mode;

[0062] S300, after the success of step S200, the network management node calculates the new route for the newly inserted function based on the information obtained in step S100 and step S200;

[0063] S400, after the success of step S300, the network management node writes the new route calculated in step S300 into NVram;

[0064] S500, after the success of step S400, the network management node informs the switch chip to reset, the switch chip works with the latest parameters, and the network management node exits the route configuration mode;

[0065] S600, after the failure of step S300, the network management node informs that the newly inserted function cannot be added to the RapidIO network without changing the existing route, and the network management node exits the route configuration mode.

[0066] In an embodiment, the present application provides a RapidIO link quality assurance device for a complex electronic system, comprising a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded by the processor to execute the method in any of the above embodiments.

[0067] In an embodiment, the present application provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is loaded by a processor to execute the method in any of the above embodiments.

[0068] The units described in the embodiments of the present application can be implemented in the form of software, or can be implemented in the form of hardware, and the described units can also be arranged in a processor. In some cases, the names of these units do not constitute a limitation on the units themselves.

[0069] According to an aspect of an embodiment of the present application, a computer program product or computer program is provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computer device to perform the method provided in the various optional implementation manners described above.

[0070] As another aspect, the embodiments of the present application also provide a computer readable medium, which can be included in the electronic device described in the above embodiments, or can exist independently without being assembled into the electronic device. The computer readable medium carries one or more programs, which, when executed by the electronic device, enable the electronic device to implement the method described in the above embodiments.

Claims

1. A RapidIO link quality assurance method for a complex electronic system, characterized in that: Based on the RapidIO link quality assurance system of complex electronic systems, the system includes: management nodes, switch chips, NVRAM modules and SRIO devices; The management node is used to support SRIO maintenance operations to access the SRIO switching network and IIC access to the switching chip; Each of the switching chips is configured with NVRAM to store configuration parameters; multiple links are formed between the switching chips to form a redundant communication system; the NVRAM module stores the communication parameter configuration and port routing configuration of the switching chip; Functional applications are implemented through one or more of the SRIO devices, and each functional application has different communication requirements for SRIO; and the following steps are performed: Step 1: In normal operating mode, after the system is powered on, the SRIO switch chip obtains relevant initialization parameters from NVRAM to implement communication parameter configuration and routing parameter configuration. After the functional application initialization is completed, the switch chip can be directly used for inter-functional communication; Step 2: When a new function is inserted into the system, the network management node enters the function insertion mode. The network management node scans the switching network through SRIO maintenance operations to obtain the network topology; obtains the existing port routing and communication requirements of each switching chip through IIC; obtains the SRIO devices required for the newly inserted function and the communication requirements between devices; After obtaining the network topology, existing network configuration, existing network requirements, and incremental network requirements for the newly inserted function, the network management node calculates the route for the newly inserted function. If the route calculation fails, it is clear that the new function cannot be added to the RapidIO network without changing the existing route. If the route calculation succeeds, the network management node records the newly added port route and communication requirements in Nvram. The communication requirements will be used when calculating the route for the newly inserted function in the future. Step 3: After the network management node calculates the newly inserted function route and stores the final routing parameters, it exits the function insertion mode. After the system is powered on again, the newly inserted function can operate normally.

2. The RapidIO link quality assurance method for complex electronic systems according to claim 1, characterized in that: The multiple links specifically include at least two physical links.

3. A RapidIO link quality assurance method for a complex electronic system, characterized in that: Based on the RapidIO link quality assurance system of complex electronic systems, the system includes: management nodes, switch chips, NVRAM modules and SRIO devices; The management node is used to support SRIO maintenance operations to access the SRIO switching network and IIC access to the switching chip; Each of the switching chips is configured with NVRAM to store configuration parameters; multiple links are formed between the switching chips to form a redundant communication system; the NVRAM module stores the communication parameter configuration and port routing configuration of the switching chip; Functional applications are implemented through one or more of the SRIO devices, and each functional application has different communication requirements for SRIO; and the following steps are performed: S100, when a new function is inserted, the network management node obtains the routing configuration in the NVRAM of each switch chip and the communication requirements of the newly inserted function. S200, after step S100 is successfully executed, the network management node scans the current network through SRIO maintenance operations, obtains the network topology, and enters the routing configuration mode; S300, after step S200 is successfully executed, the network management node calculates a route for the newly inserted function by combining the information obtained in steps S100 and S200; S400, after step S300 is successfully executed, the network management node writes the new routing configuration successfully calculated in step S300 into NVRAM; S500, after step S400 is successfully executed, the network management node notifies the switch chip to reset, the switch chip uses the latest parameters to work, and the network management node exits the routing configuration mode; S600: After step S300 fails, the network management node is informed that the new function cannot join the RapidIO network without changing the existing routing conditions, and exits the routing configuration mode.

4. A RapidIO link quality assurance device for a complex electronic system, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 1 to 3 is executed.

5. A computer-readable storage medium, characterized in that A computer program is stored in a readable storage medium, and the computer program is loaded by a processor to execute the method according to any one of claims 1 to 3.

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