Data communication method, device, equipment and medium

Abstract

The invention discloses a data communication method, a data communication device, data communication equipment and a medium, relates to the technical field of computers, and is applied to a complex programmable logic device which communicates with a south bridge chip in a preset type server and an external target substrate management controller chip through a simplified pin bus. Comprising the steps that target data sent by a south bridge chip is transmitted to a target substrate management controller chip, and after a TAR signal is monitored, a first synchronous communication signal fed back by the target substrate management controller chip is acquired; converting the first synchronous communication signal into a second synchronous communication signal; and transmitting the second synchronous communication signal to a south bridge chip, so that the south bridge chip communicates with the target substrate management controller chip based on the simplified pin bus after executing the preset short-time waiting operation. According to the application, the communication between the preset type server and the target substrate management controller chip based on the simplified pin bus is realized by connecting the complex programmable logic device in series.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data communication method, device, equipment and medium. Background Art

[0002] Currently, many platform servers are directly connected to the HAM (Human Assistant Module) chip ZX1000 through the LPC (Low Pin Count Bus) bus interface of the central processing unit, so that the server and the HAM chip ZX1000 can communicate through the LPC bus, and the HAM chip ZX1000 can monitor or manage the various functions and indicators of the server; among them, the HAM chip ZX1000 is a self-developed BMC (Baseboard Management Controller) management chip.

[0003] However, there are still many platform servers that can only communicate with a single type of baseboard management controller chip movement, such as the Loongson platform server. The motherboard of the Loongson platform server is based on the Loongson 3C5000 processor and the Loongson 7A2000 south bridge chip. Due to the special LPC bus of the Loongson platform server, the reserved data signal F in the SYNC (SYNchronous Communication) signal sent by the HAM chip ZX1000 will be identified as an error bit, resulting in the inability to directly support the HAM chip ZX1000, and the Loongson platform server has no experience in debugging with the HAM chip ZX1000. At present, the Loongson platform server can only use the BMC management chip AST2500 for monitoring or management. Although this solution can communicate directly through the LPC bus, since the Loongson platform server can only use a single chip, it will cause supply problems and other limitations that cannot be solved.

[0004] In summary, how to enable the platform server to communicate with other types of baseboard management controller chips through the LPC bus to expand the monitoring and management solution of the platform server and avoid the conditional limitation that the platform server can only use a single chip for monitoring and management is a problem that needs to be solved at present. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a data communication method, device, equipment and medium, which can realize the communication between the platform server and other types of baseboard management controller chips through the LPC bus, so as to expand the monitoring and management solution of the platform server and avoid the condition limitation that the platform server can only use a single chip for monitoring and management. The specific solution is as follows:

[0006] In a first aspect, the present application discloses a data communication method, which is applied to a complex programmable logic device, wherein the complex programmable logic device establishes a communication connection with a south bridge chip in a preset type server and a target baseboard management controller chip outside the preset type server through a reduced pin bus; wherein the method comprises:

[0007] Transmitting the target data sent by the south bridge chip to the target baseboard management controller chip, and after monitoring the TAR signal in the target data, acquiring the first synchronous communication signal fed back by the target baseboard management controller chip based on the target data;

[0008] Converting the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving the signal;

[0009] The second synchronous communication signal is transmitted to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short-time waiting operation.

[0010] Optionally, after obtaining the first synchronous communication signal fed back by the target baseboard management controller chip based on the target data, the method further includes:

[0011] Determine a preset target communication signal for controlling the south bridge chip to perform a preset short-time waiting operation after receiving the present signal, and directly transmit the target communication signal to the south bridge chip in the current clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the target communication signal;

[0012] Accordingly, converting the first synchronous communication signal into a second synchronous communication signal includes:

[0013] In the process of directly transmitting the target communication signal to the south bridge chip in the current clock cycle, converting the first synchronous communication signal into the second synchronous communication signal;

[0014] Correspondingly, the transmitting of the second synchronous communication signal to the south bridge chip so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short-time waiting operation, includes:

[0015] transmitting the second synchronous communication signal to the south bridge chip in the next clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the second synchronous communication signal;

[0016] After monitoring the third synchronous communication signal sent by the target baseboard management controller chip, the third synchronous communication signal is transmitted to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after receiving the third synchronous communication signal; the third synchronous communication signal is a signal used to characterize that the target baseboard management controller chip is in a communication ready state.

[0017] Optionally, the target data includes a reset signal, a clock signal, a frame signal and a data signal; and the data signal includes the TAR signal.

[0018] Optionally, the process of transmitting the target data sent by the south bridge chip to the target baseboard management controller chip further includes:

[0019] The clock signal in the target data is acquired, and a preset global clock is set using the clock signal, so as to perform data frequency synchronization processing based on the preset global clock and the reduced pin bus.

[0020] Optionally, the complex programmable logic device includes a first reduced pin bus interface and a second reduced pin bus interface;

[0021] Accordingly, the step of transmitting the target data sent by the south bridge chip to the target baseboard management controller chip includes:

[0022] The target data sent by the south bridge chip is acquired through the first reduced pin bus interface, and the target data is transmitted to a target baseboard management controller chip through the second reduced pin bus interface.

[0023] Optionally, the transmitting the target data sent by the south bridge chip to the target baseboard management controller chip includes:

[0024] After the target baseboard management controller chip is powered on, obtaining a target indication signal sent by the target baseboard management controller chip to indicate that the power-on is completed;

[0025] Sending the target indication signal to the south bridge chip so that the south bridge chip starts to execute the operation of sending the target data;

[0026] The target data sent by the south bridge chip is transmitted to the target baseboard management controller chip.

[0027] Optionally, the transmitting the second synchronous communication signal to the south bridge chip so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short waiting operation, further comprising:

[0028] The data debugging signal sent by the target baseboard management controller chip based on the preset debugging command is transmitted to the south bridge chip, so that after the south bridge chip obtains the data debugging signal, the data debugging signal is compared with the original data signal written by the target baseboard management controller chip based on the preset debugging command. If the comparison result is consistent, it is determined that the south bridge chip and the target baseboard management controller chip communicate successfully based on the reduced pin bus.

[0029] In a second aspect, the present application discloses a data communication device, which is applied to a complex programmable logic device, wherein the complex programmable logic device establishes communication connections with a south bridge chip in a preset type server and a target baseboard management controller chip located outside the preset type server through a reduced pin bus, wherein the device includes:

[0030] A data transmission module, used for transmitting the target data sent by the south bridge chip to the target baseboard management controller chip;

[0031] A signal acquisition module, configured to acquire a first synchronous communication signal fed back by the target baseboard management controller chip based on the target data after monitoring the TAR signal in the target data;

[0032] A signal conversion module, used for converting the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used for controlling the south bridge chip to perform a preset short-time waiting operation after receiving the signal;

[0033] The communication module is used to transmit the second synchronous communication signal to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short-time waiting operation.

[0034] In a third aspect, the present application discloses an electronic device, comprising:

[0035] Memory, used to store computer programs;

[0036] The processor is used to execute the computer program to implement the steps of the aforementioned disclosed data communication method.

[0037] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned disclosed data communication method are implemented.

[0038] It can be seen that the complex programmable logic device in the present application establishes communication connections with the south bridge chip in the preset type server and the target baseboard management controller chip located outside the preset type server through the simplified pin bus, so as to transmit the target data sent by the south bridge chip to the target baseboard management controller chip through the complex programmable logic device, and after monitoring the TAR signal in the target data, obtain the first synchronous communication signal fed back by the target baseboard management controller chip based on the target data; convert the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving this signal; and transmit the second synchronous communication signal to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the simplified pin bus after performing the preset short-time waiting operation. It can be seen that the present application connects a complex programmable logic device in series between the south bridge chip in the preset type server and the target baseboard management controller chip located outside the preset type server, so as to directly transmit the target data sent by the south bridge chip to the target baseboard management controller chip through the complex programmable logic device, and after monitoring the TAR signal, converts the first synchronous communication signal fed back by the target baseboard management controller chip into a second synchronous communication signal, and then transmits the second synchronous communication signal to the south bridge chip. The second synchronous communication signal is mainly used to control the south bridge chip to perform a preset short-time waiting operation after receiving this signal, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after performing the preset short-time waiting operation, thereby solving the problem that the preset type server and the target baseboard management controller chip cannot communicate based on the reduced pin bus, expanding the monitoring and management scheme of the preset type server, and avoiding the limitation problem that the preset type server can only use a single chip for monitoring and management. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0040] Figure 1 A flow chart of a data communication method disclosed in this application;

[0041] Figure 2 A specific connection diagram disclosed in this application;

[0042] Figure 3 A specific LPC data format diagram disclosed in this application;

[0043] Figure 4 A schematic diagram of the relationship between a SYNC signal value and a state definition disclosed in this application;

[0044] Figure 5 A flow chart of a specific data communication method disclosed in this application;

[0045] Figure 6 A schematic diagram of data format before and after data conversion disclosed in this application;

[0046] Figure 7 A schematic diagram of the structure of a data communication device disclosed in this application;

[0047] Figure 8 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] At present, there are still many platform servers that can only communicate with a single type of baseboard management controller chip movement, such as the Loongson platform server. The motherboard of the Loongson platform server is based on the Loongson 3C5000 processor and the Loongson 7A2000 south bridge chip. Since the LPC bus of the Loongson platform server is relatively special, it cannot directly support the HAM chip ZX1000, and there is no debugging experience with the HAM chip ZX1000. At present, the Loongson platform server can only use the BMC management chip AST2500 for monitoring or management. Although this solution can communicate directly through the LPC bus, since the Loongson platform server can only use a single chip, it will cause supply problems that cannot be solved and other limited problems. To this end, the embodiments of the present application disclose a data communication method, device, equipment and medium, which can realize the communication between the platform server and other types of baseboard management controller chips through the LPC bus to expand the monitoring and management solution of the platform server and avoid the conditional restrictions caused by the platform server being able to use only a single chip for monitoring and management.

[0050] See also Figure 1As shown, the embodiment of the present application discloses a data communication method, which is applied to a complex programmable logic device, wherein the complex programmable logic device establishes a communication connection with a south bridge chip in a preset type server and a target baseboard management controller chip located outside the preset type server through a reduced pin bus, and the method includes:

[0051] Step S11: transmitting the target data sent by the south bridge chip to the target baseboard management controller chip, and after monitoring the TAR signal in the target data, acquiring the first synchronous communication signal fed back by the target baseboard management controller chip based on the target data.

[0052] In this embodiment, a complex programmable logic device (CPLD) is connected in series between the south bridge chip in the preset type server and the target baseboard management controller chip located outside the preset type server, so that the target data sent by the south bridge chip is directly transmitted to the target baseboard management controller chip through the complex programmable logic device, and after the TAR signal in the target data is detected, the first synchronous communication signal fed back by the target baseboard management controller chip is obtained. In addition, the target data includes a reset signal, a clock signal, a frame signal and a data signal; the data signal specifically includes a TAR signal, and the TAR signal is used to exchange the control right of the bus.

[0053] It should be pointed out that the preset type server can be a Loongson platform server, the motherboard of which is based on the Loongson processor and the Loongson south bridge chip; the target baseboard management controller chip can be a self-developed baseboard management controller chip, such as the HAM chip ZX1000, hereinafter referred to as the HAM chip. The connection diagram of the Loongson processor, the Loongson south bridge chip, the complex programmable logic device and the self-developed baseboard management controller chip is shown in the figure. Figure 2 as shown in . Figure 2Among them, the Loongson processor is the Loongson 3B4000 / 3C5000 / 3C5000L processor, etc., not limited to single-channel or dual-channel. Dual-channel is to realize two CPUs (Central Processing Unit, i.e. central processing unit) through the HT (HyperTransport, i.e. end-to-end bus technology) bus, and the performance is better at this time. The Loongson processor is connected to the Loongson South Bridge chip through the HT bus to realize server technology and data processing; the Loongson South Bridge chip adopts the Loongson 7A2000 bridge chip, not limited to single bridge chip and dual bridge chip, the dual bridge chip uses two Loongson 7A2000s, and is divided into a main bridge chip and a deputy bridge chip, and the main bridge chip is used to connect to the CPLD through the LPC bus to realize the LPC bus function expansion; the complex programmable logic device is connected to the Loongson South Bridge chip and the HAM chip respectively through the LPC bus; the self-developed baseboard management controller chip, i.e. the HAM chip is a management module based on the ZX1000 management chip, which is connected to the CPLD through the LPC bus to provide monitoring and management functions for the Loongson server.

[0054] Furthermore, the complex programmable logic device includes a first reduced pin bus interface and a second reduced pin bus interface; accordingly, the target data sent by the south bridge chip is transmitted to the target baseboard management controller chip, including: obtaining the target data sent by the south bridge chip through the first reduced pin bus interface, and transmitting the target data to the target baseboard management controller chip through the second reduced pin bus interface. It can be understood that the CPLD of the present invention includes a first reduced pin bus interface and a second reduced pin bus interface, which correspond to Figure 2 There are two LPC bus interfaces A and B in the figure. A is the LPC slave interface and B is the LPC master interface, which are denoted as A_LPC and B_LPC respectively. Among them, A_LPC is directly connected to the Loongson South Bridge chip through the LPC bus, and B_LPC is directly connected to the HAM chip through the LPC bus. Then, after the A_LPC interface of the CPLD receives the target data sent by the South Bridge chip, it directly passes it to the HAM chip through the B_LPC interface, that is, the role of the CPLD here is to complete the data forwarding. The bus signals of the A_LPC interface are denoted as A_LPC_RESETn, A_LPC_CLKIN, A_LPC_LFRAMEn, A_LPC_D[3:0], which correspond to the reset signal, clock signal, frame signal and data signal in the target data respectively; the bus signals of the B_LPC interface are similar to those of the A_LPC, denoted as B_LPC_RESETn, B_LPC_CLKOUT, B_LPC_LFRAMEn, B_LPC_D[3:0].

[0055] It should be noted that, in the process of transmitting the target data sent by the south bridge chip to the target baseboard management controller chip, it also includes: obtaining the clock signal in the target data, and using the clock signal to set the preset global clock, so as to perform data frequency synchronization processing based on the preset global clock and the reduced pin bus. Among them, the preset global clock refers to the CPLD global clock, such as Figure 2 As shown in , the CPLD global clock is a 33MHz clock crystal, which is connected to the CPLD global clock pin to provide the CPLD with a 33MHz clock for the CPLD to process the LPC bus signal. The clock is in the same frequency as the LPC bus of the Loongson South Bridge chip and the HAM chip, maximizing the LPC bus synchronization clock. That is, after obtaining the clock signal in the target data, the clock signal is used to set the preset global clock, so that the CPLD can process data in the same frequency based on the preset global clock and the reduced pin bus.

[0056] Step S12: converting the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving the signal.

[0057] In this embodiment, the CPLD needs to convert the first synchronous communication signal fed back by the target baseboard management controller chip into a second synchronous communication signal, and the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving the signal.

[0058] It should be noted that, from the above content, it can be known that the target baseboard management controller chip in this embodiment is specifically a HAM chip. LPC data format and detailed data of HAM chip ZX1000 Figure 3 As shown in the figure, it can be seen that the SYNC (SYNchronous Communication) signal in the LPC data format has reserved data F. The Loongson platform server will define the F in the SYNC signal as an error bit. If the F data is recognized, an error will be reported and the LPC bus communication will be stopped. Therefore, the embodiment of the present application solves the problem of LPC communication between the SYNC signal of the Loongson platform server and the HAM chip by serially inserting the CPLD. Specifically, when the CPLD obtains the first synchronous communication signal F fed back by the target baseboard management controller chip, it is necessary to realize the conversion of the F signal into a second synchronous communication signal for controlling the south bridge chip to perform a preset short-time waiting operation after receiving the signal, that is, to complete the data conversion processing of the signal F and convert it into a signal that can be received by the Loongson south bridge chip, so as to solve the problem that the Loongson platform server cannot support the HAM chip.

[0059] Specifically, the first synchronous communication signal F refers to 1111, and the second synchronous communication signal refers to 0101, that is, the SYNC signal "1111" fed back by the HAM chip needs to be changed to "0101" before being passed to the Loongson South Bridge chip. Before the CPLD performs data conversion processing, the Loongson South Bridge chip reads "1111" and reports an error to stop LPC bus communication. After the data conversion processing, the Loongson South Bridge chip reads "0101" and will wait for a short time and continue normal LPC communication. In the SYNC signal, the state definition corresponding to different signal values ​​can be found in Figure 4 as shown in .

[0060] Step S13: transmitting the second synchronous communication signal to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short waiting operation.

[0061] In this embodiment, the second synchronous communication signal "0101" is transmitted to the Loongson South Bridge chip, so that the Loongson South Bridge chip performs LPC communication with the target baseboard management controller chip after executing a preset short-time waiting operation.

[0062] That is, the embodiment of the present application realizes a design scheme in which a server of Loongson 3C5000 processor + Loongson 7A2000 south bridge chip is monitored and managed through HAM chip ZX1000, wherein the CPLD is based on a 33MHz global clock, and the LPC buses of Loongson 7A2000 south bridge chip and HAM chip ZX1000 are connected in series to realize the same-frequency processing of LPC data, and the target data sent by the Loongson 7A2000 south bridge chip is directly transmitted to the HAM chip, and after monitoring the TAR signal, the SYNC signal "1111" fed back by the HAM chip is changed to "0101", and then transmitted to the Loongson 7A2000 south bridge chip, so that the Loongson 7A2000 south bridge chip can normally perform LPC communication with the HAM chip ZX1000, thereby solving the key technology of Loongson platform expanding ZX1000 monitoring and management through the LPC bus.

[0063] Furthermore, the above-mentioned transmitting the second synchronous communication signal to the south bridge chip so that the south bridge chip can communicate with the target baseboard management controller chip based on the reduced pin bus after executing the preset short waiting operation, also includes: transmitting the data debugging signal sent by the target baseboard management controller chip based on a preset debugging command to the south bridge chip, so that after the south bridge chip obtains the data debugging signal, the data debugging signal is compared with the original data signal written by the target baseboard management controller chip based on the preset debugging command; if the comparison result is consistent, it is determined that the south bridge chip and the target baseboard management controller chip communicate successfully based on the reduced pin bus.

[0064] It is understandable that when the Loongson South Bridge chip and the target baseboard management controller chip perform LPC communication, further debugging is required to determine whether the LPC bus is tuned. Specifically, the data debugging signal sent by the target baseboard management controller chip based on the preset debugging command is transmitted to the Loongson South Bridge chip, so that after the Loongson South Bridge chip obtains the data debugging signal, the data debugging signal is compared with the original data signal written by the target baseboard management controller chip based on the preset debugging command. If the comparison result is consistent, it is determined that the South Bridge chip and the target baseboard management controller chip successfully communicate based on the reduced pin bus. In a specific implementation, a preset debugging command is written through the serial port on the HAM chip side: devmem0x1e789224 32 0xaa (or 0x55). The HAM chip transmits the written original data signal 0xaa as a data debugging signal to the Loongson South Bridge chip through the CPLD. After the Loongson South Bridge chip obtains the data debugging signal, it reads the data debugging signal in the shell interface. The specific reading command is: mm 0x8000_0efd_fc00_0ca2-w 1–n. If the read data debugging signal is consistent with the original data signal written by the HAM chip, it can be determined that the LPC bus is tuned through.

[0065] It can be seen that the complex programmable logic device in the present application establishes communication connections with the south bridge chip in the preset type server and the target baseboard management controller chip located outside the preset type server through the simplified pin bus, so as to transmit the target data sent by the south bridge chip to the target baseboard management controller chip through the complex programmable logic device, and after monitoring the TAR signal in the target data, obtain the first synchronous communication signal fed back by the target baseboard management controller chip based on the target data; convert the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving this signal; and transmit the second synchronous communication signal to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the simplified pin bus after performing the preset short-time waiting operation. It can be seen that the present application connects a complex programmable logic device in series between the south bridge chip in the preset type server and the target baseboard management controller chip located outside the preset type server, so as to directly transmit the target data sent by the south bridge chip to the target baseboard management controller chip through the complex programmable logic device, and after monitoring the TAR signal, converts the first synchronous communication signal fed back by the target baseboard management controller chip into a second synchronous communication signal, and then transmits the second synchronous communication signal to the south bridge chip. The second synchronous communication signal is mainly used to control the south bridge chip to perform a preset short-time waiting operation after receiving this signal, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after performing the preset short-time waiting operation, thereby solving the problem that the preset type server and the target baseboard management controller chip cannot communicate based on the reduced pin bus, expanding the monitoring and management scheme of the preset type server, and avoiding the limitation problem that the preset type server can only use a single chip for monitoring and management.

[0066] See also Figure 5 As shown, the embodiment of the present application discloses a specific data communication method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically, it includes:

[0067] Step S21: After the target BMC chip is powered on, a target indication signal sent by the target BMC chip to indicate power-on completion is obtained, and the target indication signal is sent to the south bridge chip so that the south bridge chip starts to execute the operation of sending the target data.

[0068] In this embodiment, after the target baseboard management controller chip is powered on, a target indication signal for indicating that the power-on is completed will be sent to the CPLD, and the CPLD will then send the target indication signal to the south bridge chip so that the south bridge chip can start to execute the operation of sending the target data. That is, the embodiment of the present application needs to determine that the target baseboard management controller chip is powered on before starting to send data, so as to avoid the problem that the target baseboard management controller chip cannot receive the target data due to incomplete power-on.

[0069] Step S22: transmitting the target data sent by the south bridge chip to the target baseboard management controller chip, and after monitoring the TAR signal in the target data, acquiring a first synchronous communication signal fed back by the target baseboard management controller chip based on the target data.

[0070] Step S23: Determine a preset target communication signal for controlling the south bridge chip to perform a preset short-time waiting operation after receiving this signal, and transmit the target communication signal directly to the south bridge chip in the current clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the target communication signal.

[0071] In this embodiment, considering that the CPLD will cause a certain delay when performing data conversion, direct uploading will cause insufficient data establishment time. Therefore, in the actual processing process, the embodiment of the present application directly transmits the preset target communication signal to the south bridge chip in the current clock cycle, and the target communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving this signal. That is, the present application directly uploads the signal "0101" in the late period of the current clock to control the south bridge chip to perform a preset short-time waiting operation.

[0072] Step S24: In the process of transmitting the target communication signal directly to the south bridge chip in the current clock cycle, convert the first synchronous communication signal into the second synchronous communication signal; the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving this signal.

[0073] In this embodiment, the conversion process from the first synchronous communication signal "1111" to the second synchronous communication signal "0101" is completed by adding one "0101" to perform a short wait.

[0074] Step S25: transmitting the second synchronous communication signal to the south bridge chip in the next clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the second synchronous communication signal.

[0075] In this embodiment, the converted second synchronous communication signal is transmitted to the south bridge chip in the next clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the second synchronous communication signal. Therefore, in this embodiment, the data format before and after the data conversion is as follows: Figure 6 As shown in Figure 6 In the embodiment, when no data conversion is performed, the SYNC signal is F, 0, and the corresponding binary codes are 1111 and 0000, respectively. After the data conversion through the embodiment of the present application, the SYNC signal is 5, 5, 0, and the corresponding binary codes are 0101, 0101, 0000, respectively.

[0076] Furthermore, after completing the data conversion process, an oscilloscope can be used to monitor the LPC bus waveform. After the signal "1111" fed back by the HAM core 6 is successfully converted to "0101" by the CPLD, if the data setup time is monitored to be 17.3ns and the data hold time is 9.246ns, it means that the LPC bus timing requirements are met.

[0077] Step S26: After monitoring the third synchronous communication signal sent by the target baseboard management controller chip, the third synchronous communication signal is transmitted to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after receiving the third synchronous communication signal; the third synchronous communication signal is a signal used to characterize that the target baseboard management controller chip is in a communication ready state.

[0078] In this embodiment, after the third synchronous communication signal "0000" sent by the target baseboard management controller chip is detected, "0000" is transmitted to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after receiving the third synchronous communication signal. "0000" is a signal indicating that the target baseboard management controller chip is in a communication ready state.

[0079] For a more specific processing procedure of the above step S22, reference may be made to the corresponding contents disclosed in the above embodiments, which will not be described in detail here.

[0080] It can be seen that the embodiment of the present application needs to determine that the target baseboard management controller chip is powered on before starting the data transmission, so as to avoid the problem that the target baseboard management controller chip cannot receive the target data due to the incomplete power-on. Further, considering that the CPLD will cause a certain delay when performing data conversion, direct uploading will cause insufficient data establishment time. Therefore, in the actual processing process, the embodiment of the present application directly transmits the pre-set target communication signal "0101" to the south bridge chip in the current clock cycle to control the south bridge chip to perform a preset short-time waiting operation, and simultaneously completes the conversion process of the first synchronous communication signal "1111" to the second synchronous communication signal "0101", and then transmits the converted second synchronous communication signal to the south bridge chip in the next clock cycle. Finally, after obtaining the third synchronous communication signal "0000", "0000" is transmitted to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the simplified pin bus after receiving the third synchronous communication signal.

[0081] See also Figure 7 As shown, the embodiment of the present application discloses a data communication device, which is applied to a complex programmable logic device, wherein the complex programmable logic device establishes communication connections with a south bridge chip in a preset type server and a target baseboard management controller chip outside the preset type server through a reduced pin bus, and the device includes:

[0082] A data transmission module 11, used for transmitting the target data sent by the south bridge chip to the target baseboard management controller chip;

[0083] A signal acquisition module 12, configured to acquire a first synchronous communication signal fed back by the target baseboard management controller chip based on the target data after monitoring the TAR signal in the target data;

[0084] The signal conversion module 13 is used to convert the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving the signal;

[0085] The communication module 14 is used to transmit the second synchronous communication signal to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short waiting operation.

[0086] It can be seen that the complex programmable logic device in the present application establishes communication connections with the south bridge chip in the preset type server and the target baseboard management controller chip located outside the preset type server through the simplified pin bus, so as to transmit the target data sent by the south bridge chip to the target baseboard management controller chip through the complex programmable logic device, and after monitoring the TAR signal in the target data, obtain the first synchronous communication signal fed back by the target baseboard management controller chip based on the target data; convert the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving this signal; and transmit the second synchronous communication signal to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the simplified pin bus after performing the preset short-time waiting operation. It can be seen that the present application connects a complex programmable logic device in series between the south bridge chip in the preset type server and the target baseboard management controller chip located outside the preset type server, so as to directly transmit the target data sent by the south bridge chip to the target baseboard management controller chip through the complex programmable logic device, and after monitoring the TAR signal, converts the first synchronous communication signal fed back by the target baseboard management controller chip into a second synchronous communication signal, and then transmits the second synchronous communication signal to the south bridge chip. The second synchronous communication signal is mainly used to control the south bridge chip to perform a preset short-time waiting operation after receiving this signal, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after performing the preset short-time waiting operation, thereby solving the problem that the preset type server and the target baseboard management controller chip cannot communicate based on the reduced pin bus, expanding the monitoring and management scheme of the preset type server, and avoiding the limitation problem that the preset type server can only use a single chip for monitoring and management.

[0087] In some specific embodiments, after the signal acquisition module 12, the data communication device further includes:

[0088] A first signal sending unit, configured to determine a preset target communication signal for controlling the south bridge chip to perform a preset short-time waiting operation after receiving the present signal, and directly transmit the target communication signal to the south bridge chip in a current clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the target communication signal;

[0089] Accordingly, the signal conversion module 13 is specifically configured to convert the first synchronous communication signal into the second synchronous communication signal during the process of directly transmitting the target communication signal to the south bridge chip in the current clock cycle;

[0090] Accordingly, the communication module 14 specifically includes:

[0091] A second signal sending unit, configured to transmit the second synchronous communication signal to the south bridge chip in a next clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the second synchronous communication signal;

[0092] The third signal sending unit is used to transmit the third synchronous communication signal to the south bridge chip after monitoring the third synchronous communication signal sent by the target baseboard management controller chip, so that the south bridge chip can communicate with the target baseboard management controller chip based on the reduced pin bus after receiving the third synchronous communication signal; the third synchronous communication signal is a signal used to characterize that the target baseboard management controller chip is in a communication ready state.

[0093] In some specific embodiments, the target data includes a reset signal, a clock signal, a frame signal, and a data signal; and the data signal includes the TAR signal.

[0094] In some specific embodiments, the data transmission module 11 further includes:

[0095] A clock setting unit is used to obtain the clock signal in the target data and use the clock signal to set a preset global clock so as to perform data frequency synchronization processing with the reduced pin bus based on the preset global clock.

[0096] In some specific embodiments, the complex programmable logic device includes a first reduced pin bus interface and a second reduced pin bus interface;

[0097] Correspondingly, the data transmission module 11 is specifically configured to obtain target data sent by the south bridge chip through the first reduced pin bus interface, and transmit the target data to a target baseboard management controller chip through the second reduced pin bus interface.

[0098] In some specific embodiments, the data transmission module 11 specifically includes:

[0099] an indication signal acquisition unit, used for acquiring, after the target baseboard management controller chip is powered on, a target indication signal sent by the target baseboard management controller chip and used for indicating that power-on is completed;

[0100] an indication signal forwarding unit, used for sending the target indication signal to the south bridge chip, so that the south bridge chip starts to execute the operation of sending the target data;

[0101] The target data transmission unit is used to transmit the target data sent by the south bridge chip to the target baseboard management controller chip.

[0102] In some specific embodiments, after the communication module 14, the following is further included:

[0103] A communication debugging unit is used to transmit the data debugging signal sent by the target baseboard management controller chip based on the preset debugging command to the south bridge chip, so that after the south bridge chip obtains the data debugging signal, the data debugging signal is compared with the original data signal written by the target baseboard management controller chip based on the preset debugging command. If the comparison result is consistent, it is determined that the south bridge chip and the target baseboard management controller chip communicate successfully based on the reduced pin bus

[0104] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data communication method performed by the electronic device disclosed in any of the aforementioned embodiments.

[0105] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0106] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0107] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0108] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows, Unix, Linux, etc. In addition to including a computer program that can be used to complete the data communication method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. In addition to data received by the electronic device and transmitted from an external device, the data 223 can also include data collected by its own input and output interface 25, etc.

[0109] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the method steps performed in the data communication process disclosed in any of the aforementioned embodiments are implemented.

[0110] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0111] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0112] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0113] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0114] The above is a detailed introduction to a data communication method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data communication method, characterized in that: Applied to a complex programmable logic device, the complex programmable logic device establishes communication connections with a south bridge chip in a preset type server and a target baseboard management controller chip outside the preset type server through a reduced pin bus; wherein the method comprises: Transmitting the target data sent by the south bridge chip to the target baseboard management controller chip, and after monitoring the TAR signal in the target data, acquiring the first synchronous communication signal fed back by the target baseboard management controller chip based on the target data; Converting the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used to control the south bridge chip to perform a preset short-time waiting operation after receiving the signal; The second synchronous communication signal is transmitted to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short-time waiting operation.

2. The data communication method according to claim 1, characterized in that: After obtaining the first synchronous communication signal fed back by the target baseboard management controller chip based on the target data, the method further includes: Determine a preset target communication signal for controlling the south bridge chip to perform a preset short-time waiting operation after receiving the present signal, and directly transmit the target communication signal to the south bridge chip in the current clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the target communication signal; Accordingly, converting the first synchronous communication signal into a second synchronous communication signal includes: In the process of directly transmitting the target communication signal to the south bridge chip in the current clock cycle, converting the first synchronous communication signal into the second synchronous communication signal; Correspondingly, the transmitting of the second synchronous communication signal to the south bridge chip so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short-time waiting operation, includes: transmitting the second synchronous communication signal to the south bridge chip in the next clock cycle, so that the south bridge chip performs a corresponding preset short-time waiting operation based on the second synchronous communication signal; After monitoring the third synchronous communication signal sent by the target baseboard management controller chip, the third synchronous communication signal is transmitted to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after receiving the third synchronous communication signal; the third synchronous communication signal is a signal used to characterize that the target baseboard management controller chip is in a communication ready state.

3. The data communication method according to claim 1, characterized in that: The target data includes a reset signal, a clock signal, a frame signal and a data signal; and the data signal includes the TAR signal.

4. The data communication method according to claim 3, characterized in that: The process of transmitting the target data sent by the south bridge chip to the target baseboard management controller chip also includes: The clock signal in the target data is acquired, and a preset global clock is set using the clock signal, so as to perform data frequency synchronization processing based on the preset global clock and the reduced pin bus.

5. The data communication method according to claim 1, characterized in that: The complex programmable logic device includes a first reduced pin bus interface and a second reduced pin bus interface; Accordingly, the step of transmitting the target data sent by the south bridge chip to the target baseboard management controller chip includes: The target data sent by the south bridge chip is acquired through the first reduced pin bus interface, and the target data is transmitted to a target baseboard management controller chip through the second reduced pin bus interface.

6. The data communication method according to claim 1, characterized in that: The transmitting the target data sent by the south bridge chip to the target baseboard management controller chip comprises: After the target baseboard management controller chip is powered on, obtaining a target indication signal sent by the target baseboard management controller chip to indicate that the power-on is completed; Sending the target indication signal to the south bridge chip so that the south bridge chip starts to execute the operation of sending the target data; The target data sent by the south bridge chip is transmitted to the target baseboard management controller chip.

7. The data communication method according to any one of claims 1 to 6, characterized in that: The method further comprises: transmitting the second synchronous communication signal to the south bridge chip so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short-time waiting operation; The data debugging signal sent by the target baseboard management controller chip based on the preset debugging command is transmitted to the south bridge chip, so that after the south bridge chip obtains the data debugging signal, the data debugging signal is compared with the original data signal written by the target baseboard management controller chip based on the preset debugging command. If the comparison result is consistent, it is determined that the south bridge chip and the target baseboard management controller chip communicate successfully based on the reduced pin bus.

8. A data communication device, characterized in that: Applied to a complex programmable logic device, the complex programmable logic device establishes communication connections with a south bridge chip in a preset type server and a target baseboard management controller chip outside the preset type server through a reduced pin bus, wherein the device comprises: A data transmission module, used for transmitting the target data sent by the south bridge chip to the target baseboard management controller chip; A signal acquisition module, configured to acquire a first synchronous communication signal fed back by the target baseboard management controller chip based on the target data after monitoring the TAR signal in the target data; A signal conversion module, used for converting the first synchronous communication signal into a second synchronous communication signal; the second synchronous communication signal is used for controlling the south bridge chip to perform a preset short-time waiting operation after receiving the signal; The communication module is used to transmit the second synchronous communication signal to the south bridge chip, so that the south bridge chip communicates with the target baseboard management controller chip based on the reduced pin bus after executing the preset short-time waiting operation.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the data communication method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program; wherein, when the computer program is executed by a processor, the steps of the data communication method according to any one of claims 1 to 7 are implemented.

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