A highly reliable RS485 bus interface control system, computing chip, and industrial computer

Abstract

The present application discloses a high-reliability RS485 bus interface control system, a computing chip and an industrial computer, and relates to the field of computer technology. The system includes: when starting data transmission, placing a receiving enable signal at a low level, turning off RS485 reception, then placing the RS485 sending enable signal at a high level, for setting the next-level device to wait for data transmission, then placing the sending enable signal at a high level, sending it to a UART sending module, at which point the UART sending module can start sending data; after data transmission is completed, first placing the sending enable signal at a low level, turning off the sending state, then placing the RS485 sending enable signal at a low level, placing the receiving enable signal at a high level, turning on RS485 reception, at which point the UART receiving module can start receiving data. By automatically setting the enable signal, the system can ensure that interference signals are not mistakenly received or packets are not lost at the end of transmission due to fluctuations in the magnetic field or the power supply inside the transceiver chip, thereby improving the reliability of the RS485 bus interface.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a high-reliability RS485 bus interface control system, a computing chip, and an industrial computer. Background Art

[0002] The RS485 bus interface is a commonly used communication interface in industrial systems. Its functions are implemented by three signals: the RS485 transmit signal, the RS485 receive signal, and the RS485 transmit enable signal. Data is transmitted when the RS485 transmit enable signal is high, and data is received when the RS485 transmit enable signal is low.

[0003] The RS485 transmit enable signal generally requires strict timing control from the host computer, requiring manual setting of the enable signal according to the timing. When switching from receiving data to sending data, the rising edge transition of the RS485 transmit enable signal generates magnetic fields or power fluctuations within the transceiver chip, which can easily introduce external interference and cause false reception. When switching from sending data to receiving data, the falling edge transition of the RS485 transmit enable signal also generates magnetic fields or power fluctuations within the transceiver chip, leading to packet loss or false reception at the end of the transmission. This causes trouble for staff and affects data reliability. Summary of the Invention

[0004] The present application provides a highly reliable RS485 bus interface control system, a computing chip, and an industrial computer. By automatically setting an enable signal, packet loss and erroneous reception during the transmission and reception switching process are avoided, thereby improving the reliability of the RS485 bus interface.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, the present application provides a highly reliable RS485 bus interface control system, the system comprising: a transmit FIFO module, a UART transmit module, a transceiver control module, a UART receive module, and a receive FIFO module;

[0007] The transmitting FIFO module is used to cache UART transmit data, send a low-level empty flag signal to the transmitting and receiving control module, receive a read enable signal sent by the transmitting and receiving control module, and send the UART transmit data to the UART transmitting module when the read enable signal is high. The high level of the empty flag signal indicates that there is no data in the transmitting FIFO module, and the low level indicates that there is data in the transmitting FIFO module. The initial state of the empty flag signal is high;

[0008] The UART sending module is used to receive the UART send data sent by the send FIFO module, send a data sending completion signal to the transceiver control module after receiving the data, and send the UART send data through the RS485 sending channel after receiving the high-level send enable signal sent by the transceiver control module;

[0009] The UART receiving module is configured to receive a high-level receive enable signal sent by the transceiver control module, receive the UART receive data through the RS485 receive channel, and then send the UART receive data to the receive FIFO module; when data reception is valid, a data reception valid signal is set to a high level, and the data reception valid signal is sent to the receive FIFO module, wherein the data reception valid signal serves as a write enable signal for the receive FIFO module;

[0010] The receiving FIFO module is used to cache UART receive data, and when the write enable signal is set to a high level, the UART receive data received by the UART receiving module is written into the receiving FIFO module at the rising edge of the clock, and the receiving FIFO module sends the UART receive data to the host through the receiving FIFO module output interface;

[0011] The transceiver control module is used to set the receive enable signal to a low level when starting data transmission, turn off RS485 reception, then set the RS485 send enable signal to a high level, and then set the send enable signal to a high level; after data transmission is completed, first set the send enable signal to a low level, then set the RS485 send enable signal to a low level, and then set the receive enable signal to a high level to turn on RS485 reception, wherein when the RS485 send enable signal is at a high level, it is used to set the next level device to send data, and when the RS485 send enable signal is at a low level, it is used to set the next level device to receive data.

[0012] In some possible implementations, the transceiver control module is specifically configured to start sending data when the sending status identification signal changes from a low level to a high level, and complete data sending when the sending status identification signal changes from a high level to a low level.

[0013] In some possible implementations, the transceiver control module includes a transmission control state machine;

[0014] The initial state of the sending control state machine is an idle state, and it is judged whether the first preset condition is met. The first preset condition is that the empty flag signal is set to a low level. If the first preset condition is met, it is switched to the RS485 sending ready state, the first counter is reset, the sending state identification signal is set to a high level, the first set number of clocks is delayed, and then the sending enable signal is set to a high level. It is judged whether the second preset condition is met. The second preset condition is that the first set number of clocks has been delayed. If the second preset condition is met, it is switched to the RS485 sending state, the UART sending module sends the UART send data, and then it is judged whether the third preset condition is met. The third preset condition is that there is no UART send data buffered in the sending FIFO module. If the third preset condition is met, the sending enable signal is set to a low level and jumps to the idle state.

[0015] In some possible implementations, the transceiver control module further includes a transceiver switching state machine;

[0016] The initial state of the transceiver switching state machine is an idle state, and it is judged whether the fourth preset condition is met, and the fourth preset condition is to start sending data. If the fourth preset condition is met, it is switched to the RS485 receive closed state, the receive enable signal is set to a low level, and switched to the strobe enable state. In the strobe enable state, the RS485 send enable signal is set to a high level, and it is judged whether the fifth preset condition is met. The fifth preset condition is that the data sending is completed. If the fifth preset condition is met, it is switched to the timing closed state, the second counter is reset, the RS485 send enable signal is set to a low level, and the second set number of clocks is delayed. It is judged whether the sixth preset condition is met. The sixth preset condition is that the second set number of clocks has been delayed. If the sixth preset condition is met, it is switched to the RS485 receive open state.

[0017] In some possible implementations, the transceiver switching state machine is further specifically configured to switch from the gating-enabled state to the idle state if a fifth preset condition is not satisfied.

[0018] In some possible implementations, the transceiver switching state machine is further specifically configured to switch from the timing off state to the RS485 reception off state if a fourth preset condition is satisfied during a delay of a second set number of clocks.

[0019] In some possible implementations, the transceiver switching state machine is further specifically configured to set the receive enable signal to a high level in the RS485 receive-on state, and switch to the RS485 receive-off state if a fourth preset condition is met.

[0020] In some possible implementations, the transceiver switching state machine is further specifically configured to, in an idle state, switch from the idle state to the timing-off state if a fifth preset condition is satisfied.

[0021] In a second aspect, the present application provides a computing chip, which includes the system described in any one of the first aspects.

[0022] In a third aspect, the present application provides an industrial computer, which may include the system described in any one of the first aspects.

[0023] It can be seen from the above technical solution that this application has at least the following beneficial effects:

[0024] In the present application, a transceiver control module is added to set the receive enable signal to a low level when starting data transmission, turn off the RS485 reception, and prevent the next-level device from sending data to the UART receiving module. The RS485 transmit enable signal is then set to a high level for transmission to the next-level device, confirming that the next-level device is waiting for data transmission, and then set the transmit enable signal to a high level for sending to the UART transmitting module. At this time, the UART transmitting module can start sending data. After the data transmission is completed, the transmit enable signal is first set to a low level to turn off the sending state, and then the RS485 transmit enable signal is set to a low level, and then the receive enable signal is set to a high level to turn on the RS485 reception. At this time, the UART receiving module can start receiving data. In the traditional scheme, when receiving data switches to sending data, due to the rising edge jump of the RS485 sending enable signal, a magnetic field or fluctuation of the internal power supply of the transceiver chip will be generated, which can easily introduce external interference and cause erroneous reception; when sending data switches to receiving data, due to the falling edge jump of the RS485 sending enable signal, a magnetic field or fluctuation of the internal power supply of the transceiver chip will also be generated, resulting in packet loss or erroneous reception at the end of sending. It can be seen that the present application provides a transceiver control module to control the high and low levels of the signal, ensuring that before the rising edge jump of the RS485 sending enable signal, the RS485 reception is turned off, ensuring that the interference signal is not mistakenly received due to the fluctuation of the magnetic field or the internal power supply of the transceiver chip, and also ensuring that after the falling edge jump of the RS485 sending enable signal, the RS485 reception is turned on again, and by automatically setting the enable signal, it is ensured that the interference signal is not mistakenly received or packet loss is not sent due to the fluctuation of the magnetic field or the internal power supply of the transceiver chip, thereby improving the reliability of the RS485 bus interface.

[0025] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution or beneficial effect is included in at least one embodiment. Therefore, the description of a technical feature, technical solution or beneficial effect in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be implemented without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in specific embodiments that do not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of an RS485 bus interface control system provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of a signal transmission sequence provided in an embodiment of the present application;

[0028] Figure 3 A schematic diagram of a transmission state control state machine provided in an embodiment of the present application;

[0029] Figure 4 A schematic diagram of a transceiver switching state machine provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The terms "first", "second" and "third" in this application specification and the accompanying drawings are used to distinguish different objects rather than to limit a specific order.

[0031] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0032] To make the description of the following embodiments clear and concise, a brief introduction to the related technologies is first given:

[0033] FIFO means that the first data entered is processed or removed first. In computer technology, FIFO is often used to describe the workings of a queue. A queue is a linear data structure in which data items are arranged in the order of insertion and accessed and processed according to the first-in, first-out principle. This structure can be used in a variety of scenarios, such as task scheduling and data buffering. In network packet processing, FIFO queues ensure that packets are processed in the order they are received, thereby ensuring normal and orderly network communication.

[0034] A FIFO memory is typically a first-in, first-out, dual-port buffer. The first data entered is the first data removed. It has one input port and one output port. Data is stored in the memory in the order it was written and is sent out of the output port in the same order. The FIFO memory is actually a circular data structure, with a write pointer (WP) and a read pointer (RP) indicating the corresponding cells for data write and read, respectively. Due to its flexibility, convenience, and efficiency, FIFOs are increasingly used in high-speed data acquisition, high-speed data processing, high-speed data transmission, and multi-processor systems. FIFOs can improve system performance, increase data transfer rates, and handle large data streams.

[0035] Currently, when the receiving data switches to the sending data, the rising edge transition of the RS485 send enable signal will generate fluctuations in the magnetic field or the internal power supply of the transceiver chip, which can easily introduce external interference and cause false reception. When the sending data switches to the receiving data, the falling edge transition of the RS485 send enable signal will also generate fluctuations in the magnetic field or the internal power supply of the transceiver chip, resulting in packet loss or false reception at the end of the transmission.

[0036] In view of this, an embodiment of the present application provides a highly reliable RS485 bus interface control system, in which a transceiver control module is added to set the receive enable signal to a low level when starting data transmission, turn off the RS485 reception, and prevent the next-level device from sending data to the UART receiving module. The RS485 transmit enable signal is then set to a high level for transmission to the next-level device to determine that the next-level device is waiting for data transmission, and then the transmit enable signal is set to a high level for sending to the UART transmitting module. At this time, the UART transmitting module can start sending data; after the data transmission is completed, the transmit enable signal is first set to a low level to turn off the sending state, and then the RS485 transmit enable signal is set to a low level, and then the receive enable signal is set to a high level to turn on the RS485 reception. At this time, the UART receiving module can start receiving data. It can be seen that the present application provides a transceiver control module to control the high and low levels of the signal, thereby ensuring that the RS485 reception is turned off before the RS485 send enable signal jumps on the rising edge, ensuring that the interference signal is not mistakenly received due to the magnetic field or the fluctuation of the power supply inside the transceiver chip. It also ensures that the RS485 reception is turned on after the RS485 send enable signal jumps on the falling edge. By automatically setting the enable signal, it is ensured that the interference signal is not mistakenly received or the packet is lost at the end of the transmission due to the fluctuation of the magnetic field or the power supply inside the transceiver chip, thereby improving the reliability of the RS485 bus interface.

[0037] In order to make the technical solution of this application clearer and easier to understand, the following describes an RS485 bus interface control system provided by an embodiment of this application in conjunction with the accompanying drawings. Figure 1 As shown in the figure, this figure is a schematic diagram of an RS485 bus interface control system provided in an embodiment of the present application.

[0038] In an embodiment of the present application, the RS485 bus interface control system is always in a receiving state. When the host needs to send data, it switches to a sending data state. The control system includes: a sending FIFO module 101, a UART sending module 102, a transceiver control module 103, a UART receiving module 104 and a receiving FIFO module 105.

[0039] The sending FIFO module 101 is used to cache UART send data. The capacity of the sending FIFO module 101 is 1024 bytes, and the data width is 8 bits. The host sends UART send data to the sending FIFO module. The sending FIFO module 101 receives the data one by one and sends a low-level empty flag signal to the transceiver control module 103. The sending FIFO module 101 receives the read enable signal sent by the transceiver control module 103. When the read enable signal is high, the UART send data is sent to the UART sending module 102 in each clock cycle. The high level of the empty flag signal indicates that there is no data in the sending FIFO module, and the low level indicates that there is data in the sending FIFO module. In this application, the initial state of the empty flag signal is high.

[0040] The UART sending module 102 is used to receive the UART send data sent by the send FIFO module 101 according to the standard UART protocol, and send a data sending completion signal to the transceiver control module 103 after receiving a byte of data. After receiving the high-level send enable signal sent by the transceiver control module 103, the RS485 send is turned on to send the UART send data through the RS485 send channel. When the low-level send enable signal sent by the transceiver control module 103 is received again, the RS485 send is turned off.

[0041] The UART receiving module 104 is used to receive the high-level receive enable signal sent by the transceiver control module 103, receive UART receive data through the RS485 receive channel according to the standard UART protocol, and then send the UART receive data to the receive FIFO module 105. When the data reception is valid, that is, a data is completely sent to the receive FIFO module 105, the data reception valid signal is set to a high level, and the data reception valid signal is sent to the receive FIFO module 105 as a write enable signal of the receive FIFO module 105;

[0042] The receiving FIFO module 105 is used to buffer the UART receiving data. When the write enable signal is set to a high level, the UART receiving data is received from the UART receiving module 104 and then transmitted to the host.

[0043] The data is received and cached by the sending FIFO module 101 and the receiving FIFO module 105 , which can play a buffering role in the process of data transmission, ensuring that the data can be sent one by one in sequence.

[0044] The transceiver control module 103 is used for, when starting data transmission, placing the receiving enable signal at a low level, closing the RS485 reception, for transmitting to the next level device, then placing the RS485 transmission enable signal at a high level, then placing the transmission enable signal at a high level, for sending to the UART transmission module, at which point the UART transmission module can begin to transmit data; after data transmission is completed, first placing the transmission enable signal at a low level, closing the transmission state, then placing the RS485 transmission enable signal at a low level, then placing the receiving enable signal at a high level, opening the RS485 reception, at which point the UART reception module can begin to receive data. When the RS485 transmission enable signal is at a high level, the next level device is configured to transmit data, and when the RS485 transmission enable signal is at a low level, the next level device is configured to receive data.

[0045] In the transceiver control module 103, there is a transmission status identification signal. When the transmission status identification signal changes from low level to high level, data transmission starts. When the transmission status identification signal changes from high level to low level, data transmission is completed.

[0046] Among them, a certain delay time must be ensured between each step. The embodiment of the present application provides a schematic diagram of the signal sending sequence, such as Figure 2 As shown, the figure is a schematic diagram of a signal sending sequence provided by an embodiment of the present application. It can be seen in the figure that the sending status identification signal first changes from a low level to a high level, and after a certain delay, the receiving enable signal changes from a high level to a low level. At this time, the RS485 reception is turned off, and after a certain delay, the RS485 sending enable signal changes from a low level to a high level and is sent to the next-level device, prompting the next-level device that the host wants to send data. After another certain delay, the sending enable signal changes from a low level to a high level and is sent to the UART sending module 102. Then the UART sending module 102 can send the UART send data to the next-level device through the RS485 sending channel.

[0047] The transceiver control module 103 also includes a transmission state control state machine and a transceiver switching control state machine, which are used to implement timing control, ensure the transmission and reception of data, and improve the reliability of the RS485 bus interface. The transmission state control state machine and the transceiver switching control state machine are respectively introduced in detail below.

[0048] The embodiment of the present application provides a schematic diagram of a sending state control state machine, such as Figure 3As shown in the figure, this figure is a schematic diagram of a sending state control state machine provided in an embodiment of the present application. As can be seen in the figure, the sending state control state machine includes an idle state, an RS485 sending preparation state and an RS485 sending state. The first preset condition is that the empty flag signal is set to a low level, the second preset condition is that the clock has been delayed by a first set number, and the third preset condition is that there is no cached UART sending data in the sending FIFO module 101.

[0049] The initial state of the sending state control state machine is the idle state. At this time, the sending state identification signal is at a low level. It is judged whether the first preset condition is met. If the first preset condition is met, it means that there is data to be sent in the sending FIFO module 101 at this time, then it is switched to the RS485 sending ready state, the first counter is reset, the sending state identification signal is set to a high level, the first set number of clocks is delayed, and then the sending enable signal is set to a high level, RS485 sending is turned on, and then it is judged whether the second preset condition is met. If the second preset condition is met, it is switched to the RS485 sending state, and the UART sending module 102 sends the UART send data to the next level device, and then it is judged whether the third preset condition is met. If the third preset condition is met, the sending enable signal is set to a low level, RS485 sending is turned off, and the idle state is jumped to.

[0050] In the embodiment of the present application, the first set number is 10, which is used to ensure that the receiving enable signal and the RS485 sending enable signal complete the high and low level conversion.

[0051] The embodiment of the present application also provides a schematic diagram of a transceiver switching state machine, such as Figure 4 As shown, the figure is a schematic diagram of a transceiver switching state machine provided in an embodiment of the present application. As can be seen in the figure, the transceiver switching state machine includes an idle state, an RS485 reception closed state, a strobe enable state, a timing closed state and an RS485 reception open state. The fourth preset condition is to start sending data, the fifth preset condition is that data sending is completed, and the sixth preset condition is that the second set number of clocks has been delayed.

[0052] The initial state of the transceiver switching state machine is an idle state, and it is determined whether the fourth preset condition is met. If the fourth preset condition is met, it is switched to the RS485 receive closed state, the receive enable signal is set to a low level, and the low-level receive enable signal is sent to the UART receiving module 104. The UART receiving module 104 closes the RS485 receive channel, and the transceiver switching state machine is switched to the strobe enable state. In the strobe enable state, the RS485 transmit enable signal is set to a high level, and it is determined whether the fifth preset condition is met. If the fifth preset condition is met, it is switched to the timing closed state, the second counter is reset, the RS485 transmit enable signal is set to a low level, and the second set number of clocks is delayed to determine whether the sixth preset condition is met. If the sixth preset condition is met, all UART transmit data has been sent out at this time, and the transceiver switching state machine is switched to the RS485 receive open state.

[0053] The transceiver switching state machine is further specifically configured to switch from the timing off state to the RS485 reception off state if a fourth preset condition is satisfied during the delay of the second set number of clocks.

[0054] In an embodiment of the present application, if the host sends UART data to the transmit FIFO module 101 in the timing off state, the transmit FIFO module 101 will send a low-level empty flag signal to the transceiver control module 103, so the transceiver switching state machine will switch the timing off state to the RS485 receive off state.

[0055] The transceiver switching state machine is further specifically configured to set the receive enable signal to a high level when the RS485 receive is on; if a fourth preset condition is met, indicating that new UART transmit data is waiting to be sent, the state machine switches to the RS485 receive off state.

[0056] The transceiver switching state machine is further specifically configured to switch from the strobe-enabled state to the idle state if a fifth preset condition is not met, and in the idle state, switch from the idle state to the timer-off state if the fifth preset condition is met. During the transmission process, the transceiver switching state machine will not remain in the strobe-enabled state but will automatically switch to the idle state. When the transmission is completed, it will switch from the idle state to the timer-off state to count and wait for new transmission data to be sent. If no new transmission data is received within a second set number of clocks, the transceiver switching state machine will switch to the RS485 receive-on state.

[0057] In the embodiment of the present application, the second set number is 100, which is used to ensure that all UART transmission data is sent to the next level device.

[0058] Therefore, in the present application, a transceiver control module is added, which is used to set the receive enable signal to a low level when starting data transmission, turn off the RS485 reception, and prevent the next-level device from sending data to the UART receiving module. The RS485 transmit enable signal is then set to a high level for transmission to the next-level device, confirming that the next-level device is waiting for data transmission, and then set the transmit enable signal to a high level for sending to the UART transmitting module. At this time, the UART transmitting module can start sending data. After the data transmission is completed, the transmit enable signal is first set to a low level to turn off the sending state, and then the RS485 transmit enable signal is set to a low level, and then the receive enable signal is set to a high level to turn on the RS485 reception. At this time, the UART receiving module can start receiving data. It can be seen that the present application provides a transceiver control module to control the high and low levels of the signal, thereby ensuring that the RS485 reception is turned off before the RS485 send enable signal jumps on the rising edge, ensuring that the interference signal is not mistakenly received due to the magnetic field or the fluctuation of the power supply inside the transceiver chip. It also ensures that the RS485 reception is turned on after the RS485 send enable signal jumps on the falling edge. By automatically setting the enable signal, it is ensured that the interference signal is not mistakenly received or the packet is lost at the end of the transmission due to the fluctuation of the magnetic field or the power supply inside the transceiver chip, thereby improving the reliability of the RS485 bus interface.

[0059] The embodiment of the present application further provides a computing chip, which includes any one of the modules described in the above-mentioned high-reliability RS485 bus interface control system.

[0060] An embodiment of the present application further provides an industrial computer program product comprising instructions, which, when run on an electronic device, enables the electronic device to execute any one of the modules described in the above-mentioned high-reliability RS485 bus interface control system.

[0061] Through the description of the above embodiments, those skilled in the art will clearly understand that for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the system described above can refer to the corresponding process in the previous embodiment and will not be repeated here.

[0062] In the several embodiments provided in this embodiment, it should be understood that the disclosed system, chip, and industrial computer can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0063] In addition, the functional modules in each embodiment of the present invention may be integrated into a single processing unit, or each unit may exist physically separately, or two or more modules may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0064] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment. The aforementioned storage medium includes: various media that can store program code, such as flash memory, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk.

[0065] The embodiment of the present application further provides an industrial computer comprising any one of the modules described in the above-mentioned high-reliability RS485 bus interface control system.

[0066] The descriptions of the processes or structures corresponding to the above figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0067] The above description is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A highly reliable RS485 bus interface control system, characterized in that: The system includes: a sending FIFO module, a UART sending module, a sending and receiving control module, a UART receiving module and a receiving FIFO module; The transmitting FIFO module is used to cache UART transmit data, send a low-level empty flag signal to the transmitting and receiving control module, receive a read enable signal sent by the transmitting and receiving control module, and send the UART transmit data to the UART transmitting module when the read enable signal is high. The high level of the empty flag signal indicates that there is no data in the transmitting FIFO module, and the low level indicates that there is data in the transmitting FIFO module. The initial state of the empty flag signal is high; The UART sending module is used to receive the UART send data sent by the send FIFO module, send a data sending completion signal to the transceiver control module after receiving the data, and send the UART send data through the RS485 sending channel after receiving the high-level send enable signal sent by the transceiver control module; The UART receiving module is configured to receive a high-level receive enable signal sent by the transceiver control module, receive the UART receive data through the RS485 receive channel, and then send the UART receive data to the receive FIFO module; when data reception is valid, a data reception valid signal is set to a high level, and the data reception valid signal is sent to the receive FIFO module, wherein the data reception valid signal serves as a write enable signal for the receive FIFO module; The receiving FIFO module is used to cache UART receive data, and when the write enable signal is set to a high level, the UART receive data received by the UART receiving module is written into the receiving FIFO module at the rising edge of the clock, and the receiving FIFO module sends the UART receive data to the host through the receiving FIFO module output interface; The transceiver control module is used to set the receive enable signal to a low level when starting data transmission, turn off RS485 reception, then set the RS485 send enable signal to a high level, and then set the send enable signal to a high level; after data transmission is completed, first set the send enable signal to a low level, then set the RS485 send enable signal to a low level, and then set the receive enable signal to a high level to turn on RS485 reception, wherein when the RS485 send enable signal is at a high level, it is used to set the next level device to send data, and when the RS485 send enable signal is at a low level, it is used to set the next level device to receive data.

2. The system according to claim 1, wherein: The transceiver control module is specifically configured to start sending data when the sending status identification signal is converted from a low level to a high level, and complete data sending when the sending status identification signal is converted from a high level to a low level.

3. The system according to claim 1, wherein: The transceiver control module includes a transmission control state machine; The initial state of the sending control state machine is an idle state, and it is judged whether the first preset condition is met. The first preset condition is that the empty flag signal is set to a low level. If the first preset condition is met, it is switched to the RS485 sending ready state, the first counter is reset, the sending state identification signal is set to a high level, the first set number of clocks is delayed, and then the sending enable signal is set to a high level. It is judged whether the second preset condition is met. The second preset condition is that the first set number of clocks has been delayed. If the second preset condition is met, it is switched to the RS485 sending state, the UART sending module sends the UART send data, and then it is judged whether the third preset condition is met. The third preset condition is that there is no UART send data buffered in the sending FIFO module. If the third preset condition is met, the sending enable signal is set to a low level and jumps to the idle state.

4. The system according to claim 1, wherein: The transceiver control module also includes a transceiver switching state machine; The initial state of the transceiver switching state machine is an idle state, and it is judged whether the fourth preset condition is met, and the fourth preset condition is to start sending data. If the fourth preset condition is met, it is switched to the RS485 receive closed state, the receive enable signal is set to a low level, and switched to the strobe enable state. In the strobe enable state, the RS485 send enable signal is set to a high level, and it is judged whether the fifth preset condition is met. The fifth preset condition is that the data sending is completed. If the fifth preset condition is met, it is switched to the timing closed state, the second counter is reset, the RS485 send enable signal is set to a low level, and the second set number of clocks is delayed. It is judged whether the sixth preset condition is met. The sixth preset condition is that the second set number of clocks has been delayed. If the sixth preset condition is met, it is switched to the RS485 receive open state.

5. The system according to claim 4, characterized in that The transceiver switching state machine is further specifically configured to switch from the enable state to the idle state if a fifth preset condition is not satisfied.

6. The system according to claim 4, characterized in that The transceiver switching state machine is further specifically configured to switch from the timing off state to the RS485 reception off state if a fourth preset condition is satisfied during the delay of the second set number of clocks.

7. The system according to claim 4, wherein: The transceiver switching state machine is further specifically configured to set the receive enable signal to a high level when the RS485 receive is in the on state, and switch to the off state if a fourth preset condition is met.

8. The system according to claim 4, wherein: The transceiver switching state machine is further specifically configured to switch from the idle state to the timing-off state if a fifth preset condition is satisfied in the idle state.

9. A computing chip, characterized in that: A system comprising any one of claims 1 to 8.

10. An industrial computer, characterized in that: A system comprising any one of claims 1 to 8.

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