Memory assembly and manufacturing method thereof

Abstract

The invention provides a memory component and a manufacturing method thereof. The memory assembly includes: a plurality of active regions defined in a semiconductor substrate by isolation structures, the plurality of active regions being arranged in an array along a first direction and a second direction and extending along a third direction; and a plurality of word lines passing through the plurality of active regions in the second direction in the semiconductor substrate. The plurality of active regions are arranged in pairs in the second direction, the same pair of active regions are adjacent to each other at a first distance, and two adjacent pairs of active regions are spaced apart from each other at a larger second distance. A feature portion of each active region below the passed word line has a first side adjacent to the other active region in the same pair by a first distance and a second side spaced apart from the other pair of active regions by a second distance, and has an inclined upper surface rising from the second side to the first side.

Description

Technical Field

[0001] The present invention relates to a semiconductor component and a manufacturing method thereof, and in particular to a memory component and a manufacturing method thereof. Background Art

[0002] DRAM is a widely used volatile memory. Each DRAM cell includes an access transistor and a storage capacitor connected to the access transistor. With the development of DRAM technology, the integration density of DRAM continues to increase. This increase in integration density includes shortening the spacing between the active areas of the access transistors. By arranging DRAM cells more densely, more DRAM cells can be arranged in a given area, so the storage density of DRAM is improved. In addition, in order to further improve the performance of DRAM, it is also expected to enhance the performance of the access transistors therein while increasing the integration density of DRAM. Summary of the invention

[0003] An embodiment of the present disclosure provides a memory component, comprising: a plurality of active regions defined in a semiconductor substrate with an isolation structure, wherein the plurality of active regions are arranged in an array along a first direction and a second direction, and extend respectively along a third direction interlaced with the first direction and the second direction; and a plurality of word lines formed in the semiconductor substrate and passing through the plurality of active regions along the second direction, wherein the plurality of active regions are arranged in pairs in the second direction, the active regions of the same pair are adjacent to each other at a first distance, and the active regions of two adjacent pairs are spaced apart from each other at a second distance greater than the first distance, and a characteristic portion of each active region located below at least one of the plurality of word lines passing through has a first side adjacent to another active region of the same pair at the first distance and a second side spaced apart from the active region of the other pair at the second distance, and has an inclined upper surface climbing from the second side to the first side.

[0004] Another embodiment of the present disclosure provides a method for manufacturing a memory component, comprising: defining a plurality of active regions separated from each other in a semiconductor substrate by an isolation structure, wherein the plurality of active regions are arranged in an array along a first direction and a second direction and extend respectively along a third direction intersecting the first direction and the second direction, the plurality of active regions are arranged in pairs in the second direction, the active regions of the same pair are adjacent to each other at a first distance, and the active regions of two adjacent pairs are spaced apart from each other at a second distance greater than the first distance; forming a mask pattern on the semiconductor substrate, wherein the mask pattern has a plurality of active regions along a first direction and a second direction intersecting the first direction and the second direction; a plurality of openings extending in the second direction; performing multiple etching processes with the mask pattern as a mask to form multiple trenches passing through the isolation structure and the multiple active regions, wherein after the multiple etching processes, a feature portion of each active region located below at least one of the multiple trenches passing through has a first side that is adjacent to another active region in the same pair at the first distance and a second side that is spaced apart from the active region of the other pair at the second distance, and has an inclined upper surface that rises from the second side to the first side; and filling multiple word lines in the multiple trenches. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a plan view of a memory component according to some embodiments of the present disclosure;

[0006] Figure 1B is along Figure 1A A schematic cross-sectional view of the tangent line A-A';

[0007] Figure 1C Book Edge Figure 1A A schematic cross-sectional view of a tangent line BB';

[0008] Figure 2 is a flow chart of a method for manufacturing active areas and word lines according to some embodiments of the present disclosure;

[0009] FIG. 3A to FIG. 3J yes Figure 2 Schematic cross-sectional views of intermediate structures at various stages of the manufacturing process. DETAILED DESCRIPTION

[0010] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0011] Figure 1A 1 is a schematic plan view of a memory component 10 according to some embodiments of the present disclosure. The memory component 10 is, for example, a DRAM array including a plurality of DRAM cells. Each DRAM cell includes an access transistor and a storage capacitor connected to the access transistor. For simplicity, Figure 1A The storage capacitor disposed above the access transistor is not shown. Figure 1A Most of the insulating components are not shown. At least some of the insulating components will be referred to as Figure 1B and Figure 1C illustrate.

[0012] Please refer to Figure 1A The memory component 10 includes a plurality of active regions 100. Each active region 100 may be a semiconductor substrate (refer to Figure 1B , Figure 1C The isolation structure 102 formed in the semiconductor substrate laterally surrounds each active region 100 to electrically isolate adjacent active regions 100 from each other.

[0013] The active regions 100 of each column are arranged along a direction D1, and the active regions 100 of each row are arranged along a direction D2 that is staggered with (e.g., orthogonal to) the direction D1. The active regions 100 of each column may be offset relative to the active regions 100 of adjacent columns. Similarly, the active regions 100 of each row may be offset relative to the active regions 100 of adjacent rows. In addition, each active region 100 may extend along a direction D3 that is staggered with the direction D1 and the direction D2. A plurality of insulating structures 104 separated from each other are buried in the isolation structure 102 and are respectively located between two active regions 100 adjacent to each other in the direction D3. In some embodiments, each insulating structure 104 is concave corresponding to the active regions 100 on both sides, and has a double concave shape.

[0014] A plurality of word lines 106 penetrate the array of active areas 100 along a direction D2. The access transistor of each DRAM cell is defined at the intersection of a word line 106 and an active area 100. For each access transistor, the word line 106 it passes through serves as a gate, and the portions of the active area 100 located on both sides of the word line 106 serve as a drain and a source. In order to allow two access transistors to share an active area 100, each active area 100 is interlaced with a pair of word lines 106. In this way, the portion of each active area 100 located between the two interlaced word lines 106 can serve as a common drain / source of the shared two access transistors.

[0015] A plurality of bit lines 108 extend above the semiconductor substrate along a direction D1 and intersect with a column of active regions 100. The portion of each active region 100 that serves as a common drain / source may be connected to the upper bit line 108 via a bit line contact structure 110. As described above, the portion of each active region 100 that serves as a common drain / source may be a portion located between two intersecting word lines 106. Therefore, each active region 100 may overlap the upper bit line contact structure 110 and the bit line 108 at the portion located between the two intersecting word lines 106.

[0016] On the other hand, the portions of each active region 100 located on both sides of the two intersecting word lines 106 are connected to a storage capacitor (not shown) above via a capacitor contact structure 112. In other words, each active region 100 overlaps the two capacitor contact structures 112 at both ends. Although not shown, a plurality of storage capacitors respectively connected to a capacitor contact structure 112 may be disposed on the bit line contact structure 110, the capacitor contact structure 112, and the bit line 108. These storage capacitors may have a plurality of bottom electrodes separated from each other and respectively connected to a capacitor contact structure 112, and may share a dielectric layer and a top electrode.

[0017] Based on the staggered configuration, each word line 106 intersects some active areas 100 and overlaps the isolation structures 102 and the insulation structures 104 distributed between these active areas 100. The active areas 100 intersected by each word line 106 are adjacent to each other. Looking along each word line 106, each pair of active areas 100 adjacent to each other is arranged between two insulation structures 104, and is separated from two adjacent pairs of active areas 100 by a larger interval through the two insulation structures 104. Specifically, under each word line 106, the active areas 100 in the same pair are adjacent to each other at an interval of distance S1, and each pair of active areas 100 is separated from two adjacent pairs of active areas 100 by a distance S2 greater than the distance S1. As a result, each active area 100 is separated from two adjacent active areas 100 in the direction D2 by different distances S1 and S2. As will be described in more detail, when forming word lines 106, this unequal spacing will cause the portion of each active area 100 extending along the bottom surface of the staggered word lines 106 to have a slope that rises from one side of the long spacing to the other side of the short spacing. Correspondingly, the section of each word line 106 that passes through the active area 100 also has an inclined bottom surface.

[0018] Figure 1B is along Figure 1A A schematic cross-sectional view of the tangent line A-A', and Figure 1C is along Figure 1A It should be noted that: Figure 1B and Figure 1C Components located on the semiconductor substrate, including the bit line contact structure 110 , the capacitor contact structure 112 , and the bit line 108 , are omitted from illustration.

[0019] Please refer to the schematic diagram showing a cross section along the extension direction (third direction D3) of the active region 100. Figure 1B, the isolation structure 102 extends from the top surface of the semiconductor substrate 114 into the semiconductor substrate 114, and surrounds each active region 100. In addition, the insulating structures 104 located at both ends of each active region 100 extend from the top surface of the isolation structure 102 into the isolation structure 102, so that the isolation structure 102 covers the insulating structure 104. In some embodiments, the isolation structure 102 and the insulating structure 104 embedded in the isolation structure 102 are made of different insulating materials. For example, the isolation structure 102 can be made of silicon oxide, and the insulating structure 104 can be made of silicon nitride.

[0020] from Figure 1B It can be seen that the word line 106 is buried in the semiconductor substrate 114 and can pass through the active area 100, the isolation structure 102, and the insulating structure 104 embedded in the isolation structure 102. In addition, the word line 106 can be formed at the bottom of the trenches that penetrate into the semiconductor substrate 114, and the upper part of these trenches is filled with insulating plugs 116. Furthermore, the section of each trench that passes through the active area 100 can be lined with a gate dielectric layer 118, so that the word line 106 and the insulating plug 116 in the trench are separated from the active area 100 through the gate dielectric layer 118. On the other hand, the section of each trench that passes through the isolation structure 102 and the insulating structure 104 can have a deeper depth than the section that passes through the active area 100 and is not lined with the gate dielectric layer 118. This allows the portion of the word line 106 located in the section of each trench passing through the isolation structure 102 and the insulation structure 104 to extend downward to a deeper depth than the portion of the word line 106 located in the section of each trench passing through the active area 100. In addition, the portion of the word line 106 and the insulator plug 116 located in the section of each trench passing through the isolation structure 102 and the insulation structure 104 is not covered by the gate dielectric layer 118. In some embodiments, the insulating liner 120 extends along the top surface of the semiconductor substrate 114, the isolation structure 102, and the insulation structure 104. In these embodiments, the trenches accommodating the word line 106 and the insulator plug 116 penetrate through the insulating liner 120 into the active area 100, the isolation structure 102, and the insulation structure 104. Furthermore, although not shown, each word line 106 may have a conductive material body and a conductive barrier layer covering the conductive material body.

[0021] Figure 1C A cross section along a line 106 is schematically shown. Figure 1CIt can be seen that the section of each word line 106 passing through the isolation structure 102 and the insulation structure 104 extends downward to a deeper depth than the section passing through the active area 100. This makes the portion of each active area 100 located below the intersecting word line 106 protrude compared to the portion of the isolation structure 102 and the insulation structure 104 located below the intersecting word line 106. In addition, the active areas 100 intersecting each word line 106 are arranged in pairs along the extension direction (direction D2) of the word line 106. Among them, the active areas 100 in the same pair (for example, the active areas 100a and 100b) are adjacent to each other at a distance S1 and are separated by the isolation structure 102. In addition, each pair of active regions 100 (for example, active regions 100a and 100b) is separated from an adjacent pair of active regions 100 (for example, a pair of active regions 100 including active region 100c or another pair of active regions 100 including active region 100d) by a distance S2 greater than the distance S1, and an isolation structure 102 and an insulating structure 104 are filled between the two adjacent pairs of active regions 100.

[0022] As a result, the portion of each active region 100 located below the intersecting word line 106 has a first side spaced apart from the adjacent active region 100 by a shorter distance S1, and has a second side spaced apart from another active region 100 by a longer distance S2. Based on the etching difference, the portion of each active region 100 located below the intersecting word line 106 has an inclined upper surface 100s climbing from the second side to the first side along the direction D2. Accordingly, in a cross section along the direction D2, the portion of each active region 100 located below the intersecting word line 106 has a shape similar to the end of a utility knife. Correspondingly, each word line 106 has an inclined lower surface 106s extending along the inclined upper surface 100s of the underlying active region 100, and has a first depth DP1 at the first side of the corresponding underlying active region 100, and has a second depth DP2 greater than the first depth DP1 at the second side of the corresponding underlying active region 100. In addition, the gate dielectric layer 118 between each word line 106 and the intersecting active regions 100 also extends along the inclined upper surfaces 100 s of these active regions 100 .

[0023] Based on the fact that the active areas 100 intersected by each word line 106 are periodically arranged in a pairwise manner along the direction D2, the two active areas 100 in the same pair (for example, the active areas 100a and 100b) are symmetrical to each other with respect to the center axis therebetween. In this way, the inclined upper surfaces 100s of the two active areas 100 in the same pair (for example, the active areas 100a and 100b) rise toward the center axis therebetween. In addition, each active area 100 may also be symmetrical to another active area 100 (for example, the active areas 100b and 100c or the active areas 100a and 100d) separated by a distance S2, so that the inclined upper surfaces 100s of the two active areas 100 (the active areas 100b and 100c or the active areas 100a and 100d) descend toward the center axis therebetween.

[0024] On the other hand, the portions of the isolation structure 102 and the insulating structure 104 located below each word line 106 are not limited to having an upper surface inclined along the direction D2, and the portions of each word line 106 located above the isolation structure 102 and the insulating structure 104 may have a corresponding lower surface. For example, these portions of the isolation structure 102 and the insulating structure 104 may have a substantially flat surface or a concave upper surface in the direction D2, and the portions of each word line 106 located above the isolation structure 102 and the insulating structure 104 may correspondingly have a substantially flat surface or a convex lower surface in the direction D2.

[0025] In addition, the portions of each active region 100 that do not intersect the word lines 106 are not limited to having an upper surface inclined along the direction D2. For example, these portions of each active region 100 may have an upper surface that is substantially flat, convex, or concave in the direction D2.

[0026] The above special structures of the active region 100 and the word line 106 are derived from the arrangement and manufacturing method of the active region 100. The manufacturing method of the active region 100 and the word line 106 will be described below.

[0027] Figure 2 is a flow chart of a method for manufacturing the active region 100 and the word line 106 according to some embodiments of the present disclosure. FIG. 3A to FIG. 3J yes Figure 2 Schematic cross-sectional view of the intermediate structure at each stage of the manufacturing process. Figure 3A , Figure 3C , Figure 3E , Figure 3G , Fig. 3I It is a cross section along an extension direction (direction D3 ) of an active region 100 . Figure 3B , Figure 3D , Figure 3F , Figure 3H , Figure 3J It is a cross section along the extending direction (direction D2 ) of the word line 106 .

[0028] Please refer to Figure 2 , Figure 3A and Figure 3B In step S200, an isolation structure 102 and an insulating structure 104 are formed in the semiconductor substrate 114, and an insulating liner 120 extending along the top surfaces of the semiconductor substrate 114, the isolation structure 102, and the insulating structure 104 is formed. Specifically, the isolation structure 102 may be first formed in the semiconductor substrate 114, and then the insulating structure 104 may be formed in the isolation structure 102. After performing a possible planarization process, an insulating liner 120 is formed on the semiconductor substrate 114, the isolation structure 102, and the insulating structure 104. The isolation structure 102 defines a plurality of active regions 100 in the semiconductor substrate 114. Figure 3B As shown, in the direction D2, the active regions 100 are arranged in pairs. For example, the active regions 100a and 100b in the same pair are adjacent to each other at a distance S1, and each pair of active regions 100 (e.g., active regions 100a and 100b) is separated from another pair of active regions 100 (e.g., a pair of active regions 100 including active region 100c or another pair of active regions 100 including active region 100d) by a distance S2 greater than the distance S1.

[0029] Please refer to Figure 2 , Figure 3C and Figure 3D In step S202, a mask pattern 300 is formed on the insulating liner 120. The mask pattern 300 has a plurality of openings W 300 These openings 300 The opening W is used to define a trench for accommodating the word line 106 in a subsequent step. 300 The position and width of the word line 106 are defined. Figure 3D FIG. 1 is a diagram showing a cross section along a word line 106 formed subsequently. Figure 3D Above the insulating liner 120 is a continuously extending opening W 300 (Indicated by dashed outlines) In some embodiments, the mask pattern 300 may be a hard mask, such as a hard mask made of diamond-like carbon (DLC).

[0030] Please refer to Figure 2 , Figure 3E and Figure 3F In step S204, a first etching process is performed using the mask pattern 300 as a mask. In this way, a plurality of trenches TR are formed that pass through the insulating liner 120 and enter the active region 100, the isolation structure 102, and the insulating structure 104. Figure 3E Some cross sections of trenches TR can be seen, and from Figure 3FA longitudinal section of a trench TR (indicated by a dotted outline) can be seen. By selecting an appropriate etchant, the first etching process is mainly performed on the isolation structure 102 and the insulating structure 104. As a result, the section of the trench TR passing through the isolation structure 102 and the insulating structure 104 is deeper than the section passing through the active area 100. By controlling the etching time, the section of each trench TR passing through each active area 100 can have a depth DP3, and the section of each trench TR passing through the isolation structure 102 and the insulating structure 104 can have a depth DP4 that is significantly greater than the depth DP3.

[0031] In addition, if Figure 3F As shown, a deep slit having a depth DP greater than the first distance S1 is formed between a pair of active regions 100 (for example, active regions 100a and 100b) adjacent to each other at a first distance S1 in the direction D2. On the other hand, a wide groove having a depth DP' greater than the first distance S1 and a width greater than the above-mentioned deep slit is formed between two pairs of active regions 100 separated by a second distance S2 in the direction D2 (for example, active regions 100a and 100b and a pair of active regions 100 including active region 100c or a pair of active regions 100 including active region 100d). In this way, each active region 100 is separated from the active regions 100 adjacent to each other on both sides by a deep slit and a wide groove in the direction D2. This will cause the portion of each active region 100 located below the trench TR passing through to be subsequently etched with an inclined surface. As an example, when the aspect ratio of the deep slit (the ratio of the depth DP to the first distance S1) is in the range of 1.5 to 2.5 and the aspect ratio of the wide groove (the ratio of the depth DP' to the second distance S2) is in the range of 0.6 to 1.2, the etching result can be caused. As another example, when the aspect ratio of the deep slit is controlled to be greater than 1.5 and the depth-width of the wide groove is less than 1.2, the etching result can be caused. It is worth mentioning that in one embodiment, the ratio of the depth DP of the deep slit to the depth DP' of the wide groove can be further controlled to be between 0.9 and 1 to cause the etching result.

[0032] In addition, below each trench TR (such as Figure 3F As shown in FIG. 1 , the active region 100 now protrudes relative to the isolation structure 102 and the insulation structure 104. Furthermore, when viewed along the direction D2, the portion of each active region 100 located below the trench TR through which it passes can now be trimmed into a convex surface with an arc shape. In other embodiments, when viewed along the direction D2, the portion of each active region 100 located below the trench TR through which it passes can also now be trimmed into other convex surfaces with bilaterally symmetrical shapes.

[0033] Please refer to Figure 2 , Figure 3G and Figure 3HAt step S206, the second etching process is performed using the mask pattern 300 as a mask. By selecting an appropriate etchant, the second etching process can be performed specifically on the active area 100. As a result, the depth of the section of each trench TR passing through the active area 100 increases, and the depth of the section close to each trench TR passing through the isolation structure 102 and the insulation structure 104 is approximately equal to or slightly greater than the reference depth. Figure 3E , Figure 3F Depth DP4 described.

[0034] As reference Figure 3F As described above, the portion of each active region 100 located under the trench TR is separated from the adjacent active regions 100 on both sides by a deep slit and a wide groove, respectively. This will cause the portion of each active region 100 located under the trench TR passing through to be etched with different etching amounts on the wide groove side and the deep slit side in the current step, resulting in an asymmetric structure. Figure 3H As shown, below each trench TR, the etching amount on the wide groove side of each active region 100 is greater than the etching amount on the deep slit side. As a result, the arc-shaped convex surface of the portion of each active region 100 located below the trench TR is trimmed into an inclined upper surface 100s that rises from the wide groove side to the deep slit side. In this way, each trench TR has a depth DP5 corresponding to the deep slit side of the underlying active region 100, and has a depth DP6 greater than the depth DP5 corresponding to the wide groove side of the opposite active region 100. In addition, in the direction D2, two adjacent active regions have inclined upper surfaces 100s with different inclined directions, and the inclined upper surfaces 100s of the two adjacent active regions 100 can be symmetrical relative to the central axis between each other.

[0035] Please refer to Figure 2 , Fig. 3I and Figure 3J In step S208, the third etching process is performed using the mask pattern 300 as a mask. By selecting an appropriate etchant, the third etching process can be performed specifically on the isolation structure 102 and the insulation structure 104. As a result, the depth of the section of each trench TR that passes through the isolation structure 102 and the insulation structure 104 increases, and has a greater depth than the reference etchant. Figure 3E , Figure 3G On the other hand, the depth of the section of each trench TR passing through the active area 100 remains substantially unchanged or slightly increased, that is, in reference to the depth DP4. Figure 3H The depth DP5 to the depth DP6 is in the range or slightly larger than this range. In this way, the difference in depth between the section of each trench TR passing through the isolation structure 102 and the insulation structure 104 and the section of each trench TR passing through the active area 100 is enlarged.

[0036] like Figure 3JAs shown, under each trench TR, each active region 100 now protrudes further relative to the isolation structure 102 and the insulation structure 104, and presents an appearance similar to the end of a utility knife. At this time, the deep slit side of the portion of each active region 100 located under the trench TR through which it passes protrudes from the isolation structure 102 at a greater height than the wide groove side, and the inclined upper surface 100s connects the deep slit side and the wide groove side.

[0037] After the third etching process is completed, the mask pattern 300 may be removed before proceeding to the next process step.

[0038] Please refer to Figure 2 , Figure 1B and Figure 1C Then, at step S210, a gate dielectric layer 118 is formed to selectively line the section of the trench TR that passes through the active region 100. In some embodiments, the gate dielectric layer 118 is selectively formed at the section of the trench TR that passes through the active region 100 by a thermal oxidation process. Next, at step S212, the word line 106 and the insulator plug 116 are filled in the trench TR.

[0039] At this point, the active region 100 and the word line 106 have been fabricated. Although not shown, other process steps are subsequently used to form structures such as the bit line contact structure 110, the capacitor contact structure 112, the bit line 108, and the storage capacitor on the semiconductor substrate 114.

[0040] In summary, the embodiment of the present disclosure provides a memory component and a manufacturing method thereof. The memory component is a DRAM, comprising a plurality of access transistors defined at the intersection of a plurality of active regions and a plurality of word lines, and a plurality of storage capacitors respectively connected to an access transistor. Along each word line, the active regions are arranged in pairs. The two active regions in the same pair are adjacent to each other at a first distance, and the two adjacent pairs of active regions are spaced apart from each other at a second distance greater than the first distance. In this way, the portion of each active region located below the word line through which it passes has a first side adjacent to an active region at a first distance, and has two sides spaced apart from another active region at a second distance. Based on this configuration and the control of the etching process, the portion of each active region located below the word line through which it passes is formed into an asymmetric structure similar to the end of a utility knife, and has an inclined upper surface climbing from the second side to the first side. In addition, under each word line, the two active regions adjacent to each other at the first distance are symmetrical relative to the central axis between the two, so that the inclined upper surfaces of the two active regions climb toward the central axis between the two. On the other hand, under each word line, two active regions spaced apart from each other by a second distance are also symmetrical with respect to the center axis therebetween, so that the inclined surfaces of the two active regions extend downward toward the center axis therebetween.

[0041] Based on this special structure, the access transistor exhibits a larger on-current and a smaller sub-threshold swing. Accordingly, the access transistor has a stronger driving force and better switching characteristics. In this way, the access to the storage capacitor can be effectively improved in the operation of the memory component.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory component, characterized in that: include: A plurality of active regions defined in a semiconductor substrate by an isolation structure, wherein the plurality of active regions are arranged in an array along a first direction and a second direction and extend respectively along a third direction intersecting the first direction and the second direction; as well as A plurality of word lines are formed in the semiconductor substrate and pass through the plurality of active regions along the second direction, The multiple active regions are arranged in pairs in the second direction, the active regions of the same pair are adjacent to each other at a first distance, and the active regions of two adjacent pairs are spaced apart from each other at a second distance greater than the first distance, and a characteristic portion of each active region located below at least one of the multiple word lines passing through has a first side adjacent to another active region of the same pair at the first distance and a second side spaced apart from the active region of the other pair at the second distance, and has an inclined upper surface climbing from the second side to the first side.

2. The memory component according to claim 1, characterized in that: The feature portion of each active region protrudes compared to a portion of the isolation structure located below the plurality of word lines.

3. The memory component according to claim 1, characterized in that: A plurality of first sections of the plurality of word lines passing through the plurality of active regions are smaller in depth than a plurality of second sections of the plurality of word lines passing through the isolation structure.

4. The memory component according to claim 3, characterized in that: The first section of each word line has a lower surface inclined in the second direction.

5. The memory component according to claim 1, characterized in that: The characteristic portion of each active region is an asymmetric structure.

6. The memory component according to claim 1, characterized in that: The characteristic portions of two adjacent active regions are symmetrical relative to the central axis therebetween.

7. A method for manufacturing a memory component, characterized in that: include: A plurality of active regions separated from each other are defined in a semiconductor substrate by an isolation structure, wherein the plurality of active regions are arranged in an array along a first direction and a second direction and extend respectively along a third direction intersecting the first direction and the second direction, the plurality of active regions are arranged in pairs along the second direction, the active regions of the same pair are adjacent to each other at a first distance, and the active regions of two adjacent pairs are spaced apart from each other at a second distance greater than the first distance; forming a mask pattern on the semiconductor substrate, wherein the mask pattern has a plurality of openings extending along the second direction; Performing a plurality of etching processes with the mask pattern as a mask to form a plurality of trenches passing through the isolation structure and the plurality of active regions, wherein after the plurality of etching processes, a feature portion of each active region located below at least one of the plurality of trenches passing through has a first side that is adjacent to another active region in the same pair at the first distance and a second side that is spaced apart from the active region of the other pair at the second distance, and has an inclined upper surface that rises from the second side to the first side; and A plurality of word lines are filled in the plurality of trenches.

8. The method for manufacturing a memory component according to claim 7, characterized in that: The multiple etching processes sequentially include a first etching process, a second etching process and a third etching process.

9. The method for manufacturing a memory component according to claim 8, characterized in that: The first etching process and the third etching process selectively etches the isolation structure, and the second etching process selectively etches the multiple active regions.

10. The method for manufacturing a memory component according to claim 9, characterized in that: As a result of the first etching process, deep slits with an aspect ratio of 1.5 to 2.5 are defined between the active regions of the same pair, and wide grooves with an aspect ratio of 0.6 to 1.2 are defined between two adjacent pairs of active regions.

11. The method for manufacturing a memory component according to claim 9, characterized in that: The second etching process etches the first side and the second side of the characteristic portion of each active region in different amounts, thereby forming the inclined upper surface.

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