Semiconductor device and method of manufacturing the same, electronic device

Abstract

The application discloses a semiconductor device and a preparation method thereof and electronic equipment. The semiconductor device comprises a substrate, a channel layer stack, a gate insulating layer, a surrounding gate and a source-drain functional part. The channel layer stack is formed on one side of the substrate and comprises a plurality of functional layer groups arranged at intervals along the thickness direction of the substrate. The functional layer group comprises a channel layer and at least one protective layer arranged in a stacked manner along the thickness direction of the substrate. The length direction of the functional layer group is perpendicular to the thickness direction of the substrate. The functional layer group comprises a first region, an intermediate region and a second region arranged along the length direction. The protective layer is located at least in the intermediate region, and the channel layer is located in the first region, the intermediate region and the second region. The gate insulating layer surrounds the intermediate region along the direction surrounding the length direction of the functional layer group. The surrounding gate surrounds the gate insulating layer along the direction surrounding the length direction of the functional layer group. The performance of the semiconductor device provided by the application is significantly improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and its preparation method, and an electronic device. Background Technology

[0002] In the application of high mobility semiconductor devices (such as germanium and silicon-germanium conductive channels), since the gate insulating layer (IL layer) is formed by oxidation, germanium oxide is formed during the oxidation process of the conductive channel material. Germanium oxide causes a sharp increase in the interface state density of the conductive channel, which leads to a decrease in the performance of the semiconductor device and severely limits the development of high mobility semiconductor devices. Summary of the Invention

[0003] The purpose of this application is to at least solve the problem of low performance in semiconductor devices. This purpose is achieved through the following technical solution:

[0004] The first aspect of this application discloses a semiconductor device comprising:

[0005] Substrate;

[0006] A channel layer stack is formed on one side of the substrate and includes a plurality of functional layer groups spaced apart along the thickness direction of the substrate. Each functional layer group includes a channel layer and at least one protective layer stacked along the thickness direction of the substrate. The length direction of the functional layer group is perpendicular to the thickness direction of the substrate. The functional layer group includes a first region, an intermediate region and a second region arranged along the length direction. The protective layer is located at least in the intermediate region, and the channel layer is located in the first region, the intermediate region and the second region.

[0007] A gate insulating layer that surrounds the intermediate region along the length direction of the functional layer group;

[0008] A surround gate, wherein the surround gate surrounds the gate insulating layer along the length direction of the functional layer group;

[0009] The source-drain functional section includes a source and a drain, which are located on opposite sides of the channel layer stack section along the length direction.

[0010] In the semiconductor device provided in this application, a protective layer is formed between the channel layer and the gate insulating layer. The protective layer can prevent oxidation of the channel layer surface during the formation of the gate insulating layer, thereby reducing the interface state density of the channel layer, reducing the subthreshold swing (SS) of the semiconductor device, thereby reducing the power consumption of the semiconductor device and improving the performance of the semiconductor device.

[0011] A second aspect of this application also provides a method for fabricating a semiconductor device, comprising:

[0012] Provide substrate;

[0013] A channel layer stack is formed on one side of the substrate. The channel layer stack includes a plurality of functional layer groups arranged at intervals along the thickness direction of the substrate. Each functional layer group includes a channel layer and at least one protective layer stacked along the thickness direction of the substrate. The length direction of the functional layer group is perpendicular to the thickness direction of the substrate. The functional layer group includes a first region, an intermediate region, and a second region arranged along the length direction. The protective layer is located at least in the intermediate region, and the channel layer is located in the first region, the intermediate region, and the second region.

[0014] A gate insulating layer is formed, the gate insulating layer surrounding the intermediate region along the length direction of the functional layer group;

[0015] A surrounding gate is formed, the surrounding gate surrounding the gate insulating layer along the length direction of the functional layer group;

[0016] A source-drain functional section is formed, the source-drain functional section including a source and a drain, the source and the drain being located on opposite sides of the channel layer stack along the length direction.

[0017] A third aspect of this application also provides an electronic device, including at least one semiconductor device provided in the first aspect of this application, and / or including at least one semiconductor device formed by the method for preparing the semiconductor device provided in the second aspect of this application. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0019] Figure 1 This is a partial structural schematic diagram of a semiconductor device provided in an embodiment of this application;

[0020] Figure 2 This is a partial structural schematic diagram of another semiconductor device provided in an embodiment of this application;

[0021] Figure 3 This is a partial structural schematic diagram of another semiconductor device provided in the embodiments of this application;

[0022] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;

[0023] Figure 5 This is a schematic diagram of the formation process of stacked epitaxy in a semiconductor device fabrication method provided in this application embodiment;

[0024] Figure 6 yes Figure 5 The main view;

[0025] Figure 7 This is a schematic diagram of the thinning process of a multilayer epitaxial layer in a method for fabricating a semiconductor device provided in this application embodiment;

[0026] Figure 8 This is a front view of a semiconductor device fabrication method provided in this application, during the formation of a dummy gate;

[0027] Figure 9 This is a cross-sectional view of the formation of the inner sidewall in a method for fabricating a semiconductor device according to an embodiment of this application;

[0028] Figure 10 This is a cross-sectional view of the formation of the inner sidewall in another method for fabricating a semiconductor device provided in this application embodiment;

[0029] Figure 11 This is a front view of the formation of the outer wall in a method for fabricating a semiconductor device according to an embodiment of this application;

[0030] Figure 12 This is a front view of a semiconductor device fabrication method provided in this application, during the partial removal of the epitaxial layer.

[0031] Figure 13 This is a front view of the process of forming the source and drain in a method for fabricating a semiconductor device according to an embodiment of this application;

[0032] Figure 14 This is a front view of the semiconductor device fabrication method provided in this application, during the formation of a dielectric layer;

[0033] Figure 15 This is a front view of the process of removing a dummy gate in a method for fabricating a semiconductor device according to an embodiment of this application;

[0034] Figure 16 This is a front view of a semiconductor device fabrication method provided in this application, during the formation of a surrounding gate.

[0035] The attached figures are labeled as follows:

[0036] 1. Semiconductor device; 11. Substrate; 12. Channel layer stack; 120. Functional layer group; 121. Channel layer; 122. Protective layer; x, length direction; A1. First region; A2. Middle region; A3. Second region; 13. Gate insulating layer; 14. All-around gate; 15. Source / drain functional section; 151. Source; 152. Drain; 16. Stacked epitaxial layer; 160. Layer group to be patterned; 161. Sacrificial layer; 162. Protective material layer; B1. Removal region; B2. Retention region; 17. Dummy gate; y, second direction; 18. Inner sidewall; Q, gap; 19. Outer sidewall; 20. Dielectric layer.

[0037] Detailed implementation method =

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0039] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0040] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or sub-regions, these elements, components, regions, layers, and / or sub-regions should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or sub-region from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or sub-region discussed below may be referred to as the second element, component, region, layer, or sub-region without departing from the teachings of the exemplary embodiments.

[0041] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented as "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0042] Research has revealed that in the application of high-mobility semiconductor devices (e.g., germanium or silicon-germanium conductive channels), the gate insulating layer (IL layer) is formed by oxidation. However, the oxidation process of the conductive channel material results in the formation of germanium oxide, which causes a sharp increase in the interface state density of the conductive channel. This leads to a deterioration in the subthreshold swing (SS) of the semiconductor device, resulting in a sharp increase in power consumption and a decrease in device performance. Current industry solutions for passivating high-mobility conductive channel interfaces primarily involve depositing aluminum oxide as a passivation layer after forming germanium oxide in the IL layer. However, this method introduces aluminum oxide as a passivation layer, which introduces a threshold shift problem influenced by Al, thus limiting its effectiveness in improving semiconductor device performance. Therefore, this application provides a semiconductor device and its fabrication method to further improve the performance of the semiconductor device.

[0043] like Figure 1 and Figure 2As shown, according to an embodiment of this application, a semiconductor device 1 is proposed, including a substrate 11, a channel layer stack 12, a gate insulating layer 13, a surrounding gate 14, and source / drain functional portions 15. The channel layer stack 12 is formed on one side of the substrate 11 and includes a plurality of functional layer groups 120 spaced apart along the thickness direction of the substrate 11. Each functional layer group 120 includes a channel layer 121 and at least one protective layer 122 stacked along the thickness direction of the substrate 11. The length direction x of the functional layer group 120 is perpendicular to the thickness direction of the substrate 11. The functional layer group 120 includes a first region A1, an intermediate region A2, and a second region A3 arranged along the length direction x. The protective layer 122 is located at least in the intermediate region A2, and the channel layer 121 is located in the first region A1, the intermediate region A2, and the second region A3. The gate insulating layer 13 surrounds the intermediate region A2 along the length direction x of the functional layer group 120. The surrounding gate 14 surrounds the gate insulating layer 13 along the length direction x of the functional layer group 120. The source-drain functional section 15 includes a source electrode 151 and a drain electrode 152, which are located on opposite sides of the channel layer stack section 12 along the length direction x.

[0044] In the semiconductor device 1 provided in this application, a protective layer 122 is formed between the channel layer 121 and the gate insulating layer 13. The protective layer 122 can prevent oxidation of the surface of the channel layer 121 during the formation of the gate insulating layer 13, thereby reducing the interface state density of the channel layer 121, reducing the subthreshold swing (SS) of the semiconductor device 1, thereby reducing the power consumption of the semiconductor device 1 and improving the performance of the semiconductor device 1.

[0045] Specifically, the semiconductor device 1 provided in this application includes a gate-all-around (GAA) transistor. The gate-all-around 14 surrounds the channel layer 121 along its length, thereby increasing the contact area between the gate-all-around 14 and the channel layer 121. This allows for better control of the current flowing through the channel, thereby reducing leakage current, improving efficiency, and reducing power consumption. The gate-all-around 14 and the gate insulating layer 13 only surround the intermediate region A2; therefore, the protective layer 122 is located at least in the intermediate region A2 to isolate the gate insulating layer 13 from the channel region. Figure 3 As shown, the protective layer 122 may also be located in the first region A1 and / or the second region A3, which is not specifically limited in this application.

[0046] Specifically, the channel layer 121 may include four sides along its length direction x in the circumferential direction. The four sides include a first surface and a second surface arranged along the thickness direction of the substrate 11, and a third surface and a fourth surface connected between the first surface and the second surface, with the third surface and the fourth surface disposed opposite to each other. The areas of the first surface and the second surface are larger than the areas of the third surface and the fourth surface. Furthermore, the first surface and the second surface are (100) surfaces, and the third surface and the fourth surface are (100) surfaces. The (100) surfaces have fewer atoms than the (110) surfaces, therefore the (100) surfaces are more easily oxidized.

[0047] In one feasible implementation, the number of protective layers 122 in the functional layer group 120 is two, and they are located on both sides of the channel layer 121 along the thickness direction of the substrate 11.

[0048] In the above embodiments, since the two surfaces of the channel layer 121 arranged along the thickness direction of the substrate 11, namely the first surface and the second surface, have large areas and are easily oxidized, two protective layers 122 can be provided in each functional layer group 120. One protective layer 122 contacts the first surface and at least covers the portion of the first surface located in the middle region A2, and the other protective layer 122 contacts the second surface and at least covers the portion of the second surface located in the middle region A2. This isolates the area of ​​the channel region surrounded by the gate insulating layer 13 from the gate insulating layer 13, thereby reducing the adverse effects on the channel region when the gate insulating layer 13 is formed, and thus improving the performance of the semiconductor device 1.

[0049] Specifically, since the third and fourth surfaces are (100) surfaces, they are not easily oxidized, and the areas of the third and fourth surfaces are relatively small, and the time for preparing the gate oxide layer is very short, the third and fourth surfaces do not need to be provided with the protective layer 122, thereby reducing the difficulty of preparation and reducing the preparation cost.

[0050] In another feasible implementation, to simplify the manufacturing process, a protective layer 122 may be formed only on the first or second surface of the channel layer 121.

[0051] In one possible implementation, the protective layer 122 is made of silicon.

[0052] In the above embodiments, the material of the gate insulating layer 13 may include silicon dioxide. Specifically, during the preparation of the gate insulating layer 13, ozone can be introduced into deionized water at room temperature after the protective layer 122 is prepared, and the time can be controlled to be 20 seconds.

[0053] In one feasible implementation, the thickness of the protective layer 122 ranges from 1 nm to 5 nm.

[0054] Specifically, the thickness of the protective layer 122 can be 1nm, 2nm, 3nm, 4nm, 5nm, etc.

[0055] If the protective layer 122 is too thin, it will easily cause protection failure. If the protective layer 122 is too thick, it will easily increase the thickness of the semiconductor device 1. Controlling the thickness of the protective layer 122 within the range of 1nm-5nm can achieve both protection effect and thinning of the semiconductor device 1.

[0056] In one feasible implementation, the channel layer 121 is made of germanium-silicon or germanium.

[0057] In the above embodiments, compared with the current mainstream silicon channel layer 121, the all-around gate transistor device with germanium silicon or germanium channel layer 121 can alleviate the impact of reduced stress engineering caused by miniaturization and the influence of changes in conductive crystal orientation on mobility, and further improve driving performance.

[0058] In one feasible implementation, the thickness of the channel layer 121 is 6 nm.

[0059] In the above embodiment, the thickness of the channel layer 121 is 6nm to meet the thickness requirements of the channel layer 121 of the 3nm node device.

[0060] This application also provides a method for fabricating semiconductor device 1, such as... Figure 5 As shown, it includes:

[0061] S200 provides substrate 11.

[0062] Specifically, the material of the substrate 11 may include a silicon substrate 11.

[0063] S400, a channel layer stack 12 is formed on one side of the substrate 11. The channel layer stack 12 includes a plurality of functional layer groups 120 arranged at intervals along the thickness direction of the substrate 11. Each functional layer group 120 includes a channel layer 121 and at least one protective layer 122 stacked along the thickness direction of the substrate 11. The length direction x of the functional layer group 120 is perpendicular to the thickness direction of the substrate 11. The functional layer group 120 includes a first region A1, an intermediate region A2 and a second region A3 arranged along the length direction x. The protective layer 122 is located at least in the intermediate region A2, and the channel layer 121 is located in the first region A1, the intermediate region A2 and the second region A3.

[0064] Specifically, adjacent functional layer groups 120 are spaced apart and provided with receiving spaces for accommodating the gate insulating layer 13 and the all-around gate 14.

[0065] S600, a gate insulating layer 13 is formed, which surrounds the intermediate region A2 along the length direction x of the functional layer group 120.

[0066] S800, a surrounding gate 14 is formed, which surrounds the gate insulating layer 13 along the length direction x surrounding the functional layer group 120.

[0067] S1000, a source-drain functional section 15 is formed. The source-drain functional section 15 includes a source electrode 151 and a drain electrode 152. The source electrode 151 and the drain electrode 152 are located on opposite sides of the channel layer stack section 12 along the length direction x.

[0068] Specifically, the channel layer 121 includes a first end and a second end along its length direction x. The first end is located in the first region A1, and the second end is located in the second region A3. One of the source electrode 151 and the drain electrode 152 can contact the end face of the first end, and the other can contact the end face of the second end, thereby realizing the connection between the source electrode 151, the drain electrode 152 and the channel layer 121.

[0069] Specifically, when semiconductor device 1 is a P-MOS transistor, the source 151 and drain 152 can be made of silicon-germanium; when semiconductor device 1 is an N-MOS transistor, the source 151 and drain 152 can be made of silicon. Other materials can also be used for the source 151 and drain 152, and this application does not impose any particular limitations on this.

[0070] In the above preparation method, the channel layer stack 12 is formed first, and then the gate insulating layer 13 is formed. During the formation of the channel layer stack 12, a protective layer 122 is formed on the surface of the channel layer 121 near and / or away from the substrate 11. During the subsequent formation of the gate insulating layer 13, under the protection of the protective layer 122, the surface of the channel layer 121 is not easily oxidized to form oxides, thereby reducing the interface state density of the channel layer 121, reducing the subthreshold swing (SS) of the semiconductor device 1, thereby reducing the power consumption of the semiconductor device 1 and improving the performance of the semiconductor device 1.

[0071] In one feasible embodiment, forming a channel layer stack 12 on one side of the substrate 11 includes:

[0072] S401, such as Figure 6 As shown, a stacked epitaxial layer 16 is formed on one side of the substrate 11. The stacked epitaxial layer 16 includes a plurality of channel layers 121 and a plurality of patterned layer groups 160 alternately arranged in a direction away from the substrate 11. The patterned layer group 160 includes a sacrificial layer 161 and at least one protective material layer 162 stacked in the thickness direction of the substrate 11.

[0073] Specifically, the patterned layer group 160 includes a sacrificial layer 161 and a protective material layer 162 located on the side of the sacrificial layer 161 close to and / or far from the substrate 11. When the sacrificial layer 161 is adjacent to the protective material layer 162 only on the side close to or far from the substrate 11, the arrangement order of the sacrificial layer 161 and the protective material layer 162 in different functional layer groups 120 can be interchanged, and this application does not impose any special limitation on this.

[0074] Specifically, the channel layer 121 is the channel layer 121 in the functional layer group 120, and the protective material layer 162 is used to form the protective layer 122. The protective material layer 162 is patterned to form the protective layer 122, or the protective material layer 162 is not patterned and is directly used as the protective layer 122.

[0075] S402, such as Figure 7 As shown, the two sides of the stacked epitaxial layer 16 along the first direction are thinned to form a removal region B1 and a retention region B2, the first direction being perpendicular to the thickness direction of the substrate 11.

[0076] Specifically, the two sides along the first direction in the epitaxial layer 16 represent the two sides located along the length direction x of the channel layer 121, where the two sides include a first side and a second side. The arrangement direction of the first side and the second side is perpendicular to the first direction and perpendicular to the thickness direction of the substrate 11. In the specific fabrication process, the epitaxial outer layer needs to be thinned from both sides respectively.

[0077] Specifically, while thinning the epitaxial layer 16, a shallow trench isolation structure can be formed on the substrate 11 simultaneously to achieve electrical isolation between adjacent structures within the semiconductor device 1.

[0078] S403, such as Figure 8 As shown, a dummy gate 17 is formed, which covers a portion of the two surfaces of the retention area B2 perpendicular to the second direction y, and also covers a portion of the one surface of the retention area B2 facing away from the substrate 11. The second direction y is perpendicular to the first direction and perpendicular to the thickness direction of the substrate 11.

[0079] Specifically, the dummy gate 17 is used to cover the location where the gate is to be formed, so as to avoid other film layers from affecting the location. On the one hand, it is convenient to fabricate, and on the other hand, it can improve the yield of subsequent fabrication of the all-around gate 14.

[0080] S404, such as Figure 9 and Figure 10As shown, forming inner sidewalls 18 and functional layer groups 120 includes removing at least the portion of the sacrificial layer 161 in the patterned layer group 160 located on both sides of the dummy grid 17 along the first direction to form a gap Q; forming inner sidewalls 18 within the gap Q; removing the dummy grid 17; and removing the portion of the sacrificial layer 161 located between two adjacent inner sidewalls 18 along the first direction to form a plurality of spaced functional layer groups 120.

[0081] Specifically, since the channel layer 121 and the patterned layer group 160 in the stacked epitaxial layer 16 are stacked in a direction away from the substrate 11 without any spacing, there is no position in the stacked epitaxial layer 16 for subsequently forming the all-around gate 14. It is necessary to remove the sacrificial layer 161 in the patterned layer group 160 to form a space for accommodating the all-around gate 14.

[0082] The removal of the sacrificial layer 161 can be performed in two steps. The first step involves removing portions of the sacrificial layer 161 located on both sides of the dummy gate 17 along the first direction to form a gap Q, within which an inner sidewall 18 is formed. The second step, after the dummy gate 17 is removed, involves removing the portion of the sacrificial layer 161 that was covered by the dummy gate 17 before its removal, to release the channel layer 121. At this time, the portion of the protective material layer 162 that was covered by the dummy gate 17 before its removal is retained, and a receiving space for accommodating the gate insulating layer 13 and the all-around gate 14 is formed at the original location of the sacrificial layer 161. This receiving space is located between adjacent channel layers 121. When the protective material layer 162 is provided on both the surface of the channel layer 121 near the substrate 11 and the surface away from the substrate 11, the aforementioned receiving space is located between adjacent protective material layers 162.

[0083] The inner wall 18 is used to block the etching liquid or etching gas used to etch the sacrificial layer 161 during the second removal of the sacrificial layer 161, that is, the removal of the part of the sacrificial layer 161 originally covered by the dummy gate 17, so as to prevent the etching liquid or etching gas from continuing to flow along the first direction and damaging the source 151 and the drain 152 after the sacrificial layer 161 is completely removed during the etching process.

[0084] After removing the sacrificial layer 161, the fabrication of the functional layer group 120 is completed. The functional layer group 120 includes a channel layer 121 and at least one protective layer 122 stacked along the thickness direction of the substrate 11. The length direction x of the functional layer group 120 is parallel to the first direction. The functional layer group 120 includes a first region A1, an intermediate region A2, and a second region A3 arranged along the first direction. The protective layer 122 is located at least in the intermediate region A2, and the channel layer 121 is located in the first region A1, the intermediate region A2, and the second region A3. The orthographic projection of the first region A1 and the second region A3 onto the substrate 11 coincides with the orthographic projection of the gap Q and the inner sidewall 18 onto the substrate 11. The orthographic projection of the intermediate region A2 onto the substrate 11 coincides with the orthographic projection of the accommodating space for accommodating the all-around gate 14 onto the substrate 11.

[0085] In the above embodiment, during the formation of the gap Q, only the portions of the sacrificial layer 161 located on both sides of the dummy gate 17 along the first direction in the patterned layer group 160 can be removed, and the protective material layer 162 is directly used as the protective layer 122 without etching. At this time, the protective layer 122 can be located in the first region A1, the intermediate region A2, and the second region A3.

[0086] In the above embodiment, during the formation of the gap Q, the portions of the protective material layer 162 in the patterned layer group 160 located on both sides of the dummy gate 17 along the first direction can also be removed simultaneously to form a protective layer 122. At this time, the protective layer 122 is located in the middle region A2.

[0087] In one feasible implementation, the patterned layer group 160 includes a sacrificial layer 161 and a protective material layer 162 stacked on both sides of the sacrificial layer 161 along the thickness direction of the substrate 11.

[0088] The above-described embodiments allow the channel layer 121 to have a protective layer 122 on both the side close to the substrate 11 and the side far from the substrate 11, thereby increasing the protection effect on the channel and further improving the performance of the device.

[0089] In one feasible implementation, the thickness of the sacrificial layer 161 ranges from 1 nm to 5 nm; and / or, the thickness of the protective material layer 162 ranges from 1 nm to 5 nm; and / or, the thickness of the channel layer 121 is 6 nm.

[0090] Specifically, the thickness of the sacrificial layer 161 can be 1nm, 2nm, 3nm, 4nm, 5nm, etc.

[0091] Specifically, the thickness of the protective material layer 162 can be 1nm, 2nm, 3nm, 4nm, 5nm, etc.

[0092] If the protective layer 122 is too thin, it will easily cause protection failure. If the protective layer 122 is too thick, it will easily increase the thickness of the semiconductor device 1. Controlling the thickness of the protective layer 122 within the range of 1nm-5nm can achieve both protection effect and thinning of the semiconductor device 1.

[0093] In the above embodiment, the thickness of the channel layer 121 is 6nm to meet the thickness requirements of the channel layer 121 of the 3nm node device.

[0094] In one feasible implementation, the material of the sacrificial layer 161 includes germanium, germanium silicon, and zirconium dioxide.

[0095] In the above embodiments, the sacrificial layer 161 is made of a material that has a similar crystal structure to the underlying film layer and can be epitaxially grown from it. Specifically, when the underlying material layer protects the material layer 162, the protective material layer 162 can be made of silicon, and the sacrificial layer 161 is made of a material that has a similar crystal structure to (100) silicon and can be epitaxially grown from it. Specifically, it can be one of germanium, germanium-silicon, or zirconium dioxide.

[0096] In one feasible implementation, the removal of the sacrificial layer 161 can be performed using either a dry etching process or a wet etching process.

[0097] Specifically, when the sacrificial layer 161 is made of silicon-germanium material, it can be removed by etching with a channel release solution. The channel etching solution is a mixture of acetic acid, hydrofluoric acid, and hydrogen peroxide.

[0098] In one feasible implementation, such as Figure 11 As shown, after forming the dummy grid 17 and before forming the inner sidewall 18, the outer sidewall 19 is also formed. Specifically, the outer sidewall 19 is formed on both sides of the dummy grid 17 that are opposite to each other along the first direction, and the inner sidewall 18 exposes the two ends of the stacked extension 16 arranged along the first direction.

[0099] In the above embodiments, the position of the surrounding gate 14 after the dummy gate 17 is subsequently removed can be defined by forming the outer wall 19.

[0100] It also includes, such as Figure 12 As shown, the two ends of the epitaxial stack exposed along the first direction via the outer sidewall 19 are removed to form source and drain regions located on both sides of the epitaxial layer 16 arranged along the first direction. This facilitates subsequent contact between the source electrode 151 and the drain electrode 152 and the first region A1 and the second region A3, respectively. In one feasible embodiment, the step of forming the inner sidewall 18 within the gap Q includes:

[0101] An inner sidewall material layer is deposited, and the orthogonal projection of the inner sidewall material layer on the substrate 11 covers the dummy gate 17, the outer wall 19, the source region, and the drain region. The inner sidewall material layer wraps the outer wall 19 on the side surface opposite to the dummy gate 17, and the inner sidewall material layer fills the gap Q.

[0102] Pattern the inner wall material layer and remove the portions of the inner wall material layer located in the source and leak areas.

[0103] In the above embodiments, the inner wall material layer and the outer wall 19 can be made of the same material, both of which are silicon nitride.

[0104] The inner sidewall material layer prepared by deposition is then etched to form the inner sidewall 18. In this process, the portion of the inner sidewall material layer except for the portion located in the gap Q needs to be removed to expose the outer sidewall 19, the dummy gate 17, the source region, and the drain region, so as to facilitate the preparation of subsequent film layers.

[0105] In one feasible implementation, such as Figure 13 As shown, it also includes forming a source electrode 151 and a drain electrode 152 in the source region and the drain region, respectively, with the source electrode 151 and the drain electrode 152 contacting the two ends of the channel layer 121 along the first direction.

[0106] In the above embodiments, when forming the source 151 and the drain 152, the source 151 epitaxial layer and the drain 152 epitaxial layer can be formed first, and then the source 151 epitaxial layer and the drain 152 epitaxial layer can be doped to form the source 151 and the drain 152.

[0107] In one feasible implementation, it further includes:

[0108] like Figure 14 As shown, a dielectric layer 20 is formed, which covers the source 151, drain 152, inner sidewall 18 and dummy gate 17.

[0109] In the above embodiment, the dielectric layer 20 is used to planarize the top of the semiconductor device 1. During the fabrication process, a dielectric material layer can be deposited first, and then the side of the dielectric material layer facing away from the substrate 11 can be polished by a chemical mechanical polishing process.

[0110] In the above embodiments, such as Figure 15 As shown, after forming the dielectric layer 20, the dummy gate 17 is removed, as follows: Figure 16 As shown, after removing the dummy gate 17, the sacrificial layer 161 is removed, and the gate insulating layer 13 and the all-around gate 14 are formed. When removing the dummy gate 17, the portion of the dielectric layer 20 located on the side of the dummy gate 17 facing away from the substrate 11 is removed simultaneously.

[0111] This application also provides an electronic device, which includes at least one semiconductor device 1 provided in the above embodiments, and / or includes at least one semiconductor device 1 formed by the preparation method of the semiconductor device 1 provided in the above embodiments.

[0112] The performance of semiconductor devices in this electronic device is significantly improved, thereby significantly enhancing the overall performance of the electronic device and improving the user experience.

[0113] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A channel layer stack is formed on one side of the substrate and includes a plurality of functional layer groups spaced apart along the thickness direction of the substrate. Each functional layer group includes a channel layer and at least one protective layer stacked along the thickness direction of the substrate. The length direction of the functional layer group is perpendicular to the thickness direction of the substrate. The functional layer group includes a first region, an intermediate region and a second region arranged along the length direction. The protective layer is located at least in the intermediate region, and the channel layer is located in the first region, the intermediate region and the second region. A gate insulating layer that surrounds the intermediate region along the length direction of the functional layer group; A surround gate, wherein the surround gate surrounds the gate insulating layer along the length direction of the functional layer group; The source-drain functional unit includes a source and a drain, which are located on opposite sides of the channel layer stack along the length direction; The protective layer is used to isolate the gate insulating layer from the channel region.

2. The semiconductor device according to claim 1, characterized in that, In the functional layer group, there are two protective layers, which are located on both sides of the channel layer along the thickness direction of the substrate.

3. The semiconductor device according to claim 1, characterized in that, The channel layer is made of germanium-silicon or germanium, and / or the protective layer is made of silicon.

4. The semiconductor device according to claim 1, characterized in that, The thickness of the protective layer ranges from 1 nm to 5 nm; the thickness of the channel layer is 6 nm.

5. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A channel layer stack is formed on one side of the substrate. The channel layer stack includes a plurality of functional layer groups arranged at intervals along the thickness direction of the substrate. Each functional layer group includes a channel layer and at least one protective layer stacked along the thickness direction of the substrate. The length direction of the functional layer group is perpendicular to the thickness direction of the substrate. The functional layer group includes a first region, an intermediate region, and a second region arranged along the length direction. The protective layer is located at least in the intermediate region, and the channel layer is located in the first region, the intermediate region, and the second region. A gate insulating layer is formed, the gate insulating layer surrounding the intermediate region along the length direction of the functional layer group; A surrounding gate is formed, the surrounding gate surrounding the gate insulating layer along the length direction of the functional layer group; A source-drain functional section is formed, the source-drain functional section including a source and a drain, the source and the drain being located on opposite sides of the channel layer stack section along the length direction; The protective layer is used to isolate the gate insulating layer from the channel region.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The trench layer stack formed on one side of the substrate includes: A stacked epitaxial layer is formed on one side of the substrate. The stacked epitaxial layer includes a plurality of channel layers and a plurality of patterned layer groups alternately arranged in a direction away from the substrate. The patterned layer group includes a sacrificial layer and at least one protective material layer stacked in the thickness direction of the substrate. The epitaxial layer is thinned on both sides along a first direction to form a removal region and a retention region, wherein the first direction is perpendicular to the thickness direction of the substrate; A dummy gate is formed, which covers portions of the two surfaces of the retained area perpendicular to the second direction and a portion of the surface of the retained area facing away from the substrate. The second direction is perpendicular to the first direction and perpendicular to the thickness direction of the substrate. Forming inner walls and the functional layer groups includes removing portions of at least the sacrificial layer in the layer group to be patterned located on both sides of the dummy grid along the first direction to form gaps; forming inner walls within the gaps; removing the dummy grids; and removing portions of the sacrificial layer located between two adjacent inner walls along the first direction to form a plurality of the functional layer groups spaced apart.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The patterned layer group includes a sacrificial layer and a protective material layer stacked on both sides of the sacrificial layer along the thickness direction of the substrate.

8. The method for fabricating a semiconductor device according to claim 6, characterized in that, The thickness of the sacrificial layer is in the range of 1 nm to 5 nm; and / or the thickness of the protective material layer is in the range of 1 nm to 5 nm; and / or the thickness of the channel layer is 6 nm.

9. The method for fabricating a semiconductor device according to claim 6, characterized in that, The sacrificial layer is made of one of germanium, germanium silicon, or zirconium dioxide.

10. The method for fabricating a semiconductor device according to claim 6, characterized in that, The process includes forming an outer wall after forming the dummy grid and before forming the inner wall, specifically including forming outer walls on opposite sides of the dummy grid along the first direction, wherein the inner wall exposes the two ends of the stacked extensions arranged along the first direction; It also includes removing the two ends of the epitaxial stack that are exposed along the first direction through the outer wall to form source and drain regions located on both sides of the epitaxial stack arranged along the first direction.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The step of forming an inner wall within the gap includes: An inner sidewall material layer is deposited, the orthographic projection of the inner sidewall material layer on the substrate covering the dummy gate and the outer wall, as well as the source region and the drain region, wherein the inner sidewall material layer wraps the side surface of the outer wall facing away from the dummy gate, and the inner sidewall material layer fills the gap; The inner wall material layer is patterned, and the portions of the inner wall material layer located in the source area and the drain area are removed.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, It also includes forming a source and a drain in the source region and the drain region, respectively, with the source and drain contacting the two ends of the channel layer along the first direction.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, Also includes: A dielectric layer is formed, which covers the source, the drain, the inner wall, and the dummy gate.

14. An electronic device, characterized in that, The electronic device includes at least one semiconductor device as described in any one of claims 1 to 4, and / or includes at least one semiconductor device formed by the method for preparing a semiconductor device as described in any one of claims 5 to 13.

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