A device with a multi-potential-field plate structure and a preparation method thereof

Abstract

The present invention discloses a device with a multi-potential field plate structure and a preparation method thereof. The method comprises the following steps: preparing a basic structure and etching on the second dielectric layer of the basic structure to form a gate electrode hole; depositing and etching n layers of metal in the gate electrode hole to form n layers of field plate metal; among the n layers of field plate metal, the coefficient of thermal expansion of each layer of field plate metal gradually increases from the nth layer to the second layer; etching the end of the first layer of field plate metal; annealing the n layers of field plate metal to warp the ends of the field plate metal from the nth layer to the second layer away from the second dielectric layer; growing a third dielectric layer on the second dielectric layer and etching away the redundant third dielectric layer to form a field plate, thus obtaining the device. The preparation method of the present invention simplifies the process while preparing a device with a multi-potential field plate structure, and can effectively control the potential difference between the field plate and the two-dimensional electron gas below.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a device including a multi-potential field plate and a preparation method of the device. Background Art

[0002] At present, for the single field plate structure of the planar channel structure of AlGaN / GaN HEMT, the field plates used are gate field plates and source field plates. However, since the potential of the field plate is equal to the gate potential or the source potential, a large potential difference will be formed between the field plate and the two-dimensional electron gas below the field plate, which is the main reason for device failure. The main problems are as follows: The dielectric layer is prone to reliability failure under high electric field strength, and at the same time, the high electric field strength causes the dielectric layer to capture charges, resulting in an increase in dynamic resistance.

[0003] To solve the above problems, a HEMT (High Electron Mobility Transistor) device with a multi-potential field plate structure is proposed, which can effectively control the potential difference between the field plate and the two-dimensional electron gas below, and solve the problems of dielectric layer breakdown reliability failure caused by high electric field and the problem of dielectric layer charge capture caused by high electric field strength. However, the planar channel structure of AlGaN / GaN HEMT introduces a multi-field plate structure from a single field plate structure, which causes many problems: In order to form a gradient multi-field plate, an additional 5 to 8 process steps are added, increasing the process complexity and processing cost; at the same time, too many process steps increase the risk of introducing defects in the manufacturing process, which is not conducive to the reliability of the device. Summary of the Invention

[0004] In view of this, in order to overcome the defects of the prior art, the purpose of the present invention is to provide a device with a multi-potential field plate structure and a preparation method thereof, which can prepare a device with a multi-potential field plate while avoiding too many process steps.

[0005] To achieve the above purpose, the present invention provides a preparation method of a device with a multi-potential field plate structure, including the following steps:

[0006] Prepare a basic structure and etch the second dielectric layer of the basic structure to form a gate electrode hole;

[0007] Deposit and etch n layers of metal in the gate electrode hole to form n layers of field plate metals, where n is a positive integer greater than or equal to 3; among the n layers of field plate metals, the thermal expansion coefficient of each layer of field plate metal gradually increases from the nth layer to the second layer; ensure that the field plate metals from the second layer to the nth layer can warp upward (away from the second dielectric layer) during annealing treatment;

[0008] Etch the end of the first layer of field plate metal so that the first layer of field plate metal is recessed inward relative to the field plate metals from the nth layer to the second layer, thereby forming a first notch;

[0009] Anneal the n-layer field plate metal so that the ends of the field plate metals from the nth layer to the second layer, which are located above the first notch, warp away from the second dielectric layer;

[0010] Grow a third dielectric layer on the second dielectric layer. The third dielectric layer is also formed in the first notch and below the warped part, and the excess third dielectric layer is etched away to form a field plate, obtaining the device with the multi-potential field plate structure.

[0011] In the present invention, n layers of metal are deposited in the gate electrode hole and n-layer field plate metals are obtained through etching. After etching the end of the first-layer field plate metal at the bottom, through one annealing treatment, the ends of the field plate metals from the second layer to the nth layer above the first-layer field plate metal can be directly warped away from the second dielectric layer simultaneously to form an electric field gradient field plate. Finally, a device with a multi-potential field plate structure is obtained. Compared with the manufacturing process of the device with the traditional multi-potential field plate structure, the preparation method of the present invention can effectively reduce the process steps while preparing a device with a multi-potential field plate structure, thereby effectively controlling the potential difference between the field plate and the two-dimensional electron gas below, and avoiding the problem of introducing defect risks caused by numerous process steps, which is beneficial to the reliability of the device.

[0012] According to some preferred implementation aspects of the present invention, the method for etching the end of the first-layer field plate metal is wet etching, and the first-layer field plate metal is a metal soluble in an alkaline solution.

[0013] According to some preferred implementation aspects of the present invention, in the step of depositing and etching n layers of metal in the gate electrode hole to form n-layer field plate metals, the lengths of each layer of field plate metal in the n layers of field plate metals are the same.

[0014] According to some preferred implementation aspects of the present invention, the method for etching the end of the first-layer field plate metal includes the following steps:

[0015] Apply photoresist to one end of the first-layer field plate metal, and then use an alkaline solution to corrode the other end of the first-layer field plate metal, so that a first notch is formed at the other end of the first-layer field plate metal.

[0016] According to some preferred implementation aspects of the present invention, the method for etching the end of the first-layer field plate metal includes the following steps:

[0017] First, apply photoresist to one end of the first-layer field plate metal, and use an alkaline solution to etch the other end of the first-layer field plate metal, so that a first notch is formed at the other end of the first-layer field plate metal; then apply photoresist to the end of the first-layer field plate metal with the first notch, and use an alkaline solution to etch the end of the first-layer field plate metal away from the first notch, so that a second notch is formed at the end of the first-layer field plate metal away from the first notch.

[0018] According to some preferred embodiments of the present invention, the method for etching the end of the first-layer field plate metal includes the following steps:

[0019] Use an alkaline solution to etch both ends of the first-layer field plate metal simultaneously, so that a first notch and a second notch are respectively formed at both ends of the first-layer field plate metal.

[0020] According to some preferred embodiments of the present invention, the length of the first notch is the same as or different from the length of the second notch.

[0021] According to some preferred embodiments of the present invention, the bottom surface of the end of the second-layer field plate metal close to the first notch is a first inclined surface, and the included angle between the first inclined surface and the top surface of the second dielectric layer is 10° to 20°.

[0022] According to some preferred embodiments of the present invention, the bottom surface of the end of the second-layer field plate metal close to the first notch is an arc surface, and the central angle of the arc surface is 20° to 40°.

[0023] According to some preferred embodiments of the present invention, the bottom surface of the end of the second-layer field plate metal close to the first notch is a first inclined surface, and the bottom surface of the end of the second-layer field plate metal close to the second notch is a second inclined surface. The included angle between the first inclined surface and the top surface of the second dielectric layer is 10° to 20°, and the included angle between the second inclined surface and the top surface of the second dielectric layer is 10° to 20°.

[0024] According to some preferred embodiments of the present invention, the bottom surface of the second-layer field plate metal is an arc surface, and the central angle of the arc surface is 20° to 40°.

[0025] According to some preferred embodiments of the present invention, the length of the remaining field plate metal after etching the end of the first-layer field plate metal accounts for 40% to 50% of the length of the first-layer field plate metal before etching the end. So that the area of the positive projection of the first notch or the first notch and the second notch on the second dielectric layer accounts for a percentage greater than or equal to 50% of the area of the positive projection of the second-layer field plate metal to the nth-layer field plate metal on the second dielectric layer.

[0026] According to some preferred implementation aspects of the present invention, in the step of annealing the n-layer field plate metal, the annealing temperature is 380-500 °C.

[0027] According to some preferred implementation aspects of the present invention, the basic structure sequentially includes a substrate, an epitaxial layer, a first dielectric layer, and a second dielectric layer from bottom to top.

[0028] According to some preferred implementation aspects of the present invention, the method for preparing the basic structure includes: performing nitride epitaxial growth on the substrate to form an epitaxial layer structure, and sequentially growing a first dielectric layer and a second dielectric layer on the epitaxial layer;

[0029] Etching is performed on the epitaxial layer, the first dielectric layer, and the second dielectric layer to form source electrode holes and drain electrode holes, metal deposition and etching are performed in the source electrode holes and drain electrode holes, and then annealing is performed to form an ohmic contact, and a source electrode and a drain electrode are respectively formed.

[0030] The present invention also provides a device with a multi-potential field plate structure prepared by the above preparation method.

[0031] Due to the adoption of the above technical solutions, compared with the prior art, the advantages of the present invention are as follows: In the preparation method of the device with a multi-potential field plate structure of the present invention, after depositing n-layer metal in the gate electrode hole and etching, n-layer field plate metal is obtained. After etching the end of the first layer of field plate metal at the bottom, through a single annealing treatment, the ends of the second to nth layers of field plate metal above the first layer of field plate metal can be directly warped away from the second dielectric layer to form an electric field gradient field plate, and finally a device with a multi-potential field plate structure is obtained. Compared with the manufacturing process of the device with a traditional multi-potential field plate structure, the preparation method of the present invention can effectively reduce the process steps while preparing a device with a multi-potential field plate structure, thereby effectively controlling the potential difference between the field plate and the two-dimensional electron gas below, and avoiding the problem of introducing defect risks caused by numerous process steps, which is beneficial to the reliability of the device. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0033] Figure 1 It is a cross-sectional schematic diagram after forming the epitaxial layer in the preparation method of the device in Embodiments 1 to 4 of the present invention;

[0034] Figure 2Schematic cross-sectional view after forming the first dielectric layer in the device preparation methods of Embodiments 1 to 4 of the present invention;

[0035] Figure 3 Schematic cross-sectional view after forming the second dielectric layer in the device preparation methods of Embodiments 1 to 4 of the present invention;

[0036] Figure 4 Schematic cross-sectional view after forming source electrode holes and drain electrode holes in the device preparation methods of Embodiments 1 to 4 of the present invention;

[0037] Figure 5 Schematic cross-sectional view after forming source electrodes and drain electrodes in the device preparation methods of Embodiments 1 to 4 of the present invention;

[0038] Figure 6 Schematic cross-sectional view after forming gate electrode holes in the device preparation methods of Embodiments 1 to 3 of the present invention;

[0039] Figure 7 Schematic cross-sectional view after forming three-layer field plate metals in the device preparation methods of Embodiments 1 and 2 of the present invention;

[0040] Figure 8 Schematic cross-sectional view after forming the first notch in the device preparation methods of Embodiments 1 and 2 of the present invention;

[0041] Figure 9 Schematic cross-sectional view after one end of the third-layer field plate metal and one end of the second-layer field plate metal are warped upward in the device preparation method of Embodiment 1 of the present invention;

[0042] Figure 10 Schematic cross-sectional structure view of the device with a multi-potential field plate structure in Embodiment 1 of the present invention;

[0043] Figure 11 Schematic cross-sectional structure view after one end of the third-layer field plate metal and one end of the second-layer field plate metal are warped upward in the device preparation method of Embodiment 2 of the present invention;

[0044] Figure 12 Schematic cross-sectional structure view of the device with a multi-potential field plate structure in Embodiment 2 of the present invention;

[0045] Figure 13 Schematic cross-sectional view after forming the first notch and the second notch in the device preparation method of Embodiment 3 of the present invention;

[0046] Figure 14 Schematic cross-sectional view after one end of the third-layer field plate metal and both ends of the second-layer field plate metal are warped upward in the device preparation method of Embodiment 3 of the present invention;

[0047] Figure 15 It is a schematic cross-sectional structure diagram of the device with a multi-potential field plate structure in Embodiment 3 of the present invention;

[0048] Figure 16 It is a schematic cross-sectional view after forming a gate electrode hole in the device manufacturing method of Embodiment 4 of the present invention;

[0049] Figure 17 It is a schematic cross-sectional view after forming three-layer field plate metal in the device manufacturing method of Embodiment 4 of the present invention;

[0050] Figure 18 It is a schematic cross-sectional view after forming a first notch and a second notch in the device manufacturing method of Embodiment 4 of the present invention;

[0051] Figure 19 It is a schematic cross-sectional view after one end of the third-layer field plate metal and both ends of the second-layer field plate metal warp upward in the device manufacturing method of Embodiment 4 of the present invention;

[0052] Figure 20 It is a schematic cross-sectional structure diagram of the device with a multi-potential field plate structure in Embodiment 4 of the present invention;

[0053] In the drawings, substrate - 1, epitaxial layer - 2, drain electrode hole - 21, source electrode hole - 22, drain electrode - 3, source electrode - 4, first dielectric layer - 5, second dielectric layer - 6, gate electrode hole - 61, third dielectric layer - 7, first-layer field plate metal - 81, second-layer field plate metal - 82, third-layer field plate metal - 83, first notch - Q1, second notch - Q2. Detailed implementation manners

[0054] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0055] The manufacturing method of the device with a multi-potential field plate structure of the present invention includes the following steps:

[0056] Step 1: Select a conductive material as the substrate 1. Perform nitride epitaxial growth on the substrate 1 to successively form a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The nitride includes Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, etc. The nucleation layer, the buffer layer, the channel layer, and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer and the barrier layer, generating a conductive channel.

[0057] The substrate 1 is one or a combination of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, germanium, or any other material capable of growing Group III nitride materials.

[0058] Step 2: Deposit on the epitaxial layer 2 a combination of one or more of SiN, SiO 2 , SiON, Al 2 O 3 to form a first dielectric layer 5 for controlling the high-concentration two-dimensional electron gas channel.

[0059] Step 3: Deposit on the first dielectric layer 5 a combination of one or more of SiN, SiO 2 , SiON, Al 2 O 3 to form a second dielectric layer 6 for protecting the first dielectric layer 5 from process damage.

[0060] Step 4: Perform etching on the epitaxial layer 2, the first dielectric layer 5, and the second dielectric layer 6 to form a source electrode hole 22 and a drain electrode hole 21. Perform ohmic metal deposition and etching in the source electrode hole 22 and the drain electrode hole 21. The metal includes a combination of one or more of Ti, Al, TiN, Au, AlCu, AlSiCu, W to form an ohmic metal layer, and then perform annealing to form an ohmic contact, respectively forming a source electrode 4 and a drain electrode 3.

[0061] Step 5: Perform etching on the second dielectric layer 6 to form a gate electrode hole 61.

[0062] Step 6: Deposit an n-layer metal in the gate electrode hole 61 and etch away the excess metal to form an n-layer field plate metal, where n is a positive integer greater than or equal to 3; in the n-layer field plate metal, the thermal expansion coefficient of each layer of the field plate metal gradually increases from the nth layer to the second layer.

[0063] Step 7: Perform wet etching on the end of the first layer of the n-layer field plate metal 81 to form a first notch Q1 and / or a second notch Q2.

[0064] Step 8: Anneal the n-layer field plate metal so that the ends of the nth-layer field plate metal to the second-layer field plate metal 82 warp away from the second dielectric layer 6. The annealing temperature is 380 - 500 °C.

[0065] Step 9: Grow on the second dielectric layer 6 one or more combinations including SiN, SiO 2 , SiON, Al 2 O 3 to form a third dielectric layer 7, and etch away the excess third dielectric layer 7 to form a field plate, obtaining a device with a multi-potential field plate structure. Among them, the n-layer field plate metal serves as the conductive region, and the first dielectric layer 5, the second dielectric layer 6, and the third dielectric layer 7 serve as the electric field distribution regions. The n-layer field plate metal and the first dielectric layer 5, the second dielectric layer 6, and the third dielectric layer 7 located directly below it together form a field plate.

[0066] The device with a multi-potential multi-field plate structure of the present invention includes a drain electrode 3, a source electrode 4, an n-layer field plate metal, and a substrate 1, an epitaxial layer 2, a first dielectric layer 5, a second dielectric layer 6, and a third dielectric layer 7 arranged in sequence from bottom to top. Both the drain electrode 3 and the source electrode 4 are located in the epitaxial layer 2, the first dielectric layer 5, the second dielectric layer 6, and the third dielectric layer 7. The n-layer field plate metal is located in the second dielectric layer 6 and the third dielectric layer 7. The n-layer field plate metal is all located above the second dielectric layer 6. The n-layer field plate metal and the first dielectric layer 5, the second dielectric layer 6, and the third dielectric layer 7 located directly below it together form a field plate structure; the field plate forms an electric field gradient from bottom to top. Among the n-layer field plate metals, the length of the first-layer field plate metal 81 is less than the lengths of the remaining other layer field plate metals, and the first-layer field plate metal 81 is parallel to the second dielectric layer 6.

[0067] Further, one end of the first-layer field plate metal 81 in the n-layer field plate metal has a first notch Q1. The ends of the second to the nth-layer field plate metals close to the first notch Q1 are all inclined upward. The bottom surface of the end of the second-layer field plate metal 82 close to the first notch Q1 is a first inclined surface, and the angle between the first inclined surface and the top surface of the second dielectric layer 6 is 10° - 20°.

[0068] Further, one end of the first-layer field plate metal 81 in the n-layer field plate metal has a first notch Q1. The ends of the second-layer field plate metal 82 to the nth-layer field plate metals close to the first notch Q1 all form a concave arc. The bottom surface of the end of the second-layer field plate metal 82 close to the first notch Q1 is an arc surface, and the central angle of the arc surface is 20° - 40°.

[0069] Further, one end of the first field plate metal 81 in the n-layer field plate metals has a first notch Q1, and the other end has a second notch Q2. The ends of the second field plate metal 82 to the n-layer field plate metals close to the first notch Q1 are all inclined upward. The bottom surface of the end of the second field plate metal 82 close to the first notch Q1 is a first inclined surface, and the included angle between the first inclined surface and the top surface of the second dielectric layer 6 is 10° to 20°. The ends of the second field plate metal 82 to the n-layer field plate metals close to the second notch Q2 are also all inclined upward. The bottom surface of the end of the second field plate metal 82 close to the second notch Q2 is a second inclined surface, and the included angle between the second inclined surface and the top surface of the second dielectric layer 6 is 10° to 20°. Wherein, the length of the first notch Q1 is the same as or different from the length of the second notch Q2. When the length of the first notch Q1 is equal to the length of the second notch Q2, the included angles formed by the first inclined surface and the second inclined surface with the top surface of the second dielectric layer 6 are equal.

[0070] Further, one end of the first field plate metal 81 in the n-layer field plate metals has a first notch Q1, and the other end has a second notch Q2. The second field plate metal 82 to the n-layer field plate metals integrally form a concave arc shape. The bottom surface of the second field plate metal 82 is an arc surface, and the central angle of the arc surface is 20° to 40°.

[0071] Preparation method of a device with a multi-potential field plate structure in Embodiment 1

[0072] This embodiment provides a preparation method of a device with a multi-potential field plate structure, which specifically includes the following steps:

[0073] Step 1: As shown in Figure 1 , select silicon as the substrate 1 for nitride epitaxial growth, and sequentially form a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The nitride is GaN. The nucleation layer, the buffer layer, the channel layer, and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0074] Step 2: Deposit SiN on the epitaxial layer 2 by MOCVD (Metal Organic Chemical Vapor Deposition) method to form a first dielectric layer 5, as shown in Figure 2 , for controlling the high-concentration two-dimensional electron gas channel.

[0075] Step 3: Deposit SiO 2 on the first dielectric layer 5 to form a second dielectric layer 6, as shown in Figure 3 , for protecting the first dielectric layer 5 from process damage.

[0076] Step 4: Etch the epitaxial layer 2, the first dielectric layer 5, and the second dielectric layer 6, as shown in Figure 4As shown, source electrode holes 22 and drain electrode holes 21 are formed, ohmic metal deposition and etching are carried out in the source electrode holes 22 and the drain electrode holes 21, and then annealing is performed to form ohmic contacts, and a source electrode 4 and a drain electrode 3 are respectively formed, as Figure 5 shown.

[0077] Step Five: Etching is carried out on the second dielectric layer 6 to form a gate electrode hole 61, as Figure 6 shown.

[0078] Step Six: Three layers of metal are deposited in the gate electrode hole 61 and the excess metal is etched away to form three-layer field plate metal, as Figure 7 shown. The three-layer field plate metal is stacked in sequence. From bottom to top, they are: the first-layer field plate metal 81, the second-layer field plate metal 82, and the third-layer field plate metal 83.

[0079] Among them, the thermal expansion coefficient of the third-layer field plate metal 83 is less than that of the second-layer field plate metal 82. The thermal expansion coefficient of the third-layer field plate metal 83 is 0 to 15×10 -6 / °C, preferably 4×10 -6 to 11×10 -6 / °C; the thermal expansion coefficient of the second-layer field plate metal 82 is 20×10 -6 to 40×10 -6 / °C, preferably 20×10 -6 to 25×10 -6 / °C.

[0080] In this embodiment, the third-layer field plate metal 83 is tungsten, with a thermal expansion coefficient of 4.5×10 -6 / °C, a thickness of 100 nm, and a length of 10 μm; the second-layer field plate metal 82 is an aluminum-copper alloy, with a thermal expansion coefficient of 20×10 -6 / °C, a thickness of 100 nm, and a length of 10 μm; the first-layer field plate metal 81 is aluminum, with a thickness of 200 nm and a length of 10 μm.

[0081] Step Seven: A photoresist is applied to one end of the first-layer field plate metal 81 in the three-layer field plate metal, and then the other end of the first-layer field plate metal 81 is etched using the alkaline solution tetramethylammonium hydroxide, so that a first notch Q1 is formed at the other end of the first-layer field plate metal 81, as Figure 8 shown. In this embodiment, the length of the remaining field plate metal at the end of the first-layer field plate metal 81 after etching accounts for 40% of the length of the first-layer field plate metal 81 before etching at the end.

[0082] At the position where there is photoresist, ions cannot penetrate the photoresist, so the structure of one end of the first-layer field plate metal 81 will not be damaged, thus playing a protective role.

[0083] Step 8: Anneal the three-layer field plate metal at a temperature of 400 °C for 30 s, so that the ends of the third-layer field plate metal 83 and the second-layer field plate metal 82 near the first notch Q1 warp upward, as Figure 9 shown.

[0084] Step 9: Adopt the SOD (Spin-On Dielectric) method to grow SiO 2 on the second dielectric layer 6 by spin coating and baking to form the third dielectric layer 7, and etch away the excess third dielectric layer 7 to obtain a device with a multi-potential field plate structure as Figure 10 shown, where the height of the field plate changes in a gradient manner.

[0085] In this embodiment, the bottom surface of the end of the second-layer field plate metal 82 near the first notch Q1 is the first inclined surface, and the included angle between the first inclined surface and the top surface of the second dielectric layer 6 is 16°.

[0086] Preparation method of device with multi-potential field plate structure in Embodiment 2

[0087] This embodiment provides a preparation method of a device with a multi-potential field plate structure, which specifically includes the following steps:

[0088] Step 1: As Figure 1 shown, select silicon as the substrate 1 for nitride epitaxial growth to sequentially form a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The nitride is GaN. The nucleation layer, the buffer layer, the channel layer, and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and a high-concentration two-dimensional electron gas can be formed at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0089] Step 2: Deposit SiN on the epitaxial layer 2 by MOCVD method to form the first dielectric layer 5, as Figure 2 shown, for controlling the high-concentration two-dimensional electron gas channel.

[0090] Step 3: Deposit SiO 2 on the first dielectric layer 5 to form the second dielectric layer 6, as Figure 3 shown, for protecting the first dielectric layer 5 from process damage.

[0091] Step 4: Etch the epitaxial layer 2, the first dielectric layer 5, and the second dielectric layer 6 to form a source electrode hole 22 and a drain electrode hole 21, as Figure 4 shown, and perform ohmic metal deposition and etching in the source electrode hole 22 and the drain electrode hole 21, and then perform annealing to form an ohmic contact to respectively form a source electrode 4 and a drain electrode 3, as Figure 5 shown.

[0092] Step Five: Etch on the second dielectric layer 6 to form a gate electrode hole 61, as shown in Figure 6 shown.

[0093] Step Six: Deposit three layers of metal in the gate electrode hole 61 and etch away the excess metal to form three-layer field plate metals, as shown in Figure 7 shown. The three-layer field plate metals are stacked in sequence. From bottom to top, they are: the first-layer field plate metal 81, the second-layer field plate metal 82, and the third-layer field plate metal 83.

[0094] Among them, the thermal expansion coefficient of the third-layer field plate metal 83 is less than that of the second-layer field plate metal 82. The thermal expansion coefficient of the third-layer field plate metal 83 is 0 - 15×10 -6 / °C, preferably 4×10 -6 -11×10 -6 / °C; the thermal expansion coefficient of the second-layer field plate metal 82 is 20×10 -6 -40×10 -6 / °C, preferably 20×10 -6 -25×10 -6 / °C.

[0095] In this embodiment, the third-layer field plate metal 83 is titanium, with a thermal expansion coefficient of 10.8×10 -6 / °C, a thickness of 100 nm, and a length of 10 μm; the second-layer field plate metal 82 is an aluminum-magnesium alloy, with a thermal expansion coefficient of 24×10 -6 / °C, a thickness of 100 nm, and a length of 10 μm; the first-layer field plate metal 81 is aluminum, with a thickness of 200 nm and a length of 10 μm.

[0096] Step Seven: Apply photoresist to one end of the first-layer field plate metal 81 in the three-layer field plate metals, and then use the alkaline solution tetramethylammonium hydroxide to etch the other end of the first-layer field plate metal 81, so that a first notch Q1 is formed at the other end of the first-layer field plate metal 81, as shown in Figure 8 shown. In this embodiment, the length of the remaining field plate metal at the end of the first-layer field plate metal 81 after etching accounts for 50% of the length of the first-layer field plate metal 81 before etching at the end.

[0097] Step Eight: Anneal the three-layer field plate metals at a temperature of 450°C for 20 s, so that the ends of the third-layer field plate metal 83 and the second-layer field plate metal 82 close to the first notch Q1 warp upward, as shown in Figure 11 shown.

[0098] Step Nine: Adopt the SOD method to grow SiO 2 on the second dielectric layer 6 by spin coating and baking to form a third dielectric layer 7, and etch away the excess third dielectric layer 7 to obtain as shown in Figure 12For the device with a multi-potential-field plate structure shown, the height of the field plate changes in a gradient manner.

[0099] In this embodiment, the bottom surface of the end of the second-layer field plate metal 82 close to the first notch Q1 is an arc surface, and the central angle of the arc surface is 14°.

[0100] Preparation Method of Device with Multi-Potential-Field Plate Structure in Embodiment 3

[0101] This embodiment provides a preparation method of a device with a multi-potential-field plate structure, which specifically includes the following steps:

[0102] Step 1: As shown in Figure 1 , select silicon as the substrate 1 for nitride epitaxial growth, and sequentially form a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The nitride is GaN. The nucleation layer, the buffer layer, the channel layer, and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and a high-concentration two-dimensional electron gas can be formed at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0103] Step 2: Deposit SiN on the epitaxial layer 2 by MOCVD method to form a first dielectric layer 5, as shown in Figure 2 , for controlling the high-concentration two-dimensional electron gas channel.

[0104] Step 3: Deposit SiO 2 on the first dielectric layer 5 to form a second dielectric layer 6, as shown in Figure 3 , for protecting the first dielectric layer 5 from process damage.

[0105] Step 4: Etch the epitaxial layer 2, the first dielectric layer 5, and the second dielectric layer 6 to form a source electrode hole 22 and a drain electrode hole 21, as shown in Figure 4 . Then, perform ohmic metal deposition and etching in the source electrode hole 22 and the drain electrode hole 21, and then perform annealing to form an ohmic contact, respectively forming a source electrode 4 and a drain electrode 3, as shown in Figure 5 .

[0106] Step 5: Etch the second dielectric layer 6 to form a gate electrode hole 61, as shown in Figure 6 .

[0107] Step 6: Deposit three layers of metal in the gate electrode hole 61 and etch away the excess metal to form three-layer field plate metals, as shown in Figure 7 . The three-layer field plate metals are stacked in sequence. From bottom to top, they are: the first-layer field plate metal 81, the second-layer field plate metal 82, and the third-layer field plate metal 83.

[0108] Among them, the coefficient of thermal expansion of the third-layer field plate metal 83 is less than that of the second-layer field plate metal 82. The coefficient of thermal expansion of the third-layer field plate metal 83 is 0 to 15×10 -6 / °C, preferably 4×10 -6 ~11×10 -6 / °C; the coefficient of thermal expansion of the second-layer field plate metal 82 is 20×10 -6 ~40×10 -6 / °C, preferably 20×10 -6 ~25×10 -6 / °C.

[0109] In this embodiment, the third-layer field plate metal 83 is tungsten, with a coefficient of thermal expansion of 4.5×10 -6 / °C, a thickness of 100 nm, and a length of 10 μm; the second-layer field plate metal 82 is an aluminum-copper alloy, with a coefficient of thermal expansion of 20×10 -6 / °C, a thickness of 100 nm, and a length of 10 μm; the first-layer field plate metal 81 is aluminum, with a thickness of 200 nm and a length of 10 μm.

[0110] Step Seven: First, apply photoresist to one end of the first-layer field plate metal 81 among the three-layer field plate metals, and use the alkaline solution tetramethylammonium hydroxide to etch the other end of the first-layer field plate metal 81, so that a first notch Q1 is formed at the other end of the first-layer field plate metal 81; then apply photoresist to the end of the first-layer field plate metal 81 having the first notch Q1, and use the alkaline solution methylammonium hydroxide to etch the end of the first-layer field plate metal 81 away from the first notch Q1, so that a second notch Q2 is formed at the end of the first-layer field plate metal 81 away from the first notch Q1, as Figure 13 shown. In this embodiment, the length of the remaining field plate metal at the end of the first-layer field plate metal 81 after etching accounts for 40% of the length of the first-layer field plate metal 81 before etching at the end.

[0111] Step Eight: Anneal the three-layer field plate metals at a temperature of 400°C for 30 s, so that both ends of the third-layer field plate metal 83 and the second-layer field plate metal 82 close to the first notch Q1 and the second notch Q2 warp upward, as Figure 14 shown.

[0112] Step Nine: Adopt the SOD method, and grow SiO 2 on the second dielectric layer 6 by spin coating and baking to form a third dielectric layer 7, and etch away the excess third dielectric layer 7 to obtain a device with a multi-potential field plate structure as Figure 15 shown, where the height of the field plate changes in a gradient manner.

[0113] In this embodiment, the length of the first notch Q1 is greater than that of the second notch Q2. The bottom surface of the end of the second-layer field plate metal 82 close to the first notch Q1 is a first inclined surface, and the included angle between the first inclined surface and the top surface of the second dielectric layer 6 is 16°; the bottom surface of the end of the second-layer field plate metal 82 close to the first notch Q1 is a second inclined surface, and the included angle between the second inclined surface and the top surface of the second dielectric layer 6 is 14°.

[0114] Preparation Method of Device with Multi-Potential Field Plate Structure in Embodiment 4

[0115] This embodiment provides a preparation method of a device with a multi-potential field plate structure, which specifically includes the following steps:

[0116] Step 1: As shown in Figure 1 , select silicon as the substrate 1 for nitride epitaxial growth to successively form a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The nitride is GaN. The nucleation layer, the buffer layer, the channel layer, and the barrier layer constitute a complete semiconductor epitaxial layer 2 structure, and a high-concentration two-dimensional electron gas can be formed at the heterojunction interface between the channel layer and the barrier layer to generate a conductive channel.

[0117] Step 2: Deposit SiN on the epitaxial layer 2 by MOCVD to form a first dielectric layer 5, as shown in Figure 2 , for controlling the high-concentration two-dimensional electron gas channel.

[0118] Step 3: Deposit SiO 2 on the first dielectric layer 5 to form a second dielectric layer 6, as shown in Figure 3 , for protecting the first dielectric layer 5 from process damage.

[0119] Step 4: Etch the epitaxial layer 2, the first dielectric layer 5, and the second dielectric layer 6 to form a source electrode hole 22 and a drain electrode hole 21, as shown in Figure 4 . Then, perform ohmic metal deposition and etching in the source electrode hole 22 and the drain electrode hole 21, and then perform annealing to form an ohmic contact, respectively forming a source electrode 4 and a drain electrode 3, as shown in Figure 5 .

[0120] Step 5: Etch the second dielectric layer 6 to form a gate electrode hole 61, as shown in Figure 16 .

[0121] Step 6: Deposit three layers of metal in the gate electrode hole 61 and etch away the excess metal to form three-layer field plate metals, as shown in Figure 17 . The three-layer field plate metals are stacked in sequence. From bottom to top, they are: the first-layer field plate metal 81, the second-layer field plate metal 82, and the third-layer field plate metal 83.

[0122] Among them, the coefficient of thermal expansion of the third-layer field plate metal 83 is less than that of the second-layer field plate metal 82. The coefficient of thermal expansion of the third-layer field plate metal 83 is 0 to 15×10 -6 / °C, preferably 4×10 -6 ~11×10 -6 / °C; the coefficient of thermal expansion of the second-layer field plate metal 82 is 20×10 -6 ~40×10 -6 / °C, preferably 20×10 -6 ~25×10 -6 / °C.

[0123] In this embodiment, the third-layer field plate metal 83 is titanium, with a coefficient of thermal expansion of 10.8×10 -6 / °C, a thickness of 100 nm, and a length of 10 μm; the second-layer field plate metal 82 is an aluminum-magnesium alloy, with a coefficient of thermal expansion of 24×10 -6 / °C, a thickness of 100 nm, and a length of 10 μm; the first-layer field plate metal 81 is aluminum, with a thickness of 200 nm and a length of 10 μm.

[0124] Step Seven: Use the alkaline solution tetramethylammonium hydroxide to etch both ends of the first-layer field plate metal 81 simultaneously, so that the first notch Q1 and the second notch Q2 are respectively formed at both ends of the first-layer field plate metal 81, as Figure 18 shown. In this embodiment, the length of the remaining field plate metal at the end of the first-layer field plate metal 81 after etching accounts for 50% of the length of the first-layer field plate metal 81 before etching at the end.

[0125] Step Eight: Anneal the three-layer field plate metal at a temperature of 450°C for 20 s, so that both ends of the third-layer field plate metal 83 and the second-layer field plate metal 82 close to the first notch Q1 and the second notch Q2 warp upward, as Figure 19 shown.

[0126] Step Nine: Adopt the SOD method to grow SiO 2 on the second dielectric layer 6 by spin coating and baking to form the third dielectric layer 7, and etch away the excess third dielectric layer 7 to obtain the device with a three-layer multi-potential field plate structure as Figure 20 shown, and the height of the field plate changes in a gradient manner.

[0127] In this embodiment, the length of the first notch Q1 is equal to the length of the second notch Q2, and the bottom surface of the second-layer field plate metal 82 is an arc surface, and the central angle of the arc surface is 14°.

[0128] The preparation method of the device with a multi-potential field plate structure according to the present invention is as follows: deposit n layers of metal in the gate electrode hole 61, and obtain n layers of field plate metals after etching. Then, after etching the end of the first layer of field plate metal 81 at the bottom, through a single annealing treatment, the ends of the second to the nth layer of field plate metals above the first layer of field plate metal 81 can be directly warped away from the second dielectric layer 6 to form an electric field gradient field plate. Finally, a device with a multi-potential field plate structure is obtained. Compared with the traditional field plate process, the number of process steps is reduced by 5 to 8 steps. While the process is simplified, a device with a multi-potential field plate structure is prepared, which can effectively control the potential difference between the field plate and the two-dimensional electron gas below, and avoid the problem of introducing defect risks caused by numerous process steps, which is beneficial to the reliability of the device.

[0129] The above embodiments obtained by the method of the present invention are only for illustrating the technical concept and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and it cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for preparing a device containing a multi-potential field plate structure, characterized in that: The steps include: Prepare a base structure and etch the second dielectric layer of the base structure to form a gate electrode hole; Depositing n layers of metal in the gate electrode hole and etching to form n layers of field plate metal, wherein n is a positive integer greater than or equal to 3; in the n layers of field plate metal, the thermal expansion coefficient of each layer of field plate metal gradually increases from the nth layer to the second layer; Etching the end of the first layer of field plate metal so that the first layer of field plate metal is recessed inward relative to the field plate metals from the nth layer to the second layer, thereby forming a first notch; Annealing the n-layer field plate metal so that the end of the field plate metal from the n-th layer to the second layer located above the first notch is warped in a direction away from the second dielectric layer; A third dielectric layer is grown on the second dielectric layer, a third dielectric layer is also formed in the first notch and under the warped portion, and the redundant third dielectric layer is etched away to form a field plate, thereby obtaining the device with the multi-potential field plate structure.

2. The preparation method according to claim 1, characterized in that: The method for etching the end of the first layer of field plate metal is wet etching, and the first layer of field plate metal is a metal soluble in an alkaline solution.

3. The preparation method according to claim 1, characterized in that: In the step of depositing n layers of metal in the gate electrode hole and etching to form n layers of field plate metal, the length of each layer of the n layers of field plate metal is the same.

4. The preparation method according to claim 2, characterized in that: The method for etching the end of the first layer of field plate metal comprises the following steps: Photoresist is applied to one end of the first field plate metal layer, and then an alkaline solution is used to corrode the other end of the first field plate metal layer, so that a first notch is formed at the other end of the first field plate metal layer.

5. The preparation method according to claim 2, characterized in that: The method for etching the end of the first layer of field plate metal comprises the following steps: First, one end of the first layer of field plate metal is coated with photoresist, and the other end of the first layer of field plate metal is corroded with an alkaline solution, so that a first gap is formed at the other end of the first layer of field plate metal; then, the end of the first layer of field plate metal having the first gap is coated with photoresist, and the end of the first layer of field plate metal away from the first gap is corroded with an alkaline solution, so that a second gap is formed at the end of the first layer of field plate metal away from the first gap.

6. The preparation method according to claim 2, characterized in that: The method for etching the end of the first layer of field plate metal comprises the following steps: An alkaline solution is used to simultaneously corrode both ends of the first layer of field plate metal, so that a first gap and a second gap are formed at both ends of the first layer of field plate metal respectively.

7. The preparation method according to claim 5 or 6, characterized in that: The length of the first notch is the same as or different from the length of the second notch.

8. The preparation method according to claim 4, characterized in that: The bottom surface of the end of the field plate metal of the second layer close to the first notch is a first inclined surface, and the angle between the first inclined surface and the top surface of the second dielectric layer is 10° to 20°.

9. The preparation method according to claim 4, characterized in that: The bottom surface of the end of the field plate metal of the second layer close to the first notch is an arc surface, and the central angle of the arc surface is 20° to 40°.

10. The preparation method according to claim 5 or 6, characterized in that: The bottom surface of the end of the field plate metal of the second layer close to the first notch is a first inclined surface, the bottom surface of the end of the field plate metal of the second layer close to the second notch is a second inclined surface, the angle between the first inclined surface and the top surface of the second dielectric layer is 10° to 20°, and the angle between the second inclined surface and the top surface of the second dielectric layer is 10° to 20°.

11. The preparation method according to claim 5 or 6, characterized in that: The bottom surface of the field plate metal of the second layer is a curved surface, and the central angle of the curved surface is 20° to 40°.

12. The preparation method according to any one of claims 4 to 6, characterized in that: The length of the remaining field plate metal after the end of the first layer of field plate metal is etched accounts for 40% to 50% of the length of the end of the first layer of field plate metal before etching.

13. The preparation method according to claim 1, characterized in that: In the step of annealing the n-layer field plate metal, the annealing temperature is 380-500°C.

14. The preparation method according to claim 1, characterized in that: The basic structure comprises, from bottom to top, a substrate, an epitaxial layer, a first dielectric layer and a second dielectric layer.

15. The preparation method according to claim 14, characterized in that: The method for preparing the base structure comprises: performing nitride epitaxial growth on a substrate to form an epitaxial layer structure, and sequentially growing a first dielectric layer and a second dielectric layer on the epitaxial layer; Etching is performed on the epitaxial layer, the first dielectric layer and the second dielectric layer to form a source electrode hole and a drain electrode hole, and metal deposition and etching are performed in the source electrode hole and the drain electrode hole, and then annealing is performed to form ohmic contacts to form a source electrode and a drain electrode respectively.

16. A device containing a multi-potential field plate structure, characterized in that: The compound is prepared by the preparation method according to any one of claims 1 to 15.

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