Semiconductor device structure and forming method thereof

Abstract

Semiconductor device structures and methods of forming the same are described. The method includes forming a fin structure from a substrate, depositing a first semiconductor material on a first semiconductor layer of the fin structure, depositing a second semiconductor material on the first semiconductor material, depositing an interlayer dielectric layer over the second semiconductor material, forming an opening in the interlayer dielectric layer to expose the second semiconductor material, and performing a dopant implantation process to form a doped region. The doped region includes a first portion of the second semiconductor material. Then, the method further includes performing an amorphization process to form an amorphous region, and the amorphous region includes a second portion of the second semiconductor material. The method further includes performing an annealing process to recrystallize the amorphous region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically to a semiconductor device structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the process of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaled-down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaled-down process also increases the complexity of processing and manufacturing ICs. Summary of the invention

[0003] According to one aspect of the present application, a method is provided, comprising: forming a fin structure from a substrate; depositing a first semiconductor material on a first semiconductor layer of the fin structure; depositing a second semiconductor material on the first semiconductor material; depositing an interlayer dielectric layer on the second semiconductor material; forming an opening in the interlayer dielectric layer to expose the second semiconductor material; performing a dopant implantation process to form a doped region, wherein the doped region includes a first portion of the second semiconductor material; performing an amorphization process to form an amorphous region, wherein the amorphous region includes a second portion of the second semiconductor material; and performing an annealing process to recrystallize the amorphous region.

[0004] In some implementations, a height of the first portion of the second semiconductor material is significantly greater than a height of the second portion of the second semiconductor material.

[0005] In some implementations, the doped region includes portions of the first semiconductor material.

[0006] In some implementations, the amorphous region includes a first semiconductor material.

[0007] In some implementations, the fin structure includes a first semiconductor layer, a second semiconductor layer below the first semiconductor layer, and a third semiconductor layer below the second semiconductor layer.

[0008] In some implementations, the method further includes depositing a third semiconductor material on the second semiconductor layer and depositing a fourth semiconductor material on the third semiconductor layer, wherein the second semiconductor material is deposited on the third semiconductor material and the fourth semiconductor material.

[0009] In some implementations, the third semiconductor layer is located outside the amorphous region.

[0010] According to one aspect of the present application, a method is provided, comprising: forming a fin structure from a substrate; recessing a portion of the fin structure to expose a portion of the substrate; depositing a first semiconductor material over a portion of the substrate; depositing a first interlayer dielectric layer over the first semiconductor material; forming an opening in the interlayer dielectric layer to expose the first semiconductor material; performing an amorphization process to form an amorphous region, wherein the amorphous region includes a portion of the first semiconductor material; performing an annealing process to convert a first portion of the amorphous region into a first crystalline region; and forming a silicide layer from a second portion of the amorphous region.

[0011] In some implementations, the first semiconductor material includes a second crystalline region underlying the first crystalline region.

[0012] In some implementations, the first crystalline region has a dopant concentration that is substantially greater than a dopant concentration of the second crystalline region.

[0013] In some implementations, the silicide layer has a dopant concentration that is significantly greater than a dopant concentration of the second crystalline region.

[0014] In some implementations, the fin structure includes multiple semiconductor layers.

[0015] In some implementations, the method further includes depositing a second semiconductor material on each semiconductor layer of the plurality of semiconductor layers, wherein the first semiconductor material is deposited on the second semiconductor material.

[0016] In some implementations, the amorphous region includes a second semiconductor material in contact with a topmost semiconductor layer of the plurality of semiconductor layers.

[0017] According to one aspect of the present application, a semiconductor device structure is provided, comprising: a plurality of semiconductor layers arranged on a substrate; and a source / drain region arranged adjacent to the plurality of semiconductor layers, wherein the source / drain region comprises: a first semiconductor material in contact with each of the plurality of semiconductor layers, wherein the first semiconductor material in contact with the topmost semiconductor layer of the plurality of semiconductor layers has a first dopant concentration, and the first semiconductor material in contact with a semiconductor layer arranged below the topmost semiconductor layer of the plurality of semiconductor layers has a second dopant concentration, the second dopant concentration being significantly less than the first dopant concentration; and a second semiconductor material surrounding the first semiconductor material.

[0018] In some implementations, the semiconductor device structure further includes a silicide layer disposed on the second semiconductor material.

[0019] In some implementations, the semiconductor device structure further includes a first crystalline region disposed below the silicide layer and a second crystalline region disposed below the first crystalline region.

[0020] In some implementations, the dopant concentration of the first crystalline region is significantly greater than the dopant concentration of the second crystalline region.

[0021] In some implementations, the second semiconductor material has a dopant concentration gradient.

[0022] In some implementations, the semiconductor device structure further includes a third semiconductor material disposed on the substrate and a dielectric layer disposed on the third semiconductor material, wherein the second semiconductor material is disposed on the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood from the following specific implementations. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion.

[0024] Figures 1 to 5 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0025] Figures 6 to 20 According to some embodiments, Figure 5 Cross-sectional side views of various stages in the manufacture of a semiconductor device structure taken along line AA.

[0026] Figure 21 to Figure 24 According to an alternative embodiment, Figure 5 Cross-sectional side views of various stages in the manufacture of a semiconductor device structure taken along line AA. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0028] Additionally, spatially relative terms (e.g., "below," "lower," "above," "over," "above," "top," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0029] Various embodiments to be described below generally relate to using a solid phase epitaxial regrowth (SPER) process to increase dopant activation, thereby reducing resistance between two components. In some embodiments, the SPER process includes an amorphization process and an annealing process. The SPER process can be performed on one or more layers of the source / drain region. As a result, the contact resistance between the source / drain region and the conductive feature and / or the contact resistance between the source / drain region and the channel region (i.e., one or more semiconductor layers) is reduced.

[0030] Although embodiments of the present disclosure are discussed with respect to nanostructured channel FETs (e.g., gate all around (GAA) FETs (e.g., horizontal gate all around (HGAA) FETs or vertical gate all around (VGAA) FETs)), implementations of some aspects of the present disclosure may be used in other processes and / or other devices (e.g., planar FETs, fin FETs, and other suitable devices). A person of ordinary skill in the art will readily appreciate that other modifications that may be made are considered within the scope of the present disclosure. In the case of a gate all around (GAA) transistor structure, the GAA transistor structure may be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) may be used to pattern these structures. Typically, the double patterning process or the multi-patterning process combines a photolithography process with a self-alignment process, thereby allowing the generation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0031] Figures 1 to 20 FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that Figures 1 to 20Additional operations are provided before, during, and after the illustrated processes, and some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of the operations / processes is not limiting and may be interchangeable.

[0032] Figures 1 to 5 1 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

[0033] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type impurities). Depending on the circuit design, the dopant may be, for example, phosphorus for an n-type field effect transistor (n-type FET) and boron for a p-type field effect transistor (p-type FET).

[0034] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate devices (e.g., nanostructure channel FETs). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, any of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0035] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0036] The first semiconductor layer 106 or a portion thereof may form (one or more) nanostructure channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanostructure is used herein to represent any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term refers to an elongated material portion having a circular and substantially circular cross-section, and a beam-shaped or strip-shaped material portion including, for example, a cylindrical or substantially rectangular cross-section. The (one or more) nanostructure channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. The nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a full surround gate (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0037] Each first semiconductor layer 106 may have a thickness in a range between about 5 nm and about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in a range between about 2 nm and about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for illustrative purposes only and is not intended to limit the scope specifically recited in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100. In some embodiments, the semiconductor layer stack 104 includes two first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes three first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes four first semiconductor layers 106.

[0038] like Figure 2As shown, a fin structure 112 is formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed from a substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using a multi-patterning operation including a photolithography process and an etching process. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element including a photoresist layer. In some embodiments, patterning the photoresist layer to form a mask element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 in unprotected areas through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. The trenches 114 may be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0039] like Figure 3 As shown, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation (e.g., a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed so that the top of the fin structure 112 is exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0040] like Figure 4 As shown, the insulating material 118 is recessed to form an isolation region 120. The recessing of the insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The recessing of the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process (e.g., a dry etching process, a wet etching process, or a combination thereof). The top surface of the insulating material 118 can be flush with or below the surface of the second semiconductor layer 108 in contact with the well portion 116 formed from the substrate 101. In some embodiments, the isolation region 120 is a shallow trench isolation (STI) region.

[0041] like Figure 5 As shown, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning the layers into the sacrificial gate structure 130. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0042] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100.

[0043] Figures 6 to 20 According to some embodiments, Figure 5 The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are taken along the line AA. Figure 6 As shown, the first gate spacer 138 is deposited on the exposed surface of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structure 112, the isolation region 120, and the sacrificial gate structure 130. The first gate spacer 138 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiCON, and / or a combination thereof. The first gate spacer 138 can be formed by any suitable process. In some embodiments, the first gate spacer 138 is a conformal layer formed by a conformal process (e.g., an atomic layer deposition (ALD) process).

[0044] like Figure 7 As shown, the second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 may include any suitable dielectric material, such as SiO x, SiON, SiN, SiCON or SiCO. The second gate spacer 139 may have a thickness ranging from about 0.5 nm to about 5 nm. The second gate spacer 139 may be formed by any suitable process. In some embodiments, the second gate spacer 139 is deposited by CVD, PECVD or electron cyclotron resonance CVD (ECR-CVD).

[0045] like Figure 8 As shown, horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed by an anisotropic etching process. The anisotropic etching process may be a selective etching process that does not substantially affect the mask layer 136, the semiconductor layer stack 104, and the isolation region 120.

[0046] like Fig. 9 As shown, portions of the fin structure 112 that are not covered by the sacrificial gate structure 130 and the first gate spacer 138 and the second gate spacer 139 are recessed to a level above, at, or below the top surface of the isolation region 120. The recessing of these portions of the fin structure 112 can be accomplished by an etching process. The etching process can be a dry etch (e.g., RIE, NBE, etc.) or a wet etch (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant). The well portion 116 is exposed on the opposite side of the sacrificial gate structure 130, as shown in FIG. Fig. 9 shown.

[0047] like Fig.10 As shown, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, these portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a wet etchant (such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution) can be used to selectively etch the second semiconductor layer 108.

[0048] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 can be made of a low-K dielectric material (e.g., SiON, SiCN, SiOC, SiOCN, or SiN). The dielectric spacer 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), and then removing the portion of the conformal dielectric layer other than the dielectric spacer 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0049] like Fig.11 As shown, a first semiconductor material 150 is formed on the exposed well portion 116. In some embodiments, the first semiconductor material 150 includes undoped silicon or undoped SiGe. The first semiconductor material 150 can be first formed on a semiconductor surface (e.g., on the exposed well portion 116 and on the first semiconductor layer 106) by epitaxy. A subsequent etching process is performed to remove the portion of the first semiconductor material 150 formed on the first semiconductor layer 106. As a result of the etching process, the first semiconductor material 150 formed on the exposed well portion 116 can form a concave top surface. In some embodiments, the first semiconductor material 150 has a thickness ranging from about 5 nm to about 50 nm along the Z direction.

[0050] Next, if Fig.12As shown, a dielectric layer 152 is formed on the first semiconductor material 150. The dielectric layer 152 can be formed by first forming a dielectric layer on the exposed surface of the semiconductor device structure 100, and then performing one or more etching processes to remove the portion of the dielectric layer other than the dielectric layer 152. A mask layer (not shown), such as a bottom anti-reflective coating (BARC), can be used to help remove the portion of the dielectric layer. The dielectric layer 152 may include any suitable dielectric material. In some embodiments, the dielectric layer 152 includes SiN. The dielectric layer 152 may be formed by any suitable process. In some embodiments, the dielectric layer 152 is formed by CVD. Next, a second semiconductor material 154 is formed from the first semiconductor layer 106. The second semiconductor material 154 may be made of one or more layers of Si, SiP, SiC, SiAs, SiSb, and SiCP for n-channel FETs or Si, SiGe, and Ge for p-channel FETs. For p-channel FETs, a p-type dopant (e.g., boron (B)) may be included in the second semiconductor material 154. For an n-channel FET, an n-type dopant, such as phosphorus (P) or arsenic (As), may be included in the second semiconductor material 154. In some embodiments, the dopant concentration of the second semiconductor material 154 may be about 1×10 19 cm -3 To about 2×10 21 cm -3 The second semiconductor material 154 may be formed by an epitaxial growth method using CVD, ALD or MBE. Fig.12 As shown, in some embodiments, the second semiconductor material 154 is selectively formed on the semiconductor material (e.g., the first semiconductor layer 106) and not formed on the dielectric material (e.g., the dielectric layer 152 and the dielectric spacer 144). In some embodiments, the second semiconductor material 154 includes a facet, which can correspond to a crystal plane of the material used for the first semiconductor layer 106.

[0051] Next, if Fig.12As shown, a third semiconductor material 156 is formed from the second semiconductor material 154. The third semiconductor material 156 can be formed by an epitaxial growth method using CVD, ALD, or MBE. The third semiconductor material 156 can be made of one or more layers of Si, SiP, SiC, and SiCP for n-type FETs or Si, SiGe, Ge for p-type FETs. For p-type FETs, a p-type dopant, such as boron (B), can be included in the third semiconductor material 156. For n-type FETs, an n-type dopant, such as phosphorus (P) or arsenic (As), can be included in the third semiconductor material 156. In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 may include the same semiconductor material with different dopant concentrations. The dopant concentration of the third semiconductor material 156 may be significantly greater than the dopant concentration of the second semiconductor material 154. In some embodiments, the dopant concentration of the third semiconductor material 156 may be about 5×10 19 cm -3 To about 4×10 21 cm -3 The third semiconductor material 156 may be epitaxially grown from the second semiconductor material 154. Because of the facets of the second semiconductor material 154, the quality of the third semiconductor material 156 may be improved. In some embodiments, as a result of growing the third semiconductor material 156 from the second semiconductor material 154, a void may be formed near the top of the third semiconductor material 156. In some embodiments, the dielectric layer 152 is not present and the third semiconductor material 156 is grown from the first semiconductor material 150 and the second semiconductor material 154, which results in a third semiconductor material 156 without a void.

[0052] In some embodiments, a capping layer (not shown) may be formed on the third semiconductor material 156 . The capping layer may include a semiconductor material. In some embodiments, the capping layer includes the same material as the third semiconductor material. The capping layer may be epitaxially grown from the third semiconductor material 156 .

[0053] In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 may be in-situ doped during growth. If the dopant concentrations of the second semiconductor material 154 and the third semiconductor material 156 are greater than the respective above ranges, the quality of the second semiconductor material 154 and the third semiconductor material 156 may be negatively affected. Therefore, subsequent processes may be performed to increase the dopant concentration and / or dopant activation in order to reduce electrical contact resistance.

[0054] The second semiconductor material 154 and the third semiconductor material 156 together can be a source / drain (S / D) region. In the present disclosure, the source region and the drain region can be used interchangeably, and their structures are basically the same. In addition, (one or more) source / drain regions can refer to the source or drain, which depends on the context individually or collectively. In some embodiments, one or more mask layers can be used to form a p-type S / D region and an n-type S / D region, respectively. In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 are crystalline semiconductor materials.

[0055] Next, if Fig.12 As shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the second gate spacer 139, the isolation region 120, and the third semiconductor material 156 (or the cap layer, if present). The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL 162 is a single layer, such as Fig.12 As shown. In some embodiments, CESL 162 includes two or more layers. Next, an interlayer dielectric (ILD) layer 164 is formed on CESL 162. The material of ILD layer 164 may include a compound containing Si, O, C and / or H, such as silicon oxide, SiCOH or SiOC. Organic materials (such as polymers) may also be used for ILD layer 164. ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming ILD layer 164, semiconductor device structure 100 may be thermally treated to anneal ILD layer 164.

[0056] After forming the ILD layer 164, a planarization operation (eg, CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. Fig.12 shown.

[0057] Next, if Fig.13As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening between the first gate spacers 138 and between the first semiconductor layer 106. The ILD layer 164 protects the second semiconductor material 156 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process (e.g., dry etching, wet etching, or a combination thereof), followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process (e.g., dry etching, wet etching, or a combination thereof). In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 134, but without removing the first gate spacers 138, the ILD layer 164, and the CESL 162.

[0058] The second semiconductor layer 108 may be removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemistry used in the selective wet etching process removes SiGe without substantially affecting Si, the dielectric material of the first gate spacer 138, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 may be removed using a wet etchant such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), or phosphoric acid (H3PO4).

[0059] like Fig.14As shown, after the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106) is formed, a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the exposed surface of the first semiconductor layer 106 and the gate dielectric layer 170, and one or more work function layers (not shown) are formed between the gate dielectric layer 170 and the gate electrode layer 172. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-K dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD, or any suitable deposition technique. The work function layer may include polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, or other suitable materials. The gate electrode layer 172 may include one or more layers of conductive materials, such as platinum (Pt), palladium (Pd), tantalum (Ta), ytterbium (Yb), aluminum (Al), silver (Ag), titanium (Ti), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), copper (Cu), or similar materials and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited on the upper surface of the ILD layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed on the ILD layer 164 are then removed by using, for example, CMP until the top surface of the ILD layer 164 is exposed.

[0060] It should be understood that other processes, such as a cut metal gate (CMG) process and / or a continuous polysilicon diffusion edge (CPODE) process, may be performed on the semiconductor device structure 100. The CMG process divides the gate electrode layer 172 into multiple segments that can be controlled individually. The CPODE process forms isolation between devices.

[0061] like Fig.15As shown, an etch stop layer 166 and a second ILD layer 168 are formed over the ILD layer 164 and the gate electrode layer 172. The etch stop layer 166 may include the same material as the CESL 162 and may be formed by the same process as the CESL 162. The second ILD layer 168 may include the same material as the ILD layer 164 and may be formed by the same process as the ILD layer 164.

[0062] Next, if Fig.16 As shown, an opening 180 is formed in the second ILD layer 168, the etch stop layer 166, the ILD layer 164, and the CESL 162 to expose the third semiconductor material 156. In some embodiments, portions of the ILD layer 164 and the CESL 162 located above the third semiconductor material 156 may be removed. In some embodiments, a cap layer (not shown) and a portion of the third semiconductor material 156 may also be removed. The opening 180 may be formed by an etching process (e.g., a dry etching process, a wet etching process, or a combination thereof). A patterned mask (not shown) may be formed over the second ILD layer 168, and the pattern of the patterned mask may be transferred to the second ILD layer 168, the etch stop layer 166, the ILD layer 164, and the CESL 162.

[0063] like Fig.16 As shown, the semiconductor device structure 100 includes an IL 167 formed on the first semiconductor layer 106 and a work function layer 169 formed between the gate dielectric layer 170 and the gate electrode layer 172. In addition, the semiconductor device structure 100 includes a dielectric liner 196 and a dielectric material 198. The dielectric liner 196 and the dielectric material 198 can be isolation structures formed by a CPODE process. In some embodiments, the dielectric material 198 includes the same material as the etch stop layer 166.

[0064] like Fig.17 As shown, a liner 184 is formed on the vertical surfaces of the second ILD layer 168, the etch stop layer 166, and the first gate spacer 138. The liner 184 may include any suitable material. In some embodiments, the liner 184 is a nitride layer, such as a silicon nitride layer. In some embodiments, the liner 84 includes the same material as the etch stop layer 166. The liner 184 may be formed by first forming a dielectric layer on the exposed surface of the semiconductor device structure 100, and then performing an anisotropic etching process to remove the portion of the dielectric layer formed on the horizontal surface of the semiconductor device structure 100. For example, the portion of the dielectric layer formed on the second ILD layer 168 and the third semiconductor material 156 is removed by an anisotropic etching process. During subsequent processes, the liner 184 protects the second ILD layer 168.

[0065] As described above, in order to reduce the electrical contact resistance, one or more processes may be performed to increase the dopant concentration and / or dopant activation in the third semiconductor material 156 and / or the second semiconductor material 154. In some embodiments, a SPER process is performed on the second semiconductor material 154 and / or the third semiconductor material 156. The SPER process may include an amorphization process and an annealing process. In some embodiments, a portion of the third semiconductor material 156 (which is a crystalline semiconductor material) is amorphized by the amorphization process. For example, impurities may be implanted into the third semiconductor material 156 to form an amorphous region 186, such as Fig.18 As shown. In some examples, the amorphous region 186 can extend to the dielectric layer 152. However, it may take a long time to recrystallize such a large amorphous region 186. Therefore, in some embodiments, the amorphous region 186 extends to a level between the topmost first semiconductor layer 106 and the adjacent first semiconductor layer 106 below the topmost first semiconductor layer 106. As a result, the length of the annealing process to recrystallize the amorphous region 186 is reduced.

[0066] In some embodiments, the amorphization process is an ion implantation process that introduces a first substance into the exposed third semiconductor material 156 so that at least the top of the third semiconductor material 156 is converted into an amorphous structure (i.e., an amorphous region 186). The first substance of the ion implantation process may be a Group IV element (e.g., C, Si, Ge); a Group III element (e.g., B, Al, Ga, In); a Group V element (e.g., P, As, Sb) or a Group VIII element (e.g., He, Ar, Xe). The implantation process may have an implantation energy ranging from about 0.3 keV to about 60 keV, a density greater than about 1×10 13 cm -2 dosage and a processing temperature ranging from about -150 degrees Celsius to about 500 degrees Celsius.

[0067] In some embodiments, a dopant implantation process may be performed to introduce a second substance (e.g., a dopant) into the third semiconductor material 156. In some embodiments, the dopant implantation process is performed after the amorphization process. For a p-type FET, the second substance may include B, A, Ga, or In. For an n-type FET, the second substance may include As, P, or Sb. In an example embodiment, an energy in a range between about 0.3 keV and about 20 keV may be used to implant the second substance from about 1×10 12 cm -2 To about 1×10 17 cm -2The second substance (e.g., B or As) is implanted at a dose in the range of about 10 to about 15 degrees. The dopant implantation process may also include an implantation tilt angle ranging from about 0 degrees to about 15 degrees. As a result of the dopant implantation process, the dopant concentration of the amorphous region 186 increases, which results in a reduced contact resistance. In some embodiments, the second substance is located within the amorphous region 186 because the amorphous region 186 can prevent the second substance from tunneling through the space between the lattice structures.

[0068] In some embodiments, a dopant implantation process is performed before the amorphization process. For example, a dopant implantation process is performed to form a doped region in the third semiconductor material 156, and the doped region is located at the top of the third semiconductor material 156 and exposed to the opening 180. The doped region of the third semiconductor material 156 has a dopant concentration that is significantly greater than the dopant concentration of the rest of the third semiconductor material.

[0069] In some embodiments, a second substance (e.g., a dopant) may also be introduced into the second semiconductor material 154 by a dopant implantation process. As a result, the dopant concentration of the second semiconductor material 154 in contact with the topmost first semiconductor layer 106 increases, while the dopant concentration of the second semiconductor material 154 in contact with the first semiconductor layer 106 located below the topmost first semiconductor layer 106 is not affected by the dopant implantation process. Therefore, in some embodiments, the dopant concentration of the second semiconductor material 154 in contact with the topmost first semiconductor layer 106 is significantly greater than the dopant concentration of the second semiconductor material 154 in contact with the first semiconductor layer 106 located below the topmost first semiconductor layer 106. Increasing the dopant concentration in the second semiconductor material 154 may result in a reduction in the electrical contact resistance between the second semiconductor material 154 and the first semiconductor layer 106.

[0070] In some embodiments, the second substance is introduced into the second semiconductor material 154 (e.g., the second semiconductor material 154 in contact with the topmost first semiconductor layer 106), but not into the third semiconductor material 156. In other words, the dopant implantation process is performed to increase the dopant concentration of the second semiconductor material 154 in contact with the topmost first semiconductor layer 106, without increasing the dopant concentration of the third semiconductor material 156. The implantation tilt angle may be in a range from about 15 degrees to about 45 degrees.

[0071] In some embodiments, because the dopant implantation process is performed before the amorphization process, the second substance is not limited to being located within the amorphous region 186. As a result, the reduction in contact resistance between the third semiconductor material 156 and subsequently formed conductive features and between the second semiconductor material 154 and the first semiconductor material 106 can be fine-tuned. In some embodiments, the height of the doped region formed by the dopant implantation process in the Z direction is significantly greater than the height of the amorphous region 186. In some embodiments, when the amorphization process is performed after the dopant implantation process, the process temperature of the amorphization process is lower than the process temperature of the amorphization process performed before the dopant implantation process. The lower process temperature can reduce the risk of damaging the gate electrode layer 172.

[0072] In some embodiments, no dopant implantation process is performed.

[0073] After the amorphization process (with or without the dopant implantation process), an annealing process is performed to recrystallize the amorphous region 186. In some embodiments, the annealing process recrystallizes any amorphous source / drain region. For example, the annealing process can reorder the crystal structure of the amorphous region 186, redistributing the dopant atoms (e.g., the first substance and the second substance) by incorporating the dopant atoms into the lattice of the third semiconductor material 156. Sorting the lattice can reduce the resistivity of the doped region. In addition, the SPER process (which includes an amorphization process that converts the crystalline region into an amorphous region and an annealing process that recrystallizes the amorphous region) can promote dopant activation. One of the reasons why the SPER process can promote dopant activation is that the dopant solubility after the SPER process may be greater than the maximum equilibrium solid solubility. Higher dopant activation also reduces resistivity. In addition, high dopant concentrations (if n-type or p-type dopants are used in the amorphization process or a dopant implantation process is performed) can result in a reduction in resistivity.

[0074] In some embodiments, Fig.19As shown, the annealing process recrystallizes a portion of the amorphous region 186. In other words, a portion of the amorphous region 186 is converted into a crystalline region 188, while a portion of the amorphous region 186 remains. In some embodiments, a portion of the amorphous region 186 in contact with the third semiconductor material 156 is recrystallized, while a portion of the amorphous region 186 exposed in the opening 180 remains amorphous. Therefore, in some embodiments, the third semiconductor material 156 includes a crystalline region 190 (which is the deposited third semiconductor material 156), a crystalline region 188, and an amorphous region 186. The crystalline region 190 includes a first dopant and has a first dopant concentration as a result of in-situ doping during the growth of the third semiconductor material 156. In some embodiments, the first substance of the amorphization process and the second substance of the dopant implantation process (if performed) are the same as the first dopant, and the crystalline region 188 includes the first dopant and has a second dopant concentration that is significantly greater than the first dopant concentration. In some embodiments, the first substance of the amorphization process is different from the first dopant, and the second substance of the dopant implantation process is the same as the first dopant. As a result, the crystal region 188 includes the first dopant and the first substance, and the dopant concentration of the first dopant is substantially the same as the first dopant concentration of the crystal region 190. In some embodiments, the first substance of the amorphization process and the second substance of the dopant implantation process are different from the first dopant, and the crystal region 188 includes the first dopant, the first substance, and the second substance, and the dopant concentration of the first dopant is substantially the same as the first dopant concentration of the crystal region 190.

[0075] Similarly, in some embodiments, the first substance of the amorphization process and the second substance of the dopant implantation process (if performed) are the same as the first dopant, and the amorphous region 188 includes the first dopant and has a second dopant concentration that is significantly greater than the first dopant concentration. In some embodiments, the first substance of the amorphization process is different from the first dopant, and the second substance of the dopant implantation process is the same as the first dopant. As a result, the amorphous region 188 includes the first dopant and the first substance, and the dopant concentration of the first dopant is substantially the same as the first dopant concentration of the crystalline region 190. In some embodiments, the first substance of the amorphization process and the second substance of the dopant implantation process are different from the first dopant, and the amorphous region 188 includes the first dopant, the first substance, and the second substance, and the dopant concentration of the first dopant is substantially the same as the first dopant concentration of the crystalline region 190.

[0076] The annealing process may be any suitable thermal process, such as rapid thermal annealing (RTA), millisecond annealing (MSA), microsecond annealing, flash annealing, laser annealing, or melt laser annealing. The annealing process may have an annealing temperature ranging from about 200 degrees Celsius to about 1200 degrees Celsius.

[0077] In some embodiments, the MSA process utilizes a laser annealing process to achieve annealing times in the millisecond range. However, it is contemplated that annealing for very short amounts of time (e.g., on a millisecond time scale) may also be performed using a flash lamp annealing process or any advanced process using suitable optical radiation.

[0078] The laser annealing process can be performed by scanning a laser beam from an energy source on the exposed surface of the third semiconductor material 156. The laser beam can be applied / scanned to each portion of the third semiconductor material 156 in sequence. The energy source can be any type of laser, such as a gas laser, an excimer laser, a solid-state laser, a fiber laser, a semiconductor laser, etc. The laser beam can have a constant energy flux. The laser beam can operate within a desired wavelength and intensity range. In some embodiments, the laser beam can have a wavelength in the range of from about 200nm to about 20 microns (e.g., from about 700nm to about 1200nm (e.g., from about 950nm to about 1000nm)) and from about 0.1W / cm 2 To about 10W / cm 2 The laser annealing process may be performed such that each portion incident with the laser beam may be instantaneously raised to a temperature of about 800 degrees Celsius or higher, such as about 850 degrees Celsius or higher, such as in a range from about 900 degrees Celsius to about 1200 degrees Celsius. During the laser annealing process, the chamber pressure may be maintained at about 10 Torr to about 850 Torr. The dwell time of the laser beam may be in a range from about 0.01 milliseconds to about 10 milliseconds, such as about 0.5 milliseconds to about 5 milliseconds, such as 0.1 milliseconds to 3 milliseconds.

[0079] As described above, in some embodiments, Fig.18 The entire amorphous region 186 is transformed into a crystalline region. In some embodiments, a portion of the amorphous region 186 is transformed into a crystalline region 188, such as Fig.19 The remaining amorphous region 186 can enhance the subsequently formed silicide layer 192 ( Fig. 20 )’s growth.

[0080] like Fig. 20 As shown, the silicide layer 192 is formed from the amorphous region 186 ( Fig.19 ). When the silicide layer 192 is formed from the amorphous region 186, the thickness of the silicide layer 192 is significantly greater than the thickness of the silicide layer formed from the crystalline region. In other words, the thickness of the amorphous region 186 is proportional to the thickness of the silicide layer 192. The thickness of the silicide layer 192 is inversely proportional to the sheet resistance R. As a result, the thick silicide layer 192 formed from the amorphous region 186 can reduce the resistance.

[0081] The silicide layer 192 can be formed by any suitable process. In some embodiments, a metal layer (not shown) is first formed on the semiconductor device structure 100. The metal layer may include Ti, Ni, Ru, Co, W or other suitable metals. In some embodiments, the metal layer is a multilayer structure. The multilayer structure may include a metal layer and a metal nitride or metal oxide layer. The metal layer may be deposited by any suitable process (e.g., ALD, CVD or PVD). After the metal layer is deposited, an annealing process is performed to react the amorphous region 186 with the metal layer to form the silicide layer 192. In some embodiments, the entire amorphous region 186 is converted into a silicide layer 192. In other words, after the silicide layer 192 is formed, there is no remaining amorphous region in the third semiconductor material 156. The silicide layer 192 may include any suitable material, such as NiSi, TiSi, CoSi, RuSi or wSi.

[0082] As described above, in some embodiments, as a result of growing the third semiconductor material 156 from the second semiconductor material 154, voids may be formed near the top of the third semiconductor material 156. In some embodiments, if the SPER process is not performed, voids may be formed at the interface between the third semiconductor material 156 and the silicide layer 192. By performing the SPER process (which forms the amorphous region 186 and partially or completely recrystallizes the amorphous region 186), the voids formed near the top of the third semiconductor material 156 may be substantially removed, and no or fewer voids will be formed at the interface between the third semiconductor material 156 and the silicide layer 192. In some embodiments, void defects may be reduced to less than about 10%, such as less than about 5%, such as less than about 1% (voids per silicide to S / D region).

[0083] In some embodiments, the silicide layer 192 converted from the amorphous region 186 includes a first dopant (as a result of in-situ doping during the growth of the third semiconductor material 156), a first substance (as a result of the amorphization process), and optionally a second substance (as a result of the dopant implantation process). In some embodiments, the first dopant and the first substance (or the second substance) include the same material. For example, the first dopant and the first substance (or the second substance) are boron. The boron from the epitaxial growth process includes two isotopes: about 20% and about 10% of the first isotopes. 10 B and about 80% 11 B. Boron from the ion implantation process or dopant implantation process of the amorphization process includes 100% 11B. Thus, in some embodiments, the silicide layer 192 includes a dopant having a first percentage of a first isotope and a second percentage of a second isotope. The crystalline region 190 of the third semiconductor material 156 includes a dopant having a third percentage of the first isotope and a fourth percentage of the second isotope. The first percentage of the first isotope may be significantly less than the third percentage of the first isotope, and the second percentage of the second isotope may be significantly greater than the fourth percentage of the second isotope. In some embodiments, the first percentage of the first isotope is in a range from about 0% to about 5%, the second percentage of the second isotope is in a range from about 95% to about 100%, the third percentage of the first isotope is in a range from about 15% to about 25%, and the fourth percentage of the second isotope is in a range from about 75% to about 85%.

[0084] After forming the silicide layer 192, unreacted portions of the metal layer (not shown) may be removed by any suitable process (e.g., a selective etching process). Conductive features are then formed in the openings 180 in contact with the silicide layer 192. The contact resistance between the S / D region (third semiconductor material 156) and the conductive features is reduced due to the thicker silicide layer 192, the higher dopant activation in the crystalline region 188 of the third semiconductor material 156, and the higher dopant concentration in the crystalline region 188 of the third semiconductor material 156.

[0085] In some embodiments, the contact resistance between the conductive feature and the n-type FET is different from the contact resistance between the conductive feature and the p-type FET. For example, in some embodiments, the p-type FET has a higher contact resistance than the n-type FET. Therefore, in some embodiments, the SPER process and the optional dopant implantation process are performed on one type of FET, while the other type of FET is covered by the mask layer during the SPER process and the optional dopant implantation process. In some embodiments, as Fig.21 As shown, the semiconductor device structure 100 includes a first region 202 and a second region 204. In some embodiments, the first region 202 is a p-type metal oxide semiconductor (PMOS) region, and the second region 204 is an n-type metal oxide semiconductor (NMOS) region. In some embodiments, the first region 202 is an NMOS region, and the second region 204 is a PMOS region. Although not shown to scale in some figures, the first region 202 and the second region 204 belong to a continuous substrate 101. In some embodiments, a first type device (e.g., an n-type device or a p-type device) can be formed in the first region 202, and a second type device (e.g., a p-type device or an n-type device) can be formed in the second region 204. The first type and the second type are opposite types. The N-type device can be an n-type FET, and the P-type device can be a p-type FET.

[0086] like Fig.21 As shown, in some embodiments, the SPER process and the optional dopant implantation process are performed in the first region 202, while the second region 204 is covered by a mask layer (not shown). For example, after the SPER process and the optional dopant implantation process are performed in the first region 202, the mask layer in the second region 204 is removed. Next, a process of forming a silicide layer is performed in the first region 202 and the second region 204. As a result, the silicide layer 192 formed in the first region 202 is significantly thicker than the silicide layer 193 formed in the second region 204. In addition, the dopant concentration of the silicide layer 193 is significantly greater than the dopant concentration of the silicide layer 192. The isotope distributions of the silicide layer 193 and the silicide layer 192 are also significantly different. For example, the silicide layer 192 includes significantly more isotopes from the ion implantation process and the dopant implantation process than the silicide layer 193, while the silicide layer 193 includes significantly more isotopes from the epitaxial growth process than the silicide layer 192.

[0087] In addition, the third semiconductor material 156 located in the first region 202 may include a crystalline region 188 ( Fig. 20 ), which has a dopant concentration and isotope distribution similar to that of the silicide layer 192, while the third semiconductor material 156 located in the second region 204 has a crystalline region 190 ( Fig. 20 ) with similar dopant concentrations and isotope distributions.

[0088] By performing the SPER process and the optional dopant implantation process on one of the PMOS and NMOS regions, the contact resistance between the conductive features and the S / D regions in the NMOS and PMOS regions may be substantially the same.

[0089] In some embodiments, Fig.18 As described above, the SPER process is performed on the third semiconductor material 156 to reduce the contact resistance between the conductive feature and the S / D region. In some embodiments, the SPER process is performed on both the third semiconductor material 156 and the second semiconductor material 154 to reduce the contact resistance between the S / D region and the channel region (ie, the first semiconductor layer 106). Fig. 22 As shown, an amorphous region 194 is formed on top of the third semiconductor material 156 and in the second semiconductor material 154 in contact with the topmost first semiconductor layer 106. The amorphous region 194 may be formed by Fig.18 The amorphization process described in the for forming the amorphous region 186 is formed. The dopant implantation process may be performed before or after the amorphization process. In some embodiments, the dopant implantation process is not performed.

[0090] Next, if Fig.23 As shown, you can execute Fig.19 The annealing process described above may fully or partially recrystallize the amorphous region 194 and may form a silicide layer 197. The silicide layer 197 may include the same material, dopant concentration, and isotope distribution as the silicide layer 192. Fig.23 As shown, the crystalline region 199 is located below the silicide layer 197. The crystalline region 199 includes a portion of the third semiconductor material 156 and a portion of the second semiconductor material 154 that is in contact with the topmost first semiconductor layer 106. The crystalline region 199 can be formed as a result of the recrystallization of the amorphous region 194. Therefore, the dopant activation and dopant concentration of the third semiconductor material 156 located in the crystalline region 199 are significantly greater than the dopant activation and dopant concentration of the crystalline region 191 (which is the remaining deposited third semiconductor material 156). The isotopic distribution of the third semiconductor material 156 located in the crystalline region 199 is different from the isotopic distribution of the crystalline region 191. Similarly, the dopant activation and dopant concentration of the second semiconductor material 154 located in the crystalline region 199 are significantly greater than the dopant activation and dopant concentration of the second semiconductor material 154 that is in contact with the first semiconductor layer 106 located below the topmost first semiconductor layer 106. The isotopic distribution of the second semiconductor material 154 located in the crystalline region 199 is different from the isotopic distribution of the second semiconductor material 154 in contact with the first semiconductor layer 106 located below the topmost first semiconductor layer 106 .

[0091] In some embodiments, the contact resistance between the S / D region and the channel region (all first semiconductor layers 106) is reduced by performing a SPER process on the second semiconductor material 154 in contact with all first semiconductor layers 106, while substantially not affecting the contact resistance between the S / D region and the conductive features. Fig.24 As shown, in some embodiments, amorphous regions 195 are formed adjacent to first semiconductor layer 106 and dielectric spacer 144. Each amorphous region 195 includes a portion of second semiconductor material 154 and third semiconductor material 156 located between vertically adjacent second semiconductor materials 154. Amorphous regions 195 may be formed adjacent to first semiconductor layer 106 and dielectric spacer 144. Fig.18 The amorphization process described in the foregoing for forming the amorphous region 186 is formed. The dopant implantation process may be performed before or after the amorphization process. In some embodiments, the dopant implantation process is not performed. Next, the Fig.19The annealing process described in is performed to completely recrystallize the amorphous region 195. The resulting crystalline region includes a higher dopant concentration and dopant activation, which results in a reduced contact resistance between the S / D region and the channel region. In addition, the portion of the third semiconductor material 156 located in the crystalline region has an isotopic distribution different from that of the portion of the third semiconductor material 156 located outside the crystalline region.

[0092] Embodiments of the present disclosure provide a semiconductor device structure and a method for forming the same. In some embodiments, the method includes: performing an amorphization process on a portion of the third semiconductor material 156 and / or the second semiconductor material 154. A dopant implantation process may be optionally performed before or after the amorphization process. The doped region may be greater than, equal to, or less than the amorphous region formed by the amorphization process. The amorphous region is then partially or completely recrystallized. Some embodiments may achieve advantages. For example, the partially recrystallized amorphous region enhances the growth of the silicide layer 192. In addition, the dopant concentration and dopant activation of the recrystallized region are increased, which results in a reduced contact resistance.

[0093] One embodiment is a method. The method includes: forming a fin structure from a substrate, depositing a first semiconductor material on a first semiconductor layer of the fin structure, depositing a second semiconductor material on the first semiconductor material, depositing an interlayer dielectric layer on the second semiconductor material, forming an opening in the interlayer dielectric layer to expose the second semiconductor material, and performing a dopant implantation process to form a doped region. The doped region includes a first portion of the second semiconductor material. Then, the method also includes: performing an amorphization process to form an amorphous region, and the amorphous region includes a second portion of the second semiconductor material. The method also includes performing an annealing process to recrystallize the amorphous region.

[0094] Another embodiment is a method. The method includes: forming a fin structure from a substrate, recessing a portion of the fin structure to expose a portion of the substrate, depositing a first semiconductor material over the portion of the substrate, depositing an interlayer dielectric layer over the first semiconductor material, forming an opening in the interlayer dielectric layer to expose the first semiconductor material, and performing an amorphization process to form an amorphous region. The amorphous region includes a portion of the first semiconductor material. The method also includes: performing an annealing process to convert a first portion of the amorphous region into a first crystalline region, and forming a silicide layer from a second portion of the amorphous region.

[0095] Another embodiment is a semiconductor device structure. The structure includes a plurality of semiconductor layers disposed on a substrate and a source / drain region disposed adjacent to the plurality of semiconductor layers. The source / drain region includes a first semiconductor material in contact with each of the plurality of semiconductor layers, the first semiconductor material in contact with a topmost semiconductor layer in the plurality of semiconductor layers having a first dopant concentration, and the first semiconductor material in contact with a semiconductor layer disposed below the topmost semiconductor layer in the plurality of semiconductor layers having a second dopant concentration that is significantly less than the first dopant concentration. The source / drain region also includes a second semiconductor material surrounding the first semiconductor material.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: forming a fin structure from a substrate; depositing a first semiconductor material on the first semiconductor layer of the fin structure; depositing a second semiconductor material on the first semiconductor material; depositing an interlayer dielectric layer over the second semiconductor material; forming an opening in the interlayer dielectric layer to expose the second semiconductor material; performing a dopant implantation process to form a doped region, wherein the doped region includes a first portion of the second semiconductor material; performing an amorphization process to form an amorphized region, wherein the amorphized region includes a second portion of the second semiconductor material; and An annealing process is performed to recrystallize the amorphous region.

2. The method according to claim 1, wherein: The height of the first portion of the second semiconductor material is significantly greater than the height of the second portion of the second semiconductor material.

3. The method according to claim 1, wherein: The doped regions include portions of the first semiconductor material.

4. The method according to claim 1, wherein: The amorphous region includes the first semiconductor material.

5. The method according to claim 1, wherein: The fin structure includes the first semiconductor layer, a second semiconductor layer located below the first semiconductor layer, and a third semiconductor layer located below the second semiconductor layer.

6. The method according to claim 5, further comprising: A third semiconductor material is deposited on the second semiconductor layer and a fourth semiconductor material is deposited on the third semiconductor layer, wherein the second semiconductor material is deposited on the third semiconductor material and the fourth semiconductor material.

7. The method according to claim 6, wherein: The third semiconductor layer is located outside the amorphous region.

8. A method comprising: forming a fin structure from a substrate; recessing a portion of the fin structure to expose a portion of the substrate; depositing a first semiconductor material over the portion of the substrate; depositing a first interlayer dielectric layer over the first semiconductor material; forming an opening in the interlayer dielectric layer to expose the first semiconductor material; performing an amorphization process to form an amorphous region, wherein the amorphous region includes a portion of the first semiconductor material; performing an annealing process to transform a first portion of the amorphous region into a first crystalline region; and A silicide layer is formed from a second portion of the amorphous region.

9. The method according to claim 8, wherein: The first semiconductor material includes a second crystalline region underlying the first crystalline region.

10. A semiconductor device structure, comprising: a plurality of semiconductor layers disposed on a substrate; as well as A source / drain region disposed adjacent to the plurality of semiconductor layers, wherein the source / drain region comprises: a first semiconductor material in contact with each of the plurality of semiconductor layers, wherein the first semiconductor material in contact with a topmost semiconductor layer of the plurality of semiconductor layers has a first dopant concentration, and the first semiconductor material in contact with a semiconductor layer of the plurality of semiconductor layers disposed below the topmost semiconductor layer has a second dopant concentration that is substantially less than the first dopant concentration; and A second semiconductor material surrounds the first semiconductor material.

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