Semiconductor structure and preparation method thereof

Abstract

The present invention relates to a semiconductor structure and a method for fabricating the same. The semiconductor structure comprises: a substrate, including a substrate and a trench isolation structure within the substrate, wherein the trench isolation structure defines a plurality of spaced active regions within the substrate; a transistor, comprising a gate structure located above the active region and a first doped region located on at least one side of the gate structure in a first direction, wherein the first doped region is a doped region within the active region; a dielectric layer covering the trench isolation structure and the first doped region; and a first contact structure, wherein the orthographic projection on the substrate spans the first doped region and the trench isolation structure in the first direction, penetrates the dielectric layer, extends into the trench isolation structure, and connects to the top surface and sidewalls of the first doped region. The present invention increases the distance between the first contact structure and the gate structure, thereby reducing the difficulty in fabricating the first contact structure.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In semiconductor devices, the dimensions of structures such as contact and gate structures located above the active area are typically fixed. As semiconductor devices shrink, the dimensions of the active area become increasingly smaller, increasing the difficulty of fabricating structures such as contact and gate structures above the active area. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problem that the preparation of semiconductor structures in the prior art is relatively difficult.

[0004] In order to achieve the above objectives, the present invention provides a semiconductor structure, comprising:

[0005] A base, comprising a substrate and a trench isolation structure located in the substrate, wherein the trench isolation structure defines a plurality of active areas spaced apart in the substrate;

[0006] A transistor, the transistor comprising a gate structure located on the active region and a first doped region located on at least one side of the gate structure in a first direction, the first doped region being a doped region within the active region;

[0007] a dielectric layer, covering the trench isolation structure and the first doped region;

[0008] The orthographic projection of the first contact structure on the substrate spans the first doped region and the trench isolation structure in a first direction, penetrates the dielectric layer, and extends into the trench isolation structure.

[0009] In one embodiment, the first contact structure includes a contact layer and a contact plug, the contact layer is located on the sidewall of the first doped region, the contact plug is located on the surface of the contact layer and penetrates the dielectric layer and extends into the trench isolation structure, and the contact plug is connected to the first doped region through the contact layer.

[0010] In one embodiment, the first contact structure includes an epitaxial layer, a contact layer and a contact plug, the epitaxial layer includes a first epitaxial portion and a second epitaxial portion, the first epitaxial portion is located between the trench isolation structure and the first doped region in a first direction, the second epitaxial portion is located on the surface of the first epitaxial portion and the surface of the first doped region, the contact layer covers the epitaxial layer, the contact plug is located on the contact layer, and the contact plug is connected to the first doped region through the contact layer and the epitaxial layer.

[0011] In one embodiment, the first contact structure includes an epitaxial layer, a contact layer and a contact plug, the epitaxial layer is located between the trench isolation structure and the first doped region in a first direction, the contact layer covers the epitaxial layer and the first doped region, the contact plug is located on the contact layer, and the contact plug is connected to the epitaxial layer and the first doped region through the contact layer.

[0012] In one embodiment, in the first direction, in two adjacent active regions located on both sides of the same trench isolation structure in the first direction, the orthographic projections of the first contact structures corresponding to the first doped regions close to each other on the straight line extending along the second direction do not overlap, the second direction is perpendicular to the first direction, and the second direction and the first direction are both parallel to the main surface of the substrate.

[0013] In one embodiment, the first contact structure covers a corner of the first doped region.

[0014] In one embodiment, at least two gate structures and two transistors arranged along the first direction are formed on the same active area.

[0015] The semiconductor structure further comprises:

[0016] A second doped region, shared by the two transistors and covered by the dielectric layer;

[0017] The second contact structure penetrates the dielectric layer and is connected to the second doped region.

[0018] In one embodiment, the first contact structure includes a diffusion barrier layer and a contact plug, wherein the diffusion barrier layer wraps the sidewall and bottom of the contact plug.

[0019] The present invention also provides a method for preparing a semiconductor structure, comprising:

[0020] Providing a substrate, the substrate comprising a substrate and a trench isolation structure located in the substrate, wherein the trench isolation structure defines a plurality of active areas spaced apart in the substrate;

[0021] forming a transistor on the active region, the transistor comprising a gate structure located on the active region and a first doped region located on at least one side of the gate structure in a first direction, wherein the first doped region is a doped region within the active region;

[0022] forming a dielectric material layer covering the trench isolation structure and the first doped region;

[0023] Etching the dielectric material layer located on the trench isolation structure and the first doped region to form a first sub-contact hole, wherein an orthographic projection of the first sub-contact hole on the substrate spans the first doped region and the trench isolation structure in a first direction and exposes a portion of the first doped region and a portion of the trench isolation structure, and the remaining dielectric material layer forms a dielectric layer;

[0024] Selectively etching the trench isolation structure exposed by the first sub-contact hole to form a second sub-contact hole, wherein the second sub-contact hole exposes a sidewall of the first doped region, and the second sub-contact hole and the first sub-contact hole together form a first contact hole;

[0025] A first contact structure is formed in the first contact hole.

[0026] In one embodiment, forming the first contact structure in the first contact hole includes:

[0027] forming a contact layer on the surface of the first doped region exposed by the first contact hole;

[0028] A contact plug is formed in the first contact hole, and the contact plug is connected to the first doped region through the contact layer.

[0029] In one embodiment, forming the first contact structure in the first contact hole includes:

[0030] forming an epitaxial layer on a surface of the first doped region exposed by the first contact hole, wherein the epitaxial layer fills the second sub-contact hole;

[0031] forming a contact layer on a surface of the epitaxial layer;

[0032] A contact plug is formed in the first sub-contact hole, and the contact plug is connected to the first doped region through the contact layer and the epitaxial layer.

[0033] In one embodiment, forming the first contact structure in the first contact hole includes:

[0034] forming an epitaxial layer on a surface of the first doped region exposed by the first contact hole, wherein the epitaxial layer fills the second sub-contact hole;

[0035] Etching and removing the epitaxial layer in the first sub-contact hole to expose the first doped region;

[0036] forming a contact layer on a surface of the epitaxial layer remaining in the second sub-contact hole and a surface of the exposed first doped region;

[0037] A contact plug is formed in the first sub-contact hole, and the contact plug is connected to the epitaxial layer and the first doped region through the contact layer.

[0038] In one embodiment, in two adjacent active areas located on both sides of the same trench isolation structure in the first direction, the orthographic projections of the first contact hole structures corresponding to the first doped areas close to each other on the straight line extending along the second direction do not overlap, the second direction is perpendicular to the first direction, and the second direction and the first direction are both parallel to the main surface of the substrate.

[0039] In one embodiment, the first contact structure covers a corner of the first doped region.

[0040] In one embodiment, at least two transistors arranged along the first direction are formed based on the same active area, the two transistors share a second doped region, and the dielectric material layer also covers the second doped region;

[0041] The preparation method further comprises:

[0042] Etching the dielectric material layer on the second doped region to form a second contact hole, wherein the second contact hole exposes a portion of the second doped region;

[0043] A second contact structure is formed in the second contact hole.

[0044] The semiconductor structure and preparation method of the present invention, by setting the positive projection of the first contact structure on the substrate to span the first doped region and the trench isolation structure in the first direction, and penetrate the dielectric layer and extend into the trench isolation structure to be connected with the top surface and side wall of the first doped region, can expand the distance between the first contact structure and the gate structure while maintaining or increasing the contact area between the first contact structure and the first doped region, thereby reducing the process difficulty of preparing the first contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0047] Figures 2a to 2eA schematic diagram of an intermediate structure obtained in a method for preparing a semiconductor structure provided in one embodiment;

[0048] Figures 3a to 3f A schematic diagram of an intermediate structure obtained in a method for preparing a semiconductor structure provided in another embodiment;

[0049] Figures 4a to 4g A schematic diagram of an intermediate structure obtained in a method for preparing a semiconductor structure provided in yet another embodiment;

[0050] Figure 5 is a schematic diagram of adjacent first contact structures provided in one embodiment;

[0051] Figure 6 is a schematic diagram of adjacent first contact structures provided in another embodiment;

[0052] Figure 7 is a schematic diagram of a cross-section of a semiconductor structure provided in one embodiment;

[0053] Figure 8 FIG. 1 is a schematic diagram of a cross-section of a semiconductor structure provided in another embodiment.

[0054] Explanation of the accompanying drawings: substrate-110; active area-111; trench isolation structure-112; transistor-120; gate structure-121; gate-1211; gate dielectric layer-1212; sidewall spacer-1213; first doped region-122; second doped region-123; dielectric layer-130; first contact structure-140; second contact structure-141; diffusion barrier layer-141; contact plug-142; contact layer-150; epitaxial layer-160; first contact hole-200; first sub-contact hole-210; second sub-contact hole-220; second contact hole-300. DETAILED DESCRIPTION

[0055] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0057] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it can be directly on, adjacent to, or connected to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0058] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0059] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the invention.

[0061] In one embodiment, see Figure 1 The present invention provides a method for preparing a semiconductor structure, wherein the intermediate structure obtained is shown in FIG. Figures 2a to 2e , Figures 3a to 3f as well as Figures 4a to 4g The method for preparing a semiconductor structure comprises the following steps:

[0062] Step S100 : providing a substrate 110 , the substrate 110 including a substrate and a trench isolation structure 112 located in the substrate, the trench isolation structure 112 defining a plurality of active regions 111 spaced apart in the substrate.

[0063] Step S200 : forming a transistor 120 on the active region 111 . The transistor 120 includes a gate structure 121 on the active region 111 and a first doped region 122 located on at least one side of the gate structure 121 in a first direction. The first doped region 122 is a doped region within the active region 111 .

[0064] Step S300 : forming a dielectric material layer covering the trench isolation structure 112 and the first doped region 122 .

[0065] Step S400: Etching the dielectric material layer located on the trench isolation structure 112 and the first doped region 122 to form a first sub-contact hole 210. The orthographic projection of the first sub-contact hole 210 on the substrate 110 spans the first doped region 122 and the trench isolation structure 112 in the first direction, and exposes a portion of the first doped region 122 and a portion of the trench isolation structure 112. The remaining dielectric material layer forms a dielectric layer 130.

[0066] Step S500 : selectively etching the trench isolation structure 112 exposed by the first sub-contact hole 210 to form a second sub-contact hole 220 . The second sub-contact hole 220 exposes the sidewall of the first doped region 122 . The second sub-contact hole 220 and the first sub-contact hole 210 together form the first contact hole 200 .

[0067] Step S600 : forming a first contact structure 140 in the first contact hole 200 .

[0068] In step S100, the substrate may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. As an example, the substrate may include a silicon substrate, a silicon-germanium substrate, a silicon-germanium-carbon substrate, etc.

[0069] A trench isolation structure 112 is provided in the substrate. When forming the trench isolation structure 112, the original substrate can be etched first to form a plurality of spaced shallow trenches in the substrate. The shallow trenches are then filled to form the trench isolation structure 112. As an example, the trench isolation structure 112 can be a shallow trench isolation (STI) structure. The material of the trench isolation structure 112 is an insulating material. For example, the material of the trench isolation structure 112 is silicon oxide, silicon nitride, or silicon oxynitride. Of course, the trench isolation structure 112 can be provided with multiple film layers. For example, the trench isolation structure 112 can be provided with a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer in sequence from the sidewall of the trench isolation structure 112.

[0070] The trench isolation structure 112 extends from the upper surface of the substrate into the substrate and defines a plurality of spaced active areas 111 (AA) in the substrate. It is understood that the substrate between adjacent trench isolation structures 112 may be the active area 111 .

[0071] In step S200, transistor 120 includes a gate structure 121, a source, and a drain. Gate structure 121 includes a gate 1211, a gate dielectric layer 1212, and spacers 1213. Gate dielectric layer 1212 is located between gate 1211 and active region 111. By way of example, gate dielectric layer 1212 can be formed of a material with a high-k dielectric constant. For example, materials for gate dielectric layer 1212 include aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0072] The gate 1211 may include, but is not limited to, any one or more of polysilicon, titanium nitride, titanium, tungsten nitride, and tungsten. The material of the spacer 1213 includes at least one of silicon oxide and silicon nitride. For example, the spacer 1213 may have a NON (silicon nitride-silicon oxide-silicon nitride) structure, but is not limited thereto.

[0073] The first doped region 122 located on one side of the gate structure 121 in the first direction is one of the source and the drain. When a transistor 120 is formed on the same active region 111, the same active region 111 includes two first doped regions 122. In this case, the first doped region 122 located on the other side of the gate structure 121 in the first direction is the other of the source and the drain. As an example, Figure 2a The X direction is the first direction.

[0074] When forming the first doped region 122, ion implantation or high-temperature diffusion can be used to introduce N-type ions or P-type ions into the active region 111 to form the first doped region 122. As an example, the P-type impurity ions may include, but are not limited to, any one or more of boron ions, gallium ions, or indium ions. Similarly, the N-type impurity ions may include, but are not limited to, any one or more of phosphorus ions, arsenic ions, or antimony ions.

[0075] In step S300 , a dielectric material layer covers the trench isolation structure 112 and the first doped region 122 . Meanwhile, the dielectric material layer also covers the gate structure 121 .

[0076] The dielectric material layer may be formed using a deposition process, which may include, but is not limited to, one or more of chemical vapor deposition, atomic layer deposition, high-density plasma deposition, plasma-enhanced deposition, and spin-on dielectric layer processes.

[0077] The dielectric material layer may include one or more insulating materials such as silicon oxide or silicon nitride. The dielectric material layer may have a single-layer structure or a multi-layer structure. As an example, the dielectric material layer may include a second silicon nitride layer, a third silicon oxide layer, and a third silicon nitride layer disposed sequentially from the surface.

[0078] In step S400, the dielectric material layer located on the trench isolation structure 112 and the first doped region 122 may be etched using a dry etching method to form the first sub-contact hole 210, and the remaining dielectric material layer forms the dielectric layer 130. For example, the dry etching method may include at least any one of reactive ion etching, inductively coupled plasma etching, or high concentration plasma etching.

[0079] The first sub-contact hole 210 extends from the upper surface of the dielectric material layer to the first doped region 122 and the trench isolation structure 112. The orthographic projection of the first sub-contact hole 210 on the substrate 110 spans the first doped region 122 and the trench isolation structure 112 in a first direction. The orthographic projection of the first sub-contact hole 210 on the substrate 110 is a perpendicular projection from the upper surface of the dielectric layer 130 toward the substrate. The projection of the first sub-contact hole 210 simultaneously covers the adjacent portions of the first doped region 122 and the trench isolation structure 112.

[0080] The first sub-contact hole 210 also exposes a portion of the first doped region 122 and a portion of the trench isolation structure 112. As an example, the first sub-contact hole 210 exposes the first doped region 122 near the top of the trench isolation structure 112, and at the same time, the first sub-contact hole 210 exposes the top of the trench isolation structure 112 near the first doped region 122.

[0081] In step S500, the trench isolation structure 112 exposed by the first sub-contact hole 210 is selectively etched to form the second sub-contact hole 220. As an example, an etching method having a large etching ratio between the material of the trench isolation structure 112 and the material of the active area 111 can be used to remove the trench isolation structure 112 exposed by the first sub-contact hole 210, while retaining the active area 111 exposed by the first sub-contact hole 210.

[0082] After selectively etching the trench isolation structure 112 exposed by the first sub-contact hole 210, the second sub-contact hole 220 exposes more of the sidewall of the first doped region 122 facing the trench isolation structure 112. It can be understood that the second sub-contact hole 220 extends from the bottom of the first sub-contact hole 210 into the trench isolation structure 112. As an example, the depth of the second sub-contact hole 220 ranges from 3nm to 12nm. For example, the depth of the second sub-contact hole 220 ranges from 5nm to 10nm. The above data are for example only, and in actual embodiments, the depth of the second sub-contact hole 220 is not limited to the above data.

[0083] The second sub-contact hole 220 is connected to the first sub-contact hole 210 , and together they form the first contact hole 200 .

[0084] In step S600 , as an example, the first contact structure 140 may include a diffusion barrier layer 141 and a contact plug 142 . The diffusion barrier layer 141 wraps around the sidewalls and bottom of the contact plug 142 . The diffusion barrier layer 141 prevents ions of the contact plug 142 from diffusing into the dielectric layer 130 .

[0085] As an example, the diffusion barrier layer 141 may include titanium or titanium nitride, etc. The contact plug 142 may include a conductive material such as tungsten, aluminum, or copper.

[0086] The diffusion barrier layer 141 may be located on the sidewall of the first contact hole 200 , or may be located on the upper surface of the dielectric layer 130 .

[0087] In this embodiment, by forming the first sub-contact hole 210 and the second sub-contact hole 220, and by having the orthographic projection of the first sub-contact hole 210 on the substrate 110 span the first doped region 122 and the trench isolation structure 112 in the first direction, the distance between the first contact structure 140 and the gate structure 121 can be effectively increased within an active area of ​​the same size, thereby reducing the process difficulty of fabricating the first contact structure 140. Furthermore, when the distance between the gate structure 121 and the first contact structure 140 is the same, this embodiment can effectively reduce the size of the active area 111, thereby increasing the device arrangement density.

[0088] In addition, the second sub-contact hole 220 exposes the sidewall of the first doped region 122, and the first contact structure 140 is located in the second sub-contact hole 220 and the first sub-contact hole 210, thereby ensuring that the first contact structure 140 has sufficient contact area with the active region 111, thereby ensuring the performance of the semiconductor structure.

[0089] In one embodiment, step S600 includes:

[0090] Step S610 : forming a contact layer 150 on the surface of the first doped region 122 exposed by the first contact hole 200 .

[0091] Step S611 : forming a contact plug 142 in the first contact hole 200 , wherein the contact plug 142 is connected to the first doped region 122 through the contact layer 150 .

[0092] In step S610 , the contact layer 150 is located on the surface of the first doped region 122 . The contact layer 150 can reduce the contact resistance between the subsequently formed contact plug 142 and the first doped region 122 .

[0093] The material of the contact layer 150 may include metal silicide, such as cobalt silicide, titanium silicide, nickel silicide, etc.

[0094] As an example, when forming the contact layer 150, a metal layer can be formed within the first contact hole 200 and subjected to a first rapid thermal annealing process. Subsequently, the metal layer outside the surface of the first doped region 122 is etched away, leaving the metal layer on the surface of the first doped region 122. Finally, the structure is subjected to a second rapid thermal annealing process.

[0095] During the first rapid thermal annealing process, the metal layer may react with the semiconductor material in the first doped region 122 to form a transitional electrical contact layer. For example, the metal layer may react with the silicon material in the first doped region 122 to form a metal silicide layer. At this point, the transitional electrical contact layer has a relatively high resistance.

[0096] After the first rapid thermal annealing, the metal layer that has not participated in the first rapid thermal annealing reaction can be removed by wet etching, that is, the metal layer away from the first doping region 122 can be removed by wet etching. In this way, the metal silicide layer remains on the surface of the first doping region 122. At this time, as an example, refer to Figure 3e , the metal silicide layer (contact layer 150) may also be located on the top surface of the epitaxial layer 160. In another example, see Figure 4e The metal silicide layer (contact layer 150 ) is located on both the top surface of the epitaxial layer 160 and the top surface of the contact layer 150 .

[0097] During the second rapid thermal annealing process, the transitional electrical contact layer 150 may be transformed into a contact layer 150 having a lower resistance. In this case, the contact layer 150 having a lower resistance may reduce the contact resistance between the first doped region 122 and the contact plug 142 .

[0098] In step S611 , the contact plug 142 is connected to the first doped region 122 through the contact layer 150 .

[0099] In this embodiment, a contact layer 150 is formed on the surface of the first doped region 122 exposed by the first contact hole 200 . The contact layer 150 can reduce the contact resistance between the first doped region 122 and the contact plug 142 .

[0100] In one embodiment, see Figures 3c to 3f , step S600 includes:

[0101] Step S620 : forming an epitaxial layer 160 on the surface of the first doped region 122 exposed by the first contact hole 200 , and filling the second sub-contact hole 220 with the epitaxial layer 160 .

[0102] Step S621 : forming a contact layer 150 on the surface of the epitaxial layer 160 .

[0103] Step S622 : forming a contact plug 142 in the first sub-contact hole 210 , wherein the contact plug 142 is connected to the first doped region 122 through the contact layer 150 and the epitaxial layer 160 .

[0104] In step S620, an epitaxial layer 160 is grown on the surface of the first doping region 122. The epitaxial layer 160 may be a doped semiconductor layer. The doping type of the epitaxial layer 160 is the same as the doping type of the first doping region 122. For example, when the doping ions in the first doping region 122 are P-type ions, the epitaxial layer 160 is also doped with P-type ions.

[0105] As an example, the material of the active region 111 and the epitaxial layer 160 may be silicon or the like.

[0106] After epitaxial growth, the epitaxial layer 160 may also fill the second sub-contact hole 220 and be located on the upper surface of the first doped region 122 .

[0107] In step S621, a contact layer 150 is formed on the surface of the epitaxial layer 160. The step of forming the contact layer 150 may be similar to the step of forming the contact layer 150 in step S610. For example, see Figure 3d A metal layer is formed on the surface of the epitaxial layer 160 , and then the metal layer is subjected to a first rapid thermal annealing process and a second rapid thermal annealing process, so that the metal layer can react with the semiconductor material in the epitaxial layer 160 to form a metal silicide layer (contact layer 150 ).

[0108] In step S622 , a contact plug 142 is formed in the first sub-contact hole 210 , and the contact plug 142 is connected to the first doped region 122 through the contact layer 150 and the epitaxial layer 160 .

[0109] In this embodiment, an epitaxial layer 160 is formed to fill the second sub-contact hole 220. The epitaxial layer 160 and the first doped region 122 can be considered as the source region or drain region of the transistor. At the same time, a contact layer 150 is formed on the surface of the epitaxial layer 160, so that the contact plug 142 is effectively electrically connected to the source region or drain region of the transistor through the contact layer 150.

[0110] In one embodiment, see Figures 4c to 4g , step S600 includes:

[0111] Step S630 : forming an epitaxial layer 160 on the surface of the first doped region 122 exposed by the first contact hole 200 , and filling the second sub-contact hole 220 with the epitaxial layer 160 .

[0112] Step S631 : etching and removing the epitaxial layer 160 located in the first sub-contact hole 210 to expose the first doped region 122 .

[0113] Step S632 : forming a contact layer 150 on the surface of the epitaxial layer 160 remaining in the second sub-contact hole 220 and the surface of the exposed first doped region 122 .

[0114] Step S633 : forming a contact plug 142 in the first sub-contact hole 210 , wherein the contact plug 142 is connected to the epitaxial layer 160 and the first doped region 122 through the contact layer 150 .

[0115] In step S630, an epitaxial layer 160 is grown on the surface of the first doping region 122. After epitaxial growth, the epitaxial layer 160 can fill the second sub-contact hole 220 and be higher than the upper surface of the first doping region 122.

[0116] In step S631 , the epitaxial layer 160 at the bottom of the first sub-contact hole 210 is removed by etching to expose the first doped region 122 . The remaining epitaxial layer 160 is located in the second sub-contact hole 220 and between the sidewall of the first doped region 122 and the trench isolation structure 112 .

[0117] In step S632, a contact layer 150 is formed on the surface of the epitaxial layer 160 located in the second sub-contact hole 220 and the surface of the exposed first doped region 122. The step of forming the contact layer 150 may be similar to the step of forming the contact layer 150 in step S610. For example, see Figure 4dA metal layer is formed on the top surface of the remaining epitaxial layer 160 and the surface of the first doped region 122, and then the metal layer is subjected to a first rapid thermal annealing treatment and a second rapid thermal annealing treatment, so that the metal layer can react with the semiconductor material on the top surface of the remaining epitaxial layer 160 to form a metal silicide layer (contact layer 150). At the same time, the metal layer also reacts with the semiconductor material in the first doped region 122 to form a metal silicide layer (contact layer 150).

[0118] In step S633 , a contact plug 142 is formed in the first sub-contact hole 210 . At this time, the contact plug 142 is connected to the epitaxial layer 160 and the first doped region 122 through the contact layer 150 .

[0119] In this embodiment, the epitaxial layer 160 located within the first sub-contact hole 210 is removed by etching, thereby leaving the remaining epitaxial layer 160 within the second sub-contact hole 220. At this time, when the bottom surface of the first sub-contact hole 220 is lower than the upper surface of the first doped layer, a uniform contact layer 150 is formed on the surface of the first doped region 122 located at the bottom and sidewalls of the first sub-contact hole 220, thereby effectively increasing the area of ​​the contact layer 150 and further effectively reducing the contact resistance between the contact plug 142 and the first doped region 122.

[0120] In one embodiment, in two adjacent active regions 111 located on both sides of the same trench isolation structure 112 in the first direction, the orthographic projections of the first contact hole structures 140 corresponding to the adjacent first doped regions 122 on the straight line extending along the second direction do not overlap.

[0121] See also Figure 5 , the second direction is perpendicular to the first direction, and both the second direction and the first direction are parallel to the main surface of the substrate 110. As an example, Figure 5 The Y direction is the second direction, and the straight line AB is a straight line extending from the second direction.

[0122] The orthographic projections of the two first contact structures 140 on the straight line extending along the second direction may be projections of the two first contact structures 140 respectively extending in the second direction, and the projections do not overlap. As an example, the orthographic projections of the two first contact structures 140 on the straight line extending along the second direction may be projections of the two first contact structures 140 respectively onto the straight line AB.

[0123] Because the first contact structure 140 spans the first doped region and the trench isolation structure in the first direction, the distance between two adjacent active regions 111 in the first direction and the first contact structure 140 is shortened. When a voltage is applied to the first contact structure 140, coupling interference may occur between the two adjacent active regions 111 and the first contact structure 140, thereby affecting the normal operation of the semiconductor device.

[0124] In this embodiment, by staggering the first contact structures 140 corresponding to the adjacent first doped regions 122 of two adjacent active regions 111 in the second direction, short circuits or coupling interference can be prevented between the first contact structures 140 that are too close to each other.

[0125] For further information, see Figure 6 , the first contact structure 140 covers a corner of the first doping region 122 .

[0126] During the actual fabrication process, the active region 111 may have rounded corners. In a top view, the corners of the active region 111 may be arc-shaped. At this time, the first contact structure 140 covers a corner of the first doped region 122 .

[0127] In this embodiment, the arrangement 140 covers a corner of the first doped region 122 , thereby increasing the contact area between the first contact structure 140 and the active region 111 , thereby reducing the contact resistance between the first contact structure 140 and the first doped region 122 .

[0128] In one embodiment, when at least two transistors arranged along a first direction are formed based on the same active region 111, the two transistors 120 share a second doping region 123. In this case, along the first direction, the first doping region 122, the second doping region 123, and the first doping region 122 are arranged in sequence. In this case, the doping type of the second doping region 123 is the same as the doping type of the first doping region 122.

[0129] In step S300 , the dielectric material layer covers the first doping region 122 and the second doping region 123 .

[0130] The method for preparing a semiconductor structure includes:

[0131] Step S40 : etching the dielectric material layer on the second doping region 123 to form a second contact hole 300 , wherein the second contact hole 300 exposes a portion of the second doping region 123 .

[0132] Step S60 : forming a second contact structure 141 in the second contact hole 300 .

[0133] In step S40, the second contact hole 300 extends from the upper surface of the dielectric material layer to the second doped region 123. At this point, etching the second contact hole 300 may remove a portion of the material located on top of the second doped region 123. At this point, the bottom surface of the second contact hole 300 is lower than the upper surface of the second doped layer. Alternatively, etching the second contact hole 300 may stop at the second doped region 123.

[0134] As an example, step S40 can be performed simultaneously with step S400. At this point, the bottom surface of the first sub-contact hole 210 is lower than the upper surface of the first doped region 122. Thus, when forming the contact layer 150 or the epitaxial layer 160 on the surface of the first doped region 122, the bottom surface of the first sub-contact hole 210 is lower than the upper surface of the first doped region 122, thereby increasing the contact area with both, thereby further reducing the contact resistance.

[0135] Of course, step S40 and step S400 can also be performed separately. This embodiment does not limit the order of step S40 and step S400.

[0136] In step S60, a second contact structure 141 is formed in the second contact hole 300. The second contact structure 141 may include a diffusion barrier layer 141 and a contact plug 142. The diffusion barrier layer 141 wraps around the sidewalls and bottom of the contact plug 142.

[0137] As an example, step S60 can be performed simultaneously with step S600. Of course, step S60 can also be performed separately from step S600. This embodiment does not limit the order of step S60 and step S600.

[0138] Because a portion of the material located at the top of the second doped region 123 is removed during the formation of the second contact hole 300, when the contact layer 150 is formed at the bottom of the second contact hole 300, the bottom surface of the second contact hole 300 is lower than the top surface of the second doped layer. This increases the contact area between the contact layer 150 and the second doped region 123, thereby increasing the contact area between the bottom of the second contact structure 141 and the contact layer 150, further reducing the contact resistance between the second contact structure 141 and the second doped region 123.

[0139] Also, see Figures 3c to 3f In step S620 and step S630 , when the epitaxial layer 160 is formed on the surface of the first doped region 122 exposed by the first contact hole 200 , the epitaxial layer 160 may also be formed on the surface of the second doped region 123 exposed by the second contact hole 300 .

[0140] Also, see Figures 4c to 4g In step S631, when the epitaxial layer 160 located in the first sub-contact hole 210 is removed by etching, the epitaxial layer 160 located in the second contact hole 300 is also removed. In step S632, when the contact layer 150 is formed on the surface of the epitaxial layer 160 remaining in the second sub-contact hole 220 and the surface of the exposed first doped region 122, the contact layer 150 is also formed on the surface of the second doped region 123 exposed in the second contact hole 300.

[0141] It should be understood that although Figure 1The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0142] Please continue reading Figure 2e 、 Figure 3f as well as Figure 4g In one embodiment, the present invention further provides a semiconductor structure including: a substrate 110 , a transistor 120 , a dielectric layer 130 and a first contact structure 140 .

[0143] The base 110 includes a substrate and a trench isolation structure 112 located within the substrate. The trench isolation structure 112 is made of an insulating material. For example, the trench isolation structure 112 is made of silicon oxide, silicon nitride, or silicon. Of course, the trench isolation structure 112 may be formed of multiple film layers.

[0144] The trench isolation structure 112 defines a plurality of active regions 111 spaced apart in the substrate. The active regions 111 extend along a first direction.

[0145] The transistor 120 includes a gate structure 121 located on the active region 111 and a first doped region 122 located on at least one side of the gate structure 121 in a first direction.

[0146] The gate structure 121 includes a gate 1211, a gate dielectric layer 1212, and spacers 1213. The gate dielectric layer 1212 is located between the gate 1211 and the active region 111. As an example, the gate dielectric layer 1212 can be formed of a material with a high-k dielectric constant. For example, the material of the gate dielectric layer 1212 includes aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, or strontium titanium oxide.

[0147] The gate 1211 may include, but is not limited to, any one or more of polysilicon, titanium nitride, titanium, tungsten silicide, and tungsten. The material of the spacer 1213 includes at least one of silicon oxide and silicon nitride. For example, the spacer 1213 may have a NON (silicon nitride-silicon oxide-silicon nitride) structure, but is not limited thereto.

[0148] The first doped region 122 located on one side of the gate structure 121 in the first direction serves as one of the source and drain of the transistor 120. When one transistor 120 is formed on the same active region 111, the same active region 111 includes two first doped regions 122. In this case, the first doped region 122 located on the other side of the gate structure 121 in the first direction serves as the other of the source and drain.

[0149] The doping ions of the first doping region 122 are N-type ions or P-type ions. As an example, the P-type impurity ions may include, but are not limited to, any one or more of boron ions, gallium ions, or indium ions. Similarly, the N-type impurity ions may include, but are not limited to, any one or more of phosphorus ions, arsenic ions, or antimony ions.

[0150] The dielectric layer 130 covers the trench isolation structure 112 and the first doped region 122 . The dielectric layer 130 also covers the gate structure 121 .

[0151] The dielectric layer 130 may be made of one or more insulating materials such as silicon oxide or silicon nitride. The dielectric layer 130 may have a single-layer structure or a multi-layer structure. For example, the dielectric material layers may include a second silicon nitride layer, a third silicon oxide layer, and a third silicon nitride layer, disposed sequentially from the surface.

[0152] The first contact structure 140 extends from the upper surface of the dielectric layer 130 inwardly through the dielectric layer 130 into the trench isolation structure 112 .

[0153] The orthographic projection of the bottom wall of the first contact structure 140 on the substrate 110 spans the first doped region 122 and the trench isolation structure 112 in the first direction. It can be understood that the first contact structure 140 is connected to the top surface of the first doped region 122.

[0154] As an example, the first contact structure 140 includes a first substructure and a second substructure that are connected to each other. The first substructure penetrates the dielectric layer 130 , and the second substructure is located between the first doped region 122 and the trench isolation structure 112 .

[0155] As an example, the first contact structure 140 may include a diffusion barrier layer 141 and a contact plug 142 . The diffusion barrier layer 141 wraps around the sidewalls and bottom of the contact plug 142 . The diffusion barrier layer 141 prevents ions of the contact plug 142 from diffusing into the dielectric layer 130 .

[0156] As an example, the diffusion barrier layer 141 may include titanium or titanium nitride, etc. The contact plug 142 may include a conductive material such as tungsten, aluminum, or copper.

[0157] The diffusion barrier layer 141 may be located on the sidewall of the first contact hole 200 , or may be located on the upper surface of the dielectric layer 130 .

[0158] In this embodiment, by providing a first contact structure 140 connected to the top surface of the first doped region 122, the distance between the first contact structure 140 and the gate structure 121 can be effectively increased within an active region of the same size, thereby reducing the difficulty of manufacturing the first contact structure 140. Furthermore, when the distance between the gate structure 121 and the first contact structure 140 is the same, this embodiment can effectively reduce the size of the active region 111, thereby increasing the device arrangement density.

[0159] In one embodiment, the first contact structure 140 includes a contact layer 150 and a contact plug 142 .

[0160] The contact layer 150 extends from the top surface of the first doped region 122 to the sidewalls of the first doped region 122. The contact plug 142 is located on the surface of the contact layer 150, penetrates the dielectric layer 130, and extends into the trench isolation structure 112. At this time, the contact plug 142 is connected to the first doped region 122 through the contact layer 150. As an example, the material of the contact layer 150 can be cobalt silicide, titanium silicide, nickel silicide, etc.

[0161] In this embodiment, the contact layer 150 is located on the surface of the first doped region 122 . The contact layer 150 can reduce the contact resistance between the contact plug 142 and the active region 111 .

[0162] Furthermore, the contact plug 142 extends into the trench isolation structure 112 , thereby ensuring that the first contact structure 140 and the active region 111 have sufficient contact area, thereby ensuring the performance of the semiconductor structure.

[0163] In one embodiment, the first contact structure 140 includes an epitaxial layer 160 , a contact layer 150 , and a contact plug 142 .

[0164] The epitaxial layer 160 includes a first epitaxial portion and a second epitaxial portion. The first epitaxial portion is located between the trench isolation structure 112 and the first doped region 122 in the first direction, and the second epitaxial portion is located above the first epitaxial portion.

[0165] The doping type of the epitaxial layer 160 is the same as the doping type of the first doping region 122. As an example, when the doping ions of the first doping region 122 are P-type ions, the epitaxial layer 160 is also doped with P-type ions.

[0166] The contact layer 150 covers the epitaxial layer 160 . As an example, the contact layer 150 covers the second epitaxial portion. The contact plug 142 is located on the contact layer 150 . The contact plug 142 is connected to the first doped region 122 through the contact layer 150 and the epitaxial layer 160 .

[0167] In this embodiment, by providing the first epitaxial portion and the second epitaxial portion, and with the contact layer 150 covering the epitaxial layer 160, the contact plug 142 is connected to the first doped region 122 through the contact layer 150 and the epitaxial layer 160. The epitaxial layer 160 and the contact layer 150 further reduce the contact resistance between the contact plug 142 and the first doped region 122.

[0168] In one embodiment, the first contact structure 140 includes an epitaxial layer 160 , a contact layer 150 , and a contact plug 142 .

[0169] Epitaxial layer 160 is located between trench isolation structure 112 and first doped region 122 in the first direction, and contact layer 150 covers epitaxial layer 160 and first doped region 122. Contact plug 142 is located on contact layer 150 and is connected to epitaxial layer 160 and first doped region 122 through contact layer 150.

[0170] Likewise, the contact plug 142 is connected to the first doped region 122 through the contact layer 150 and the epitaxial layer 160 . Both the epitaxial layer 160 and the contact layer 150 reduce the contact resistance between the contact plug 142 and the first doped region 122 .

[0171] In one embodiment, see Figure 5 In two adjacent active regions 111 located on both sides of the same trench isolation structure 112 in the first direction, the orthographic projections of the first contact hole structures 140 corresponding to the first doped regions 122 close to each other on the straight line extending along the second direction do not overlap.

[0172] The second direction is perpendicular to the first direction, and both the second direction and the first direction are parallel to the main surface of the substrate 110. As an example, as an example, Figure 5 The Y direction is the second direction, and the straight line AB is a straight line extending from the second direction.

[0173] The orthographic projections of the two first contact structures 140 on the straight line extending along the second direction may be projections of the two first contact structures 140 respectively extending in the second direction, and the projections do not overlap. As an example, the orthographic projections of the two first contact structures 140 on the straight line extending along the second direction may be projections of the two first contact structures 140 respectively onto the straight line AB.

[0174] In this embodiment, the first contact structures 140 corresponding to the first doped regions 122 close to each other of two adjacent active regions 111 are staggered in the second direction, thereby increasing the distance between the two first contact structures 140 and preventing coupling interference between first contact structures 140 that are too close.

[0175] In one embodiment, see Figure 6, the first contact structure 140 covers a corner of the first doping region 122 .

[0176] During the actual fabrication process, the active region 111 may have rounded corners. In a top view, the corners of the active region 111 may be arc-shaped. The first contact structure 140 covers a corner of the first doped region 122 .

[0177] In this embodiment, the arrangement 140 covers a corner of the first doped region 122 , thereby increasing the contact area between the first contact structure 140 and the active region 111 , thereby reducing the contact resistance between the first contact structure 140 and the first doped region 122 .

[0178] In one embodiment, when at least two transistors arranged along the first direction are formed based on the same active region 111 , the semiconductor structure further includes a second doped region 123 and a second contact structure 141 .

[0179] The two transistors 120 share one second doping region 123. At this time, along the first direction, the first doping region 122, the second doping region 123 and the first doping region 122 are arranged in sequence.

[0180] The dielectric layer 130 covers the first doping region 122 and the second doping region 123 .

[0181] The second contact structure 141 penetrates the dielectric layer 130 and is connected to the second doped region 123. The bottom surface of the second contact structure 141 is lower than the top surface of the second doped region 123. The second contact structure 141 may include a diffusion barrier layer 141 and a contact plug 142. The diffusion barrier layer 141 wraps around the sidewalls and bottom of the contact plug 142.

[0182] The contact layer 150 is located at the bottom of the second contact structure 141 , and reduces the contact resistance between the second contact structure 141 and the second doped region 123 .

[0183] See also Figure 7 As an example, when the distance between the gate structure 121 and the first contact structure 140 is the same, the present embodiment can reduce the size of the active region 111 . Figure 7 In FIG. 1 , the length of the line segment X is the reduced side length of the active region 111 of this embodiment compared to the active region 111 of the conventional technology. For example, the side length of the active region 111 can be reduced by 10 nm to 20 nm.

[0184] See also Figure 8 As another example, when the size of the active region 111 remains unchanged, this embodiment allows the distance between the first contact structure 140 and the gate structure 121 to be increased, thereby effectively preventing a short circuit between the two. Figure 8In FIG. 1 , the length of line segment Y is the length by which the distance between adjacent gate structures 121 in this embodiment is increased relative to the distance between adjacent gate structures in conventional technology. For example, the distance between adjacent gate structures 121 may be increased by 5 nm to 10 nm.

[0185] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0186] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A base, comprising a substrate and a trench isolation structure located in the substrate, wherein the trench isolation structure defines a plurality of active areas spaced apart in the substrate; A transistor, the transistor comprising a gate structure located on the active region and a first doped region located on at least one side of the gate structure in a first direction, the first doped region being a doped region within the active region; a dielectric layer, covering the trench isolation structure and the first doped region; a first contact structure, an orthographic projection of which on the substrate spans the first doped region and the trench isolation structure in a first direction, penetrates the dielectric layer, and extends into the trench isolation structure; In which, in the two adjacent active areas located on both sides of the same trench isolation structure in the first direction, the orthographic projections of the first contact structures corresponding to the first doping areas close to each other on the straight line extending along the second direction do not overlap, the second direction is perpendicular to the first direction, and the second direction and the first direction are both parallel to the main surface of the substrate.

2. The semiconductor structure according to claim 1, wherein: The first contact structure includes a contact layer and a contact plug. The contact layer is located on the sidewall of the first doped region. The contact plug is located on the surface of the contact layer and penetrates the dielectric layer and extends into the trench isolation structure. The contact plug is connected to the first doped region through the contact layer.

3. The semiconductor structure according to claim 1, wherein: The first contact structure includes an epitaxial layer, a contact layer and a contact plug, the epitaxial layer includes a first epitaxial portion and a second epitaxial portion, the first epitaxial portion is located between the trench isolation structure and the first doped region in a first direction, the second epitaxial portion is located on the surface of the first epitaxial portion and the surface of the first doped region, the contact layer covers the epitaxial layer, the contact plug is located on the contact layer, and the contact plug is connected to the first doped region through the contact layer and the epitaxial layer.

4. The semiconductor structure according to claim 1, wherein: The first contact structure includes an epitaxial layer, a contact layer and a contact plug, the epitaxial layer is located between the trench isolation structure and the first doped region in a first direction, the contact layer covers the epitaxial layer and the first doped region, the contact plug is located on the contact layer, and the contact plug is connected to the epitaxial layer and the first doped region through the contact layer.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The first contact structure covers a corner of the first doping region.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: At least two transistors arranged along the first direction are formed based on the same active area. The semiconductor structure further comprises: A second doped region, shared by the two transistors and covered by the dielectric layer; The second contact structure penetrates the dielectric layer and is connected to the second doped region.

7. The semiconductor structure according to any one of claims 2 to 4, characterized in that: The first contact structure further includes a diffusion barrier layer, which wraps the sidewall and bottom of the contact plug.

8. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a trench isolation structure located in the substrate, wherein the trench isolation structure defines a plurality of active areas spaced apart in the substrate; forming a transistor on the active region, the transistor comprising a gate structure located on the active region and a first doped region located on at least one side of the gate structure in a first direction, wherein the first doped region is a doped region within the active region; forming a dielectric material layer covering the trench isolation structure and the first doped region; Etching the dielectric material layer located on the trench isolation structure and the first doped region to form a first sub-contact hole, wherein an orthographic projection of the first sub-contact hole on the substrate spans the first doped region and the trench isolation structure in a first direction and exposes a portion of the first doped region and a portion of the trench isolation structure, and the remaining dielectric material layer forms a dielectric layer; Selectively etching the trench isolation structure exposed by the first sub-contact hole to form a second sub-contact hole, wherein the second sub-contact hole exposes a sidewall of the first doped region, and the second sub-contact hole and the first sub-contact hole together form a first contact hole; A first contact structure is formed in the first contact hole.

9. The method for preparing a semiconductor structure according to claim 8, wherein: forming the first contact structure in the first contact hole, comprising: forming a contact layer on the surface of the first doped region exposed by the first contact hole; A contact plug is formed in the first contact hole, and the contact plug is connected to the first doped region through the contact layer.

10. The method for preparing a semiconductor structure according to claim 8, wherein: forming the first contact structure in the first contact hole, comprising: forming an epitaxial layer on a surface of the first doped region exposed by the first contact hole, wherein the epitaxial layer fills the second sub-contact hole; forming a contact layer on a surface of the epitaxial layer; A contact plug is formed in the first sub-contact hole, and the contact plug is connected to the first doped region through the contact layer and the epitaxial layer.

11. The method for preparing a semiconductor structure according to claim 8, wherein: forming the first contact structure in the first contact hole, comprising: forming an epitaxial layer on a surface of the first doped region exposed by the first contact hole, wherein the epitaxial layer fills the second sub-contact hole; Etching and removing the epitaxial layer in the first sub-contact hole to expose the first doped region; forming a contact layer on a surface of the epitaxial layer remaining in the second sub-contact hole and a surface of the exposed first doped region; A contact plug is formed in the first sub-contact hole, and the contact plug is connected to the epitaxial layer and the first doped region through the contact layer.

12. The method for preparing a semiconductor structure according to any one of claims 8 to 11, wherein: In the two adjacent active areas located on both sides of the same trench isolation structure in the first direction, the orthographic projections of the first contact hole structures corresponding to the first doped areas close to each other on the straight line extending along the second direction do not overlap, the second direction is perpendicular to the first direction, and the second direction and the first direction are both parallel to the main surface of the substrate.

13. The method for preparing a semiconductor structure according to claim 12, wherein: The first contact structure covers a corner of the first doping region.

14. The method for preparing a semiconductor structure according to any one of claims 8 to 11, characterized in that: At least two transistors arranged along the first direction are formed on the same active area, the two transistors share a second doped region, and the dielectric material layer also covers the second doped region; The preparation method further comprises: Etching the dielectric material layer on the second doped region to form a second contact hole, wherein the second contact hole exposes a portion of the second doped region; A second contact structure is formed in the second contact hole.

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