Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a display area and a first frame area, and the first frame area is arranged on one side of the display area in the circumferential direction. The first frame area comprises a signal access area, the signal access area is provided with an initial signal port, the initial signal port is accessed to the display area through an initial signal line, the initial signal line comprises a plurality of electrically connected metal wires, and at least one of the plurality of metal wires is set as a source-drain metal wire. The display device comprises the display panel.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display devices, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display technology has the advantages of being light, self-luminous, wide viewing angle, fast response speed, low brightness and low power consumption, and has become the main development direction in the field of display technology. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] At least one embodiment of the present disclosure provides a display panel, comprising a display area and a first frame area, wherein the first frame area is arranged on one side of the display area in a circumferential direction;

[0005] The first frame area includes a signal access area, the signal access area is provided with an initial signal port, the initial signal port is connected to the display area through an initial signal line, the initial signal line includes a plurality of electrically connected metal traces, and at least one of the plurality of metal traces is configured as a source-drain metal trace.

[0006] In some exemplary embodiments, the signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area;

[0007] The driving chip area and / or the circuit binding area is provided with the initial signal port.

[0008] In some exemplary embodiments, the initial signal port includes a chip port located in the driver chip region;

[0009] The plurality of metal traces include a first metal trace and a second metal trace that are electrically connected, wherein one end of the second metal trace is configured to be connected one-to-one with the chip port, and the other end is respectively connected to the first access end of the display area;

[0010] The first metal wiring is configured such that one end is connected to the second metal wiring and the other end is connected to the second access end of the display area.

[0011] In some exemplary embodiments, there are two chip ports, and the two chip ports are configured to input the same signal;

[0012] There are two first metal wires, one end of each of the two second metal wires is configured to be connected to the two chip ports in a one-to-one correspondence, and the other end of each of the two second metal wires is respectively connected to the two first access terminals of the display area;

[0013] The first metal wiring is configured to connect the two second metal wirings and to be connected to the second access end of the display area.

[0014] In some exemplary embodiments, the first metal wiring has three terminals, two of the terminals are respectively connected to two of the second metal wirings, and the other terminal is connected to the second access terminal.

[0015] In some exemplary embodiments, both of the second metal routing lines are provided with a first connection point, the first metal routing line is configured as a source-drain metal routing line, the first metal routing line includes a first branch line and a second branch line, and the first branch line is provided with a centrally arranged second connection point;

[0016] Two ends of the first branch line are configured as two connection terminals of the first metal wiring, and the two ends of the first branch line are electrically connected to two first connection points of the second metal wiring respectively;

[0017] One end of the second branch line is configured as the other connection terminal of the first metal wiring and connected to the second connection point, and the other end of the second branch line is connected to the second access terminal.

[0018] In some exemplary embodiments, a first power line is further included, the first power line is arranged between the signal access area and the display area, and the first power line includes a first metal layer and a second metal layer stacked in a first direction;

[0019] The first metal layer is arranged in the same layer as the second branch line in the first direction and is provided with a gap, and the second branch line passes through the gap.

[0020] In some exemplary embodiments, the initial signal port further comprises a plurality of circuit board ports disposed on the circuit binding area, the circuit board ports being configured to input the same signal as the chip port;

[0021] The plurality of metal traces further include a third metal trace, one end of the third metal trace being electrically connected to the second metal trace, and the other end of the third metal trace being connected to a port on the circuit board.

[0022] In some exemplary embodiments, a power line group is further included, the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, the second metal line is further provided with a third connection point, and the first connection point and the third connection point are respectively arranged on both sides of the power line group;

[0023] The plurality of circuit board ports include a first port and a second port, the second port is arranged close to an edge of the circuit binding area, the first port is arranged on a side of the second port facing the driver chip area, and the first port and the second port are electrically connected via an internal wiring located in the circuit binding area;

[0024] One end of the third metal routing is configured to be connected to the third connection point, and the other end is connected to the second port. The third metal routing is configured to be a source-drain metal routing.

[0025] In some exemplary embodiments, a power line group is further included, the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, and the second metal line is further provided with a plurality of third connection points, the third connection points are arranged to correspond one to one with the circuit board ports;

[0026] One end of the third metal routing line is configured to be electrically connected to the third connection point, and the other end is connected to the circuit board port. The third metal routing line is configured to be a source-drain metal routing line.

[0027] In some exemplary embodiments, the first frame area further includes a bending area, and the bending area is arranged between the display area and the signal access area;

[0028] The initial signal ports are all arranged in the circuit binding area;

[0029] The plurality of metal routings include a first metal routing and a second metal routing connected to each other, one end of the first metal routing is connected to the initial signal port, and the other end is connected to the bending area;

[0030] One end of the second metal wiring is connected to the bending area and electrically connected to the first metal wiring, and the other end is connected to the display area;

[0031] The first metal wiring is configured as a source-drain metal wiring.

[0032] In some exemplary embodiments, the resistance value of the initial signal line is set to be less than or equal to 60 ohms.

[0033] In some exemplary embodiments, the initial signal port is provided in plurality, and the plurality of initial signal ports include a first initial signal port, a second initial signal port, and a third initial signal port for inputting different signals;

[0034] The first initial signal port is configured to access the display area through a first signal line, the second initial signal port is configured to access the display area through a second signal line, and the third initial signal port is configured to access the display area through a third signal line;

[0035] Among the first signal line, the second signal line, and the third signal line, at least the second signal line is set as the initial signal line.

[0036] In some exemplary embodiments, the first signal line, the second signal line, and the third signal line are all set as the initial signal line and are arranged in parallel.

[0037] At least one embodiment of the present disclosure provides a display panel, comprising a display area and a first frame area, wherein the first frame area is arranged on one side of the display area in a circumferential direction;

[0038] The first frame area includes a signal access area, the signal access area is provided with an initial signal port, the initial signal port is connected to the display area through an initial signal line, and the initial signal line includes a plurality of electrically connected metal traces;

[0039] The metal wiring includes at least three metal layers stacked in a first direction, and an insulating layer is provided between adjacent metal layers.

[0040] In some exemplary embodiments, the at least three metal layers include three gate metal layers stacked in sequence, or include three gate metal layers stacked in sequence and at least one source / drain metal layer.

[0041] In some exemplary embodiments, the signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area;

[0042] The initial signal port includes a chip port located in the driver chip area;

[0043] The plurality of metal traces include a first metal trace and a second metal trace that are electrically connected, wherein one end of the second metal trace is configured to be connected one-to-one with the chip port, and the other end is respectively connected to the first access end of the display area;

[0044] One end of the first metal wiring is connected to the second metal wiring, and the other end is connected to another access end of the display area.

[0045] In some exemplary embodiments, there are two chip ports, and the two chip ports are configured to input the same signal;

[0046] There are two first metal wires, one end of each of the two second metal wires is configured to be connected to the two chip ports in a one-to-one correspondence, and the other end of each of the two second metal wires is respectively connected to the two first access terminals of the display area;

[0047] The first metal wiring is configured to connect the two second metal wirings and to be connected to the second access end of the display area.

[0048] In some exemplary embodiments, both of the second metal routing lines are provided with a first connection point, the first metal routing line includes a first branch line and a second branch line, and the first branch line is provided with a centrally arranged second connection point;

[0049] Two ends of the first branch line are configured as two connection terminals of the first metal wiring, and the two ends of the first branch line are electrically connected to two first connection points of the second metal wiring respectively;

[0050] One end of the second branch line is configured as the other connection terminal of the first metal wiring and connected to the second connection point, and the other end of the second branch line is connected to the second access terminal.

[0051] In some exemplary embodiments, the initial signal port further comprises a plurality of circuit board ports disposed on the circuit binding area, the circuit board ports being configured to input the same signal as the chip port;

[0052] The plurality of metal traces further include a third metal trace, one end of the third metal trace being electrically connected to the second metal trace, and the other end of the third metal trace being connected to a port on the circuit board.

[0053] In some exemplary embodiments, a power line group is further included, the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, the second metal line is further provided with a third connection point, and the first connection point and the third connection point are respectively arranged on both sides of the power line group;

[0054] The plurality of circuit board ports include a first port and a second port, the second port is arranged close to an edge of the circuit binding area, the first port is arranged on a side of the second port facing the driver chip area, and the first port and the second port are electrically connected via an internal wiring located in the circuit binding area;

[0055] One end of the third metal wiring is configured to be connected to the third connection point, and the other end is connected to the second port.

[0056] In some exemplary embodiments, a power line group is further included, the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, and the second metal line is further provided with a plurality of third connection points, the third connection points are arranged to correspond one to one with the circuit board ports;

[0057] One end of the third metal trace is configured to be electrically connected to the third connection point, and the other end is connected to the circuit board port.

[0058] In some exemplary embodiments, the first frame area further includes a bending area, and the bending area is arranged between the display area and the signal access area;

[0059] The signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area;

[0060] The initial signal ports are all arranged in the circuit binding area;

[0061] The plurality of metal routings include a first metal routing and a second metal routing connected to each other, one end of the first metal routing is connected to the initial signal port, and the other end is connected to the bending area;

[0062] One end of the second metal wiring is connected to the bending area and electrically connected to the first metal wiring, and the other end is connected to the display area.

[0063] At least one embodiment of the present disclosure provides a display device including the above-mentioned display panel.

[0064] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0066] Figure 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0067] Figure 2 for Figure 1 A local enlarged schematic diagram of point A in FIG.

[0068] Figure 3 for Figure 1 A partial schematic diagram of a display panel in FIG.

[0069] Figure 4 for Figure 2 Schematic diagram of the cross section at BB in FIG.

[0070] Figure 5 for Figure 1 A wiring diagram of a display panel in FIG.

[0071] Figure 6 for Figure 5 Schematic diagram of local wiring in ;

[0072] Figure 7 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0073] Figure 8 for Figure 7 A partial schematic diagram of a display panel in FIG.

[0074] Fig. 9 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0075] Fig.10 for Fig. 9 A partial schematic diagram of a display panel in FIG.

[0076] Fig.11 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0077] Fig.12 is a schematic diagram of a related display panel;

[0078] Fig.13 for Fig.12 A schematic diagram of a display panel in FIG.

[0079] Fig.14 for Fig.12 A circuit diagram of a display panel in FIG.

[0080] Fig.15 for Fig.12 A timing diagram of a display panel in FIG.

[0081] Fig.16 for Fig.12 A cross-sectional schematic diagram of a first metal routing in FIG.

[0082] Fig.17 is a schematic cross-sectional view of a display panel according to yet another embodiment of the present disclosure;

[0083] Fig.18 for Fig.17 Schematic diagram of the cross section of the metal trace at CC;

[0084] Fig.19 is a schematic cross-sectional view of metal wiring of a display panel according to another embodiment of the present disclosure;

[0085] Fig. 20is a schematic cross-sectional view of metal wiring of a display panel according to another embodiment of the present disclosure;

[0086] Fig.21 FIG. 4 is a schematic cross-sectional diagram of metal wiring of a display panel according to another embodiment of the present disclosure.

[0087] Description of reference numerals:

[0088] 1-display area, 2-signal access area, 3-initial signal line, 4-circuit binding area, 5-driver chip area, 6-metal routing, 7-power line group, 8-second metal routing, 9-first metal routing, 10-first branch line, 11-second branch line, 12-first connection point, 13-second connection point, 14-initial signal port, 15-second power line, 16-first power line, 17-binding area, 18-first fan-out area, 19-circuit board port, 20-first port, 21-second port, 22-third metal routing, 23-third connection point, 24-first gate metal layer, 25-second gate metal layer, 26-second gate insulation layer, 27-third gate metal layer, 28-third gate insulation layer, 29-interlayer dielectric material layer, 30-first source and drain metal layer, 31-passivation layer, 32-first planarization layer, 33-second source and drain metal layer, 34-second planarization layer, 35-third source and drain metal layer, 36-first metal layer, 37-second metal layer, 38-gap, 39-second fan-out area, 40-first signal line, 41-second signal line, 42-third signal line, 43-dielectric layer, 44-first filling layer, 45-second filling layer, 47-first initial signal port, 48-second initial signal port, 49-third initial signal port, 50-chip port, 51-third branch line, 52-fourth branch line, 53-fifth branch line, 54-first access terminal, 55-second access terminal, 56-pin line, 57-first border area. DETAILED DESCRIPTION

[0089] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0090] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0091] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0092] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0093] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0094] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged. In the disclosed embodiments, the gate electrode may be referred to as a control electrode.

[0095] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0096] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0097] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0098] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0099] The term "about" in the embodiments of the present disclosure means that the limits are not strictly defined and a numerical value within the range of process and measurement errors is allowed.

[0100] LTPO (Low Temperature Polycrystalline and Oxide) technology is an improved OLED screen driving technology. At present, LTPO 2.0 has become the mainstream design of current mobile phones. LTPO 2.0 is based on the LTPO structure and can achieve different frequency switching to meet the screen requirements in different application scenarios. However, in the process of high-precision screen cutting, the display device using LTPO 2.0 has an undesirable phenomenon of three-point screen. In the circuit of LTPO 2.0, such as Figures 12 to 15As shown, the pixel circuit of this example may include eight transistors (i.e., the first transistor T1 to the eighth transistor T8) and a storage capacitor Cst. The first transistor T1 is also called the first reset transistor, the second transistor T2 is also called the threshold compensation transistor, the third transistor T3 is also called the driving transistor, the fourth transistor T4 is also called the data writing transistor, the fifth transistor T5 is also called the first light emission control transistor, the sixth transistor T6 is also called the second light emission control transistor, the seventh transistor T7 is also called the second reset transistor, the eighth transistor T8 is also called the third reset transistor, and the light emitting element is an OLED. The first transistor T1, the third transistor T3 to the eighth transistor T8 may be a first type transistor, the first type transistor may be a low temperature polysilicon thin film transistor, the second transistor T2 may be a second type transistor, the second type transistor may be an oxide thin film transistor, the active layer of the low temperature polysilicon thin film transistor may be low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor may be an oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate, which can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality. When the seventh transistor T7 is turned on, the second initial signal provided by the second signal line (Vinit2) is provided to the fourth node (N1), and the fourth node (N1) is initialized. The resistance value of the second signal line will affect the initialization of the fourth node (N1). The first signal line (Vinit1) and the third signal line (Vinit3) will provide corresponding initial signals to the affected nodes when the connected transistors are turned on. Due to the use of LTPO 2.0, the wiring of the display panel located on the backing plate may have a multi-layer structure. For example, the multi-layer structure may have a first gate metal layer, a second gate metal layer, a third gate metal layer, a first source and drain metal layer, a second source and drain metal layer, and a third source and drain metal layer stacked in sequence in a first direction, or the wiring may have one or more layers in the multi-layer structure, the first direction is set to be perpendicular to the backing plate, and many wirings are arranged in a first plane, and the first direction is perpendicular to the first plane.

[0101] The display panel using LTPO 2.0 adopts high-precision frequency cutting, the OLED lighting speed slows down, the display is dim, especially in the process of high-precision screen cutting, there is an undesirable phenomenon of three-part screen. The applicant found that in the circuit of LTPO 2.0, if Fig.14The three-pulse cycle timing shown will bring about a difference in the load of the second signal line in the blanking area (Porch area, i.e., the time period between the previous frame and the next frame) and the normal display area (Normal area), making the voltage of the initial signal line in the blanking area lower, causing the OLED to light up slower and the display to be darker. At the same time, the input resistance of the main second signal line has a significant impact on the transient current of the second signal line. The larger the resistance, the more severe the fluctuation of the voltage of the second initial signal network in the display area 1 with the load change. Fig.12 and Fig.13 As shown, in the relevant display panel, two chip ports 50 on the driver chip area 5 are connected to the display area 1 on the left and right sides through the first metal wiring 8, and only the first metal wiring 8 is used as the second signal line, and the resistance value of the first metal wiring 8 is the resistance value of the second signal line, that is, R. The first metal wiring 8 is relatively long and is mostly a wiring of the gate metal layer of Mo material, with a relatively large impedance. From the chip port 50 to the position where the display area 1 is connected, the resistance of this section of wiring is generally about 150Ω.

[0102] like Figure 1 , Figure 3 and Figure 5 As shown, at least one embodiment of the present disclosure provides a display panel, which includes a display area 1 (AA area) and a first frame area 57, and the first frame area 57 is arranged on one side of the circumference of the display area 1. The first frame area 57 may include a signal access area 2, and the signal access area 2 is provided with an initial signal port 14. The initial signal port 14 is connected to the display area 1 (AA area) through an initial signal line 3, and the initial signal line 3 includes a plurality of electrically connected metal traces 6, and at least one of the plurality of metal traces 6 is set as a source-drain metal trace, that is, a trace structure in the source-drain metal layer. As a result, the initial signal line 3 has a relatively small impedance, which can improve the display effect and avoid the phenomenon of poor display of the three-point screen during the high-precision screen cutting process.

[0103] In some exemplary embodiments, Figure 1As shown, the display panel includes a display area 1, and a peripheral area surrounding the periphery of the display area 1, and the peripheral area may include a first frame area 57 located on one side of the display area 1, and frame areas located on other sides of the display area 1. Among them, the first frame area 57 may be the lower frame of the display panel, and the frame areas on the other sides may include the upper frame, left frame and right frame of the display panel. The first frame area 57 may include a first fan-out area 18, a bending area 17, a second fan-out area 39 and a signal access area 2, which are sequentially arranged in a direction away from the display area 1. The first fan-out area 18 may be connected to the display area 1, and the bending area 17 may be connected between the first fan-out area 18 and the second fan-out area 39, and may be configured so that the signal access area 2 is bent to the back of the display area 1. The first fan-out area 18 may be provided with at least a power line and a plurality of display lead lines, and the bending area 17 may be provided with a plurality of bending connection lines.

[0104] In some exemplary embodiments, Figure 1 , Figure 3 and Figure 5 As shown, the signal access area 2 includes a driver chip area 5 and a circuit binding area 4, and the circuit binding area 4 is arranged on a side of the driver chip area 5 away from the display area 1, and the driver chip area 5 is close to the second fan-out area 39. The driver chip area 5 can be provided with a plurality of contact pads (Bump), and the plurality of contact pads can be configured to be bound and connected with at least one driver chip. The driver chip can be configured to generate a driving signal required for driving the sub-pixel and provide the driving signal to the data line of the display area 1. The circuit binding area 4 can be provided with a plurality of contact pads, and the plurality of contact pads can be configured to be bound and connected with at least one circuit board, for example, a flexible printed circuit (FPC), and the driver chip of the driver chip area 5 is connected to the circuit board of the circuit binding area 4 through a pin line 56.

[0105] In some exemplary embodiments, Figure 6As shown, the initial signal port 14 may have multiple initial signal ports, and the multiple initial signal ports 14 may include a first initial signal port 47, a second initial signal port 48 and a third initial signal port 49, and the first initial signal port 47, the second initial signal port 48 and the third initial signal port 49 are configured to input different signals. The first initial signal port 47, the second initial signal port 48 and the third initial signal port 49 are arranged close to each other. For example, the second initial signal port 48 may be provided in the driver chip area 5, and a first initial signal port 47 and a third initial signal port 49 are arranged close to the second initial signal port 48, so that each second initial signal port 48 forms a group of ports with a first initial signal port 47 and a third initial signal port 49 and are arranged in a centralized manner. The display panel may have a first signal line 40, a second signal line 41 and a third signal line 42, the first signal line 40 may electrically connect the first initial signal port 47 and the display area 1, the second signal line 41 may electrically connect the second initial signal port 48 and the display area 1, and the third signal line 42 may electrically connect the third initial signal port 49 and the display area 1. The first signal line 40, the second signal line 41 and the third signal line 42 are arranged in parallel in the plane formed by the second direction and the third direction, and the extension direction is consistent. The first direction, the second direction and the third direction are perpendicular to each other. Among the first signal line 40, the second signal line 41 and the third signal line 42, only the second signal line 41 may adopt the routing structure of the initial signal line 3; or the first signal line 40, the second signal line 41 and the third signal line 42 may adopt the routing structure of the initial signal line 3; or in addition to the first signal line 40 adopting the routing structure of the initial signal line 3, one of the first signal line 40 and the third signal line 42 adopts the routing structure of the initial signal line 3. Therefore, on the basis that the second signal line 41 has a smaller impedance, the first signal line 40 and the third signal line 42 may also have a smaller impedance, further ensuring the display effect.

[0106] The following takes the second signal line 41 and the second initial signal port 48 as an example to specifically explain the routing structure of the initial signal line. Figure 3 and Figure 5As shown, the driver chip area 5 may be provided with two chip ports 50, the two chip ports 50 may input the same signal, the two chip ports 50 serve as the second initial signal port 48, the chip port 50 is on the side of the driver chip area 5 close to the display area 1, and the two chip ports 50 are symmetrical according to the center line C1, the two chip ports 50 are symmetrically arranged according to the center line C1, and the center line C1 is the center line passing through the geometric center of the driver chip area 5. At the same time, the first initial signal port 47 and the third initial signal port 49 may also be arranged with corresponding ports corresponding to the chip port 50 of the second initial signal port 48, and are also symmetrical according to the center line C1. The second signal line 41 is set as an initial signal routing line, and the second signal line 41 may include a first metal routing line 9 and a second metal routing line 8, the two second metal routing lines 8 are arranged in a mirror image according to the center line C1, one end of the two second metal routing lines 8 may be connected to the two chip ports 50 one by one, and the other ends of the two second metal routing lines 8 may be set to access the display area 1. The second metal wiring 8 may be a gate metal wiring located in the gate metal layer, but is not limited thereto. For example, the second metal wiring 8 may be a source-drain metal wiring, which is a metal wiring located in the source-drain metal layer. The first metal wiring 9 may be a source-drain metal wiring, and the first metal wiring 9 may be connected in parallel with part of the wiring of the second metal wiring 8.

[0107] In some exemplary embodiments, Figure 3 As shown, the second metal wiring 8 includes a third branch line 51, a fourth branch line 52 and a fifth branch line 53 connected in sequence, wherein one end of the third branch line 51 is connected to the chip port 50 and is away from the driver chip area 5 along the second direction; one end of the fourth branch line 52 is connected to the third branch line 51, and the connection point between the fourth branch line 52 and the third branch line 51 is set to the first connection point 12, and the other end of the fourth branch line 52 extends away from the first connection point 12, and the fourth branch line 52 extends along the third direction. One end of the fifth branch line 53 is connected to the fourth branch line 52, and the connection point between the fourth branch line 52 and the fifth branch line 53 is the third connection point 23, and the other end of the fifth branch line 53 extends away from the circuit binding area 4 along the second direction and extends to a first access end 54 of the display area 1. The two second metal wirings 8 are also symmetrically arranged according to the center line C1, and the two second metal wirings 8 are respectively connected to the two first access ends 54 of the display area 1.

[0108] In some exemplary embodiments, Figure 3As shown, the first metal wiring 9 includes two wirings, namely, a first branch line 10 and a second branch line 11. The first branch line 10 and the second branch line 11 are made of the same material and are both source-drain metal wirings. A second connection point 13 is provided at the central position of the first branch line 10. The first branch line 10 extends along the third direction. The two ends of the first branch line 10 are respectively electrically connected to the first connection points 12 of the two second metal wirings 8, so that the first branch line 10 connects the two second metal wirings 8. In addition, the second branch line 11 extends along the second direction, which is perpendicular to the third direction. One end of the second branch line 11 is connected to the second connection point 13, and the other end is connected to the second access terminal 55 of the display area 1. The position where the first branch line 10 connects the two first connection points 12 serves as the two wiring terminals of the first metal wiring 9, and the position where the second branch line 11 connects the second access terminal 55 serves as another wiring terminal of the first metal wiring 9, so that the first metal wiring 9 has three wiring terminals. The first metal routing 9 can be a source-drain metal routing, and the second metal routing 8 can be a gate metal routing. The materials of the two are different, and the gate metal routing and the source-drain metal routing are in different layers in the first direction. The connection between the first branch line 10 and the second metal routing 8 at the first connection point 12 can be connected by punching, and the first direction is perpendicular to the plane formed by the second direction and the third direction.

[0109] In some exemplary embodiments, Figure 1 , Figure 2 and Figure 5As shown, the display panel also includes a power line group 7, which may include a first power line 16 (VDD) and a second power line 15 (VSS). The first power line 16 and the second power line 15 are arranged between the circuit binding area 4 and the display area 1, and can be electrically connected to the circuit binding area 4 to access the connection of the bending area 17. In addition, the first fan-out area 18 also has corresponding first power lines 16 and second power lines 15 (not shown in the figure), so that the first power lines 16 and the second power lines 15 continue to access the connection lines of the display area 1. The second metal trace 8 needs to cross the power line group 7 to connect to the display area 1 during the extension process to the display area, and the second branch line 11 also needs to cross the power line group 7 to connect to the display area 1. The first power line 16 may be a dual source-drain metal wiring, and the first power line 16 may include a first metal layer 35 and a second metal layer 36 stacked in a first direction, and the first metal layer 35 and the second branch line 11 may both be a first source-drain metal layer wiring structure, and the second metal layer 36 may be a second source-drain metal layer wiring structure, so that the first metal layer 35 and the second branch line 11 are arranged in the same layer in the first direction. The first metal layer 35 is disposed on the dielectric layer 43, and the second metal layer 36 is located on the side of the first metal layer 35 away from the dielectric layer 43. The first metal layer 35 is provided with a notch 37 corresponding to the second branch line 11, so that the first metal layer 35 is disconnected. The second branch line 11 can pass through the gap 37, and the second branch line 11 is spaced apart from the edge of the gap 37, so that the first metal layer 35 and the second branch line 11 are avoided and are not electrically connected. The second metal layer 36 passes over the second branch line 11 and is spaced apart from the second branch line 11. The first filling layer 44 and the second filling layer 45 can be filled in the gap 37 and between the second metal layer 36 and the second branch line 11, so that the second branch line 11 crosses the power line group 7 and connects to the display area 1. The second metal wiring 8 can be a gate metal wiring. The second metal wiring 8 and the power line group 7 are in different layers, that is, the gate metal wiring and the source and drain metal wiring are in different layers in the first direction, and the second metal wiring 8 and the wiring of the power line group 7 do not affect each other.

[0110] like Figure 1 and Figure 3 As shown, in this example, relative to the relevant display panel, the second signal line 41 adds a first metal routing line 9, and the first metal routing line 9 and part of the second metal routing line 8 are connected in parallel. The overall resistance of the second metal routing line 8 is about 150Ω, and the resistance of the first metal routing line 9 is about 50Ω. After resistance calculation, the resistance of the second signal line 41 is about 37.5Ω. The second signal line 41 adopts the routing structure of the initial signal line 3 mentioned above, which can reduce the impedance and improve the poor display phenomenon. In particular, when the resistance is controlled below 60 ohms, the display effect is significantly improved. The equivalent resistance of the second signal line 41 is about 37.5Ω. Compared with 150Ω, the resistance is significantly reduced, which can improve the display effect. The first signal line 40 and the third signal line 42 can also be used as shown in Figure 3 The routing structure of the second signal line 41 is also the initial signal line.

[0111] In some exemplary embodiments, Figure 7 and Figure 8 As shown, the circuit binding area 4 is also provided with a plurality of circuit board ports 19, and the circuit board port 19 also serves as the second initial signal port 48. Thus, the second initial signal port 48 has the circuit board port 19 in the circuit binding area 4 and the chip port 50 in the driver chip 5, and the circuit board port 19 and the chip port 50 input the same signal. At the same time, the first initial signal port and the third initial signal port can also be arranged with corresponding ports corresponding to the chip port 50 and the circuit board port 19 of the second initial signal port 48, and are also symmetrical according to the center line C1. The chip port 50 is connected to the three access terminals (two first access terminals 54 and one second access terminal 55) of the display area 1 through the first metal trace 9 and the second metal trace 8, and the circuit board port 19 is connected to the initial signal line through the third metal trace 22. There are four circuit board ports 19, and the four circuit board ports 19 include two first ports 20 and two second ports 21. The two first ports 20 and the two second ports 21 correspond to each other. One first port 20 and one second port 21 are located on one side of the driver chip area 5, and another first port 20 and another second port 21 are located on the other side of the driver chip area 5, and are arranged symmetrically about the center line C1. The second port 21 may be located near the edge of the driver chip area 5, and the first port 20 may be located on the side of the second port 21 facing the driver chip area 5 in the third direction, and the corresponding first port 20 and second port 21 are electrically connected through the internal wiring located in the circuit binding area 4. The circuit board ports 19 are not limited to being provided with four, for example, there may be six, including three first ports 20 and three second ports 21.

[0112] In some exemplary embodiments, Figure 7 and Figure 8As shown, the second metal wiring 8 has a third connection point 23 in addition to the first connection point 12, wherein the second metal wiring 8 includes a third branch line 51, a fourth branch line 52 and a fifth branch line 53 connected in sequence, wherein one end of the third branch line 51 is connected to the chip port 50 and is away from the driver chip area 5 along the second direction; one end of the fourth branch line 52 is connected to the third branch line 51, the connection point between the fourth branch line 52 and the third branch line 51 is the first connection point 12, the other end of the fourth branch line 52 extends away from the first connection point 12, and the fourth branch line 52 extends along the third direction. One end of the fifth branch line 53 is connected to the fourth branch line 52, the connection point between the fourth branch line 52 and the fifth branch line 53 is the third connection point 23, the other end of the fifth branch line 53 extends away from the circuit binding area 4 along the second direction, and extends to a first access end 54 of the display area 1. The fourth branch line 52 crosses the power line group 7, and the first connection point 12 and the third connection point 23 are respectively located on both sides of the power line group 7 in the third direction. The third metal wiring 22 is a source-drain metal wiring, that is, a wiring structure in the source-drain metal layer. The third metal wiring 22 extends along the second direction. One end of the third metal wiring 22 can be connected to the third connection point 23, and the other end is connected to the second port 21. The third metal wiring 22 and the second metal wiring 8 are in different layers in the first direction. The connection between the third metal wiring 22 and the second metal wiring 8 at the third connection point 23 can be connected by punching. Therefore, the display panel is connected to the display area 1 by setting multiple initial signal ports and multiple parallel lines, which effectively reduces the resistance of the second signal line 41 and improves the display effect. The first signal line and the third signal line can also be connected as shown in the following example. Figure 8 The routing structure of the second signal line 41 is also the initial signal line.

[0113] In some exemplary embodiments, Fig. 9 and Fig.10As shown, the circuit binding area 4 is also provided with a plurality of circuit board ports 19, and the circuit board port 19 also serves as the second initial signal port 48. Thus, the second initial signal port 48 has the circuit board port 19 in the circuit binding area 4 and the chip port 50 in the driver chip 5, and the circuit board port 19 and the chip port 50 input the same signal. At the same time, the first initial signal port and the third initial signal port can also be arranged with corresponding ports corresponding to the chip port 50 and the circuit board port 19 of the second initial signal port 48, and are also symmetrical according to the center line C1. The chip port 50 is connected to the three access terminals (two first access terminals 54 and one second access terminal 55) of the display area 1 through the first metal trace 9 and the second metal trace 8, and the circuit board port 19 is connected to the initial signal line through the third metal trace 22. There are four circuit board ports 19, and the four circuit board ports 19 include two first ports 20 and two second ports 21. The two first ports 20 and the two second ports 21 correspond to each other. One first port 20 and one second port 21 are located on one side of the driver chip area 5, and another first port 20 and another second port 21 are located on the other side of the driver chip area 5, and are symmetrically arranged about the center line C1. The second port 21 may be located near the edge of the driver chip area 5, and the first port 20 may be located on the side of the second port 21 facing the driver chip area 5 in the third direction, and the two circuit board ports 19 have no electrical connection relationship. The two circuit board ports 19 on one side of the driver chip area 5 are respectively located on both sides of the position where the power line group 7 is connected to the circuit binding area 4. The circuit board ports 19 are not limited to being provided with four, for example, there may be six, including three first ports 20 and three second ports 21.

[0114] In some exemplary embodiments, Fig. 9 and Fig.10As shown, each second metal trace 8 has two third connection points 23 in addition to the first connection point 12, so that the number of the third connection points 23 is the same as the number of the circuit board ports 19. The second metal trace 8 has a third connection point 23 in addition to the first connection point 12, wherein the second metal trace 8 includes a third branch line 51, a fourth branch line 52 and a fifth branch line 53 connected in sequence, wherein one end of the third branch line 51 is connected to the chip port 50 and is away from the driver chip area 5 along the second direction; one end of the fourth branch line 52 is connected to the third branch line 51, the connection point between the fourth branch line 52 and the third branch line 51 is the first connection point 12, the other end of the fourth branch line 52 extends away from the first connection point 12, and the fourth branch line 52 extends along the third direction. One end of the fifth branch line 53 is connected to the fourth branch line 52, the connection point between the fourth branch line 52 and the fifth branch line 53 is the third connection point 23, and the other end of the fifth branch line 53 extends away from the circuit binding area 4 along the second direction and extends to a first access end 54 of the display area 1. The fourth branch line 52 crosses the power line group 7, and the two third connection points 23 are respectively located on both sides of the power line group 7 in the third direction. One third connection point 23 and the first connection point 12 are on the same side of the power line group 7, and each third connection point 23 has a corresponding circuit board port 19 in the second direction. The third metal routing 22 is a source-drain metal routing, that is, a routing structure in the source-drain metal layer. The third metal routing 22 extends along the second direction. One end of the third metal routing 22 can be connected to the third connection point 23, and the other end is connected to the circuit board port 19. The third metal routing 22 and the second metal routing 8 are in different layers in the first direction, and the connection between the third metal routing 22 and the second metal routing 8 at the third connection point 23 can be connected by punching. Therefore, the display panel is connected to the display area 1 by setting multiple initial signal ports, and multiple parallel lines are connected to the display area 1, which effectively reduces the resistance of the second signal line 41 and improves the display effect. The first signal line and the third signal line can also be connected as follows Fig.10 The routing structure of the second signal line 41 is also the initial signal line.

[0115] In some exemplary embodiments, Fig.11As shown, the circuit binding area 4 is provided with two circuit board ports 19, and the two circuit board ports 19 serve as the second initial signal ports 48. The two circuit board ports 19 are respectively located at the two end edges of the circuit binding area 4 in the third direction, and are symmetrical according to the center line C1 of the driver chip area 5. At the same time, the first initial signal port and the third initial signal port may also be arranged with corresponding ports corresponding to the circuit board port 19 of the second initial signal port 48, and are also symmetrical according to the center line C1. The second signal line 41 may include two first metal traces 9 and two second metal traces 8, and the two first metal traces 9 and the two second metal traces 8 are connected one by one. The second metal trace 8 may be a source-drain metal trace, that is, a trace structure in the source-drain metal layer, and the first metal trace 9 may be a gate metal trace, that is, a trace structure in the gate metal layer. The second metal trace 8 and the first metal trace 9 may be connected by punching, that is, a jumper connection is performed in the bending area 17. Among them, the second metal trace 8 and the first metal trace 9 both extend along the second direction, one end of the first metal trace 9 can be connected to the circuit board port 19, and the other end is connected to the bending area 17, one end of the second metal trace 8 is connected to the bending area 17 and electrically connected to the first metal trace 9, and the other end is connected to the first access terminal 54 of the display area 1. In addition, the second signal line 41 does not need to cross the power line group 7, which reduces the trace length and reduces the manufacturing difficulty. Fig. 9 In the related display panel, the port on the driver chip area 5 is cancelled in this example, and the initial signal routing is directly input from the circuit binding area 4. At the same time, the source and drain metals are used as routing to connect to the bending area 17. The dielectric constant of the source and drain metals is 0.042, which is smaller than the dielectric constant of the gate metal of 0.41, so that the overall impedance will have at least ten times the gain, and the purpose of reducing resistance can also be achieved.

[0116] In some exemplary embodiments, Fig. 9 On the basis of the related display panel shown, the two chip ports 50 on the driving chip area 5 are connected to the display area 1 on the left and right sides through the first metal wiring 8, and only the first metal wiring 8 is used as the second signal line. The first metal wiring 8 uses the source-drain metal wiring. The main material of the source-drain metal wiring is source-drain metal, and the dielectric constant of the source-drain metal is 0.042. Compared with the dielectric constant of 0.41 of the gate metal dielectric used in the related technology, the dielectric constant is smaller, so that the overall impedance will have at least ten times the benefit, and the purpose of reducing resistance can also be achieved.

[0117] In some exemplary embodiments, a display panel, such as Fig.17 and Fig.18As shown, the display panel includes a display area 1 (AA area) and a first frame area 57, and the first frame area 57 is arranged on one side of the circumference of the display area 1. The first frame area 57 may include a signal access area 2, and the signal access area 2 is provided with an initial signal port 14. The initial signal port 14 is connected to the display area 1 (AA area) through an initial signal line 3, and the initial signal line 3 includes a plurality of electrically connected metal traces 6, and the metal traces 6 include at least three layers of metal layers stacked in a first direction, and an insulating layer is provided between adjacent metal layers. As a result, the initial signal line 3 has a smaller impedance, which can improve the display effect and avoid the phenomenon of poor display of the three-point screen during the high-precision screen cutting process.

[0118] In some exemplary embodiments, Fig.17 As shown, the initial signal line 3 routing layout adopts Figure 3 The plurality of metal traces 6 include: Figure 3 The second metal wiring 8 and the first metal wiring 9 shown in the figure have at least three metal layers stacked in the first direction. However, it is not limited thereto. For example, the wiring layout of the initial signal line 3 in this example adopts the following Figure 8 , Fig.10 The second signal line 41 shown in FIG. 1 is arranged in the same manner, and the plurality of metal lines 6 include: Figure 8 and Fig.10 The second metal routing 8, the first metal routing 9, and the third metal routing 22 shown in the figure all have at least three metal layers stacked in the first direction; for another example, the routing layout of the initial signal line 3 in this example adopts the following Fig.11 The second signal line 41 shown in FIG. 1 is arranged in the same manner, and the plurality of metal lines 6 include: Fig.11 The second metal wiring 8 and the first metal wiring 9 shown in the figure have at least three metal layers stacked in the first direction; for example, the wiring layout of the initial signal line 3 in this example and the use of Fig.12 The first metal wiring 8 has the same routing mode as shown, and the first metal wiring 8 has at least three metal layers stacked in the first direction. Fig.18 for Fig.17The schematic cross-sectional view of the metal routing 6 at CC is shown in FIG. The metal routing may include three metal layers stacked in a first direction, with an insulating layer provided between adjacent metal layers. The three metal layers are provided on a backing plate (not shown in the figure) and are connected in parallel, with the first direction being perpendicular to the second direction and the third direction. The three metal layers are, in order from the side close to the backing plate (not shown in the figure) to the side away from the backing plate (not shown in the figure), a first gate metal layer 24, a second gate metal layer 25, and a third gate metal layer 27. A second gate insulating layer 26 is provided between the first gate metal layer 24 and the second gate metal layer 25 as an insulating layer; a third gate insulating layer 28 is provided between the second gate metal layer 25 and the third gate metal layer 27 as an insulating layer. Fig.11 The cross-sectional schematic diagram of the second metal wiring 8 of the related display panel shown adopts a two-layer metal stacking structure, that is, a first gate metal layer 24 and a second gate metal layer 25 are stacked in the first direction. Therefore, in this example, three metal layers are used, and one metal layer is added compared to the related display panel. By connecting multiple metal layers in parallel, the resistance of the wiring is effectively reduced. In some exemplary embodiments, there are multiple initial signal lines 3, and all initial signal lines 3 can use the same metal wiring 6, all of which have a three-layer structure.

[0119] In some exemplary embodiments, Fig.19 As shown, the metal wiring includes four metal layers stacked in the first direction, an insulating layer is provided between adjacent metal layers, and the four metal layers are provided on a liner (not shown in the figure) and form a parallel relationship. The four metal layers are sequentially a first gate metal layer 24, a second gate metal layer 25, a third gate metal layer 27 and a first source-drain metal layer 30 from the side close to the liner (not shown in the figure) to the side away from the liner (not shown in the figure), forming three gate metal layers and one source-drain metal layer. A second gate insulating layer 26 is provided between the first gate metal layer 24 and the second gate metal layer 25 as an insulating layer; a third gate insulating layer 28 is provided between the second gate metal layer 25 and the third gate metal layer 27 as an insulating layer; and an interlayer dielectric layer 29 is provided between the third gate metal layer 27 and the first source-drain metal layer 30 as an insulating layer. Therefore, in this example, four metal layers are used, and two metal layers are added compared to the relevant display panel. By connecting multiple metal layers in parallel, the resistance of the wiring is effectively reduced. In some exemplary embodiments, there are multiple initial signal lines 3 , and all initial signal lines 3 may use the same metal routing line 6 , and all have a four-layer structure.

[0120] In some exemplary embodiments, Fig. 20As shown, the metal wiring includes five metal layers stacked in a first direction, an insulating layer is provided between adjacent metal layers, and the five metal layers are arranged on a liner (not shown in the figure) and are connected in parallel. The five metal layers are, from the side close to the liner (not shown in the figure) to the side away from the liner (not shown in the figure), the first gate metal layer 24, the second gate metal layer 25, the third gate metal layer 27, the first source-drain metal layer 30, and the second source-drain metal layer 33, forming three gate metal layers and two source-drain metal layers. A second gate insulating layer 26 is provided between the first gate metal layer 24 and the second gate metal layer 25 as an insulating layer; a third gate insulating layer 28 is provided between the second gate metal layer 25 and the third gate metal layer 27 as an insulating layer; an interlayer dielectric layer 29 is provided between the third gate metal layer 27 and the first source-drain metal layer 30 as an insulating layer; a passivation layer 31 and a first planarization layer 32 are provided between the first source-drain metal layer 30 and the second source-drain metal layer 33, the passivation layer 31 and the first planarization layer 32 serve as insulating layers, the first filling layer 44 is made of the same material as the passivation layer 31, and the second filling layer 45 is made of the same material as the first planarization layer 32. Therefore, in this example, five metal layers are used, and three metal layers are added compared to the related display panel. By connecting multiple metal layers in parallel, the resistance of the wiring is effectively reduced. In some exemplary embodiments, there are multiple initial signal lines 3, and all initial signal lines 3 can use the same metal wiring 6, all with a five-layer structure.

[0121] In some exemplary embodiments, Fig.21As shown, the metal wiring includes six metal layers stacked in a first direction, an insulating layer is provided between adjacent metal layers, and the six metal layers are arranged on a liner (not shown in the figure) and are connected in parallel. The six metal layers are sequentially arranged from the side close to the liner (not shown in the figure) to the side away from the liner (not shown in the figure), namely, the first gate metal layer 24, the second gate metal layer 25, the third gate metal layer 27, the first source-drain metal layer 30, the second source-drain metal layer 33, and the third source-drain metal layer 35, forming three gate metal layers and two source-drain metal layers. A second gate insulating layer 26 is provided between the first gate metal layer 24 and the second gate metal layer 25 as an insulating layer; a third gate insulating layer 28 is provided between the second gate metal layer 25 and the third gate metal layer 27 as an insulating layer; an interlayer dielectric layer 29 is provided between the third gate metal layer 27 and the first source-drain metal layer 30 as an insulating layer; a passivation layer 31 and a first planarization layer 32 are provided between the first source-drain metal layer 30 and the second source-drain metal layer 33, and the passivation layer 31 and the first planarization layer 32 serve as insulating layers. A second planarization layer 34 is provided between the second source-drain metal layer 33 and the third source-drain metal layer 35 as an insulating layer. Therefore, in this example, five metal layers are used, and three metal layers are added compared to the related display panel, and the resistance of the wiring is effectively reduced by connecting multiple metals in parallel. In some exemplary embodiments, there are multiple initial signal lines 3, and all initial signal lines 3 can use the same metal wiring 6, all with a six-layer structure.

[0122] In some exemplary embodiments, a display device includes the above-mentioned display panel, and the display device may be an OLED display device, such as a mobile phone, a monitor, etc.

[0123] In combination with the above embodiments, the display panel forms a parallel routing method by adopting source-drain metal routing and multi-port routing of the second initial signal, thereby reducing the impedance and making the resistance target value of the second signal line 41 as small as possible to be less than 50Ω, thereby avoiding the undesirable phenomenon of three-part screen cutting during high-precision screen cutting and improving the display effect.

[0124] The above-described embodiments only express several embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed, but the contents described are only embodiments adopted for facilitating the understanding of the present disclosure, and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure, but the scope of patent protection of the present disclosure shall still be defined by the attached claims.

Claims

1. A display panel, characterized in that: It includes a display area and a first frame area, wherein the first frame area is arranged on one side of the display area in a circumferential direction; The first frame area includes a signal access area, the signal access area is provided with an initial signal port, the initial signal port is connected to the display area through an initial signal line, the initial signal line includes a plurality of electrically connected metal traces, and at least one of the plurality of metal traces is configured as a source-drain metal trace.

2. The display panel according to claim 1, characterized in that: The signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area; The driving chip area and / or the circuit binding area is provided with the initial signal port.

3. The display panel according to claim 2, characterized in that: The initial signal port includes a chip port located in the driver chip area; The plurality of metal traces include a first metal trace and a second metal trace that are electrically connected, wherein one end of the second metal trace is configured to be connected one-to-one with the chip port, and the other end is respectively connected to the first access end of the display area; The first metal wiring is configured such that one end is connected to the second metal wiring and the other end is connected to the second access end of the display area.

4. The display panel according to claim 3, characterized in that: There are two chip ports, and the two chip ports are configured to input the same signal; There are two second metal wires, one end of each of the two second metal wires is configured to be connected to the two chip ports in a one-to-one correspondence, and the other end of each second metal wire is respectively connected to the two first access terminals of the display area; The first metal wiring is configured to connect the two second metal wirings and to be connected to the second access end of the display area.

5. The display panel according to claim 4, characterized in that: The first metal wiring is provided with three connection terminals, two of the connection terminals are respectively connected to two of the second metal wirings, and the other connection terminal is connected to the second access terminal.

6. The display panel according to claim 5, characterized in that: Both of the two second metal routings are provided with a first connection point, the first metal routing is configured as a source-drain metal routing, the first metal routing includes a first branch line and a second branch line, and the first branch line is provided with a centrally arranged second connection point; Two ends of the first branch line are configured as two connection terminals of the first metal wiring, and the two ends of the first branch line are electrically connected to two first connection points of the second metal wiring respectively; One end of the second branch line is configured as the other connection terminal of the first metal wiring and connected to the second connection point, and the other end of the second branch line is connected to the second access terminal.

7. The display panel according to claim 6, characterized in that: It also includes a first power line, which is arranged between the signal access area and the display area, and includes a first metal layer and a second metal layer stacked in a first direction; The first metal layer is arranged in the same layer as the second branch line in the first direction and is provided with a gap, and the second branch line passes through the gap.

8. The display panel according to claim 7, characterized in that: The initial signal port also includes a plurality of circuit board ports arranged on the circuit binding area, and the circuit board ports are arranged to input the same signal as the chip port; The plurality of metal traces further include a third metal trace, one end of the third metal trace being electrically connected to the second metal trace, and the other end of the third metal trace being connected to a port on the circuit board.

9. The display panel according to claim 8, characterized in that: It also includes a power line group, the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, the second metal line is further provided with a third connection point, and the first connection point and the third connection point are respectively arranged on both sides of the power line group; The plurality of circuit board ports include a first port and a second port, the second port is arranged close to an edge of the circuit binding area, the first port is arranged on a side of the second port facing the driver chip area, and the first port and the second port are electrically connected via an internal wiring located in the circuit binding area; One end of the third metal routing is configured to be connected to the third connection point, and the other end is connected to the second port. The third metal routing is configured to be a source-drain metal routing.

10. The display panel according to claim 8, characterized in that: It also includes a power line group, the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, and the second metal line is further provided with a plurality of third connection points, and the third connection points are arranged to correspond one to one with the circuit board ports; One end of the third metal routing line is configured to be electrically connected to the third connection point, and the other end is connected to the circuit board port. The third metal routing line is configured to be a source-drain metal routing line.

11. The display panel according to claim 2, characterized in that: The first frame area further includes a bending area, and the bending area is arranged between the display area and the signal access area; The initial signal ports are all arranged in the circuit binding area; The plurality of metal routings include a first metal routing and a second metal routing connected to each other, one end of the first metal routing is connected to the initial signal port, and the other end is connected to the bending area; One end of the second metal wiring is connected to the bending area and electrically connected to the first metal wiring, and the other end is connected to the display area; The first metal wiring is configured as a source-drain metal wiring.

12. The display panel according to any one of claims 1 to 11, characterized in that: The resistance value of the initial signal line is set to be less than or equal to 60 ohms.

13. The display panel according to any one of claims 1 to 11, characterized in that: There are multiple initial signal ports, and the multiple initial signal ports include a first initial signal port, a second initial signal port and a third initial signal port for inputting different signals; The first initial signal port is configured to access the display area through a first signal line, the second initial signal port is configured to access the display area through a second signal line, and the third initial signal port is configured to access the display area through a third signal line; Among the first signal line, the second signal line, and the third signal line, at least the second signal line is set as the initial signal line.

14. The display panel according to claim 13, characterized in that: The first signal line, the second signal line, and the third signal line are all set as the initial signal line and arranged in parallel.

15. A display panel, characterized in that: It includes a display area and a first frame area, wherein the first frame area is arranged on one side of the display area in a circumferential direction; The first frame area includes a signal access area, the signal access area is provided with an initial signal port, the initial signal port is connected to the display area through an initial signal line, and the initial signal line includes a plurality of electrically connected metal traces; The metal wiring includes at least three metal layers stacked in a first direction, and an insulating layer is provided between adjacent metal layers.

16. The display panel according to claim 15, characterized in that: The at least three metal layers include three gate metal layers stacked in sequence, or include three gate metal layers stacked in sequence and at least one source / drain metal layer.

17. The display panel according to claim 16, characterized in that: The signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area; The initial signal port includes a chip port located in the driver chip area; The plurality of metal traces include a first metal trace and a second metal trace that are electrically connected, wherein one end of the second metal trace is configured to be connected one-to-one with the chip port, and the other end is respectively connected to the first access end of the display area; One end of the first metal wiring is connected to the second metal wiring, and the other end is connected to another access end of the display area.

18. The display panel according to claim 17, characterized in that: There are two chip ports, and the two chip ports are configured to input the same signal; There are two second metal wires, one end of each of the two second metal wires is configured to be connected to the two chip ports in a one-to-one correspondence, and the other end of each second metal wire is respectively connected to the two first access terminals of the display area; The first metal wiring is configured to connect the two second metal wirings and to be connected to the second access end of the display area.

19. The display panel according to claim 18, characterized in that: The two second metal routing lines are both provided with a first connection point, the first metal routing line includes a first branch line and a second branch line, and the first branch line is provided with a centrally arranged second connection point; Two ends of the first branch line are configured as two connection terminals of the first metal wiring, and the two ends of the first branch line are electrically connected to two first connection points of the second metal wiring respectively; One end of the second branch line is configured as the other connection terminal of the first metal wiring and connected to the second connection point, and the other end of the second branch line is connected to the second access terminal.

20. The display panel according to claim 19, characterized in that: The initial signal port also includes a plurality of circuit board ports arranged on the circuit binding area, and the circuit board ports are arranged to input the same signal as the chip port; The plurality of metal traces further include a third metal trace, one end of the third metal trace being electrically connected to the second metal trace, and the other end of the third metal trace being connected to a port on the circuit board.

21. The display panel according to claim 20, characterized in that: It also includes a power line group, the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, the second metal line is further provided with a third connection point, and the first connection point and the third connection point are respectively arranged on both sides of the power line group; The plurality of circuit board ports include a first port and a second port, the second port is arranged close to an edge of the circuit binding area, the first port is arranged on a side of the second port facing the driver chip area, and the first port and the second port are electrically connected via an internal wiring located in the circuit binding area; One end of the third metal wiring is configured to be connected to the third connection point, and the other end is connected to the second port.

22. The display panel according to claim 20, characterized in that: It also includes a power line group, the power line group is arranged between the signal access area and the display area, the second metal line crosses the power line group, and the second metal line is further provided with a plurality of third connection points, and the third connection points are arranged to correspond one to one with the circuit board ports; One end of the third metal trace is configured to be electrically connected to the third connection point, and the other end is connected to the circuit board port.

23. The display panel according to claim 15, characterized in that: The first frame area further includes a bending area, and the bending area is arranged between the display area and the signal access area; The signal access area includes a driver chip area and a circuit binding area, and the circuit binding area is arranged on a side of the driver chip area away from the display area; The initial signal ports are all arranged in the circuit binding area; The plurality of metal routings include a first metal routing and a second metal routing connected to each other, one end of the first metal routing is connected to the initial signal port, and the other end is connected to the bending area; One end of the second metal wiring is connected to the bending area and electrically connected to the first metal wiring, and the other end is connected to the display area.

24. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 23.

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